All IPs > Interface Controller & PHY
Interface Controller & PHY semiconductor IPs are integral components in modern digital systems that facilitate communication between various parts of an electronic system, including processors, memory, and peripherals. These IPs are designed to manage data traffic efficiently, ensuring reliable and high-speed data transfer between different interfaces and devices. This catalog features a wide range of IPs that serve various standard and custom interface protocols, making them indispensable for semiconductor companies developing complex SoCs (System on Chips) and digital systems.
In this category, you will find a selection of IPs tailored for popular interface protocols such as AMBA (AHB, APB, AXI), HDMI, PCI, USB, and MIPI, among others. Each IP solution is optimized for performance, supporting high-speed data transfer and reduced latency to meet the demanding needs of today's applications. These IPs not only provide seamless integration capabilities into your design but also ensure compliance with industry standards, which is crucial for interoperability in multi-vendor environments.
The embedded controllers within these IPs handle the logical functions necessary for device communication, while the PHY (physical layer) IPs manage the actual transmission and reception of data across physical media. Together, they enable efficient bridging between different communication protocols, making them critical components in a vast array of devices ranging from consumer electronics like smartphones and gaming consoles to industrial systems and automotive applications.
Our catalog also offers specialized solutions such as Multi-Protocol PHYs that support multiple standards within a single IP, providing flexibility and reducing the footprint for designs that require versatile connectivity options. By selecting the right Interface Controller & PHY IP from our catalog, developers can significantly enhance the functionality and overall performance of their products, leveraging the latest advancements in data interface technology. Explore our offerings and find the precise IP solutions needed to bring your innovative designs to life.
The KL730 is a third-generation AI chip that integrates advanced reconfigurable NPU architecture, delivering up to 8 TOPS of computing power. This cutting-edge technology enhances computational efficiency across a range of applications, including CNN and transformer networks, while minimizing DDR bandwidth requirements. The KL730 also boasts enhanced video processing capabilities, supporting 4K 60FPS outputs. With expertise spanning over a decade in ISP technology, the KL730 stands out with its noise reduction, wide dynamic range, fisheye correction, and low-light imaging performance. It caters to markets like intelligent security, autonomous vehicles, video conferencing, and industrial camera systems, among others.
Addressing the need for high-performance AI processing, the Metis AIPU PCIe AI Accelerator Card from Axelera AI offers an outstanding blend of speed, efficiency, and power. Designed to boost AI workloads significantly, this PCIe card leverages the prowess of the Metis AI Processing Unit (AIPU) to deliver unparalleled AI inference capabilities for enterprise and industrial applications. The card excels in handling complex AI models and large-scale data processing tasks, significantly enhancing the efficiency of computational tasks within various edge settings. The Metis AIPU embedded within the PCIe card delivers high TOPs (Tera Operations Per Second), allowing it to execute multiple AI tasks concurrently with remarkable speed and precision. This makes it exceptionally suitable for applications such as video analytics, autonomous driving simulations, and real-time data processing in industrial environments. The card's robust architecture reduces the load on general-purpose processors by offloading AI tasks, resulting in optimized system performance and lower energy consumption. With easy integration capabilities supported by the state-of-the-art Voyager SDK, the Metis AIPU PCIe AI Accelerator Card ensures seamless deployment of AI models across various platforms. The SDK facilitates efficient model optimization and tuning, supporting a wide range of neural network models and enhancing overall system capabilities. Enterprises leveraging this card can see significant improvements in their AI processing efficiency, leading to faster, smarter, and more efficient operations across different sectors.
The Mixel MIPI C-PHY IP (MXL-CPHY) is a high-frequency, low-power, low cost, physical layer. (Learn more about Mixel’s MIPI ecosystem at Mixel MIPI Central which gives you access to Mixel’s best of class MIPI ecosystem supply chain partners.) The C-PHY configuration consists of up to three lane modules and is based on 3-Phase symbol encoding technology, delivering 2.28 bits per symbol over three-wire trios and targeting a maximum rate of 2.5 Gsps, 5.7Gbps. The C-PHY is partitioned into a digital module – CIL (Control and Interface Logic) and a mixed-signal module. The PHY IP is provided as a combination of soft IP views (RTL, and STA Constraints) for the digital module, and hard IP views (GDSII/CDL/LEF/LIB) for the mixed-signal module. This unique offering of both soft and hard IP permits architectural design flexibility and seamless implementation in customer-specific design flow. The CIL module interfaces with the protocol layer and determines the global operation of the module. The interface between the PHY and the protocol is using the PHY-Protocol Interface (PPI). The mixed-signal module includes high-speed signaling mode for fast-data traffic and low-power signaling mode for control purposes. During normal operation, a lane switches between low-power and high-speed mode. Bidirectional lanes can also switch communication direction. The change of operating mode or direction requires enabling and disabling of certain electrical functions. These enable and disable events do not cause glitches on the lines that would result in a detection of incorrect signal levels. All mode and direction changes are smooth to always ensure a proper detection of the line signals. Mixel’s C-PHY is a complete PHY, silicon-proven at multiple foundries and multiple nodes. It is built to support the MIPI Camera Serial Interface (CSI) and Display Serial Interface (DSI).
The 1G to 224G SerDes technology by Alphawave Semi is a robust connectivity solution designed for high-speed data transmission. It integrates seamlessly into various applications including Ethernet, PCI Express, and die-to-die connections, enabling fast and reliable data transfer. This technology supports a broad spectrum of signaling schemes such as PAM2, PAM4, PAM6, and PAM8, ensuring compatibility with over 30 different industry protocols and standards. As the demand for high-performance data centers and networking solutions increases, the 1G to 224G SerDes proves indispensable, delivering the speed and bandwidth required by modern systems. Alphawave Semi's SerDes supports data rates from as low as 1Gbps to a staggering 224Gbps, making it highly versatile for a multitude of configurations. Its application extends beyond traditional data centers, also covering areas like AI and 5G communication networks where latency and data throughput are critical. This flexibility is further enhanced by its low power consumption, which is essential for efficient data processing in today's power-conscious technological environment. Incorporating the 1G to 224G SerDes into your chip designs guarantees reduced latency and increased data throughput, which is vital for applications that demand real-time data processing. By ensuring high data integrity and reducing signal degradation, this SerDes solution aids in maintaining steadfast connectivity, even under heavy data loads, promising a future-ready component in the evolving tech landscape.
The Mixel MIPI C/D-PHY combo IP (MXL-CPHY-DPHY) is a high-frequency low-power, low cost, physical layer compliant with the MIPI® Alliance Standard for C-PHY and D-PHY. (Learn more about Mixel’s MIPI ecosystem at Mixel MIPI Central which gives you access to Mixel’s best of class MIPI ecosystem supply chain partners.) The PHY can be configured as a MIPI Master or MIPI Slave, supporting camera interface CSI-2 v1.2 or display interface DSI v1.3 applications in the D-PHY mode. It also supports camera interface CSI-2 v1.3 and display interface DSI-2 v1.0 applications in the C-PHY mode. The high-speed signals have a low voltage swing, while low-power signals have large swing. High-Speed functions are used for high-speed data traffic while low-power functions are mostly used for control. The C-PHY is based on 3-Phase symbol encoding technology, delivering 2.28 bits per symbol over three-wire trios, operating with a symbol rate range of 80 to 4500 Msps per lane, which is the equivalent of about 182.8 to 10260 Mbps per lane. The D-PHY supports a bit rate range of 80 to 1500 Mbps per Lane without deskew calibration, and up to 4500 Mbps with deskew calibration. The low-power mode and escape mode are the same in both the D-PHY and C-PHY modes. To minimize EMI, the drivers for low-power mode are slew-rate controlled and current limited. The data rate in low-power mode is 10 Mbps. For a fixed clock frequency, the available data capacity of a PHY configuration can be increased by using more lanes. Effective data throughput can be reduced by employing burst mode communication. Mixel’s C-PHY/D-PHY combo is a complete PHY, silicon-proven at multiple foundries and multiple nodes. The C/D-PHY is fully integrated and has analog circuitry, digital, and synthesizable logic.
The GL3590-S is a USB 3.2 Gen 2 hub controller that features integrated support for USB Type-C connections and multiple upstream ports. This product is engineered to enhance connectivity by providing efficient data transfer speeds up to 10 Gbps, facilitating rapid communication across various peripherals. It supports advanced power management capabilities, allowing devices to negotiate power delivery efficiently. Additionally, the GL3590-S incorporates robust security protocols to ensure data integrity during transmission. This controller is ideal for applications needing versatile USB connectivity with high-speed data transfers. It can be utilized in computing setups, where the demand for reliable and fast data exchanges is paramount. Moreover, its compatibility with USB Type-C enables seamless integration with a wide array of modern devices, enhancing its applicability in contemporary technological environments. In terms of technical advancements, the GL3590-S simplifies the integration process by supporting multiple upstream ports, making it easier for developers to utilize its capabilities in complex designs. Furthermore, the energy-efficient design reduces power consumption, making it a sustainable choice for manufacturers looking to include environmentally friendly components in their products. Thanks to its advanced features, the GL3590-S is an attractive option for any stakeholder in need of high-speed data management and efficient power usage. Its adaptability and performance make it a cornerstone in the development of innovative USB solutions.
Primesoc's PCIE GEn7 IP is dual mode controller , supporting upto 128Gbps per lane data rate , which can work as root complex or as an endpoint. This is a soft IP which can support serdes and non serdes architectures and PIPE interface of 64bit and lanes configurable from 1/2/4/8/16.
iWave Global introduces the ARINC 818 Switch, a pivotal component in the management and routing of video data within avionics systems. Designed for applications that require efficient video data distribution and management, the switch is optimized for performance in environments with stringent data handling requirements. The switch's architecture supports a high level of bandwidth, allowing for the smooth routing of multiple video streams in real-time. Its design includes advanced features that ensure low-latency, error-free data transfer, integral to maintaining the integrity and reliability of video data in critical applications. Featuring robust interoperability characteristics, the ARINC 818 Switch easily integrates into existing systems, facilitating modular expansion and adaptability to new technological standards. It is indispensable for any aerospace project that involves complex video data management, providing a stable platform for video data routing and switching.
The Yitian 710 Processor is a landmark server chip released by T-Head Semiconductor, representing a breakthrough in high-performance computing. This chip is designed with cutting-edge architecture that utilizes advanced Armv9 structure, accommodating a range of demanding applications. Engineered by T-Head's dedicated research team, Yitian 710 integrates high efficiency and bandwidth properties into a unique 2.5D package, housing two dies and a staggering 60 billion transistors. The Yitian 710 encompasses 128 Armv9 high-performance cores, each equipped with 64KB L1 instruction cache, 64KB L1 data cache, and 1MB L2 cache, further amplified by a collective on-chip system cache of 128MB. These configurations enable optimal data processing and retrieval speeds, making it suitable for data-intensive tasks. Furthermore, the memory subsystem stands out with its 8-channel DDR5 support, reaching peak bandwidths of 281GB/s. In terms of connectivity, the Yitian 710's I/O system includes 96 PCIe 5.0 channels with a bidirectional theoretical total bandwidth of 768GB/s, streamlining high-speed data transfer critical for server operations. Its architecture is not only poised to meet the current demands of data centers and cloud services but also adaptable for future advancements in AI inference and multimedia processing tasks.
The AI Camera Module from Altek is a versatile, high-performance component designed to meet the increasing demand for smart vision solutions. This module features a rich integration of imaging lens design and combines both hardware and software capacities to create a seamless operational experience. Its design is reinforced by Altek's deep collaboration with leading global brands, ensuring a top-tier product capable of handling diverse market requirements. Equipped to cater to AI and IoT interplays, the module delivers outstanding capabilities that align with the expectations for high-resolution imaging, making it suitable for edge computing applications. The AI Camera Module ensures that end-user diversity is meaningfully addressed, offering customization in device functionality which supports advanced processing requirements such as 2K and 4K video quality. This module showcases Altek's prowess in providing comprehensive, all-in-one camera solutions which leverage sophisticated imaging and rapid processing to handle challenging conditions and demands. The AI Camera's technical blueprint supports complex AI algorithms, enhancing not just image quality but also the device's interactive capacity through facial recognition and image tracking technology.
The Universal Chiplet Interconnect Express (UCIe) by EXTOLL is a cutting-edge interconnect framework designed to revolutionize chip-to-chip communication within heterogeneous systems. This product exemplifies the shift towards chiplet architecture, a modular approach enabling enhanced performance and flexibility in semiconductor designs. UCIe offers an open and customizable platform that supports a wide range of technology nodes, particularly excelling in the 12nm to 28nm range. This adaptability ensures it can meet the diverse needs of modern semiconductor applications, providing a bridge that enhances integration across various chiplet components. Such capabilities make it ideal for applications requiring high bandwidth and low latency. The design of UCIe focuses on minimizing power consumption while maximizing data throughput, aligning with EXTOLL’s objective of delivering eco-efficient technology. It empowers manufacturers to forge robust connections between chiplets, allowing optimized performance and scalability in data-intensive environments like data centers and advanced consumer electronics.
KPIT Technologies is a leader in providing AUTOSAR and Adaptive AUTOSAR solutions, facilitating the development of software architectures that standardize interoperability across the automotive industry. Designed to support the increasing complexity of modern vehicle electronic infrastructures, KPIT's solutions enable seamless integration of software components, promoting scalability and reliability. AUTOSAR (Automotive Open System Architecture) is essential for developing modular and flexible software systems, allowing automakers to focus on innovative application features while ensuring software compatibility and integration ease. KPIT offers a comprehensive range of services, from basic software to complex component development, tailored to fit specific industry needs. With Adaptive AUTOSAR, KPIT accelerates the transition to software-defined vehicles by providing flexible, scalable, and upgradable software solutions that cater to the dynamic requirements of connected and autonomous vehicles. By aligning with industry standards, KPIT’s AUTOSAR solutions ensure cost efficiency, reduce development time, and enhance the overall quality and functionality of automotive software systems.
The Mixel MIPI D-PHY IP (MXL-DPHY) is a high-frequency low-power, low cost, source-synchronous, physical layer compliant with the MIPI® Alliance Standard for D-PHY. (Learn more about Mixel’s MIPI ecosystem at Mixel MIPI Central which gives you access to Mixel’s best of class MIPI ecosystem supply chain partners.) Although primarily used for connecting cameras and display devices to a core processor, this MIPI PHY can also be used for many other applications. It is used in a master-slave configuration, where high-speed signals have a low voltage swing, and low-power signals have large swing. High-speed functions are used for high-speed data traffic while low-power functions are mostly used for control. The D-PHY is partitioned into a Digital Module – CIL (Control and Interface Logic) and a Mixed Signal Module. It is provided as a combination of Soft IP views (RTL, and STA Constraints) for Digital Module, and Hard IP views (GDSII/CDL/LEF/LIB) for the Mixed Signal Module. This unique offering of Soft and Hard IP permits architectural design flexibility and seamless implementation in customer-specific design flow. The CIL module interfaces with the protocol layer and determines the global operation of the lane module. The interface between the D-PHY and the protocol is called the PHY-Protocol Interface (PPI). During normal operation, the data lane switches between low-power mode and high-speed mode. Bidirectional lanes can also switch communication direction. The change of operating mode or direction requires enabling and disabling certain electrical functions. These enable and disable events do not cause glitches on the lines that would otherwise result in detections of incorrect signal levels. Therefore, all mode and direction changes occur smoothly, ensuring proper detection of the line signals. Mixel’s D-PHY is a complete PHY, silicon-proven at multiple foundries and multiple nodes. This MIPI PHY is fully integrated and has analog circuitry, digital, and synthesizable logic. Our D-PHY is built to support the MIPI Camera Serial Interface (CSI) and Display Serial Interface (DSI) using the PHY Protocol Interface (PPI). Mixel has provided this IP in many different configurations to accommodate different applications. The Universal Lane configuration can be used to support any allowed use-case, while other configurations are optimized for many different use cases such as Transmit only, Receive only, DSI, CSI, TX+ and RX+. Both TX+ and RX+ configurations support full-speed loopback operation without the extra area associated with a universal lane configuration.
This LVDS IP offers seamless transmission solutions for high-speed data in digital systems. Its design allows for minimized electromagnetic interference while maintaining signal integrity. Often used in video and graphic applications, the LVDS IP ensures efficient data handling, making it a critical component in complex electronic interfaces.
The Aries fgOTN processor family is engineered according to the ITU-T G.709.20 fgOTN standard. This line of processors handles a variety of signals, including E1/T1, FE/GE, and STM1/STM4, effectively monitoring and managing alarms and performance metrics. Aries processors excel at fine-grain traffic aggregation, efficiently channeling fgODUflex traffic across OTN lines to support Ethernet, SDH, PDH client services. Their capacity to map signals to fgODUflex containers, which are then multiplexed into higher order OTN signals, demonstrates their versatility and efficiency. By allowing cascaded configurations with other Aries devices or Apodis processors, Aries products optimize traffic routes through OTN infrastructures, positioning them as essential components in optical networking and next-generation access scenarios.
Advanced Peripheral Bus (APB) is one of the Advanced Microcontroller Bus Architecture (AMBA) family protocols. It is a low-cost interface that is designed for low power consumption and interface simplicity. Unlike AHB, it is a non-pipelined protocol for connecting low-bandwidth peripherals. Mostly used to link external peripherals to the SOC. Every APB transfer requires at least two clock cycles (SETUP Cycle and ACCESS Cycle) to finish. The APB interface is designed for accessing the programmable control registers of peripheral devices. The APB protocol has two independent data buses, one for read data and one for write data. The buses can be 8, 16, or 32 bits wide. The read and write data buses must have the same width. Data transfers cannot occur concurrently because the read data and write data buses do not have their own individual handshake signals.
Silicon Creations' SerDes Interfaces are crafted to handle high-speed data transmission challenges over varied processes, ranging from 12nm to 180nm. Addressing multiple protocols such as CPRI, PCIe, and SATA, these interfaces demonstrate flexibility by supporting data transmission speeds from 100 Mbps to beyond 32 Gbps. The architecture incorporates a host of advanced features including adaptive equalization techniques and programmable de-serialization widths, making it stand out in terms of performance and signal integrity even under challenging conditions. With ultra-low latency PMAs, they sustain excellent operational speed and efficiency, imperative for sophisticated communication applications. Moreover, Silicon Creations partners with leading entities to provide comprehensive solutions, including complete PCIe PHY integrations. This synergy ensures that SerDes Interfaces are fully optimized for operational excellence, delivering stable and reliable communication signals. With an emphasis on low power and minimized area requirements, they cater to burgeoning industry needs for power-efficient and space-conservative designs.
Chimera GPNPU is engineered to revolutionize AI/ML computational capabilities on single-core architectures. It efficiently handles matrix, vector, and scalar code, unifying AI inference and traditional C++ processing under one roof. By alleviating the need for partitioning AI workloads between different processors, it streamlines software development and drastically speeds up AI model adaptation and integration. Ideal for SoC designs, the Chimera GPNPU champions an architecture that is both versatile and powerful, handling complex parallel workloads with a single unified binary. This configuration not only boosts software developer productivity but also ensures an enduring flexibility capable of accommodating novel AI model architectures on the horizon. The architectural fabric of the Chimera GPNPU seamlessly blends the high matrix performance of NPUs with C++ programmability found in traditional processors. This core is delivered in a synthesizable RTL form, with scalability options ranging from a single-core to multi-cluster designs to meet various performance benchmarks. As a testament to its adaptability, the Chimera GPNPU can run any AI/ML graph from numerous high-demand application areas such as automotive, mobile, and home digital appliances. Developers seeking optimization in inference performance will find the Chimera GPNPU a pivotal tool in maintaining cutting-edge product offerings. With its focus on simplifying hardware design, optimizing power consumption, and enhancing programmer ease, this processor ensures a sustainable and efficient path for future AI/ML developments.
Ethernet MAC 10M/100M/1G/2.5G IP is a solution that enables the host to communicate data using the IEEE 802.3 standard for 10M, 100M, 1G, 2.5G speeds and is suited for use in networking equipment such as switches and routers. The Client-side interface for the IP is AXI-S and the Ethernet MAC IP comes with GMII, RGMII or MII interfaces on the PHY side. The Ethernet MAC 10M/100M/1G/2.5G IP features a compact and low latency solution, it is highly configurable and can optionally include IEEE 1588 Timestamping Unit (TSU). The Silicon agnostic Ethernet MAC IP, suitable for ASICs and FPGAs, is prepared for easy integration with Ethernet PCS 10M/ 100M/1G/2.5G IP from Comcores.
xcore.ai is XMOS Semiconductor's innovative programmable chip designed for advanced AI, DSP, and I/O applications. It enables developers to create highly efficient systems without the complexity typical of multi-chip solutions, offering capabilities that integrate AI inference, DSP tasks, and I/O control seamlessly. The chip architecture boasts parallel processing and ultra-low latency, making it ideal for demanding tasks in robotics, automotive systems, and smart consumer devices. It provides the toolset to deploy complex algorithms efficiently while maintaining robust real-time performance. With xcore.ai, system designers can leverage a flexible platform that supports the rapid prototyping and development of intelligent applications. Its performance allows for seamless execution of tasks such as voice recognition and processing, industrial automation, and sensor data integration. The adaptable nature of xcore.ai makes it a versatile solution for managing various inputs and outputs simultaneously, while maintaining high levels of precision and reliability. In automotive and industrial applications, xcore.ai supports real-time control and monitoring tasks, contributing to smarter, safer systems. For consumer electronics, it enhances user experience by enabling responsive voice interfaces and high-definition audio processing. The chip's architecture reduces the need for exterior components, thus simplifying design and reducing overall costs, paving the way for innovative solutions where technology meets efficiency and scalability.
The Metis AIPU M.2 Accelerator Module by Axelera AI is a compact and powerful solution designed for AI inference at the edge. This module delivers remarkable performance, comparable to that of a PCIe card, all while fitting into the streamlined M.2 form factor. Ideal for demanding AI applications that require substantial computational power, the module enhances processing efficiency while minimizing power usage. With its robust infrastructure, it is geared toward integrating into applications that demand high throughput and low latency, making it a perfect fit for intelligent vision applications and real-time analytics. The AIPU, or Artificial Intelligence Processing Unit, at the core of this module provides industry-leading performance by offloading AI workloads from traditional CPU or GPU setups, allowing for dedicated AI computation that is faster and more energy-efficient. This not only boosts the capabilities of the host systems but also drastically reduces the overall energy consumption. The module supports a wide range of AI applications, from facial recognition and security systems to advanced industrial automation processes. By utilizing Axelera AI’s innovative software solutions, such as the Voyager SDK, the Metis AIPU M.2 Accelerator Module enables seamless integration and full utilization of AI models and applications. The SDK offers enhancements like compatibility with various industry tools and frameworks, thus ensuring a smooth deployment process and quick time-to-market for advanced AI systems. This product represents Axelera AI’s commitment to revolutionizing edge computing with streamlined, effective AI acceleration solutions.
AMBA AHB is a bus interface designed for high-performance synthesizable applications. It specifies the interface between components such as initiator , interconnects, and targets. AMBA AHB incorporates the features needed for high-performance, high clock frequency systems. The most common AHB targets are internal memory devices, external memory interfaces, and high-bandwidth peripherals.
The Mixel MIPI M-PHY (MXL-MPHY) is a high-frequency low-power, Physical Layer IP that supports the MIPI® Alliance Standard for M-PHY. (Learn more about Mixel’s MIPI ecosystem at Mixel MIPI Central which gives you access to Mixel’s best of class MIPI ecosystem supply chain partners.) The IP can be used as a physical layer for many applications, connecting flash memory-based storage, cameras and RF subsystems, and for providing chip-to-chip inter-processor communications (IPC). It supports MIPI UniPro and JEDEC Universal Flash Storage (UFS) standard. By using efficient BURST mode operation with scalable speeds, significant power savings can be obtained. Selection of signal slew rate and amplitude allows reduction of EMI/RFI, while maintaining low bit error rates.
RaiderChip's GenAI v1 is a pioneering hardware-based generative AI accelerator, designed to perform local inference at the Edge. This technology integrates optimally with on-premises servers and embedded devices, offering substantial benefits in privacy, performance, and energy efficiency over traditional hybrid AI solutions. The design of the GenAI v1 NPU streamlines the process of executing large language models by embedding them directly onto the hardware, eliminating the need for external components like CPUs or internet connections. With its ability to support complex models such as the Llama 3.2 with 4-bit quantization on LPDDR4 memory, the GenAI v1 achieves unprecedented efficiency in AI token processing, coupled with energy savings and reduced latency. What sets GenAI v1 apart is its scalability and cost-effectiveness, significantly outperforming competitive solutions such as Intel Gaudi 2, Nvidia's cloud GPUs, and Google's cloud TPUs in terms of memory efficiency. This solution maximizes the number of tokens generated per unit of memory bandwidth, thus addressing one of the primary limitations in generative AI workflow. Furthermore, the adept memory usage of GenAI v1 reduces the dependency on costly memory types like HBM, opening the door to more affordable alternatives without diminishing processing capabilities. With a target-agnostic approach, RaiderChip ensures the GenAI v1 can be adapted to various FPGAs and ASICs, offering configuration flexibility that allows users to balance performance with hardware costs. Its compatibility with a wide range of transformers-based models, including proprietary modifications, ensures GenAI v1's robust placement across sectors requiring high-speed processing, like finance, medical diagnostics, and autonomous systems. RaiderChip's innovation with GenAI v1 focuses on supporting both vanilla and quantized AI models, ensuring high computation speeds necessary for real-time applications without compromising accuracy. This capability underpins their strategic vision of enabling versatile and sustainable AI solutions across industries. By prioritizing integration ease and operational independence, RaiderChip provides a tangible edge in applying generative AI effectively and widely.
The AHB-Lite APB4 Bridge serves as a crucial interconnect that facilitates communication between the AMBA 3 AHB-Lite and AMBA APB bus protocols. As a parameterized soft IP, it offers flexibility and adaptability in managing system interconnections, bridging the gap between high-speed and low-speed peripherals with efficiency. The bridge's architecture is designed to maintain data integrity while transferring information across different protocol tiers. This bridge supports the implementation of a seamless transition for data exchanges, ensuring data packets are transmitted with minimal latency. It is ideal for systems that require stable connectivity across multiple peripheral interfaces, delivering a cohesive platform for system designers to enhance operational uniformity. By enabling efficient bus conversion, it supports broader system architectures, contributing to the overall efficiency of embedded designs. With its open-architecture design, the AHB-Lite APB4 Bridge caters to a wide range of applications, providing necessary adaptability to meet the unique demands of each project. Its robust design ensures that it can accommodate the complex architectures of modern embedded systems, enhancing both performance and reliability.
The GenAI v1-Q from RaiderChip brings forth a specialized focus on quantized AI operations, reducing memory requirements significantly while maintaining impressive precision and speed. This innovative accelerator is engineered to execute large language models in real-time, utilizing advanced quantization techniques such as Q4_K and Q5_K, thereby enhancing AI inference efficiency especially in memory-constrained environments. By offering a 276% boost in processing speed alongside a 75% reduction in memory footprint, GenAI v1-Q empowers developers to integrate advanced AI capabilities into smaller, less powerful devices without sacrificing operational quality. This makes it particularly advantageous for applications demanding swift response times and low latency, including real-time translation, autonomous navigation, and responsive customer interactions. The GenAI v1-Q diverges from conventional AI solutions by functioning independently, free from external network or cloud auxiliaries. Its design harmonizes superior computational performance with scalability, allowing seamless adaptation across variegated hardware platforms including FPGAs and ASIC implementations. This flexibility is crucial for tailoring performance parameters like model scale, inference velocity, and power consumption to meet exacting user specifications effectively. RaiderChip's GenAI v1-Q addresses crucial AI industry needs with its ability to manage multiple transformer-based models and confidential data securely on-premises. This opens doors for its application in sensitive areas such as defense, healthcare, and financial services, where confidentiality and rapid processing are paramount. With GenAI v1-Q, RaiderChip underscores its commitment to advancing AI solutions that are both environmentally sustainable and economically viable.
The ARINC 818 Streaming IP Core is tailored to convert pixel bus data into an ARINC 818 formatted Fibre Channel stream and vice versa. It offers real-time streaming capabilities, which are essential for aerospace systems requiring precise format conversion. This dual-functionality enhances its utility in scenarios where adaptable data interchange is necessary for effective visual data communication. With its intricate design, this core is highly efficient in supporting video transmission protocols, providing robustness for streaming data between digital formats. Ensuring seamless data integration helps mitigate potential data loss or delays, critical in flight operations and real-time video processing. Thus, it stands as a valuable component in avionics communication networks where reliable data streams are paramount.
The KL630 is a pioneering AI chipset featuring Kneron's latest NPU architecture, which is the first to support Int4 precision and transformer networks. This cutting-edge design ensures exceptional compute efficiency with minimal energy consumption, making it ideal for a wide array of applications. With an ARM Cortex A5 CPU at its core, the KL630 excels in computation while maintaining low energy expenditure. This SOC is designed to handle both high and low light conditions optimally and is perfectly suited for use in diverse edge AI devices, from security systems to expansive city and automotive networks.
Time-Triggered Ethernet (TTEthernet) is a pioneering development by TTTech that offers deterministic Ethernet capabilities for safety-critical applications. This technology supports real-time communication between network nodes while maintaining the standard Ethernet infrastructure. TTEthernet enables reliable data delivery, with built-in mechanisms for fault tolerance that are vital for spaces like aviation, industrial automation, and space missions. One of the key aspects of TTEthernet is its ability to provide triple-redundant communication, ensuring network reliability even in the case of multiple failures. Licensed for significant projects such as NASA's Orion spacecraft, TTEthernet demonstrates its efficacy in environments that require dual fault-tolerance. As part of the ECSS engineering standard, the protocol supports human spaceflight standards and integrates seamlessly into space-based and terrestrial networks. The application of TTEthernet spans across multiple domains due to its robust nature and compliance with industry standards. It is particularly esteemed in markets that emphasize the importance of precise time synchronization and high availability. By using TTEthernet, companies can secure communications in networks without compromising on the speed and flexibility inherent to Ethernet-based systems.
With a focus on maintaining signal integrity in high-speed interfaces, the PCIe Retimer extends the reach of PCI Express connections while preserving data quality. Essential for long signal paths, it works by regenerating signals to boost performance and provide reliable connections across distances. The retimer is particularly effective in environments with substantial electromagnetic interference, ensuring data transmission remains error-free and efficient across extended cable runs. By including line equalization and using advanced clock recovery techniques, the PCIe Retimer strengthens signal quality, allowing for greater system performance and reliability in a wide array of computing applications.
Great River Technology offers the ARINC 818 Product Suite, a comprehensive collection of tools and products designed to cover the full spectrum of ARINC 818 applications. This suite is pivotal for engineers and designers who are focused on the aviation sector, providing solutions necessary for the creation, testing, and deployment of high-speed digital interfaces in avionics. The suite supports design and implementation phases by offering robust support tools tailored for ARINC 818 development, including detailed implementers' guides and simulation resources. What's unique about this suite is its ability to facilitate process integrations for ARINC 818 standards across various platforms, making it adaptable for differing needs in aviation systems. The integration tools provided ensure that systems can efficiently manage data and video transmissions, providing clarity, speed, and reliability, all essential factors in mission-critical environments. Great River Technology’s ARINC 818 Product Suite is engineered to ensure seamless interoperability, offering support from initial project development through to practical operation, thus enabling avionic systems to function optimally in both standard and specialized conditions.
The Maverick-2 Intelligent Compute Accelerator represents the pinnacle of Next Silicon's innovative approach to computational resources. This state-of-the-art accelerator leverages the Intelligent Compute Architecture for software-defined adaptability, enabling it to autonomously tailor its real-time operations across various HPC and AI workloads. By optimizing performance using insights gained through real-time telemetry, Maverick-2 ensures superior computational efficiency and reduced power consumption, making it an ideal choice for demanding computational environments.\n\nMaverick-2 brings transformative performance enhancements to large-scale scientific research and data-heavy industries by dispensing with the need for codebase modifications or specialized software stacks. It supports a wide range of familiar development tools and frameworks, such as C/C++, FORTRAN, and Kokkos, simplifying the integration process for developers and reducing time-to-discovery significantly.\n\nEngineered with advanced features like high bandwidth memory (HBM3E) and built on TSMC's 5nm process technology, this accelerator provides not only unmatched adaptability but also an energy-efficient, eco-friendly computing solution. Whether embedded in single-die PCIe cards or dual-die OCP Accelerator Modules, the Maverick-2 is positioned as a future-proof solution capable of evolving with technological advancements in AI and HPC.
The SERDES technology by Analog Bits represents a pinnacle in high-speed data serialization and deserialization, fundamental for maximizing data throughput in sophisticated electronics. This IP is engineered to accommodate extensive data volumes across interconnected systems, elevating data transfer rates significantly. It supports various communication standards, providing seamless integration across multiple vehicular and networking applications. Analog Bits' SERDES stands out due to its robustness in maintaining signal clarity and reducing latency during data transmission, even across significant distances. It is a critical component in applications that demand reliable, high-speed data movement, such as data centers, telecommunications, and automotive systems. Its design flexibility allows it to be a match for varied serialization protocols, an essential aspect of modern digital communications. The SERDES technology also enhances thermal performance and power efficiency, reducing the overall energy footprint of systems engaged in continual high-speed operations. As such, it becomes a cornerstone for innovations looking to up the ante on data transmission capabilities while maintaining environmentally friendly operations.
The PDM-to-PCM Converter from Archband Labs leads in transforming pulse density modulation signals into pulse code modulation signals. This converter is essential in applications where high fidelity of audio signal processing is vital, including digital audio systems and communication devices. Archband’s solution ensures accurate conversion, preserving the integrity and clarity of the original audio. This converter is crafted to seamlessly integrate with a wide array of systems, offering flexibility and ease-of-use in various configurations. Its robust design supports a wide range of input frequencies, making it adaptable to different signal environments. The PDM-to-PCM Converter also excels in minimizing latency and reducing overhead processing times. It’s engineered for environments where precision and sound quality are paramount, ensuring that audio signals remain crisp and undistorted during conversion processes.
PCIE is a layered protocol high speed interconnect interface supporting speeds up to 128Gbps and multi lanes and links. The layers speci_ied in PCIE speci_ication Transport, Datalink, Physical layers (digital packet) are implemented in PRIMEXPRESS IP along with PIPE interface logic connecting to PHY and AXI Bridging logic to connect to applications. Features: • Supports PCIE Gen 7 Spec. • Supports Pipe 6.X Spec. • PCIE Gen 7.0 Core supports Flit and non – Flit Mode. • Supports X16, X8, X4, X2, X1 Lane Configura􀆟on. • AXI MM and Streaming supported. • Supports Gen 1, Gen 2, Gen 3, Gen 4, Gen 5, Gen 6, Gen 7 modes. • Data rate support of 2.5 Gbps, 5 Gbps, 8 Gbps, 16 Gbps, 32 Gbps, 64 Gbps, 128 Gbps. • PAM support when operating at 64Gbps/ 128Gbps. • 8b/10b,128b/130b,1b/1b encoding , decoding support. • Supports serdes and non – serdes architecture. • Op􀆟onal DMA support as plugin module. • Support for alternate nego􀆟a􀆟on protocol. • Lane polarity thru register control. • Lane deskew supported. • Support for L1 states. • L0P Supported. • SKP OS add/removal. • SRIS mode supported. • No equalization support thru configura􀆟on. • Deemphasis negotiation support at 5GT/s. • EI inferences in all modes. • PTM, OBFF, MSI, MSIX, Power management and all message format supports.
Overview: The MIPI CSI-2 (Camera Serial Interface) defines an interface between a peripheral device (camera) and host processor (application engine) for mobile applications. It offers the mobile industry a standard, robust, scalable, low-power, high-speed, and cost-effective interface that supports a wide range of imaging solutions for mobile devices. Key Features:  Compliance with MIPI-CSI-2 version 3.0  Compliance with C-PHY 2.0 for MIPI CSI-2 Version 3.0  Compliance with D-PHY 2.5 for MIPI CSI-2 Version 3.0  Compatibility with I2C and I3C (SDR, DDR) for CCI interface  Support for C-PHY 2.0, D-PHY 2.5, A-PHY, M-PHY with configurable PHY layer  Processor Interfaces: AHB Lite/APB/AXI for configuration  Lane Merging Function for consolidating packet data in CSI-2 Receiver  De-skew detection in D-PHY and sync word detection in C-PHY  Pixel Formats Supported: YUV, RGB, and RAW data  Virtual Channels: 16 for D-PHY, 32 for C-PHY  Error detection, interleaving, scrambling, and descrambling support  Byte to pixel conversion in LLP layer Applications:  Imaging  Surveillance  Gaming  Sensor devices  Internet of Things (IoT)  Wearable devices  Virtual Reality  Augmented Reality  Automotive Systems
The NuLink Die-to-Die PHY for Standard Packaging by Eliyan is engineered to facilitate superior die-to-die interconnectivity on standard organic/laminate package substrates. This innovative PHY IP supports key industry standards such as UCIe and BoW, and includes proprietary technologies like UMI and SBD. The NuLink PHY delivers leading performance and power efficiency, comparable to advanced packaging technologies, but at a fraction of the cost. It features configurations with up to 64 data lanes, supporting a data rate per lane of up to 64Gbps, making it ideal for applications demanding high bandwidth and low latency. The implementation enhances system design while reducing the necessary area and thermal load, which significantly eases integration into existing hardware ecosystems.
aiSim 5 stands as a cutting-edge simulation tool specifically crafted for the automotive sector, with a strong focus on validating ADAS and autonomous driving solutions. It distinguishes itself with an AI-powered digital twin creation capability, offering a meticulously optimized sensor simulation environment that guarantees reproducibility and determinism. The adaptable architecture of aiSim allows seamless integration with existing industry toolchains, significantly minimizing the need for costly real-world testing.\n\nOne of the key features of aiSim is its capability to simulate various challenging weather conditions, enhancing testing accuracy across diverse environments. This includes scenarios like snowstorms, heavy fog, and rain, with sensors simulated based on physics, offering changes in conditions in real-time. Its certification with ISO 26262 ASIL-D attests to its automotive-grade quality and reliability, providing a new standard for testing high-fidelity sensor data in varied operational design domains.\n\nThe flexibility of aiSim is further highlighted through its comprehensive SDKs and APIs, which facilitate smooth integration into various systems under test. Additionally, users can leverage its extensive 3D asset library to establish detailed, realistic testing environments. AI-based rendering technologies underpin aiSim's data simulation, achieving both high efficiency and accuracy, thereby enabling rapid and effective validation of advanced driver assistance and autonomous driving systems.
PCIE is a layered protocol high speed interconnect interface supporting speeds up to 128Gbps and multi lanes and links. The layers speci_ied in PCIE speci_ication Transport, Datalink, Physical layers (digital packet) are implemented in PRIMEXPRESS IP along with PIPE interface logic connecting to PHY and AXI Bridging logic to connect to applications. Features: • Supports PCIE Gen 7 draft Spec. • Supports Pipe 6.X Spec. • PCIE Gen 7.0 Core supports Flit and non – Flit Mode. • Supports X16, X8, X4, X2, X1 Lane Configuration. • AXI MM and Streaming supported. • Supports Gen 1, Gen 2, Gen 3, Gen 4, Gen 5, Gen 6, Gen 7 modes. • Data rate support of 2.5 Gbps, 5 Gbps, 8 Gbps, 16 Gbps, 32 Gbps, 64 Gbps, 128 Gbps. • PAM support when operating at 64Gbps/ 128Gbps. • 8b/10b,128b/130b,1b/1b encoding , decoding support. • Supports serdes and non – serdes architecture. • Optional DMA support as plugin module. • Support for alternate negotiation protocol. • Lane polarity thru register control. • Lane deskew supported. • Support for L1 states. • L0P Supported. • SKP OS add/removal. • SRIS mode supported. • No equalization support thru configuration. • Deemphasis negotiation support at 5GT/s. • EI inferences in all modes. • PTM, OBFF, MSI, MSIX, Power management and all message format supports.
The EZiD211, also known as Oxford-2, is a leading-edge demodulator and modulator developed by EASii IC to facilitate advanced satellite communications. It embodies a sophisticated DVB-S2X wideband tuner capable of supporting LEO, MEO, and GEO satellites, integrating proprietary features like Beam Hopping, VLSNR, and Super Frame applications. With EZiD211 at the helm, satellite communications undergo a transformation in efficiency and capacity, addressing both current and future demands for fixed data infrastructures, mobility, IoT, and M2M applications. Its technological forefront facilitates seamless operations in varied European space programs, validated by its full production readiness. EZiD211's design offers a unique capability to manage complex satellite links, enhance performance, and ensure robust and reliable data transmission. EASii IC provides comprehensive support through evaluation boards and samples, allowing smooth integration and testing to meet evolving satellite communication standards.
Digital Blocks' AXI4 DMA Controller is a robust solution designed for transferring data efficiently between systems over the AXI4 interface. Supporting up to 16 independent channels, it excels in high data throughput both for small and large data sets. Its capabilities are extended with advanced DMA features, allowing custom configurations to minimize silicon usage and licensing costs. Precise control over DMA operations is facilitated through its customizable settings, supporting a flexible range of interface buses and addressing modes.
KPIT Technologies' Connected Vehicle Solutions provide a comprehensive suite of capabilities designed to enhance the connectivity, security, and functionality of modern vehicles. These solutions encompass a wide range of connectivity features, including vehicle-to-everything (V2X) communication systems, in-vehicle network integration, and telematics platforms. By leveraging cloud technology and edge analytics, KPIT ensures seamless data exchange and processing, which is essential for real-time decision-making and enhanced vehicle utility. The solutions are crafted to support next-generation vehicles' multifaceted digital interfaces, from infotainment systems to advanced driver communication platforms. KPIT's connected vehicle offerings are engineered to meet stringent automotive-grade requirements, guaranteeing high reliability, security, and interoperability. This positions KPIT as a pivotal player in the evolution of connected vehicle ecosystems, facilitating the industry’s move towards smarter and more efficient vehicular technologies. Through strategic partnerships with automakers, KPIT continually refines its connected vehicle platforms to address the critical privacy and security challenges posed by increasing vehicle connectivity. With a focus on end-to-end connectivity, KPIT empowers the automotive sector to harness the full potential of networked vehicles, ensuring drivers and passengers enjoy a more connected journey.
eSi-Connect offers an extensive suite of AMBA-compliant peripheral IPs designed to streamline SoC integration. This suite encompasses versatile memory controllers, standard off-chip interface support, and essential control functions. Its configurability and compatibility with low-level software drivers make it suitable for real-time deployment in complex system architectures, promoting reliable connectivity across various applications.
The Ncore Cache Coherent Interconnect is designed to tackle the complexities inherent in multicore SoC environments. By maintaining coherence across heterogeneous cores, it enables efficient data sharing and optimizes cache use. This in turn enhances the throughput of the system, ensuring reliable performance with reduced latency. The architecture supports a wide range of cores, making it a versatile option for many applications in high-performance computing. With Ncore, designers can address the challenges of maintaining data consistency across different processor cores without incurring significant power or performance penalties. The interconnect's capability to handle multicore scenarios means it is perfectly suited for advanced computing solutions where data integrity and speed are paramount. Additionally, its configuration options allow customization to meet specific project needs, maintaining flexibility in design applications. Its efficiency in multi-threading environments, coupled with robust data handling, marks it as a crucial component in designing state-of-the-art SoCs. By supporting high data throughput, Ncore keeps pace with the demands of modern processing needs, ensuring seamless integration and operation across a variety of sectors.
This product offers an extensive range of high-speed interface IP solutions developed using an array of process technologies from 28nm to 90nm nodes. It supports various technology needs and provides tailored services for IP customization and transfer, enhancing adaptability for state-of-the-art processes or more mature ones ranging from 90-180nm. These encompass technologies like USB, DDR, and MIPI, ensuring robust solutions for advanced data communication requirements.
Systems4Silicon's DPD solution enhances power efficiency in RF power amplifiers by using advanced predistortion techniques. This technology is part of a comprehensive subsystem known as FlexDPD, which is adaptive and scalable, independent of any particular hardware platform. It supports multiple radio standards, including 5G and O-RAN, and is ready for deployment on either ASICs or FPGA platforms. Engineered for field performance, it offers a perfect balance of reliability and adaptability across numerous applications, meeting broad technical requirements.
RapidGPT by PrimisAI is a revolutionary AI-based tool that transforms the landscape of Electronic Design Automation (EDA). Using generative AI, RapidGPT facilitates a seamless transition from traditional design methods to a more dynamic and intuitive process. This tool is characterized by its ability to interpret natural language inputs, enabling hardware designers to communicate design intentions effortlessly and effectively. Through RapidGPT, engineers gain access to a powerful code assistant that simplifies the conversion of ideas into fully realized Verilog code. By integrating third-party semiconductor IP seamlessly, the tool extends beyond basic design needs to offer a comprehensive framework for accelerating development times. RapidGPT further distinguishes itself by guiding users through the entire design lifecycle, from initial concepts to complete bitstream and GDSII stages, thus redefining productivity in hardware design. With RapidGPT, PrimisAI supports a wide spectrum of interactions and is trusted by numerous companies, underscoring its reliability and impact in the field. The tool's ability to enhance productivity and reduce time-to-market makes it a preferred choice for engineers aiming to combine efficiency with innovation in their projects. Easy to integrate into existing workflows, RapidGPT sets new standards in EDA, empowering users with an unparalleled interface and experience.
The SerDes PHY offered by Credo Semiconductor epitomizes the pinnacle of performance in data communication. This physical layer device is crafted to deliver high-speed serial connections critical for data centers and AI infrastructures. Using advanced technology, it supports data rates that can extend up to an impressive 224Gbps per lane. The product is meticulously designed to facilitate PAM4 data transmission, enabling significant improvements in bandwidth that cater to next-generation data demands. Embedded with cutting-edge features, the SerDes PHY ensures seamless integration across multiple platform architectures. It is well-suited for systems employing Multichip Module System on Chip (MCM SoC) and 2.5D Silicon Interposer designs. These capabilities make it highly adaptable for diverse applications ranging from switch fabric ASIC and AI ASIC to machine learning processes, providing unparalleled solutions for expanding data processing needs. Credo's SerDes PHY stands out not only for its high data rate capabilities but also for its exceptional power efficiency. Even at demanding data transmission speeds, it ensures lower power consumption, thus reducing operational costs while maintaining top-tier performance. Its dedicated design approach embodies a commitment to reliability and scalability, ensuring that it can efficiently handle the rigors of extensive AI and hyperscale network operations.
The Advanced eXtensible Interface(AXI) bus is a high-performance parallel bus that connects on-chip peripheral circuits (or IP blocks) to processor cores. The AXI bus employs "channels" to divide read and write transactions into semi-independent activities that can run at their own pace. The Read Address and Read Data channels send data from the target to the initiator, whereas the Write Address, Write Data, and Write Response channels transfer data from the initiator to the target.
The EW6181 GPS and GNSS solution from EtherWhere is tailored for applications requiring high integration levels, offering licenses in RTL, gate-level netlist, or GDS formats. This highly adaptable IP can be ported across various technology nodes, provided an RF frontend is available. Designed to be one of the smallest and most power-efficient cores, it optimizes battery life significantly in devices such as tags and modules, making it ideal for challenging environments. The IP's strengths lie in its digital processing capabilities, utilizing cutting-edge DSP algorithms for precision and reliability in location tracking. With a digital footprint approximately 0.05mm² on a 5nm node, the EW6181 boasts a remarkably compact size, aiding in minimal component use and a streamlined Bill of Materials (BoM). Its stable firmware ensures accurate and reliable position fixations. In terms of implementation, this IP offers a combination of compact design and extreme power efficiency, providing substantial advantages in battery-operated environments. The EW6181 delivers critical support and upgrades, facilitating seamless high-reliability tracking for an array of applications demanding precise navigation.
Join the world's most advanced semiconductor IP marketplace!
It's free, and you'll get all the tools you need to discover IP, meet vendors and manage your IP workflow!
No credit card or payment details required.
Join the world's most advanced AI-powered semiconductor IP marketplace!
It's free, and you'll get all the tools you need to advertise and discover semiconductor IP, keep up-to-date with the latest semiconductor news and more!
Plus we'll send you our free weekly report on the semiconductor industry and the latest IP launches!