All IPs > Interface Controller & PHY
Interface Controller & PHY semiconductor IPs are integral components in modern digital systems that facilitate communication between various parts of an electronic system, including processors, memory, and peripherals. These IPs are designed to manage data traffic efficiently, ensuring reliable and high-speed data transfer between different interfaces and devices. This catalog features a wide range of IPs that serve various standard and custom interface protocols, making them indispensable for semiconductor companies developing complex SoCs (System on Chips) and digital systems.
In this category, you will find a selection of IPs tailored for popular interface protocols such as AMBA (AHB, APB, AXI), HDMI, PCI, USB, and MIPI, among others. Each IP solution is optimized for performance, supporting high-speed data transfer and reduced latency to meet the demanding needs of today's applications. These IPs not only provide seamless integration capabilities into your design but also ensure compliance with industry standards, which is crucial for interoperability in multi-vendor environments.
The embedded controllers within these IPs handle the logical functions necessary for device communication, while the PHY (physical layer) IPs manage the actual transmission and reception of data across physical media. Together, they enable efficient bridging between different communication protocols, making them critical components in a vast array of devices ranging from consumer electronics like smartphones and gaming consoles to industrial systems and automotive applications.
Our catalog also offers specialized solutions such as Multi-Protocol PHYs that support multiple standards within a single IP, providing flexibility and reducing the footprint for designs that require versatile connectivity options. By selecting the right Interface Controller & PHY IP from our catalog, developers can significantly enhance the functionality and overall performance of their products, leveraging the latest advancements in data interface technology. Explore our offerings and find the precise IP solutions needed to bring your innovative designs to life.
The KL730 is a sophisticated AI System on Chip (SoC) that embodies Kneron's third-generation reconfigurable NPU architecture. This SoC delivers a substantial 8 TOPS of computing power, designed to efficiently handle CNN network architectures and transformer applications. Its innovative NPU architecture significantly optimizes DDR bandwidth, providing powerful video processing capabilities, including supporting 4K resolution at 60 FPS. Furthermore, the KL730 demonstrates formidable performance in noise reduction and low-light imaging, positioning it as a versatile solution for intelligent security, video conferencing, and autonomous applications.
The LVDS (Low Voltage Differential Signaling) IP by Sunplus is crafted for applications that require high-speed data transmission with minimal electromagnetic interference. It is especially conducive to use in displays and communication systems where signal integrity is paramount. This IP supports robust data communication protocols, making it essential for systems that demand fast, reliable transfer rates like those found in monitors and video display units. By utilizing low power differential signaling, the LVDS IP from Sunplus ensures that signal noise is minimized, which is crucial in environments where bandwidth and clarity are priorities. Incorporating this IP can greatly enhance a system's capability to deliver consistent performance at high data rates, while maintaining energy efficiency. It's particularly advantageous in consumer electronics and automotive display applications, where precise signal transmission directly impacts the quality and clarity of the output.
The Metis AIPU PCIe AI Accelerator Card offers exceptional performance for AI workloads demanding significant computational capacity. It is powered by a single Metis AIPU and delivers up to 214 TOPS, catering to high-demand applications such as computer vision and real-time image processing. This PCIe card is integrated with the Voyager SDK, providing developers with a powerful yet user-friendly software environment for deploying complex AI applications seamlessly. Designed for efficiency, this accelerator card stands out by providing cutting-edge performance without the excessive power requirements typical of data center equipment. It achieves remarkable speed and accuracy, making it an ideal solution for tasks requiring fast data processing and inference speeds. The PCIe card supports a wide range of AI application scenarios, from enhancing existing infrastructure capabilities to integrating with new, dynamic systems. Its utility in various industrial settings is bolstered by its compatibility with the suite of state-of-the-art neural networks provided in the Axelera AI ecosystem.
Advanced Peripheral Bus (APB) is one of the Advanced Microcontroller Bus Architecture (AMBA) family protocols. It is a low-cost interface that is designed for low power consumption and interface simplicity. Unlike AHB, it is a non-pipelined protocol for connecting low-bandwidth peripherals. Mostly used to link external peripherals to the SOC. Every APB transfer requires at least two clock cycles (SETUP Cycle and ACCESS Cycle) to finish. The APB interface is designed for accessing the programmable control registers of peripheral devices. The APB protocol has two independent data buses, one for read data and one for write data. The buses can be 8, 16, or 32 bits wide. The read and write data buses must have the same width. Data transfers cannot occur concurrently because the read data and write data buses do not have their own individual handshake signals.
Primesoc's PCIE GEn7 IP is dual mode controller , supporting upto 128Gbps per lane data rate , which can work as root complex or as an endpoint. This is a soft IP which can support serdes and non serdes architectures and PIPE interface of 64bit and lanes configurable from 1/2/4/8/16.
Silicon Creations' SerDes Interfaces are crafted to handle high-speed data transmission challenges over varied processes, ranging from 12nm to 180nm. Addressing multiple protocols such as CPRI, PCIe, and SATA, these interfaces demonstrate flexibility by supporting data transmission speeds from 100 Mbps to beyond 32 Gbps. The architecture incorporates a host of advanced features including adaptive equalization techniques and programmable de-serialization widths, making it stand out in terms of performance and signal integrity even under challenging conditions. With ultra-low latency PMAs, they sustain excellent operational speed and efficiency, imperative for sophisticated communication applications. Moreover, Silicon Creations partners with leading entities to provide comprehensive solutions, including complete PCIe PHY integrations. This synergy ensures that SerDes Interfaces are fully optimized for operational excellence, delivering stable and reliable communication signals. With an emphasis on low power and minimized area requirements, they cater to burgeoning industry needs for power-efficient and space-conservative designs.
The GS-065-008-1-L is engineered for high-voltage operations, providing an ideal solution for applications that necessitate efficient energy management. Its enhancement mode design results in impressive power handling capabilities, supported by a low on-resistance which minimizes power loss even in challenging environments. This GaN transistor highlights a bottom-side cooling feature that significantly aids thermal management, ensuring stable performance over extended periods. Its build quality accommodates compact electronic designs where efficiency and reduced size are important, serving industries like renewable energy and automotive. With its capacity to handle larger loads without compromising on efficiency, the GS-065-008-1-L is crucial in power system designs requiring reliability and durability. Adopting this component into energy systems can lead to improved performance metrics across the board, substantially impacting cost reductions and energy conservation strategies.
The CXL 3.1 Switch by Panmnesia is a high-tech solution designed to manage diverse CXL devices within a cache-coherent system, minimizing latency through its proprietary low-latency CXL IP. This switch supports a scalable and flexible architecture, offering multi-level switching and port-based routing capabilities that allow expansive system configurations to meet various application demands. It is engineered to connect system devices such as CPUs, GPUs, and memory modules, ideal for constructing large-scale systems tailored to specific needs.
The Mixel MIPI C-PHY IP (MXL-CPHY) is a high-frequency, low-power, low cost, physical layer. (Learn more about Mixel’s MIPI ecosystem at Mixel MIPI Central which gives you access to Mixel’s best of class MIPI ecosystem supply chain partners.) The C-PHY configuration consists of up to three lane modules and is based on 3-Phase symbol encoding technology, delivering 2.28 bits per symbol over three-wire trios and targeting a maximum rate of 2.5 Gsps, 5.7Gbps. The C-PHY is partitioned into a digital module – CIL (Control and Interface Logic) and a mixed-signal module. The PHY IP is provided as a combination of soft IP views (RTL, and STA Constraints) for the digital module, and hard IP views (GDSII/CDL/LEF/LIB) for the mixed-signal module. This unique offering of both soft and hard IP permits architectural design flexibility and seamless implementation in customer-specific design flow. The CIL module interfaces with the protocol layer and determines the global operation of the module. The interface between the PHY and the protocol is using the PHY-Protocol Interface (PPI). The mixed-signal module includes high-speed signaling mode for fast-data traffic and low-power signaling mode for control purposes. During normal operation, a lane switches between low-power and high-speed mode. Bidirectional lanes can also switch communication direction. The change of operating mode or direction requires enabling and disabling of certain electrical functions. These enable and disable events do not cause glitches on the lines that would result in a detection of incorrect signal levels. All mode and direction changes are smooth to always ensure a proper detection of the line signals. Mixel’s C-PHY is a complete PHY, silicon-proven at multiple foundries and multiple nodes. It is built to support the MIPI Camera Serial Interface (CSI) and Display Serial Interface (DSI).
The Yitian 710 Processor is an advanced Arm-based server chip developed by T-Head, designed to meet the extensive demands of modern data centers and enterprise applications. This processor boasts 128 high-performance Armv9 CPU cores, each coupled with robust caches, ensuring superior processing speeds and efficiency. With a 2.5D packaging technology, the Yitian 710 integrates multiple dies into a single unit, facilitating enhanced computational capability and energy efficiency. One of the key features of the Yitian 710 is its memory subsystem, which supports up to 8 channels of DDR5 memory, achieving a peak bandwidth of 281 GB/s. This configuration guarantees rapid data access and processing, crucial for high-throughput computing environments. Additionally, the processor is equipped with 96 PCIe 5.0 lanes, offering a dual-direction bandwidth of 768 GB/s, enabling seamless connectivity with peripheral devices and boosting system performance overall. The Yitian 710 Processor is meticulously crafted for applications in cloud services, big data analytics, and AI inference, providing organizations with a robust platform for their computing needs. By combining high core count, extensive memory support, and advanced I/O capabilities, the Yitian 710 stands as a cornerstone for deploying powerful, scalable, and energy-efficient data processing solutions.
The Metis AIPU M.2 Accelerator Module is designed for edge AI applications that demand high-performance inference capabilities. This module integrates a single Metis AI Processing Unit (AIPU), providing an excellent solution for AI acceleration within constrained devices. Its capability to handle high-speed data processing with limited power consumption makes it an optimal choice for applications requiring efficiency and precision. With 1GB of dedicated DRAM memory, it seamlessly supports a wide array of AI pipelines, ensuring rapid integration and deployment. The design of the Metis AIPU M.2 module is centered around maximizing performance without excessive energy consumption, making it suitable for diverse applications such as real-time video analytics and multi-camera processing. Its compact form factor eases incorporation into various devices, delivering robust performance for AI tasks without the heat or power trade-offs typically associated with such systems. Engineered to problem-solve current AI demands efficiently, the M.2 module comes supported by the Voyager SDK, which simplifies the integration process. This comprehensive software suite empowers developers to build and optimize AI models directly on the Metis platform, facilitating a significant reduction in time-to-market for innovative solutions.
The AI Camera Module by Altek Corporation exemplifies cutting-edge image capture technology, integrating both hardware and software to deliver high-quality, intelligent imaging solutions. This module is built on robust AI frameworks allowing it to adapt and optimize image processing based on specific application needs. It finds use in areas where high-resolution and real-time processing are essential, such as security systems and automotive industries.<br/><br/>Equipped with versatile imaging sensors, the AI Camera Module ensures excellent picture quality even in challenging lighting conditions, thanks to its AI-driven image enhancement algorithms. It supports edge computing, which reduces latency and enhances the speed of image analysis, thus providing timely insights and data processing right on the device itself.<br/><br/>This camera module stands out for its interoperability with IoT devices, paving the way for a more interconnected and intelligent ecosystem. Its advanced features such as facial detection, motion tracking, and object recognition empower users across various domains, from consumer electronics to industrial solutions, making it an indispensable tool for modern digital infrastructures.
The Mixel MIPI D-PHY IP (MXL-DPHY) is a high-frequency low-power, low cost, source-synchronous, physical layer compliant with the MIPI® Alliance Standard for D-PHY. (Learn more about Mixel’s MIPI ecosystem at Mixel MIPI Central which gives you access to Mixel’s best of class MIPI ecosystem supply chain partners.) Although primarily used for connecting cameras and display devices to a core processor, this MIPI PHY can also be used for many other applications. It is used in a master-slave configuration, where high-speed signals have a low voltage swing, and low-power signals have large swing. High-speed functions are used for high-speed data traffic while low-power functions are mostly used for control. The D-PHY is partitioned into a Digital Module – CIL (Control and Interface Logic) and a Mixed Signal Module. It is provided as a combination of Soft IP views (RTL, and STA Constraints) for Digital Module, and Hard IP views (GDSII/CDL/LEF/LIB) for the Mixed Signal Module. This unique offering of Soft and Hard IP permits architectural design flexibility and seamless implementation in customer-specific design flow. The CIL module interfaces with the protocol layer and determines the global operation of the lane module. The interface between the D-PHY and the protocol is called the PHY-Protocol Interface (PPI). During normal operation, the data lane switches between low-power mode and high-speed mode. Bidirectional lanes can also switch communication direction. The change of operating mode or direction requires enabling and disabling certain electrical functions. These enable and disable events do not cause glitches on the lines that would otherwise result in detections of incorrect signal levels. Therefore, all mode and direction changes occur smoothly, ensuring proper detection of the line signals. Mixel’s D-PHY is a complete PHY, silicon-proven at multiple foundries and multiple nodes. This MIPI PHY is fully integrated and has analog circuitry, digital, and synthesizable logic. Our D-PHY is built to support the MIPI Camera Serial Interface (CSI) and Display Serial Interface (DSI) using the PHY Protocol Interface (PPI). Mixel has provided this IP in many different configurations to accommodate different applications. The Universal Lane configuration can be used to support any allowed use-case, while other configurations are optimized for many different use cases such as Transmit only, Receive only, DSI, CSI, TX+ and RX+. Both TX+ and RX+ configurations support full-speed loopback operation without the extra area associated with a universal lane configuration.
The bus converter module transforms wide initiator data buses to smaller target data buses or vice-versa. A narrow target on a wide bus, only requires external logic and no internal design changes. * APB: 32-bit wide initiator data buses to 16-bit target data buses. * AHB: 64-bit wide initiator data buses to 32-bit target data buses. * AXI: 256-bit wide initiator data buses to 64-bit target data buses A wide target on a narrow bus, only requires external logic and no internal design changes. * APB: 16-bit wide initiator data buses to 32-bit target data buses. * AHB: 32-bit wide initiator data buses to 64-bit target data buses. * AXI: 64-bit wide initiator data buses to 256-bit target data buses.
AMBA AHB is a bus interface designed for high-performance synthesizable applications. It specifies the interface between components such as initiator , interconnects, and targets. AMBA AHB incorporates the features needed for high-performance, high clock frequency systems. The most common AHB targets are internal memory devices, external memory interfaces, and high-bandwidth peripherals.
The Aries fgOTN processor family is engineered according to the ITU-T G.709.20 fgOTN standard. This line of processors handles a variety of signals, including E1/T1, FE/GE, and STM1/STM4, effectively monitoring and managing alarms and performance metrics. Aries processors excel at fine-grain traffic aggregation, efficiently channeling fgODUflex traffic across OTN lines to support Ethernet, SDH, PDH client services. Their capacity to map signals to fgODUflex containers, which are then multiplexed into higher order OTN signals, demonstrates their versatility and efficiency. By allowing cascaded configurations with other Aries devices or Apodis processors, Aries products optimize traffic routes through OTN infrastructures, positioning them as essential components in optical networking and next-generation access scenarios.
The Advanced eXtensible Interface(AXI) bus is a high-performance parallel bus that connects on-chip peripheral circuits (or IP blocks) to processor cores. The AXI bus employs "channels" to divide read and write transactions into semi-independent activities that can run at their own pace. The Read Address and Read Data channels send data from the target to the initiator, whereas the Write Address, Write Data, and Write Response channels transfer data from the initiator to the target.
The AHB-Lite APB4 Bridge from Roa Logic is a versatile interconnect bridge designed to facilitate communication between the AMBA 3 AHB-Lite and AMBA APB bus protocols. As a parameterized soft IP, it offers flexibility in adapting to different system requirements, ensuring smooth data transfer between high-performance and low-performance buses. This bridge is crucial for systems that integrate diverse peripherals requiring seamless interaction across varying bus standards. Its design prioritizes efficiency and performance, minimizing latency and maximizing data throughput. The AHB-Lite APB4 Bridge supports extensive customization options to meet specific design criteria, making it suitable for a wide range of applications across different industries. By serving as a conduit between different bus protocols, it plays a central role in maintaining system cohesiveness and reliability. Roa Logic enhances the bridge's usability through detailed technical documentation and supportive testbenches, easing its integration into existing frameworks. Developers can readily incorporate the bridge into their designs, optimizing inter-bus communication and ensuring that system performance remains uncompromised. This bridge exemplifies Roa Logic's dedication to providing robust, adaptable IP solutions for contemporary digital environments.
RaiderChip's GenAI v1 is a pioneering hardware-based generative AI accelerator, designed to perform local inference at the Edge. This technology integrates optimally with on-premises servers and embedded devices, offering substantial benefits in privacy, performance, and energy efficiency over traditional hybrid AI solutions. The design of the GenAI v1 NPU streamlines the process of executing large language models by embedding them directly onto the hardware, eliminating the need for external components like CPUs or internet connections. With its ability to support complex models such as the Llama 3.2 with 4-bit quantization on LPDDR4 memory, the GenAI v1 achieves unprecedented efficiency in AI token processing, coupled with energy savings and reduced latency. What sets GenAI v1 apart is its scalability and cost-effectiveness, significantly outperforming competitive solutions such as Intel Gaudi 2, Nvidia's cloud GPUs, and Google's cloud TPUs in terms of memory efficiency. This solution maximizes the number of tokens generated per unit of memory bandwidth, thus addressing one of the primary limitations in generative AI workflow. Furthermore, the adept memory usage of GenAI v1 reduces the dependency on costly memory types like HBM, opening the door to more affordable alternatives without diminishing processing capabilities. With a target-agnostic approach, RaiderChip ensures the GenAI v1 can be adapted to various FPGAs and ASICs, offering configuration flexibility that allows users to balance performance with hardware costs. Its compatibility with a wide range of transformers-based models, including proprietary modifications, ensures GenAI v1's robust placement across sectors requiring high-speed processing, like finance, medical diagnostics, and autonomous systems. RaiderChip's innovation with GenAI v1 focuses on supporting both vanilla and quantized AI models, ensuring high computation speeds necessary for real-time applications without compromising accuracy. This capability underpins their strategic vision of enabling versatile and sustainable AI solutions across industries. By prioritizing integration ease and operational independence, RaiderChip provides a tangible edge in applying generative AI effectively and widely.
The NuLink Die-to-Die PHY is a state-of-the-art IP solution designed to facilitate efficient die-to-die communication on standard organic/laminate packaging. It supports multiple industry standards, including UCIe and Bunch of Wires (BoW) protocols, and features advanced bidirectional signaling capabilities to enhance data transfer rates. The NuLink technology enables exceptional performance, power economy, and reduced area footprint, which elevates its utility in AI applications and complex chiplet systems. A unique feature of this PHY is its simultaneous bidirectional signaling (SBD), that allows data to be sent and received simultaneously on the same physical line, effectively doubling the available bandwidth. This capacity is crucial for applications needing high interconnect performance, such as AI training or inference workloads, without requiring advanced packaging techniques like silicon interposers. The PHY's design supports 64 data lanes configured for optimal placement and bump map layout. With a focus on power efficiency, the NuLink achieves competitive performance metrics even in standard packaging, making it particularly suitable for high-density systems-in-package solutions.
The Mixel MIPI C/D-PHY combo IP (MXL-CPHY-DPHY) is a high-frequency low-power, low cost, physical layer compliant with the MIPI® Alliance Standard for C-PHY and D-PHY. (Learn more about Mixel’s MIPI ecosystem at Mixel MIPI Central which gives you access to Mixel’s best of class MIPI ecosystem supply chain partners.) The PHY can be configured as a MIPI Master or MIPI Slave, supporting camera interface CSI-2 v1.2 or display interface DSI v1.3 applications in the D-PHY mode. It also supports camera interface CSI-2 v1.3 and display interface DSI-2 v1.0 applications in the C-PHY mode. The high-speed signals have a low voltage swing, while low-power signals have large swing. High-Speed functions are used for high-speed data traffic while low-power functions are mostly used for control. The C-PHY is based on 3-Phase symbol encoding technology, delivering 2.28 bits per symbol over three-wire trios, operating with a symbol rate range of 80 to 4500 Msps per lane, which is the equivalent of about 182.8 to 10260 Mbps per lane. The D-PHY supports a bit rate range of 80 to 1500 Mbps per Lane without deskew calibration, and up to 4500 Mbps with deskew calibration. The low-power mode and escape mode are the same in both the D-PHY and C-PHY modes. To minimize EMI, the drivers for low-power mode are slew-rate controlled and current limited. The data rate in low-power mode is 10 Mbps. For a fixed clock frequency, the available data capacity of a PHY configuration can be increased by using more lanes. Effective data throughput can be reduced by employing burst mode communication. Mixel’s C-PHY/D-PHY combo is a complete PHY, silicon-proven at multiple foundries and multiple nodes. The C/D-PHY is fully integrated and has analog circuitry, digital, and synthesizable logic.
Overview: The MIPI I3C Controller IP Core is fully compliant with the latest I3C specification, offering high bandwidth and scalability for integrating multiple sensors into mobile, automotive, and IoT system-on-chips (SoCs). This controller support in-band interrupts within the 2-wire interface, reducing pin count, simplifying board design, and lowering power and system costs. Backward compatibility with I2C ensures future-proof designs, and the controller's operating modes enable efficient connectivity for systems with multiple ICs and sensors on a single I3C bus. The ARM® AMBA® Advanced High-Performance Bus (AHB) facilitates seamless integration of the IP into the SoC. Key Features:  Compliance with MIPI-I3C Basic v1.0  Backward compatibility with I2C  Two-wire serial interface up to 12.5MHz using Push-Pull  Dynamic and Static Addressing support  Single Data Rate messaging (SDR)  Broadcast and Direct Common Command Code (CCC) Messages support  In-Band Interrupt capability  Hot-Join Support Applications:  Consumer Electronics  Defense  Aerospace  Virtual Reality  Augmented Reality  Medical  Biometrics (Fingerprints, etc.)  Automotive Devices  Sensor Devices
The eSi-Connect suite introduces a fully integrated solution encompassing a wide variety of processor peripherals, each interfacing seamlessly through standard AMBA protocols like AXI, AHB, or APB, simplifying integration and development of SoC architectures. This suite features memory controllers for DDR, SPI Flash, and interfaces including USB, UART, and GPIO among others, bounded by real-time and control functionalities such as timers and watchdogs. Each peripheral component is highly configurable to adjust features like FIFO sizes for UART, I2C clock rates, SPI operating modes, providing modular flexibility to target specific application needs. Low-level driver software accompanies each peripheral for real-time deployments, enhancing the module's utility for prompt SoC integration and application fulfillment. This attribute ensures enhanced interoperability within diverse design environments fulfilling both immediate and long-term product objectives through architectural simplicity and reliable performance-level adaptability.
The Multi-Protocol SERDES offered by Pico Semiconductor is a versatile solution capable of handling a variety of communication protocols. This series of SERDES includes a 4-channel configuration that supports data rates up to 32Gbps, designed for integration with XAUI, RXAUI, and SGMII. It is compatible with multiple process nodes provided by foundries like TSMC and GF, offering robust performance across different semiconductor environments. These SERDES are crafted to meet high-performance metrics, capturing speeds up to 16Gbps and 6.5Gbps across various models, with advanced versions reaching up to 32Gbps. This exceptional range not only ensures compatibility with current technologies but also prepares systems for future updates, sustaining high data throughput. By delivering reliable high-speed data transmission capabilities, the Multi-Protocol SERDES from Pico Semiconductor is integral for networking, high-speed computing, and data storage applications, where efficient and speedy data transfer is paramount.
The AHB-Lite Multilayer Switch developed by Roa Logic is engineered to provide a high-performance, low-latency interconnect solution for systems using the AHB-Lite bus protocol. This IP is designed to support an unlimited number of bus masters and slaves, ensuring scalability and flexibility in complex system architectures. By enabling efficient data routing, the switch enhances throughput and overall system performance, making it indispensable in data-intensive applications. Capable of handling multiple data paths simultaneously, the multilayer switch ensures that there are no bottlenecks in data flow, facilitating real-time data processing and communication. Its design features are tailored to optimize latency and throughput, effectively addressing the challenges encountered in high-demand environments. Roa Logic provides a comprehensive suite of resources, including thorough documentation and testbench environments, to simplify the integration of this switch into larger system designs. This support ensures that developers can achieve optimal performance with ease, utilizing the switch's capabilities to enhance system interconnectivity and efficiency significantly. The AHB-Lite Multilayer Switch exemplifies the commitment of Roa Logic to provide innovative, responsive solutions that cater to the evolving needs of the semiconductor industry.
The CT25205 is a comprehensive digital controller designed for 10BASE-T1S Ethernet applications, providing seamless integration with Ethernet MACs and offering essential PMA, PCS, and PLCA Reconciliation Sublayer components. Crafted in Verilog 2005 HDL, this core is fully synthesizable on standard cells and FPGA systems, ensuring versatile deployment in various network architectures. The IP also supports PLCA RS, enabling advanced Ethernet features without the need for additional MAC extensions. It's developed to function with the OPEN Alliance 10BASE-T1S PMD interface, making it a robust solution for modern Ethernet-based systems.
Overview: The MIPI CSI-2 (Camera Serial Interface) defines an interface between a peripheral device (camera) and host processor (application engine) for mobile applications. It offers the mobile industry a standard, robust, scalable, low-power, high-speed, and cost-effective interface that supports a wide range of imaging solutions for mobile devices. Key Features:  Compliance with MIPI-CSI-2 version 3.0  Compliance with C-PHY 2.0 for MIPI CSI-2 Version 3.0  Compliance with D-PHY 2.5 for MIPI CSI-2 Version 3.0  Compatibility with I2C and I3C (SDR, DDR) for CCI interface  Support for C-PHY 2.0, D-PHY 2.5, A-PHY, M-PHY with configurable PHY layer  Processor Interfaces: AHB Lite/APB/AXI for configuration  Lane Merging Function for consolidating packet data in CSI-2 Receiver  De-skew detection in D-PHY and sync word detection in C-PHY  Pixel Formats Supported: YUV, RGB, and RAW data  Virtual Channels: 16 for D-PHY, 32 for C-PHY  Error detection, interleaving, scrambling, and descrambling support  Byte to pixel conversion in LLP layer Applications:  Imaging  Surveillance  Gaming  Sensor devices  Internet of Things (IoT)  Wearable devices  Virtual Reality  Augmented Reality  Automotive Systems
The USB PHY offering from this company facilitates efficient data transfer by supporting USB 2.0 protocols. Known for its versatility and reliability, this interface IP provides seamless integration into various digital platforms, ensuring high performance in data communication tasks. It's engineered to support a wide range of applications, reinforcing USB's significant role in both consumer electronics and industrial applications. The design of the USB PHY is optimized for low power consumption while maintaining data integrity and speed. Its adaptability makes it suitable for integration into systems requiring robust communication links, thereby enhancing the user experience in connecting multiple devices across different environments. Moreover, the USB PHY is designed with consideration for ease of use and compatibility, making it a valuable asset for developers looking to implement high-speed data solutions in their projects. This component underlines the company's commitment to providing effective, efficient, and easy-to-implement IP solutions, cementing its reputation in the semiconductor industry.
The secondary or slave PHY for LPDDR4/4X/5 is designed to serve memory-side applications, facilitating efficient communication between diverse devices and processing units in AI and in-memory computing. Its low power, high-speed nature makes it ideal for dynamic environments adhering to current JEDEC standards.
iWave Global introduces the ARINC 818 Switch, a pivotal component in the management and routing of video data within avionics systems. Designed for applications that require efficient video data distribution and management, the switch is optimized for performance in environments with stringent data handling requirements. The switch's architecture supports a high level of bandwidth, allowing for the smooth routing of multiple video streams in real-time. Its design includes advanced features that ensure low-latency, error-free data transfer, integral to maintaining the integrity and reliability of video data in critical applications. Featuring robust interoperability characteristics, the ARINC 818 Switch easily integrates into existing systems, facilitating modular expansion and adaptability to new technological standards. It is indispensable for any aerospace project that involves complex video data management, providing a stable platform for video data routing and switching.
The Chimera GPNPU from Quadric is designed as a general-purpose neural processing unit intended to meet a broad range of demands in machine learning inference applications. It is engineered to perform both matrix and vector operations along with scalar code within a single execution pipeline, which offers significant flexibility and efficiency across various computational tasks. This product achieves up to 864 Tera Operations per Second (TOPs), making it suitable for intensive applications including automotive safety systems. Notably, the GPNPU simplifies system-on-chip (SoC) hardware integration by consolidating hardware functions into one processor core. This unification reduces complexity in system design tasks, enhances memory usage profiling, and optimizes power consumption when compared to systems involving multiple heterogeneous cores such as NPUs and DSPs. Additionally, its single-core setup enables developers to efficiently compile and execute diverse workloads, improving performance tuning and reducing development time. The architecture of the Chimera GPNPU supports state-of-the-art models with its Forward Programming Interface that facilitates easy adaptation to changes, allowing support for new network models and neural network operators. It’s an ideal solution for products requiring a mix of traditional digital signal processing and AI inference like radar and lidar signal processing, showcasing a rare blend of programming simplicity and long-term flexibility. This capability future-proofs devices, expanding their lifespan significantly in a rapidly evolving tech landscape.
Overview: The MIPI DSI Transmitter IP is designed to transmit data to the host processor, providing the mobile industry with a standard, robust, scalable, low-power, high-speed, and cost-effective interface that supports a wide range of imaging solutions for mobile devices. Key Features:  Compliance with MIPI-DSI-2 version 2.0  Compliance with C-PHY version 2.0 for DSI-2 Version-2  Compliance with D-PHY version 1.2 for DSI-2 Version-2.0  Compliance with D-PHY version 2.0 for DSI-2 Version-2.0  Compliance with D-PHY version 3.0 for DSI-2 Version-2.0  Compliance with MIPI SDF specification  Compliance with DBI-2 and DPI-2  Pixel to Byte conversion support from Application layer to LLP layer  Support for Command Mode and Video Mode  Continuous clock behavior in clock lane for D-PHY physical layer  De-skew sequence pattern for video mode support  Lane Distribution Function for distributing packet bytes across N-Lanes  Connectivity with two, three, or four DSI Receivers  HS mode and Escape mode support for transmission of Packets in both C-PHY and D-PHY  Symbol slip detection code and sync symbol insertion in C-PHY physical layer Target Applications:  Imaging  Surveillance  Gaming  Sensor devices  Internet of Things (IoT)  Wearable devices  Virtual Reality  Augmented Reality  Automotive Systems
Time-Triggered Ethernet (TTE) combines the robustness of Ethernet technology with the precision of time-triggered communication. Designed for critical applications that demand reliability and synchronized communication, TTE finds its place in aerospace and industrial sectors. TTE operates by affording secure, deterministic data transmission over Ethernet networks. It achieves this by dedicating specific time slots for high-priority traffic, ensuring latency and jitter are minimized. This segregation allows time-sensitive data to safely coexist with traditional Ethernet traffic, without sacrificing normal network operations. The protocol's architecture underlies a mixed-criticality networking environment, supporting integration with standard Ethernet devices. TTE's scheduling mechanism guarantees timely delivery of critical messages, crucial in environments where even microsecond delays can impact overall system performance. Its application ensures Ethernet networks meet the stringent requirements of real-time operations synonymous with safety-critical systems.
YouSerdes provides a versatile high-speed serial data interface, supporting multiple data rates ranging from 2.5Gbps to 32Gbps. It integrates multiple SERDES channels, ensuring it delivers top-tier performance, area efficiency, and power consumption relative to its peers in the market. It's ideal for applications requiring robust, high-speed data communication.
The Mixed-Signal CODEC offered by Archband Labs integrates advanced analog and digital audio processing to deliver superior sound quality. Designed for a variety of applications such as portable audio devices, automotive systems, and entertainment systems, this CODEC provides efficiency and high performance. With cutting-edge technologies, it handles complex signal conversions with minimal power consumption. This CODEC supports numerous interface standards, making it a versatile component in numerous audio architectures. It's engineered to offer precise sound reproduction and maintains audio fidelity across all use cases. The integrated components within the CODEC streamline design processes and reduce the complexity of audio system implementations. Furthermore, the Mixed-Signal CODEC incorporates features that support high-resolution audio, ensuring compatibility with high-definition sound systems. It's an ideal choice for engineers looking for a reliable and comprehensive audio processing solution.
The KL630 chip stands out with its pioneering NPU architecture, making it the industry's first to support Int4 precision alongside transformer networks. This unique capability enables it to achieve exceptional computational efficiency and low energy consumption, suitable for a wide variety of applications. The chip incorporates an ARM Cortex A5 CPU, providing robust support for all major AI frameworks and delivering superior ISP capabilities for handling low light conditions and HDR applications, making it ideal for security, automotive, and smart city uses.
Overview: The SPD5 Hub controller IP is designed to interface with the I3C/I2C Host Bus, allowing for the isolation of local devices such as Temperature Sensors (TS) from the master host bus. It features a Two-wire serial interface with SCL and SDA busses. Key Features:  Compliance with JEDEC's JESD300-5  Support for speeds up to 12.5MHz  Bus Reset functionality  SDA arbitration support  Enabled Parity Check  Support for Packet Error Check (PEC)  Switch between I2C and I3C Basic Mode  Default Read address pointer Mode  Write and read operations for SPD5 Hub with or without PEC  In-band Interrupt (IBI) support  Write Protection for NVM memory blocks  Arbitration for Interrupts  Clearing of Device Status and IBI Status Registers  Error handling for Packet Error Check and Parity Errors  Common Command Codes (CCC) for I3C Basic Mode  Dynamic IO Operation Mode Switching  Bus Clear and Bus Reset capabilities  SPD5 Command features for NVM memory and Register Space  Read and Write access to NVM memory  Support for Offline Tester operation Applications:  DDR5 DIMM Application Environment  DDR5 NVDIMM Application Environment  Automotive Devices  Memory Devices  Power Management Devices  Defense/Aerospace/Customer Electronics
The AHB-Lite Timer from Roa Logic is a precision timing module designed to comply with the RISC-V Privileged specification. This timer is engineered to manage time-sensitive operations within systems that utilize the AHB-Lite bus protocol, ensuring accurate timing for a variety of applications. By providing robust timer functionalities, the AHB-Lite Timer assists in overseeing operations where precise timing is crucial, such as coordinating tasks within embedded systems or managing periods in control processes. Its compliance with RISC-V standards ensures that it integrates seamlessly with systems based on this widely adopted open standard, enhancing compatibility and performance. Developers can take advantage of Roa Logic's comprehensive support materials, which include detailed documentation and pre-configured test environments, to facilitate the easy integration of the timer into existing designs. This support infrastructure is indicative of Roa Logic's commitment to simplifying the adoption and effective utilization of its sophisticated IP offerings within diverse system architectures.
The Polar ID Biometric Security System by Metalenz revolutionizes smartphone biometric security with its advanced imaging capabilities that capture the full polarization state of light. This system detects unique facial polarization signatures, enabling high-precision face authentication that even sophisticated 3D masks cannot deceive. Unlike traditional systems requiring multiple optical modules, Polar ID achieves secure recognition with a single image, ideal for secure digital payments and more. Operating efficiently across various lighting conditions, from bright daylight to complete darkness, Polar ID ensures robust security without compromising user convenience. By leveraging meta-optic technology, it offers a compact, cost-effective alternative to structured light solutions, suitable for widespread deployment across millions of mobile devices.
The 10G TCP Offload Engine (TOE) is a specialized hardware solution designed to alleviate CPU loads by handling TCP/IP traffic directly. Particularly useful in high-speed network environments, this offload engine ensures that servers can maintain optimal performance levels by significantly reducing the computational load associated with TCP processing. This TOE implementation offers low latency operation and supports a broad range of network protocols, making it an ideal fit for data centers and enterprise network settings. It ensures high throughput with minimal packet loss, which is crucial for applications like video streaming and large file transfers where data integrity and speed are paramount. Built with scalability in mind, the TOE can manage multiple connections concurrently, providing consistent performance even as network demands grow. The integration with existing network infrastructure is seamless, making it a cost-effective upgrade for enhancing network efficiency and reducing bottlenecks.
MAXVY UCIe VIP , a state-of-the-art solution that offers a comprehensive set of features and capabilities to ensure the quality and performance of your UCIe designs. MAXVY UCIe VIP is fully compliant with UCIe Specification version 1.0 and supports all the layers of the UCIe stack, such as FDI, RDI, LogPHY, PCIe, and CXL protocols. MAXVY UCIe VIP is also very user-friendly and flexible, with simple APIs, easy integrations, and configurable parameters. You can easily customize and control the UCIe functionality according to your needs. MAXVY UCIe VIP also provides a rich set of verification capabilities, such as protocol checks, functional coverage, traffic generation, error injection, and debug tools. You can easily monitor, detect, and report any issues or violations in your UCIe designs. MAXVY UCIe VIP is compatible with the industry-standard Universal Verification Methodology (UVM) and supports all leading simulators. With MAXVY UCIe VIP, very flexible for unit level testing, you can achieve faster verification closure and higher quality of your UCIe designs.
The GL3590-S is a sophisticated USB 3.2 Gen 2 hub controller designed with multiple advanced features to handle high-speed data transfer and effective power management. It integrates Genesys Logic's proprietary USB 3.1 Gen 2 Super Speed PHY, and supports USB 2.0 High-Speed PHY, enabling it to efficiently manage Super Speed, Hi-Speed, and Full-Speed USB connections. This controller is backward compatible with USB 2.0 and USB 1.1 standards, ensuring versatile connectivity options for various devices. Key to its design is its ability to support multiple Transaction Translators (TTs), which allocate dedicated resources for each downstream port, optimizing full-speed data transfer when managing multiple devices. Compliant with the USB-IF battery charging specifications, the GL3590-S supports fast-charging for a wide array of mobile devices, aligning with the latest industry standards. This controller also offers integrated USB Type-C functions, which eliminates the need for external mux or CC controllers for USB-C ports. Its power management capabilities are notable, offering configurations like configurable charging ports and in-system firmware updates via SPI-flash. The GL3590-S is engineered to provide a cost-effective solution with enhanced features for modern devices, making it an ideal component for standalone USB hubs, docking stations, and other smart applications.
The HOTLink II Product Suite is another remarkable offering from Great River Technology. Built to complement their ARINC 818 suite, HOTLink II provides an integrated framework for crafting high-performance digital data links. This suite ensures seamless, secure, and reliable data transmission over fiber or copper cables across various platforms. Developed with a focus on flexibility and functionality, the HOTLink II capabilities enhance system integrators' ability to deploy effective communication solutions within aircraft and other demanding environments. The emphasis on robust, low-latency data transfer makes it an ideal choice for real-time applications where precision and reliability are paramount. Broad compatibility is a hallmark of HOTLink II, facilitating integration into diverse infrastructures. Backed by Great River Technology's expertise and support, customers are empowered to advance their system communication capabilities efficiently and cost-effectively.
MIPI I3C Controller IP Core is fully compliant with the latest I3C specification and delivers high bandwidth and scalability for integration of multiple sensors into mobile, automotive and IoT system-on-chips (SoCs). The MIPI I3C Controller supports in-band interrupts within the 2-wire interface provides significantly lower pin count, simplifying board design and reducing power and cost of the system. The MIPI I3C Controller IP is fully backward compatible with I2C, allowing designers to future proof their design, and the I3C controller IP operating modes enable systems with several ICs to efficiently connect to all sensors on a single I3C bus. The standard-based ARM® AMBA® Advanced High Performance Bus (AHB) connects the IP to the rest of the SoC offering easy IP integration. MIPI I3C Controller IP is designed to easily integrate into any SoC offering lowest gate count and quickly fit into any Chip development flow.
Designed for high-speed transmission, the 16x112G Tx Chiplet showcases superior integration with 16 channels, each operating at 112Gbps. It includes a modulator and driver within a single silicon unit, optimized for optical communication systems requiring high-speed, high-bandwidth data transfer. This sophisticated chiplet ensures seamless modulation of optical signals, supporting efficient driver control and optimized data transmission. The integrated design simplifies system architecture, reducing the overall footprint while maintaining exceptional reliability and performance. Its built-in digital control aids in managing complex signal processing requirements, suitable for diverse applications within optical networking infrastructures. Verifying its design through silicon-proven processes assures users of its capability to meet rigorous industry standards. The application of this chiplet spans high-speed data centers, telecommunications networks, and beyond, where its efficiency and performance are indispensable. The innovation behind its creation reflects Enosemi's dedication to advancing optical technology, offering clients robust and reliable tools to meet current and future communication needs.
The ePHY-5616 is a high-performance SerDes solution from eTopus, designed for versatile use across enterprise, data center, and 5G applications. Operating efficiently at data rates from 1 to 56 Gbps, this product exploits advanced DSP techniques for superior signal integrity and robustness. It accommodates wide insertion loss ranges of 10dB to over 35dB, thus ensuring reliable performance in challenging communication environments. Its architecture supports direct optical drives and quad/octal configurations, making it ideal for network interface cards, routers, and high-speed switches in a data center setup. The embedded DSP architecture is developed with eTopus's proprietary algorithms, which enable rapid SerDes tuning and performance optimization. The ePHY-5616 is also characterized by its low Bit Error Rate (BER), ensuring data reliability and integrity. Moreover, it supports multiple protocols, including Ethernet and PCIe, enhancing its integration potential in modern broadband networks.
The PDM-to-PCM Converter from Archband Labs leads in transforming pulse density modulation signals into pulse code modulation signals. This converter is essential in applications where high fidelity of audio signal processing is vital, including digital audio systems and communication devices. Archband’s solution ensures accurate conversion, preserving the integrity and clarity of the original audio. This converter is crafted to seamlessly integrate with a wide array of systems, offering flexibility and ease-of-use in various configurations. Its robust design supports a wide range of input frequencies, making it adaptable to different signal environments. The PDM-to-PCM Converter also excels in minimizing latency and reducing overhead processing times. It’s engineered for environments where precision and sound quality are paramount, ensuring that audio signals remain crisp and undistorted during conversion processes.
EW6181 is an IP solution crafted for applications demanding extensive integration levels, offering flexibility by being licensable in various forms such as RTL, gate-level netlist, or GDS. Its design methodology focuses on delivering the lowest possible power consumption within the smallest footprint. The EW6181 effectively extends battery life for tags and modules due to its efficient component count and optimized Bill of Materials (BoM). Additionally, it is backed by robust firmware ensuring highly accurate and reliable location tracking while offering support and upgrades. The IP is particularly suitable for challenging application environments where precision and power efficiency are paramount, making it adaptable across different technology nodes given the availability of its RF frontend.
Silicon Creations crafts highly reliable LVDS interfaces designed to meet diverse application needs, going from bi-directional I/Os to specialized uni-directional configurations. Spanning process compatibilities from 90nm CMOS to advanced 7nm FinFET, these interfaces are a cornerstone for high-speed data communication systems, thriving particularly in video data transmission and chip-to-chip communications. Supporting robust data rates over multiple channels, the LVDS Interfaces guarantee flexible programmability and protocol compatibility with standards such as FPD-Link and Camera-Link. They capitalize on proven PLL and CDR architectures for superior signal integrity and error-free data transfers. Operating efficiently in various technology nodes, they remain highly effective across collaborative chipset environments. The interfaces are fortified with adaptable features like dynamic phase alignment to stabilize data sequences and on-die termination options for superior signal integrity. Their proven record places them as a critical enabler in applications where consistent high-speed data transfer is paramount, demonstrating Silicon Creations’ prowess in delivering industry-leading communication solutions.
The 10G TCP Offload Engine with MAC and PCIe interface is engineered for ultra-low latency environments, serving as a robust solution for efficient data transmission in high-speed networks. By offloading TCP processing from the host CPU, it significantly reduces processing demands, enabling data centers and network infrastructures to streamline operations and enhance throughput. This offload engine demonstrates impressive scalability, supporting a variety of session capacities with consistent, minimal latency. Implemented using advanced architecture techniques, this offload engine offers a comprehensive TCP stack with MAC interface capabilities, ensuring seamless data flow across network devices. Its hardware-centric design further eliminates system bottlenecks, delivering high bandwidth and reliable data transmission even under high-load conditions. The PCIe integration allows for rapid, efficient communication within network systems, improving overall data handling efficiency. This solution is designed to minimize jitter and operates effectively in various network setups, making it ideal for cloud computing, large-scale data centers, and other demanding environments. Its robust configuration options and support for multiple sessions simultaneously make it a versatile choice for enterprises looking to maximize their network performance while reducing overhead costs.
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