All IPs > Interface Controller & PHY
Interface Controller & PHY semiconductor IPs are integral components in modern digital systems that facilitate communication between various parts of an electronic system, including processors, memory, and peripherals. These IPs are designed to manage data traffic efficiently, ensuring reliable and high-speed data transfer between different interfaces and devices. This catalog features a wide range of IPs that serve various standard and custom interface protocols, making them indispensable for semiconductor companies developing complex SoCs (System on Chips) and digital systems.
In this category, you will find a selection of IPs tailored for popular interface protocols such as AMBA (AHB, APB, AXI), HDMI, PCI, USB, and MIPI, among others. Each IP solution is optimized for performance, supporting high-speed data transfer and reduced latency to meet the demanding needs of today's applications. These IPs not only provide seamless integration capabilities into your design but also ensure compliance with industry standards, which is crucial for interoperability in multi-vendor environments.
The embedded controllers within these IPs handle the logical functions necessary for device communication, while the PHY (physical layer) IPs manage the actual transmission and reception of data across physical media. Together, they enable efficient bridging between different communication protocols, making them critical components in a vast array of devices ranging from consumer electronics like smartphones and gaming consoles to industrial systems and automotive applications.
Our catalog also offers specialized solutions such as Multi-Protocol PHYs that support multiple standards within a single IP, providing flexibility and reducing the footprint for designs that require versatile connectivity options. By selecting the right Interface Controller & PHY IP from our catalog, developers can significantly enhance the functionality and overall performance of their products, leveraging the latest advancements in data interface technology. Explore our offerings and find the precise IP solutions needed to bring your innovative designs to life.
The KL730 AI SoC is an advanced powerhouse, utilizing third-generation NPU architecture to deliver up to 8 TOPS of efficient computing. This architecture excels in both CNN and transformer applications, optimizing DDR bandwidth usage. Its robust video processing features include 4K 60FPS video output, with exceptional performance in noise reduction, dynamic range, and low-light scenarios. With versatile application support ranging from intelligent security to autonomous driving, the KL730 stands out by delivering exceptional processing capabilities.
The Mixel MIPI C-PHY IP (MXL-CPHY) is a high-frequency, low-power, low cost, physical layer. (Learn more about Mixel’s MIPI ecosystem at Mixel MIPI Central which gives you access to Mixel’s best of class MIPI ecosystem supply chain partners.) The C-PHY configuration consists of up to three lane modules and is based on 3-Phase symbol encoding technology, delivering 2.28 bits per symbol over three-wire trios and targeting a maximum rate of 2.5 Gsps, 5.7Gbps. The C-PHY is partitioned into a digital module – CIL (Control and Interface Logic) and a mixed-signal module. The PHY IP is provided as a combination of soft IP views (RTL, and STA Constraints) for the digital module, and hard IP views (GDSII/CDL/LEF/LIB) for the mixed-signal module. This unique offering of both soft and hard IP permits architectural design flexibility and seamless implementation in customer-specific design flow. The CIL module interfaces with the protocol layer and determines the global operation of the module. The interface between the PHY and the protocol is using the PHY-Protocol Interface (PPI). The mixed-signal module includes high-speed signaling mode for fast-data traffic and low-power signaling mode for control purposes. During normal operation, a lane switches between low-power and high-speed mode. Bidirectional lanes can also switch communication direction. The change of operating mode or direction requires enabling and disabling of certain electrical functions. These enable and disable events do not cause glitches on the lines that would result in a detection of incorrect signal levels. All mode and direction changes are smooth to always ensure a proper detection of the line signals. Mixel’s C-PHY is a complete PHY, silicon-proven at multiple foundries and multiple nodes. It is built to support the MIPI Camera Serial Interface (CSI) and Display Serial Interface (DSI).
Sunplus’s LVDS IP is designed for efficient data transmission in applications requiring low power consumption and high noise immunity. This Low Voltage Differential Signaling technology is particularly effective for transferring large amounts of data over long distances with minimal signal degradation. Ideal for use in display panels and digital communication systems, LVDS technology offers high-speed data rates while maintaining low electromagnetic interference (EMI). This allows for clearer and more reliable data communication, essential for high-resolution video and complex data streams. The architecture supports scalability and adaptability, making it suitable for various applications including video displays, automotive infotainment systems, and industrial communications. It is engineered to maintain signal integrity even under challenging environmental conditions, a testament to its robustness and reliability.
The Metis AIPU PCIe AI Accelerator Card by Axelera AI is designed for developers seeking top-tier performance in vision applications. Powered by a single Metis AIPU, this PCIe card delivers up to 214 TOPS, handling demanding AI tasks with ease. It is well-suited for high-performance AI inference, featuring two configurations: 4GB and 16GB memory options. The card benefits from the Voyager SDK, which enhances the developer experience by simplifying the deployment of applications and extending the card's capabilities. This accelerator PCIe card is engineered to run multiple AI models and support numerous parallel neural networks, enabling significant processing power for advanced AI applications. The Metis PCIe card performs at an industry-leading level, achieving up to 3,200 frames per second for ResNet-50 tasks and offering exceptional scalability. This makes it an excellent choice for applications demanding high throughput and low latency, particularly in computer vision fields.
The 1G to 224G SerDes platform stands out as one of Alphawave Semi's flagship offerings. It showcases a wide range of capabilities by supporting data transmission rates from 1Gbps to a staggering 224Gbps. This SerDes solution is compatible with a multitude of industry protocols and leverages innovative signaling schemes such as PAM2, PAM4, PAM6, and PAM8, which ensures robust performance across varied applications. Engineered to facilitate seamless integration, the SerDes IP meets the expansive data needs of modern computing environments. Crafted with high-speed digital data transmission in mind, the 1G to 224G SerDes delivers outstanding performance in handling interfaces that require precise timing and jitter management. This IP is adept at boosting signal integrity, a crucial feature in high-performance data centers and telecommunications infrastructure. Additionally, it offers a flexible framework adaptable to evolving connectivity demands within para-silicon environments, making it essential for companies aiming to maintain cutting-edge data solutions. Alphawave's SerDes IP is an integral component for industries that demand reliable and accelerated data pathways. Its flexibility further allows customization to match specific client requirements, ensuring optimized performance at minimized power usage. With strategic support for a broad array of process nodes, this SerDes IP is a future-proof investment for any technology-driven enterprise.
Primesoc's PCIE GEn7 IP is dual mode controller , supporting upto 128Gbps per lane data rate , which can work as root complex or as an endpoint. This is a soft IP which can support serdes and non serdes architectures and PIPE interface of 64bit and lanes configurable from 1/2/4/8/16.
Panmnesia's CXL 3.1 Switch is an integral component designed to facilitate high-speed, low-latency data transfers across multiple connected devices. It is architected to manage resource allocation seamlessly in AI and high-performance computing environments, supporting broad bandwidth, robust data throughput, and efficient power consumption, creating a cohesive foundation for scalable AI infrastructures. Its integration with advanced protocols ensures high system compatibility.
Universal Chiplet Interconnect Express (UCIe) is a cutting-edge technology designed to enhance chiplet-based system integrations. This innovative interconnect solution supports seamless data exchange across heterogeneous chiplets, promoting a highly efficient and scalable architecture. UCIe is expected to revolutionize system efficiencies by enabling a smoother and more integrated communication framework. By employing this technology, developers can leverage its superior power efficiency and adaptability to different mainstream technology nodes. It makes it possible to construct complex systems with reduced energy consumption while ensuring performance integrity. UCIe plays a pivotal role in accelerating the transition to the chiplet paradigm, ensuring systems are not only up to current standards but also adaptable for future advancements. Its robust framework facilitates improved interconnect strategies, crucial for next-generation semiconductor products.
The Mixel MIPI C/D-PHY combo IP (MXL-CPHY-DPHY) is a high-frequency low-power, low cost, physical layer compliant with the MIPI® Alliance Standard for C-PHY and D-PHY. (Learn more about Mixel’s MIPI ecosystem at Mixel MIPI Central which gives you access to Mixel’s best of class MIPI ecosystem supply chain partners.) The PHY can be configured as a MIPI Master or MIPI Slave, supporting camera interface CSI-2 v1.2 or display interface DSI v1.3 applications in the D-PHY mode. It also supports camera interface CSI-2 v1.3 and display interface DSI-2 v1.0 applications in the C-PHY mode. The high-speed signals have a low voltage swing, while low-power signals have large swing. High-Speed functions are used for high-speed data traffic while low-power functions are mostly used for control. The C-PHY is based on 3-Phase symbol encoding technology, delivering 2.28 bits per symbol over three-wire trios, operating with a symbol rate range of 80 to 4500 Msps per lane, which is the equivalent of about 182.8 to 10260 Mbps per lane. The D-PHY supports a bit rate range of 80 to 1500 Mbps per Lane without deskew calibration, and up to 4500 Mbps with deskew calibration. The low-power mode and escape mode are the same in both the D-PHY and C-PHY modes. To minimize EMI, the drivers for low-power mode are slew-rate controlled and current limited. The data rate in low-power mode is 10 Mbps. For a fixed clock frequency, the available data capacity of a PHY configuration can be increased by using more lanes. Effective data throughput can be reduced by employing burst mode communication. Mixel’s C-PHY/D-PHY combo is a complete PHY, silicon-proven at multiple foundries and multiple nodes. The C/D-PHY is fully integrated and has analog circuitry, digital, and synthesizable logic.
Silicon Creations' SerDes Interfaces are crafted to handle high-speed data transmission challenges over varied processes, ranging from 12nm to 180nm. Addressing multiple protocols such as CPRI, PCIe, and SATA, these interfaces demonstrate flexibility by supporting data transmission speeds from 100 Mbps to beyond 32 Gbps. The architecture incorporates a host of advanced features including adaptive equalization techniques and programmable de-serialization widths, making it stand out in terms of performance and signal integrity even under challenging conditions. With ultra-low latency PMAs, they sustain excellent operational speed and efficiency, imperative for sophisticated communication applications. Moreover, Silicon Creations partners with leading entities to provide comprehensive solutions, including complete PCIe PHY integrations. This synergy ensures that SerDes Interfaces are fully optimized for operational excellence, delivering stable and reliable communication signals. With an emphasis on low power and minimized area requirements, they cater to burgeoning industry needs for power-efficient and space-conservative designs.
Advanced Peripheral Bus (APB) is one of the Advanced Microcontroller Bus Architecture (AMBA) family protocols. It is a low-cost interface that is designed for low power consumption and interface simplicity. Unlike AHB, it is a non-pipelined protocol for connecting low-bandwidth peripherals. Mostly used to link external peripherals to the SOC. Every APB transfer requires at least two clock cycles (SETUP Cycle and ACCESS Cycle) to finish. The APB interface is designed for accessing the programmable control registers of peripheral devices. The APB protocol has two independent data buses, one for read data and one for write data. The buses can be 8, 16, or 32 bits wide. The read and write data buses must have the same width. Data transfers cannot occur concurrently because the read data and write data buses do not have their own individual handshake signals.
The AI Camera Module is an innovative solution designed to bring cutting-edge AI capabilities to camera systems. Known for its enhanced image quality and AI-based processing, this module integrates seamlessly with a wide array of systems to deliver superior performance in real-time scenarios. It is equipped to handle complex image processing tasks, making it invaluable for applications ranging from security to AI-driven analytics. By incorporating the latest AI advancements into its operation, this module facilitates heightened awareness and analysis capabilities across various sectors. Altek's AI Camera Module emphasizes high-resolution image capture, ensuring that every detail is accurately recorded and processed for precise analysis. This technology not only supports high-definition imaging but also optimizes power consumption, making it suitable for integration into IoT and edge computing environments. Such adaptations are crucial for systems requiring constant, real-time image processing while retaining high operational efficiency. The module's design also promotes adaptability, allowing for custom configurations that meet specific client requirements. Its capability to integrate AI functionalities directly into the camera hardware enhances its appeal in industries focused on automation, surveillance, and smart analytics. This product affirms Altek's role in pioneering technological advancements that align with current and future demands for intelligent, efficient, and scalable solutions.
The Yitian 710 Processor is T-Head's flagship ARM-based server chip that represents the pinnacle of their technological expertise. Designed with a pioneering architecture, it is crafted for high efficiency and superior performance metrics. This processor is built using a 2.5D packaging method, integrating two dies and boasting a substantial 60 billion transistors. The core of the Yitian 710 consists of 128 high-performance Armv9 CPU cores, each accompanied by advanced memory configurations that streamline instruction and data caching processes. Each CPU integrates 64KB of L1 instruction cache, 64KB of L1 data cache, and 1MB of L2 cache, supplemented by a robust 128MB system-level cache on the chip. To support expansive data operations, the processor is equipped with an 8-channel DDR5 memory system, enabling peak memory bandwidth of up to 281GB/s. Its I/O subsystem is formidable, featuring 96 PCIe 5.0 channels capable of achieving dual-direction bandwidth up to 768GB/s. With its multi-layered design, the Yitian 710 Processor is positioned as a leading solution for cloud services, data analytics, and AI operations.
xcore.ai stands as a cutting-edge processor that brings sophisticated intelligence, connectivity, and computation capabilities to a broad range of smart products. Designed to deliver optimal performance for applications in consumer electronics, industrial control, and automotive markets, it efficiently handles complex processing tasks with low power consumption and rapid execution speeds. This processor facilitates seamless integration of AI capabilities, enhancing voice processing, audio interfacing, and real-time analytics functions. It supports various interfacing options to accommodate different peripheral and sensor connections, thus providing flexibility in design and deployment across multiple platforms. Moreover, the xcore.ai ensures robust performance in environments requiring precise control and high data throughput. Its compatibility with a wide array of software tools and libraries enables developers to swiftly create and iterate applications, reducing the time-to-market and optimizing the design workflows.
The Mixel MIPI D-PHY IP (MXL-DPHY) is a high-frequency low-power, low cost, source-synchronous, physical layer compliant with the MIPI® Alliance Standard for D-PHY. (Learn more about Mixel’s MIPI ecosystem at Mixel MIPI Central which gives you access to Mixel’s best of class MIPI ecosystem supply chain partners.) Although primarily used for connecting cameras and display devices to a core processor, this MIPI PHY can also be used for many other applications. It is used in a master-slave configuration, where high-speed signals have a low voltage swing, and low-power signals have large swing. High-speed functions are used for high-speed data traffic while low-power functions are mostly used for control. The D-PHY is partitioned into a Digital Module – CIL (Control and Interface Logic) and a Mixed Signal Module. It is provided as a combination of Soft IP views (RTL, and STA Constraints) for Digital Module, and Hard IP views (GDSII/CDL/LEF/LIB) for the Mixed Signal Module. This unique offering of Soft and Hard IP permits architectural design flexibility and seamless implementation in customer-specific design flow. The CIL module interfaces with the protocol layer and determines the global operation of the lane module. The interface between the D-PHY and the protocol is called the PHY-Protocol Interface (PPI). During normal operation, the data lane switches between low-power mode and high-speed mode. Bidirectional lanes can also switch communication direction. The change of operating mode or direction requires enabling and disabling certain electrical functions. These enable and disable events do not cause glitches on the lines that would otherwise result in detections of incorrect signal levels. Therefore, all mode and direction changes occur smoothly, ensuring proper detection of the line signals. Mixel’s D-PHY is a complete PHY, silicon-proven at multiple foundries and multiple nodes. This MIPI PHY is fully integrated and has analog circuitry, digital, and synthesizable logic. Our D-PHY is built to support the MIPI Camera Serial Interface (CSI) and Display Serial Interface (DSI) using the PHY Protocol Interface (PPI). Mixel has provided this IP in many different configurations to accommodate different applications. The Universal Lane configuration can be used to support any allowed use-case, while other configurations are optimized for many different use cases such as Transmit only, Receive only, DSI, CSI, TX+ and RX+. Both TX+ and RX+ configurations support full-speed loopback operation without the extra area associated with a universal lane configuration.
The Aries fgOTN processor family is engineered according to the ITU-T G.709.20 fgOTN standard. This line of processors handles a variety of signals, including E1/T1, FE/GE, and STM1/STM4, effectively monitoring and managing alarms and performance metrics. Aries processors excel at fine-grain traffic aggregation, efficiently channeling fgODUflex traffic across OTN lines to support Ethernet, SDH, PDH client services. Their capacity to map signals to fgODUflex containers, which are then multiplexed into higher order OTN signals, demonstrates their versatility and efficiency. By allowing cascaded configurations with other Aries devices or Apodis processors, Aries products optimize traffic routes through OTN infrastructures, positioning them as essential components in optical networking and next-generation access scenarios.
The AHB-Lite APB4 Bridge is a critical interconnect component that facilitates communication between AMBA 3 AHB-Lite and AMBA APB bus protocols. This soft IP is parametrically designed, allowing for optimized connections between an AHB-Lite bus master and a range of APB peripherals. Its architecture is focused on providing efficient, low-latency data transfer, supporting streamlined communication in complex SoC designs. Implementing this bridge in a system allows developers to seamlessly integrate a wide variety of peripheral devices, leveraging the simplicity and reduced resource demands of the APB protocol. The design is highly configurable, supporting various data widths and clock domains, enabling precise tailoring to fit the specific needs of any system. By using the AHB-Lite APB4 Bridge, designers can ensure comprehensive and efficient integration of peripherals into larger system-on-chip (SoC) designs, enhancing their functionality and performance.
The GL3590-S is a USB 3.2 Gen 2 Hub Controller designed to provide seamless connectivity via integrated USB Type-C® support. This controller is capable of managing multiple upstream ports, making it ideal for complex data management tasks in modern electronics. Its sophisticated architecture allows for high-speed data transfer, ensuring efficiency in demanding computational environments. Integrated with USB 3.2 Gen 2 hub capabilities, the GL3590-S supports rapid data exchange rates essential for applications needing swift resolution and connectivity. The device plays a crucial role in amplifying the USB connection bandwidth, thereby enhancing the performance and reliability of connected devices. Moreover, this hub controller is equipped with advanced compatibility features, supporting various data transfer protocols. It aims to streamline the integration process across computing platforms, providing a robust solution for today's data-driven ecosystems.
Chimera GPNPU provides a groundbreaking architecture, melding the efficiency of neural processing units with the flexibility and programmability of processors. It supports a full range of AI and machine learning workloads autonomously, eliminating the need for supplementary CPUs or GPUs. The processor is future-ready, equipped to handle new and emerging AI models with ease, thanks to its C++ programmability. What makes Chimera stand out is its ability to manage a diverse array of workloads within a singular processor framework that combines matrix, vector, and scalar operations. This harmonization ensures maximum performance for applications across various market sectors, such as automotive, mobile devices, and network edge systems. These capabilities are designed to streamline the AI development process and facilitate high-performance inference tasks, crucial for modern gadget ecosystems. The architecture is fully synthesizable, allowing it to be implemented in any process technology, from current to advanced nodes, adjusting to desired performance targets. The adoption of a hybrid Von Neuman and 2D SIMD matrix design supports a broad suite of DSP operations, providing a comprehensive toolkit for complex graph and AI-related processing.
RaiderChip's GenAI v1 is a pioneering hardware-based generative AI accelerator, designed to perform local inference at the Edge. This technology integrates optimally with on-premises servers and embedded devices, offering substantial benefits in privacy, performance, and energy efficiency over traditional hybrid AI solutions. The design of the GenAI v1 NPU streamlines the process of executing large language models by embedding them directly onto the hardware, eliminating the need for external components like CPUs or internet connections. With its ability to support complex models such as the Llama 3.2 with 4-bit quantization on LPDDR4 memory, the GenAI v1 achieves unprecedented efficiency in AI token processing, coupled with energy savings and reduced latency. What sets GenAI v1 apart is its scalability and cost-effectiveness, significantly outperforming competitive solutions such as Intel Gaudi 2, Nvidia's cloud GPUs, and Google's cloud TPUs in terms of memory efficiency. This solution maximizes the number of tokens generated per unit of memory bandwidth, thus addressing one of the primary limitations in generative AI workflow. Furthermore, the adept memory usage of GenAI v1 reduces the dependency on costly memory types like HBM, opening the door to more affordable alternatives without diminishing processing capabilities. With a target-agnostic approach, RaiderChip ensures the GenAI v1 can be adapted to various FPGAs and ASICs, offering configuration flexibility that allows users to balance performance with hardware costs. Its compatibility with a wide range of transformers-based models, including proprietary modifications, ensures GenAI v1's robust placement across sectors requiring high-speed processing, like finance, medical diagnostics, and autonomous systems. RaiderChip's innovation with GenAI v1 focuses on supporting both vanilla and quantized AI models, ensuring high computation speeds necessary for real-time applications without compromising accuracy. This capability underpins their strategic vision of enabling versatile and sustainable AI solutions across industries. By prioritizing integration ease and operational independence, RaiderChip provides a tangible edge in applying generative AI effectively and widely.
KPIT Technologies offers comprehensive AUTOSAR solutions that are pivotal for the development of modern, adaptive automotive systems. Emphasizing middleware integration and E/E architecture transformation, their solutions simplify the complexities of implementing adaptive AUTOSAR platforms, enabling streamlined application development and expeditious vehicle deployment. With extensive experience in traditional and adaptive AUTOSAR ecosystems, KPIT assists OEMs in navigating the challenges associated with software-defined vehicles. Their expertise facilitates the separation of hardware and software components, which is crucial for the future of vehicle digital transformation. KPIT's middleware development capabilities enhance vehicle systems' robustness and scalability, allowing for seamless integration across various automotive applications and ensuring compliance with industry standards. By fostering strategic partnerships and investing in cutting-edge technology solutions, KPIT ensures that its clients can confidently transition to and maintain advanced AUTOSAR platforms. The company's commitment to innovation and excellence positions it as a trusted partner for automakers striving to stay ahead in the competitive automotive landscape by embracing the shift towards fully software-defined vehicles.
AMBA AHB is a bus interface designed for high-performance synthesizable applications. It specifies the interface between components such as initiator , interconnects, and targets. AMBA AHB incorporates the features needed for high-performance, high clock frequency systems. The most common AHB targets are internal memory devices, external memory interfaces, and high-bandwidth peripherals.
Intilop offers a sophisticated 10G TCP Offload Engine that integrates MAC, PCIe, and Host IF to deliver ultra-low latency performance. This engine is designed to significantly reduce CPU workload by offloading TCP/IP processing onto the hardware, ensuring faster data transmission with minimal delay. It efficiently supports extensive data flow and high-speed connectivity through its advanced architecture, making it an optimal solution for enterprises seeking high-performance network infrastructure. The engine is specifically engineered to handle up to 10 Gbps speed, maintaining consistent levels of performance even under heavy data loads. Its robust design supports full state offload, checksum offload, and large send offload, making it adept at managing high volumes of data without compromising speed or reliability. By including features like dual 10G SFP+ ports, it offers users flexibility and increased bandwidth, catering to the needs of bandwidth-intensive applications. Additional highlights include zero jitter and the ability to manage multiple sessions simultaneously, thereby enhancing data throughput while minimizing network latency. The integration of features such as kernel bypass and no-CPU-needed architecture underscores its design geared towards efficiency and resource optimization. Ideal for data centers, cloud computing environments, and high-speed network servers, this offload engine is structured to provide significant improvements in cost, space, and overall network infrastructure efficiency.
The NuLink Die-to-Die PHY for Standard Packaging represents Eliyan's cornerstone technology, engineered to harness the power of standard packaging for die-to-die interconnects. This technology circumvents the limitations of advanced packaging by providing superior performance and power efficiencies traditionally associated only with high-end solutions. Designed to support multiple standards, such as UCIe and BoW, the NuLink D2D PHY is an ideal solution for applications requiring high bandwidth and low latency without the cost and complexity of silicon interposers or silicon bridges. In practical terms, the NuLink D2D PHY enables chiplets to achieve unprecedented bandwidth and power efficiency, allowing for increased flexibility in chiplet configurations. It supports a diverse range of substrates, providing advantages in thermal management, production cycle, and cost-effectiveness. The technology's ability to split a Network on Chip (NoC) across multiple chiplets, while maintaining performance integrity, makes it invaluable in ASIC designs. Eliyan's NuLink D2D PHY is particularly beneficial for systems requiring physical separation between high-performance ASICs and heat-sensitive components. By delivering interposer-like bandwidth and power in standard organic or laminate packages, this product ensures optimal system performance across varied applications, including those in AI, data processing, and high-speed computing.
Designed for real-time streaming applications, the ARINC 818 Streaming Core excels in converting pixel bus data into ARINC 818 formatted Fibre Channel serial data streams and vice versa. Ideal for aerospace applications, this core enables seamless data integration and high-speed serial communication, crucial in enhancing the efficiency of avionics systems. Its ability to handle large data formats with precision bolsters its appeal in mission-critical operations.
The bus converter module transforms wide initiator data buses to smaller target data buses or vice-versa. A narrow target on a wide bus, only requires external logic and no internal design changes. * APB: 32-bit wide initiator data buses to 16-bit target data buses. * AHB: 64-bit wide initiator data buses to 32-bit target data buses. * AXI: 256-bit wide initiator data buses to 64-bit target data buses A wide target on a narrow bus, only requires external logic and no internal design changes. * APB: 16-bit wide initiator data buses to 32-bit target data buses. * AHB: 32-bit wide initiator data buses to 64-bit target data buses. * AXI: 64-bit wide initiator data buses to 256-bit target data buses.
iWave Global introduces the ARINC 818 Switch, a pivotal component in the management and routing of video data within avionics systems. Designed for applications that require efficient video data distribution and management, the switch is optimized for performance in environments with stringent data handling requirements. The switch's architecture supports a high level of bandwidth, allowing for the smooth routing of multiple video streams in real-time. Its design includes advanced features that ensure low-latency, error-free data transfer, integral to maintaining the integrity and reliability of video data in critical applications. Featuring robust interoperability characteristics, the ARINC 818 Switch easily integrates into existing systems, facilitating modular expansion and adaptability to new technological standards. It is indispensable for any aerospace project that involves complex video data management, providing a stable platform for video data routing and switching.
The ARINC 818 Product Suite is a comprehensive solution set designed to support the entire lifecycle of ARINC 818 enabled equipment. This suite offers tools and resources essential for developing, qualifying, testing, and simulating ARINC 818 products. It is recognized for its robust design and ability to address the complexities of high-performance avionics systems. Within the product suite, users can access the ARINC 818 Development Suite and Flyable Products, providing a framework for both development and in-field application. The suite is indispensable for organizations aiming to integrate ARINC 818 into their systems, ensuring precise data handling and compatibility. Great River Technology's experience in crafting over 100 mission-critical systems is embedded into the suite, offering unmatched expertise and dependability. By leveraging this suite, companies can ensure the reliable operation and seamless integration of ARINC 818 technologies.
Time-Triggered Ethernet (TTEthernet) is an advanced form of Ethernet designed for applications that require high levels of determinism and redundancy, particularly evident in aerospace and space projects. TTEthernet offers an integrated solution for complex systems that mandates reliable time-sensitive operations, such as those required in human spaceflight where triple redundancy is crucial for mission-critical environments. This technology supports dual fault-tolerance by using triple-redundant networks, ensuring that the system continues to function if failures occur. It's exceptionally suited for systems with rigorous safety-critical requirements and has been employed in ventures like NASA's Orion spacecraft thanks to its robust standard compliance and support for fault-tolerant synchronization protocols. Adhering to the ECSS engineering standards, TTEthernet facilitates seamless integration and enables bandwidth efficiencies that are significant for both onboard and ground-based operations. TTTech's TTEthernet solutions have been further complemented by their proprietary scheduling tools and chip IP offerings, which continue to set industry benchmarks in network precision and dependability.
EXOSTIV is an advanced FPGA capture solution designed to monitor and visualize internal FPGA signals operating at full speed. Particularly focused on providing efficient debugging and validation, EXOSTIV is invaluable for engineers dealing with complex FPGA designs that surpass the capabilities of traditional simulation methods. Its primary advantage lies in enabling full-speed analysis in real-world environments, minimizing production-level FPGA bugs and reducing total engineering costs. With its probe connectivity featuring QSFP28 and various compatible adapters, EXOSTIV ensures seamless integration with existing FPGA chips. It supports up to 4 transceivers at significant bandwidths, allowing comprehensive signal capture. The system's capacity to handle up to 65 Gbps ensures that a vast amount of data can be analyzed and stored, enabling engineers to uncover intricate design issues that would otherwise go unnoticed. EXOSTIV leverages powerful software environments to enhance usability and functionality. It includes tools like the Exostiv Core Inserter, which aids in the generation and modification of IP instances across multiple levels--from RTL to netlist insertion. These capabilities provide users with extensive control over their debug and validation processes, making the EXOSTIV a versatile addition to their FPGA development toolkit.
The Advanced eXtensible Interface(AXI) bus is a high-performance parallel bus that connects on-chip peripheral circuits (or IP blocks) to processor cores. The AXI bus employs "channels" to divide read and write transactions into semi-independent activities that can run at their own pace. The Read Address and Read Data channels send data from the target to the initiator, whereas the Write Address, Write Data, and Write Response channels transfer data from the initiator to the target.
The AHB-Lite Multilayer Switch is a sophisticated interconnect solution designed to support multiple bus masters and slaves within an AMBA AHB-Lite system. It features high performance and low latency, facilitating efficient communication between various system components by providing a flexible interconnection fabric. This architecture can manage a significant number of simultaneous data transfers, optimizing the throughput in complex SoC environments. This switch fabric empowers designers to construct scalable systems with numerous processors and peripherals without compromising on speed or efficiency. Its configurability allows for tailored setups in terms of bus masters and slaves, supporting high-priority traffic schemes for enhanced system operations. By providing a robust and versatile solution, the AHB-Lite Multilayer Switch plays a crucial role in managing data flow, ensuring seamless operation across diverse embedded applications.
Overview: The MIPI I3C Controller IP Core is fully compliant with the latest I3C specification, offering high bandwidth and scalability for integrating multiple sensors into mobile, automotive, and IoT system-on-chips (SoCs). This controller support in-band interrupts within the 2-wire interface, reducing pin count, simplifying board design, and lowering power and system costs. Backward compatibility with I2C ensures future-proof designs, and the controller's operating modes enable efficient connectivity for systems with multiple ICs and sensors on a single I3C bus. The ARM® AMBA® Advanced High-Performance Bus (AHB) facilitates seamless integration of the IP into the SoC. Key Features:  Compliance with MIPI-I3C Basic v1.0  Backward compatibility with I2C  Two-wire serial interface up to 12.5MHz using Push-Pull  Dynamic and Static Addressing support  Single Data Rate messaging (SDR)  Broadcast and Direct Common Command Code (CCC) Messages support  In-Band Interrupt capability  Hot-Join Support Applications:  Consumer Electronics  Defense  Aerospace  Virtual Reality  Augmented Reality  Medical  Biometrics (Fingerprints, etc.)  Automotive Devices  Sensor Devices
Overview: The MIPI CSI-2 (Camera Serial Interface) defines an interface between a peripheral device (camera) and host processor (application engine) for mobile applications. It offers the mobile industry a standard, robust, scalable, low-power, high-speed, and cost-effective interface that supports a wide range of imaging solutions for mobile devices. Key Features:  Compliance with MIPI-CSI-2 version 3.0  Compliance with C-PHY 2.0 for MIPI CSI-2 Version 3.0  Compliance with D-PHY 2.5 for MIPI CSI-2 Version 3.0  Compatibility with I2C and I3C (SDR, DDR) for CCI interface  Support for C-PHY 2.0, D-PHY 2.5, A-PHY, M-PHY with configurable PHY layer  Processor Interfaces: AHB Lite/APB/AXI for configuration  Lane Merging Function for consolidating packet data in CSI-2 Receiver  De-skew detection in D-PHY and sync word detection in C-PHY  Pixel Formats Supported: YUV, RGB, and RAW data  Virtual Channels: 16 for D-PHY, 32 for C-PHY  Error detection, interleaving, scrambling, and descrambling support  Byte to pixel conversion in LLP layer Applications:  Imaging  Surveillance  Gaming  Sensor devices  Internet of Things (IoT)  Wearable devices  Virtual Reality  Augmented Reality  Automotive Systems
The USB PHY offered by Silicon Library Inc. is a high-speed interface solution designed for seamless communication in digital consumer applications. This versatile product supports the USB 2.0 standard, providing an efficient and reliable connection for end-user devices. It ensures quick data transmission rates while maintaining low power consumption, crucial for portable and battery-operated devices. The design of the USB PHY is optimized for integration with other system components, allowing for smooth and efficient data exchanges without bottlenecks. Its compatibility with multiple process nodes ensures that it can be easily incorporated into a variety of product designs, catering to different performance and cost requirements. This product is not only tailored for consumer electronics but also extends its utility to IoT devices and automotive applications where consistent performance and robust connectivity are required. By employing advanced design techniques, the USB PHY achieves a balance between high-speed data transfer and minimal power draw, which is vital for modern electronic solutions.
The Multi-Protocol SERDES offered by Pico Semiconductor is a versatile solution capable of handling a variety of communication protocols. This series of SERDES includes a 4-channel configuration that supports data rates up to 32Gbps, designed for integration with XAUI, RXAUI, and SGMII. It is compatible with multiple process nodes provided by foundries like TSMC and GF, offering robust performance across different semiconductor environments. These SERDES are crafted to meet high-performance metrics, capturing speeds up to 16Gbps and 6.5Gbps across various models, with advanced versions reaching up to 32Gbps. This exceptional range not only ensures compatibility with current technologies but also prepares systems for future updates, sustaining high data throughput. By delivering reliable high-speed data transmission capabilities, the Multi-Protocol SERDES from Pico Semiconductor is integral for networking, high-speed computing, and data storage applications, where efficient and speedy data transfer is paramount.
eSi-Connect offers an extensive suite of AMBA-compliant peripheral IPs designed to streamline SoC integration. This suite encompasses versatile memory controllers, standard off-chip interface support, and essential control functions. Its configurability and compatibility with low-level software drivers make it suitable for real-time deployment in complex system architectures, promoting reliable connectivity across various applications.
With cutting-edge NPU architecture, the KL630 AI SoC pushes the boundaries of performance efficiency and low energy consumption. It stands as a pioneering solution supporting Int4 precision and transformer neural networks, offering noteworthy performance for diverse applications. Anchored by an ARM Cortex A5 CPU, it boasts compute efficiency and energy savings, making it ideal for various edge devices.
The AHB-Lite Timer is a robust timer module compliant with the RISC-V Privileged Specification 1.9.1, designed to provide precise timing and control within a system. This module is an integral part of complex SoC designs where accurate timing functions are essential. Its design offers flexibility and precision, making it ideal for a range of applications that demand reliable timekeeping and event management. The timer supports various counting modes and functions, allowing users to define cycles and generate interrupts based on time-based events. Its versatility and adaptability make it an indispensable component in managing scheduling and timing tasks within embedded systems. By integrating the AHB-Lite Timer, designers can enhance system efficiency and performance, ensuring responsive and accurate operational outcomes.
The CT25205 is a robust digital IP core designed for IEEE 802.3cg 10BASE-T1S Ethernet Physical Layer. It includes PMA, PCS, and PLCA Reconciliation Sublayer blocks, enhancing compatibility with standard IEEE MACs via the MII. Featuring a fully synthesizable Verilog design, it is deployable on standard cells and FPGAs. With integrated PLCA RS, this IP provides advanced features without necessitating additional extensions, making it a vital component for Zonal Gateways SoCs.
The Secondary/Slave PHY by Green Mountain Semiconductor, designed for LPDDR4/4X/5 applications, focuses on enhancing the flexibility and scalability of memory systems. This PHY works in conjunction with primary controllers to expand memory configurations, aiding in the efficient management of complex networking and computing architectures. Engineered to support seamless extension of memory systems, it plays a pivotal role in augmenting the system’s capacity to handle larger data loads without sacrificing speed or efficiency. By providing reliable secondary data paths, it ensures balanced load distribution and enhanced system reliability under varying workloads. The Secondary/Slave PHY is particularly effective in high-performance environments where system robustness and memory accessibility are key. Its integration into platforms demands a nuanced approach to memory management, ensuring continuous and high-performance operations in diverse application landscapes.
EW6181 is an IP solution crafted for applications demanding extensive integration levels, offering flexibility by being licensable in various forms such as RTL, gate-level netlist, or GDS. Its design methodology focuses on delivering the lowest possible power consumption within the smallest footprint. The EW6181 effectively extends battery life for tags and modules due to its efficient component count and optimized Bill of Materials (BoM). Additionally, it is backed by robust firmware ensuring highly accurate and reliable location tracking while offering support and upgrades. The IP is particularly suitable for challenging application environments where precision and power efficiency are paramount, making it adaptable across different technology nodes given the availability of its RF frontend.
With a focus on maintaining signal integrity in high-speed interfaces, the PCIe Retimer extends the reach of PCI Express connections while preserving data quality. Essential for long signal paths, it works by regenerating signals to boost performance and provide reliable connections across distances. The retimer is particularly effective in environments with substantial electromagnetic interference, ensuring data transmission remains error-free and efficient across extended cable runs. By including line equalization and using advanced clock recovery techniques, the PCIe Retimer strengthens signal quality, allowing for greater system performance and reliability in a wide array of computing applications.
The PDM-to-PCM Converter from Archband Labs leads in transforming pulse density modulation signals into pulse code modulation signals. This converter is essential in applications where high fidelity of audio signal processing is vital, including digital audio systems and communication devices. Archband’s solution ensures accurate conversion, preserving the integrity and clarity of the original audio. This converter is crafted to seamlessly integrate with a wide array of systems, offering flexibility and ease-of-use in various configurations. Its robust design supports a wide range of input frequencies, making it adaptable to different signal environments. The PDM-to-PCM Converter also excels in minimizing latency and reducing overhead processing times. It’s engineered for environments where precision and sound quality are paramount, ensuring that audio signals remain crisp and undistorted during conversion processes.
Silicon Creations crafts highly reliable LVDS interfaces designed to meet diverse application needs, going from bi-directional I/Os to specialized uni-directional configurations. Spanning process compatibilities from 90nm CMOS to advanced 7nm FinFET, these interfaces are a cornerstone for high-speed data communication systems, thriving particularly in video data transmission and chip-to-chip communications. Supporting robust data rates over multiple channels, the LVDS Interfaces guarantee flexible programmability and protocol compatibility with standards such as FPD-Link and Camera-Link. They capitalize on proven PLL and CDR architectures for superior signal integrity and error-free data transfers. Operating efficiently in various technology nodes, they remain highly effective across collaborative chipset environments. The interfaces are fortified with adaptable features like dynamic phase alignment to stabilize data sequences and on-die termination options for superior signal integrity. Their proven record places them as a critical enabler in applications where consistent high-speed data transfer is paramount, demonstrating Silicon Creations’ prowess in delivering industry-leading communication solutions.
Designed for high-speed transmission, the 16x112G Tx Chiplet showcases superior integration with 16 channels, each operating at 112Gbps. It includes a modulator and driver within a single silicon unit, optimized for optical communication systems requiring high-speed, high-bandwidth data transfer. This sophisticated chiplet ensures seamless modulation of optical signals, supporting efficient driver control and optimized data transmission. The integrated design simplifies system architecture, reducing the overall footprint while maintaining exceptional reliability and performance. Its built-in digital control aids in managing complex signal processing requirements, suitable for diverse applications within optical networking infrastructures. Verifying its design through silicon-proven processes assures users of its capability to meet rigorous industry standards. The application of this chiplet spans high-speed data centers, telecommunications networks, and beyond, where its efficiency and performance are indispensable. The innovation behind its creation reflects Enosemi's dedication to advancing optical technology, offering clients robust and reliable tools to meet current and future communication needs.
Overview: The MIPI DSI Transmitter IP is designed to transmit data to the host processor, providing the mobile industry with a standard, robust, scalable, low-power, high-speed, and cost-effective interface that supports a wide range of imaging solutions for mobile devices. Key Features:  Compliance with MIPI-DSI-2 version 2.0  Compliance with C-PHY version 2.0 for DSI-2 Version-2  Compliance with D-PHY version 1.2 for DSI-2 Version-2.0  Compliance with D-PHY version 2.0 for DSI-2 Version-2.0  Compliance with D-PHY version 3.0 for DSI-2 Version-2.0  Compliance with MIPI SDF specification  Compliance with DBI-2 and DPI-2  Pixel to Byte conversion support from Application layer to LLP layer  Support for Command Mode and Video Mode  Continuous clock behavior in clock lane for D-PHY physical layer  De-skew sequence pattern for video mode support  Lane Distribution Function for distributing packet bytes across N-Lanes  Connectivity with two, three, or four DSI Receivers  HS mode and Escape mode support for transmission of Packets in both C-PHY and D-PHY  Symbol slip detection code and sync symbol insertion in C-PHY physical layer Target Applications:  Imaging  Surveillance  Gaming  Sensor devices  Internet of Things (IoT)  Wearable devices  Virtual Reality  Augmented Reality  Automotive Systems
Overview: The SPD5 Hub controller IP is designed to interface with the I3C/I2C Host Bus, allowing for the isolation of local devices such as Temperature Sensors (TS) from the master host bus. It features a Two-wire serial interface with SCL and SDA busses. Key Features:  Compliance with JEDEC's JESD300-5  Support for speeds up to 12.5MHz  Bus Reset functionality  SDA arbitration support  Enabled Parity Check  Support for Packet Error Check (PEC)  Switch between I2C and I3C Basic Mode  Default Read address pointer Mode  Write and read operations for SPD5 Hub with or without PEC  In-band Interrupt (IBI) support  Write Protection for NVM memory blocks  Arbitration for Interrupts  Clearing of Device Status and IBI Status Registers  Error handling for Packet Error Check and Parity Errors  Common Command Codes (CCC) for I3C Basic Mode  Dynamic IO Operation Mode Switching  Bus Clear and Bus Reset capabilities  SPD5 Command features for NVM memory and Register Space  Read and Write access to NVM memory  Support for Offline Tester operation Applications:  DDR5 DIMM Application Environment  DDR5 NVDIMM Application Environment  Automotive Devices  Memory Devices  Power Management Devices  Defense/Aerospace/Customer Electronics
The Apodis family of Optical Transport Network processors adheres to ITU-T standards, offering a comprehensive suite for signal termination, processing, and multiplexing. Designed to handle both SONET/SDH and Ethernet client services, these processors map signals to Optical Transport Network (OTN), empowering versatile any-port, any-service configurations. Apodis processors are notable for their capacity to support up to 16 client ports and four 10G OTN line ports, delivering bandwidth scalability up to 40G, crucial for wireless backhaul and fronthaul deployments. With a robust, non-blocking OTN switching fabric, Apodis facilitates seamless client-to-line and line-to-line connections while optimally managing network bandwidth. This adaptability makes the Apodis processors an ideal choice for next-generation access networks and optical infrastructures.
The HOTLink II Product Suite is engineered to deliver advanced capabilities in high-speed data and video link technologies. It serves as an essential toolset for developing and implementing HOTLink II protocols effectively, catering to the specific needs of modern avionics systems requiring reliable and high-throughput data transfer. This suite includes various components that enable the seamless transmission and conversion of data, supporting both development and operational phases. Its design incorporates technologies that enhance data integrity and efficiency, making it integral to systems where performance and reliability are critical. Great River Technology ensures that each component of the HOTLink II suite is crafted with precision, providing comprehensive support and simplifying integration processes. The suite redounds to the extensive expertise of Great River Technology in the sector, reinforcing their standing as providers of pioneering solutions.
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