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Yorchip Inc.

Yorchip Inc. stands at the forefront of semiconductor innovations with their advanced PHY solutions that cater to both standard and specialized packaging options, including costly interposers. With a focus on ultra-low power consumption and cost-effectiveness, their PHY supports cutting-edge packaging techniques down to a 20-micron pitch. This innovative approach enables significant reductions in area, power, and overall costs, which in turn accelerates the deployment of next-gen solutions for a variety of markets. The company's commitment to revolutionizing the edge market is evident in their development of budget-friendly Chiplets. These compact silicon solutions, often priced below $0.50 in large volumes, facilitate swift integration for components like CPUs and ADCs across multiple applications. Furthermore, Yorchip's proprietary technology optimizes the UCIe standard—originally targeted at high-performance computing and data center environments—for broader commercial adoption, ensuring cost and power efficiency. Yorchip's innovations do not stop at cost-effectiveness and power savings. The company emphasizes scalability and reusability of chiplets, enabling customers to customize their silicon designs effectively. By integrating low-cost, off-the-shelf chiplets, companies can focus more on refining their core designs, all while leveraging Yorchip's packaging technologies to achieve greater efficiency in mass markets. Read more

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Universal PHY Technology

The Universal PHY Technology developed by Yorchip Inc. serves as a cornerstone in offering advanced packaging solutions suitable for both standard interface technologies and bespoke interposer designs. This PHY is characterized by its micro-pitch compatibility, going as low as 20 microns, which substantially enhances its applicability in high-density packaging scenarios. Its low-power design requires less than 0.1 picojoules per bit during operation, making it a preferred choice for energy-conscious applications. This PHY solution is specifically engineered for efficiency, utilizing a 20X reduced area compared to conventional UCIe SP offerings. It includes Built-In Self-Test (BIST) features for Known Good Dies (KGD), ensuring robust quality assurance. Moreover, the technology covers a broad spectrum of foundry support, adaptable from older 28nm processes to modern advanced FinFet nodes, underscoring its versatility and adaptability to various technological needs. Yorchip’s Universal PHY Technology is particularly advantageous for those aiming to deploy accessible, high-volume chiplets that are both cost-efficient and capable of rapid market integration. By employing this technology, companies can significantly streamline their product development cycles and reduce overall deployment costs, enabling them to swiftly respond to market demands with chiplets tailored for mass-market use cases.

Yorchip Inc.
TSMC
12nm FinFET, 28nm
Multi-Protocol PHY
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