All IPs > Interface Controller & PHY > MIPI
The MIPI category under Interface Controller & PHY encompasses a broad range of semiconductor IPs tailored for high-speed data transfer between components in mobile and IoT devices. MIPI, which stands for Mobile Industry Processor Interface, is an industry-driven standard aimed at simplifying the integration of different advanced technologies into small form factor devices while ensuring optimal communication efficiency and power consumption.
Within this category, you will find semiconductor IPs that address the critical need for reducing latency and increasing the bandwidth of data communication across various internal components. These MIPI interfaces are vital in smartphones, tablets, and other portable electronics, where space is at a premium, yet there's a demand for high-performance data exchange and energy efficiency. The IPs provide solutions for connecting processors to modems, sensors, displays, and cameras, enabling manufacturers to build devices with faster data processing capabilities and higher battery life.
MIPI semiconductor IPs in this category include MIPI D-PHY, C-PHY, and M-PHY, among others. These IPs are designed to support versatile and scalable designs, allowing for personalization depending on the specific requirements of the end product. MIPI D-PHY, for instance, is often used in applications requiring video transmission with high-quality imaging sensors, providing a robust method to deliver both power and data through the same interface.
By leveraging MIPI semiconductor IPs, designers can ensure that their products adhere to the latest industry standards, providing a competitive edge in the technology market. These IPs support a seamless interface experience, enhance data transmission efficiencies, and reduce both development time and costs. Integrating MIPI interface controller and PHY solutions will drive innovation and bring sophisticated electronic products to market faster and more efficiently than ever before.
The Mixel MIPI C-PHY IP (MXL-CPHY) is a high-frequency, low-power, low cost, physical layer. (Learn more about Mixel’s MIPI ecosystem at Mixel MIPI Central which gives you access to Mixel’s best of class MIPI ecosystem supply chain partners.) The C-PHY configuration consists of up to three lane modules and is based on 3-Phase symbol encoding technology, delivering 2.28 bits per symbol over three-wire trios and targeting a maximum rate of 2.5 Gsps, 5.7Gbps. The C-PHY is partitioned into a digital module – CIL (Control and Interface Logic) and a mixed-signal module. The PHY IP is provided as a combination of soft IP views (RTL, and STA Constraints) for the digital module, and hard IP views (GDSII/CDL/LEF/LIB) for the mixed-signal module. This unique offering of both soft and hard IP permits architectural design flexibility and seamless implementation in customer-specific design flow. The CIL module interfaces with the protocol layer and determines the global operation of the module. The interface between the PHY and the protocol is using the PHY-Protocol Interface (PPI). The mixed-signal module includes high-speed signaling mode for fast-data traffic and low-power signaling mode for control purposes. During normal operation, a lane switches between low-power and high-speed mode. Bidirectional lanes can also switch communication direction. The change of operating mode or direction requires enabling and disabling of certain electrical functions. These enable and disable events do not cause glitches on the lines that would result in a detection of incorrect signal levels. All mode and direction changes are smooth to always ensure a proper detection of the line signals. Mixel’s C-PHY is a complete PHY, silicon-proven at multiple foundries and multiple nodes. It is built to support the MIPI Camera Serial Interface (CSI) and Display Serial Interface (DSI).
Silicon Creations' SerDes Interfaces are crafted to handle high-speed data transmission challenges over varied processes, ranging from 12nm to 180nm. Addressing multiple protocols such as CPRI, PCIe, and SATA, these interfaces demonstrate flexibility by supporting data transmission speeds from 100 Mbps to beyond 32 Gbps. The architecture incorporates a host of advanced features including adaptive equalization techniques and programmable de-serialization widths, making it stand out in terms of performance and signal integrity even under challenging conditions. With ultra-low latency PMAs, they sustain excellent operational speed and efficiency, imperative for sophisticated communication applications. Moreover, Silicon Creations partners with leading entities to provide comprehensive solutions, including complete PCIe PHY integrations. This synergy ensures that SerDes Interfaces are fully optimized for operational excellence, delivering stable and reliable communication signals. With an emphasis on low power and minimized area requirements, they cater to burgeoning industry needs for power-efficient and space-conservative designs.
The Mixel MIPI C/D-PHY combo IP (MXL-CPHY-DPHY) is a high-frequency low-power, low cost, physical layer compliant with the MIPI® Alliance Standard for C-PHY and D-PHY. (Learn more about Mixel’s MIPI ecosystem at Mixel MIPI Central which gives you access to Mixel’s best of class MIPI ecosystem supply chain partners.) The PHY can be configured as a MIPI Master or MIPI Slave, supporting camera interface CSI-2 v1.2 or display interface DSI v1.3 applications in the D-PHY mode. It also supports camera interface CSI-2 v1.3 and display interface DSI-2 v1.0 applications in the C-PHY mode. The high-speed signals have a low voltage swing, while low-power signals have large swing. High-Speed functions are used for high-speed data traffic while low-power functions are mostly used for control. The C-PHY is based on 3-Phase symbol encoding technology, delivering 2.28 bits per symbol over three-wire trios, operating with a symbol rate range of 80 to 4500 Msps per lane, which is the equivalent of about 182.8 to 10260 Mbps per lane. The D-PHY supports a bit rate range of 80 to 1500 Mbps per Lane without deskew calibration, and up to 4500 Mbps with deskew calibration. The low-power mode and escape mode are the same in both the D-PHY and C-PHY modes. To minimize EMI, the drivers for low-power mode are slew-rate controlled and current limited. The data rate in low-power mode is 10 Mbps. For a fixed clock frequency, the available data capacity of a PHY configuration can be increased by using more lanes. Effective data throughput can be reduced by employing burst mode communication. Mixel’s C-PHY/D-PHY combo is a complete PHY, silicon-proven at multiple foundries and multiple nodes. The C/D-PHY is fully integrated and has analog circuitry, digital, and synthesizable logic.
The Mixel MIPI D-PHY IP (MXL-DPHY) is a high-frequency low-power, low cost, source-synchronous, physical layer compliant with the MIPI® Alliance Standard for D-PHY. (Learn more about Mixel’s MIPI ecosystem at Mixel MIPI Central which gives you access to Mixel’s best of class MIPI ecosystem supply chain partners.) Although primarily used for connecting cameras and display devices to a core processor, this MIPI PHY can also be used for many other applications. It is used in a master-slave configuration, where high-speed signals have a low voltage swing, and low-power signals have large swing. High-speed functions are used for high-speed data traffic while low-power functions are mostly used for control. The D-PHY is partitioned into a Digital Module – CIL (Control and Interface Logic) and a Mixed Signal Module. It is provided as a combination of Soft IP views (RTL, and STA Constraints) for Digital Module, and Hard IP views (GDSII/CDL/LEF/LIB) for the Mixed Signal Module. This unique offering of Soft and Hard IP permits architectural design flexibility and seamless implementation in customer-specific design flow. The CIL module interfaces with the protocol layer and determines the global operation of the lane module. The interface between the D-PHY and the protocol is called the PHY-Protocol Interface (PPI). During normal operation, the data lane switches between low-power mode and high-speed mode. Bidirectional lanes can also switch communication direction. The change of operating mode or direction requires enabling and disabling certain electrical functions. These enable and disable events do not cause glitches on the lines that would otherwise result in detections of incorrect signal levels. Therefore, all mode and direction changes occur smoothly, ensuring proper detection of the line signals. Mixel’s D-PHY is a complete PHY, silicon-proven at multiple foundries and multiple nodes. This MIPI PHY is fully integrated and has analog circuitry, digital, and synthesizable logic. Our D-PHY is built to support the MIPI Camera Serial Interface (CSI) and Display Serial Interface (DSI) using the PHY Protocol Interface (PPI). Mixel has provided this IP in many different configurations to accommodate different applications. The Universal Lane configuration can be used to support any allowed use-case, while other configurations are optimized for many different use cases such as Transmit only, Receive only, DSI, CSI, TX+ and RX+. Both TX+ and RX+ configurations support full-speed loopback operation without the extra area associated with a universal lane configuration.
Intilop's 10G TCP Offload Engine (TOE) offers an advanced solution integrating MAC, PCIe, and Host Interface to deliver ultra-low latency network performance. This solution is crafted for environments requiring high-speed data transmission and minimal delays, ensuring a robust system for demanding networking tasks. With its capability for full TCP stack implementation, the TOE handles up to 16,000 concurrent sessions, operating with remarkably low latency and without the need for additional CPU processing.\n\nThe engine's design incorporates key features like zero jitter, dual 10G ports, and extensive offloading capabilities including checksum offload and large send offload. It supports multiple DMA engines, ensuring high throughput across varied network conditions. The architecture is highly adaptable, offering both hardware and software customization options to suit specific customer requirements, leveraging Intilop's expertise in FPGA and SoC design.\n\nThis IP is deployed globally, supporting configurations in cloud computing, data centers, and high-performance computing environments. Its ability to offload significant networking tasks from the CPU allows enterprises to maximize application performance while minimizing power consumption and system costs, delivering a comprehensive network acceleration solution. The product is part of Intilop's extensive portfolio, designed to enhance network throughput and efficiency while significantly reducing processing overhead.
The NuLink Die-to-Die PHY for Standard Packaging represents Eliyan's cornerstone technology, engineered to harness the power of standard packaging for die-to-die interconnects. This technology circumvents the limitations of advanced packaging by providing superior performance and power efficiencies traditionally associated only with high-end solutions. Designed to support multiple standards, such as UCIe and BoW, the NuLink D2D PHY is an ideal solution for applications requiring high bandwidth and low latency without the cost and complexity of silicon interposers or silicon bridges. In practical terms, the NuLink D2D PHY enables chiplets to achieve unprecedented bandwidth and power efficiency, allowing for increased flexibility in chiplet configurations. It supports a diverse range of substrates, providing advantages in thermal management, production cycle, and cost-effectiveness. The technology's ability to split a Network on Chip (NoC) across multiple chiplets, while maintaining performance integrity, makes it invaluable in ASIC designs. Eliyan's NuLink D2D PHY is particularly beneficial for systems requiring physical separation between high-performance ASICs and heat-sensitive components. By delivering interposer-like bandwidth and power in standard organic or laminate packages, this product ensures optimal system performance across varied applications, including those in AI, data processing, and high-speed computing.
Time-Triggered Ethernet is a cutting-edge networking technology designed to bring real-time capabilities to Ethernet networks. It enhances standard Ethernet by incorporating time-triggered mechanisms, which support synchronized data transmission across network nodes. This is important in industries such as aerospace and automotive, where precise timing and reliable data transmission are essential for safe operations.
Overview: The MIPI CSI-2 (Camera Serial Interface) defines an interface between a peripheral device (camera) and host processor (application engine) for mobile applications. It offers the mobile industry a standard, robust, scalable, low-power, high-speed, and cost-effective interface that supports a wide range of imaging solutions for mobile devices. Key Features: Compliance with MIPI-CSI-2 version 3.0 Compliance with C-PHY 2.0 for MIPI CSI-2 Version 3.0 Compliance with D-PHY 2.5 for MIPI CSI-2 Version 3.0 Compatibility with I2C and I3C (SDR, DDR) for CCI interface Support for C-PHY 2.0, D-PHY 2.5, A-PHY, M-PHY with configurable PHY layer Processor Interfaces: AHB Lite/APB/AXI for configuration Lane Merging Function for consolidating packet data in CSI-2 Receiver De-skew detection in D-PHY and sync word detection in C-PHY Pixel Formats Supported: YUV, RGB, and RAW data Virtual Channels: 16 for D-PHY, 32 for C-PHY Error detection, interleaving, scrambling, and descrambling support Byte to pixel conversion in LLP layer Applications: Imaging Surveillance Gaming Sensor devices Internet of Things (IoT) Wearable devices Virtual Reality Augmented Reality Automotive Systems
The Multi-Protocol SERDES offered by Pico Semiconductor is a versatile solution capable of handling a variety of communication protocols. This series of SERDES includes a 4-channel configuration that supports data rates up to 32Gbps, designed for integration with XAUI, RXAUI, and SGMII. It is compatible with multiple process nodes provided by foundries like TSMC and GF, offering robust performance across different semiconductor environments. These SERDES are crafted to meet high-performance metrics, capturing speeds up to 16Gbps and 6.5Gbps across various models, with advanced versions reaching up to 32Gbps. This exceptional range not only ensures compatibility with current technologies but also prepares systems for future updates, sustaining high data throughput. By delivering reliable high-speed data transmission capabilities, the Multi-Protocol SERDES from Pico Semiconductor is integral for networking, high-speed computing, and data storage applications, where efficient and speedy data transfer is paramount.
Overview: The MIPI I3C Controller IP Core is fully compliant with the latest I3C specification, offering high bandwidth and scalability for integrating multiple sensors into mobile, automotive, and IoT system-on-chips (SoCs). This controller support in-band interrupts within the 2-wire interface, reducing pin count, simplifying board design, and lowering power and system costs. Backward compatibility with I2C ensures future-proof designs, and the controller's operating modes enable efficient connectivity for systems with multiple ICs and sensors on a single I3C bus. The ARM® AMBA® Advanced High-Performance Bus (AHB) facilitates seamless integration of the IP into the SoC. Key Features: Compliance with MIPI-I3C Basic v1.0 Backward compatibility with I2C Two-wire serial interface up to 12.5MHz using Push-Pull Dynamic and Static Addressing support Single Data Rate messaging (SDR) Broadcast and Direct Common Command Code (CCC) Messages support In-Band Interrupt capability Hot-Join Support Applications: Consumer Electronics Defense Aerospace Virtual Reality Augmented Reality Medical Biometrics (Fingerprints, etc.) Automotive Devices Sensor Devices
The CT25205 digital core serves as a comprehensive solution for implementing the IEEE 802.3cg® 10BASE-T1S Ethernet Physical Layer. Crafted in Verilog 2005 HDL, this synthesizable core adapts elegantly to standard cells and FPGA environments. It incorporates critical components like the PMA, PCS, and PLCA Reconciliation Sublayer, working seamlessly with any Ethernet MAC conforming to the IEEE CSMA/CD standards using the MII interface. A unique feature of CT25205 is its integrated PLCA RS, which enables existing MAC devices to access PLCA functionalities without further hardware modifications. This digital core also features connectivity with a standard OPEN Alliance 10BASE-T1S PMD interface, making it pivotal in enhancing communication for Zonal Gateway SoCs and MCUs that demand advanced 10BASE-T1S capabilities.
Overview: The SPD5 Hub controller IP is designed to interface with the I3C/I2C Host Bus, allowing for the isolation of local devices such as Temperature Sensors (TS) from the master host bus. It features a Two-wire serial interface with SCL and SDA busses. Key Features: Compliance with JEDEC's JESD300-5 Support for speeds up to 12.5MHz Bus Reset functionality SDA arbitration support Enabled Parity Check Support for Packet Error Check (PEC) Switch between I2C and I3C Basic Mode Default Read address pointer Mode Write and read operations for SPD5 Hub with or without PEC In-band Interrupt (IBI) support Write Protection for NVM memory blocks Arbitration for Interrupts Clearing of Device Status and IBI Status Registers Error handling for Packet Error Check and Parity Errors Common Command Codes (CCC) for I3C Basic Mode Dynamic IO Operation Mode Switching Bus Clear and Bus Reset capabilities SPD5 Command features for NVM memory and Register Space Read and Write access to NVM memory Support for Offline Tester operation Applications: DDR5 DIMM Application Environment DDR5 NVDIMM Application Environment Automotive Devices Memory Devices Power Management Devices Defense/Aerospace/Customer Electronics
Overview: The MIPI DSI Transmitter IP is designed to transmit data to the host processor, providing the mobile industry with a standard, robust, scalable, low-power, high-speed, and cost-effective interface that supports a wide range of imaging solutions for mobile devices. Key Features: Compliance with MIPI-DSI-2 version 2.0 Compliance with C-PHY version 2.0 for DSI-2 Version-2 Compliance with D-PHY version 1.2 for DSI-2 Version-2.0 Compliance with D-PHY version 2.0 for DSI-2 Version-2.0 Compliance with D-PHY version 3.0 for DSI-2 Version-2.0 Compliance with MIPI SDF specification Compliance with DBI-2 and DPI-2 Pixel to Byte conversion support from Application layer to LLP layer Support for Command Mode and Video Mode Continuous clock behavior in clock lane for D-PHY physical layer De-skew sequence pattern for video mode support Lane Distribution Function for distributing packet bytes across N-Lanes Connectivity with two, three, or four DSI Receivers HS mode and Escape mode support for transmission of Packets in both C-PHY and D-PHY Symbol slip detection code and sync symbol insertion in C-PHY physical layer Target Applications: Imaging Surveillance Gaming Sensor devices Internet of Things (IoT) Wearable devices Virtual Reality Augmented Reality Automotive Systems
The HOTLink II Product Suite from Great River Technology exemplifies a high-performance video and data communication solution, tailored to meet the demanding requirements of aerospace applications. This suite is designed to facilitate the seamless transfer of high-speed data using the HOTLink II protocol, supporting the implementation of systems that require synchronization and reliability. With its focus on bridging video interfaces efficiently, Great River Technology provides a formidable toolset for avionics engineers looking to streamline their data communication systems. Leveraging the HOTLink II suite, users can expect a credible solution that offers both adaptability and robust performance, capable of integrating into a multitude of platforms. Great River Technology's commitment to technical excellence delivers a product suite that not only caters to current industry needs but is also adaptable for future advancements within the domain of video data exchange systems. By combining the tools and expertise offered in this suite, clients can develop, test, and implement HOTLink II systems that enhance communication capabilities within their network infrastructure. The suite is backed by comprehensive support to ensure optimal performance in all stages of product deployment, making it a vital component in achieving strategic communication objectives in aerospace technology.
MIPI I3C Controller IP Core is fully compliant with the latest I3C specification and delivers high bandwidth and scalability for integration of multiple sensors into mobile, automotive and IoT system-on-chips (SoCs). The MIPI I3C Controller supports in-band interrupts within the 2-wire interface provides significantly lower pin count, simplifying board design and reducing power and cost of the system. The MIPI I3C Controller IP is fully backward compatible with I2C, allowing designers to future proof their design, and the I3C controller IP operating modes enable systems with several ICs to efficiently connect to all sensors on a single I3C bus. The standard-based ARM® AMBA® Advanced High Performance Bus (AHB) connects the IP to the rest of the SoC offering easy IP integration. MIPI I3C Controller IP is designed to easily integrate into any SoC offering lowest gate count and quickly fit into any Chip development flow.
Silicon Creations crafts highly reliable LVDS interfaces designed to meet diverse application needs, going from bi-directional I/Os to specialized uni-directional configurations. Spanning process compatibilities from 90nm CMOS to advanced 7nm FinFET, these interfaces are a cornerstone for high-speed data communication systems, thriving particularly in video data transmission and chip-to-chip communications. Supporting robust data rates over multiple channels, the LVDS Interfaces guarantee flexible programmability and protocol compatibility with standards such as FPD-Link and Camera-Link. They capitalize on proven PLL and CDR architectures for superior signal integrity and error-free data transfers. Operating efficiently in various technology nodes, they remain highly effective across collaborative chipset environments. The interfaces are fortified with adaptable features like dynamic phase alignment to stabilize data sequences and on-die termination options for superior signal integrity. Their proven record places them as a critical enabler in applications where consistent high-speed data transfer is paramount, demonstrating Silicon Creations’ prowess in delivering industry-leading communication solutions.
The Titanium Ti375 FPGA presents an advanced solution ideal for developers seeking high-density, low-power configurations. Within its design is Efinix's Quantum compute fabric, which offers superior computational efficiency bundled with a robust I/O interface. Highlighting its versatility, the Ti375 incorporates a hardened RISC-V block, facilitating complex data processing tasks without confining power usage. Additionally, features such as a SerDes transceiver and LPDDR4 DRAM controller mark it as a powerful asset in high-demand environments, ensuring smooth and reliable data transactions. Further empowering its capability is an integrated MIPI D-PHY, making it particularly well-suited for modern applications demanding high-speed data exchange and connectivity.
Arasan's MIPI DSI-2 Transmitter IP is tailored for high-definition display panel interfaces, facilitating smooth and efficient data transmission from graphics processors to display modules. It implements the MIPI DSI protocol, supporting the seamless transfer of pixel data for vibrant visual outputs. This transmitter IP is optimized for high bandwidth and low power consumption, ideal for use in cutting-edge displays found in mobile devices, gaming consoles, and IoT devices.
The C100 is a highly integrated SoC designed for IoT applications, boasting efficient control and connectivity features. It is powered by an enhanced 32-bit RISC-V CPU running at up to 1.5GHz, making it capable of tackling demanding processing tasks while maintaining low power consumption. The inclusion of embedded RAM and ROM further enriches its computational prowess and operational efficiency. Equipped with integrated Wi-Fi, the C100 facilitates seamless wireless communication, making it ideal for varied IoT applications. It supports multiple types of transmission interfaces and features key components such as an ADC and LDO, enhancing its versatility. The C100 also offers built-in temperature sensors, providing higher integration levels for simplified product designs across security systems, smart homes, toys, healthcare, and more. Aiming to offer a compact form factor without compromising on performance, the C100 is engineered to help developers rapidly prototype and bring to market devices that are safe, stable, and efficient. Whether for audio, video, or edge computing tasks, this single-chip solution embodies the essence of Chipchain's commitment to pioneering in the IoT domain.
Overview: The MIPI CSI-2 (Camera Serial Interface) Transmitter IP establishes an interface between a peripheral device (camera) and host processor (application engine) for mobile applications. It offers the mobile industry a standard, robust, scalable, low-power, high-speed, and cost-effective interface that caters to a wide range of imaging solutions for mobile devices. Key Features: Compliance with MIPI-CSI-2 version 3.0 Compliance with C-PHY 2.0 for MIPI CSI-2 Version 3.0 Compliance with D-PHY 2.5 for MIPI CSI-2 Version 3.0 Compatibility with I2C and I3C (SDR, DDR) for CCI interface Pixel to Byte conversion support from Application layer to LLP layer Continuous clock behavior in clock lane for D-PHY physical layer De-skew sequence pattern in Data Lane Module Lane Distribution Function for distributing packet bytes across N-Lanes Sync word insertion through PPI command in C-PHY physical layer Insertion of Filler bytes in LLP layer for packet footer alignment Setting specific bits in packet header Defining frame blanking period Seed selection in scrambler and de-scrambler by Sync word Support for C-PHY/D-PHY/A-PHY/M-PHY with one PHY layer configuration Target Applications: Imaging Surveillance Gaming Sensor devices Internet of Things (IoT) Wearable devices Virtual Reality Augmented Reality Automotive Systems
The Mixel MIPI M-PHY (MXL-MPHY) is a high-frequency low-power, Physical Layer IP that supports the MIPI® Alliance Standard for M-PHY. (Learn more about Mixel’s MIPI ecosystem at Mixel MIPI Central which gives you access to Mixel’s best of class MIPI ecosystem supply chain partners.) The IP can be used as a physical layer for many applications, connecting flash memory-based storage, cameras and RF subsystems, and for providing chip-to-chip inter-processor communications (IPC). It supports MIPI UniPro and JEDEC Universal Flash Storage (UFS) standard. By using efficient BURST mode operation with scalable speeds, significant power savings can be obtained. Selection of signal slew rate and amplitude allows reduction of EMI/RFI, while maintaining low bit error rates.
The THOR platform is a versatile tool for developing application-specific NFC sensor and data logging solutions. It incorporates silicon-proven IP blocks, creating a comprehensive ASIC platform suitable for rigorous monitoring and continuous data logging applications across various industries. THOR is designed for accelerated development timelines, leveraging low power and high-security features. Equipped with multi-protocol NFC capabilities and integrated temperature sensors, the THOR platform supports a wide range of external sensors, enhancing its adaptability to diverse monitoring needs. Its energy-efficient design allows operations via energy harvesting or battery power, ensuring sustainability in its applications. This platform finds particular utility in sectors demanding precise environmental monitoring and data management, such as logistics, pharmaceuticals, and industrial automation. The platform's capacity for AES/DES encrypted data logging ensures secure data handling, making it a reliable choice for sectors with stringent data protection needs.
The Time-Triggered Protocol (TTP) is an innovative real-time communications protocol used primarily in space and aviation networks. TTP ensures synchronized communication across various nodes in a network, providing deterministic message delivery, which is crucial in systems where timing and reliability are critical. By supporting highly dependable system architectures, it aids in achieving high safety levels required in critical aerospace applications.
Topaz FPGAs are engineered to be a go-to solution for industries requiring a swift scale-up to volume production without compromising on performance or efficiency. Centered around an efficient architectural framework, these FPGAs deliver the power and functionality needed to address mainstream applications. They are renowned for their innovative fabric, which optimizes both die area and performance metrics. As such, Topaz FPGAs are indispensable for projects ranging from consumer electronics to automotive solutions, ensuring adaptability and scalability along evolving technological paths. Furthermore, with their seamless system integration capability, these FPGAs significantly shorten the development cycle, facilitating a faster go-to-market strategy while maintaining the high standards Efinix is known for.
The DisplayPort 1.4 is an advanced IP core solution, ideal for fulfilling modern DisplayPort requirements. Available as both a source (DPTX) and a sink (DPRX), it caters to a variety of link rates including 1.62, 2.7, 5.4, and 8.1 Gbps—covering eDP rates as well. Offering support for 1, 2, and 4 DP lanes, this IP core features Native video and AXI stream video interfaces. This IP core supports Single Stream Transport (SST) and Multiple Stream Transport (MST), along with dual and quad pixel clocks for 8 and 10-bit video in RGB, YCbCr 4:4:4, YCbCr 4:2:2, and YCbCr 4:2:0 colorspaces. It also incorporates a secondary data packet interface conducive for audio and metadata transport. To facilitate video processing, the IP comes with a Video Toolbox (VTB), equipped with a timing generator, test pattern generator, and video clock recovery. Its design ensures broad FPGA adaptability, working seamlessly with a variety of devices including AMD UltraScale+, AMD Artix-7, Intel Cyclone 10 GX, Intel Arria 10 GX, and Lattice CertusPro-NX.
The FC Anonymous Subscriber Messaging (ASM) IP Core offers a streamlined hardware-based full-network stack solution specialized for FC-AE-ASM protocols. This core is instrumental in providing hardware-centric approaches to data distribution tasks, offering key features like label lookup, DMA controllers, and sophisticated message chain engines. F-35 aircraft compatibility and the integration of AS5643 protocols allow this core to ensure optimal performance in the exacting realms of aerospace communication systems. By minimizing software overhead, the ASM Core offers enhanced speeds and operational efficiency. This IP is advantageous where high-speed communication integrity is paramount, and where precise, real-time data exchanges are needed. Through performance-focused design, it upholds efficient data management, ensuring that communication networks maintain a dependable and responsive nature vital in mission-critical applications.
Overview: The Power Management IC (PMIC) is specifically designed for DDR5 RDIMM, DDR5 LRDIMM, and DDR5 NVDIMM applications. It includes switching and LDO regulators to efficiently manage power distribution. The PMIC utilizes a MIPI-I3C Interface to select appropriate power settings for various application environments and is capable of operating at speeds up to 12.5MHz. Key Features: Maximum Operating speed of 12.5MHz Flexible Open-Drain IO (I2C) and Push-Pull (I3C) IO Support Multi-Time Programmable Non-Volatile Memory Interface Programmable and DIMM-specific registers for customization Error log registers for tracking Packet Error Check (PEC) and Parity Error Check functions Bus Reset function Support I3C Basic mode In-Band Interrupt (IBI) support Write, read, and default read operations in I2C mode Error handling for PEC, Parity errors, and CCC errors I3C Basic Common Command Codes (CCC) support Applications: DDR5 DIMM Application Environment DDR5 NVDIMM Application Environment Automotive Devices Memory Devices Power Management Devices Defense/Aerospace/Customer Electronics
The Multi-Protocol SerDes provided by Silicon Creations serves as an essential component for high-speed data interfaces across multiple industry protocols. This SerDes portfolio accommodates a vast array of protocols such as PCIe, JESD204, XAUI, and many more, facilitating broad compatibility with industry standards. Operating across 12nm to 180nm processes, these interfaces support data rates from 100 Mbps to an impressive 32.75 Gbps. Incorporating advanced features like programmable de-serialization widths and adaptive equalization, the Multi-Protocol SerDes ensures optimal signal integrity and performance even in demanding environments. The design includes jitter cleaner functions and employs low-latency optimized PMAs, delivering high precision and speed across various operational scenarios. This comprehensive adaptability ensures seamless integration into a wide range of applications from communications to high-performance computing. Supported by robust architectures, the SerDes enables enhanced efficiency and reliability, featuring low power consumption and reduced area overheads. With a commitment to customer satisfaction, Silicon Creations offers complete solutions through partnerships with leading controller vendors, cementing its products as high-value choices for modern electronic systems.
The MXL-LVDS-MIPI-RX is a high-frequency, low-power, low-cost, source-synchronous, Physical Layer that supports the MIPI® Alliance Standard for D-PHY and compatible with the TIA/EIA-644 LVDS standard. (Learn more about Mixel’s MIPI ecosystem at Mixel MIPI Central which gives you access to Mixel’s best of class MIPI ecosystem supply chain partners.) The IP is configured as a MIPI slave and consists of 5 lanes: 1 Clock lane and 4 data lanes, which make it suitable for display serial interface applications (DSI). The High-Speed signals have a low voltage swing, while Low-Power signals have large swing. High-Speed functions are used for High-Speed Data traffic while low power functions are mostly used for control.
The MXL-LVDS-DPHY-DSI-TX is a combo PHY that consists of a high-frequency low-power, low-cost, source-synchronous, Physical Layer supporting the MIPI® Alliance Standard for D-PHY and a high performance 4-channel LVDS Serializer implemented using digital CMOS technology. (Learn more about Mixel’s MIPI ecosystem at Mixel MIPI Central which gives you access to Mixel’s best of class MIPI ecosystem supply chain partners.) In LVDS mode, both the serial and parallel data are organized into 4 channels. The parallel data is 7 bits wide per channel. The input clock is 25MHz to 150MHz. The serializer is highly integrated and requires no external components. The circuit is designed in a modular fashion and desensitized to process variations. This facilitates process migration, and results in a robust design.
The GNSS VHDL Library developed by GNSS Sensor Ltd is a comprehensive collection of modules designed to facilitate the integration of satellite navigation systems into various platforms. This library is highly configurable, offering components like a GNSS engine, fast search engines for GPS, Glonass, and Galileo systems, a Viterbi decoder, and several internal self-test modules. With its design focused on maximum CPU platform independence and flexibility, this library is a powerful tool for developers seeking to incorporate advanced navigation capabilities into their products. This VHDL library allows for the creation of System-on-Chip (SoC) configurations by utilizing pre-built FPGA images that integrate the GNSS library. These images are compatible with both 32-bit SPARC-V8 and 64-bit RISC-V architectures, supporting a wide range of external bus interfaces via a simplified core bus (SCB) that incorporates bridge modules for AMBA and SPI interfaces. This architectural flexibility significantly reduces development costs and complexity. The GNSS VHDL Library ensures seamless compatibility with a variety of frequencies and satellite systems, providing a robust framework for satellite navigation in modern electronic devices. It includes RF front-end modules for GLONASS-L1 and GPS/Galileo/SBAS, which enhance the verification of GNSS configurations. This modularity and adaptability make it an ideal choice for innovative applications in navigation and positioning systems.
Imec's Hyperspectral Imaging System is designed for advanced optical sensing applications. This system integrates state-of-the-art sensors that can capture high-resolution spectral data across a wide range of wavelengths. Utilizing Imec's expertise in compact chip design, the system is engineered to be both portable and efficient, making it suitable for industries such as agriculture, food safety, and environmental monitoring. Its sophisticated image processing algorithms and user-friendly interface allow for seamless integration into existing workflows, providing comprehensive data analysis and reporting capabilities.
The ARINC 818 Product Suite by Great River Technology is an industry-leading collection of tools and solutions designed to address every aspect of ARINC 818 protocol implementation. This suite provides comprehensive resources for developing, qualifying, testing, and simulating ARINC 818 products, ensuring seamless integration and operation in mission-critical environments. With a focus on the unique requirements of avionics systems, this product suite supports a wide range of high-fidelity video and data communications applications. Great River Technology's suite is renowned for its role in helping organizations bring ARINC 818 products to fruition, offering unparalleled support throughout the product lifecycle. Their guidance in the protocol's implementation is enhanced by an expansive set of development tools and resources, making them a preferred partner for companies looking to enhance their avionics capabilities. This integration capability is essential for creating robust systems that meet the rigorous demands of modern aerospace engineering. The ARINC 818 Product Suite is complemented by expert service and support from Great River Technology, ensuring that customers not only receive top-tier products but also benefit from the company’s extensive experience in the field. As a cornerstone of the company’s offerings, the ARINC 818 suite empowers clients to deliver exceptional performance in their aviation technology projects.
The FC Upper Layer Protocol (ULP) IP Core is engineered for a complete network stack implementation tailored to the Fibre Channel - Aerospace Environment (FC-AE) Remote Direct Memory Access (RDMA) or FC-AV standards. Designed for demanding aerospace contexts, this core enables efficient data handling through advanced buffer mapping and direct memory access capabilities. The ULP Core provides comprehensive hardware solutions for label lookup functions, DMA controllers, and message chain engines, enhancing network communication performance. Notably, this core is compatible with F-18 and F-15 aircraft interface modes, ensuring seamless integration across military communication systems. With its robust architecture, the FC ULP Core meets the high-performance demands of fibre channel systems, enabling reliable data path optimization for mission-critical environments. The core supports complex data networking needs, facilitating high-speed data transactions with remarkable efficiency.
The MXL-SR-LVDS is a high performance 4-channel LVDS Serializer implemented using digital CMOS technology. Both the serial and parallel data are organized into four channels. The parallel data width is programmable, and the input clock is 25MHz to 165MHz. The Serializer is highly integrated and requires no external components. It employs optional pre-emphasis to enable transmission over a longer distance while achieving low BER. The circuit is designed in a modular fashion and desensitized to process variations. This facilitates process migration, and results in a robust design.
Dyumnin's RISCV SoC is a versatile platform centered around a 64-bit quad-core server-class RISCV CPU, offering extensive subsystems, including AI/ML, automotive, multimedia, memory, cryptographic, and communication systems. This test chip can be reviewed in an FPGA format, ensuring adaptability and extensive testing possibilities. The AI/ML subsystem is particularly noteworthy due to its custom CPU configuration paired with a tensor flow unit, accelerating AI operations significantly. This adaptability lends itself to innovations in artificial intelligence, setting it apart in the competitive landscape of processors. Additionally, the automotive subsystem caters robustly to the needs of the automotive sector with CAN, CAN-FD, and SafeSPI IPs, all designed to enhance systems connectivity within vehicles. Moreover, the multimedia subsystem boasts a complete range of IPs to support HDMI, Display Port, MIPI, and more, facilitating rich audio and visual experiences across devices.
The MIPI D-PHY, compliant with version 2.5, is a fully integrated hard macro offering lane control and interface logic. Capable of up to 1.5 Gbps per lane, this IP is designed to support low-power and ultra-low-power state modes. This flexibility in power states makes it particularly suited for mobile and energy-sensitive applications, ensuring reliable data transmission across high-speed communication platforms.
The FC Link Layer (LL) IP Core serves as a full-fledged hardware solution for implementing the Fibre Channel FC-1 and FC-2 layers. Designed for high-speed data environments, it directly addresses the challenges of handling complex data streams across networks in mission-critical aerospace applications. This IP core ensures precise and reliable communication through its robust architecture, excelling in data throughput and latency management. Its functionality enriches network layers, allowing seamless integration into systems requiring stable, high-speed data services. By supporting advanced interface modes and providing a complete hardware configuration, the LL Core enhances operational capabilities and reliability for military and aerospace industries. This vital component in the communication infrastructure underscores high levels of interconnectivity needed in complex network frameworks.
The BlueLynx Chiplet Interconnect is a sophisticated die-to-die interconnect solution that offers industry-leading performance and flexibility for both advanced and conventional packaging applications. As an adaptable subsystem, BlueLynx supports the integration of Universal Chiplet Interconnect Express (UCIe) as well as Bunch of Wires (BoW) standards, facilitating high bandwidth capabilities essential for contemporary chip designs.\n\nBlueLynx IP emphasizes seamless connectivity to on-die buses and network-on-chip (NoCs) using standards such as AMBA, AXI, and ACE among others, thereby accelerating the design process from system-on-chip (SoC) architectures to chiplet-based designs. This innovative approach not only allows for faster deployment but also mitigates development risks through a predictable and silicon-friendly design process with comprehensive support for rapid first-pass silicon success.\n\nWith BlueLynx, designers can take advantage of a highly optimized performance per watt, offering customizable configurations tailored to specific application needs across various markets like AI, high-performance computing, and mobile technologies. The IP is crafted to deliver outstanding bandwidth density and energy efficiency, bridging the requirements of advanced nodal technologies with compatibility across several foundries, ensuring extensive applicability and cost-effectiveness for diverse semiconductor solutions.
Silicon Library's MIPI solutions provide efficient and reliable physical layer connections for mobile and other digital devices, supporting Mobile Industry Processor Interface standards. These solutions encompass the MIPI DPHY transmitter and receiver, which are crucial for device communications in high-speed data environments such as mobile phones and tablets. The DPHY-Tx and DPHY-Rx are engineered to support a versatile range of data rates, making them ideal for high-density data operations required in current mobile computing and imaging applications. By delivering efficient power management and optimized space utilization, these solutions offer significant advantages in compact and portable device designs. Engineers and manufacturers benefit from the robust architecture of Silicon Library's MIPI solutions, which are designed for easy integration and high performance across a broad spectrum of applications. Their implementation ensures devices can transmit and receive data smoothly, maintaining the integrity and synchronization necessary for complex digital communications.
The MIPITM SVRPlus2500 provides an efficient solution for high-speed 4-lane video reception. It's compliant with CSI2 rev 2.0 and DPHY rev 1.2 standards, designed to facilitate easy timing closure with a low clock rating. This receiver supports PRBS, boasts calibration capabilities, and offers a versatile output of 4/8/16 pixels per clock. It features 16 virtual channels and 1:16 input deserializers per lane, handling data rates up to 10Gbps, making it ideal for complex video processing tasks.
The MIPITM CSI2MUX-A1F is an innovative video multiplexor designed to manage and aggregate multiple video streams effortlessly. It supports CSI2 rev 1.3 and DPHY rev 1.2 standards, handling inputs from up to four CSI2 cameras and producing a single aggregated video output. With data rates of 4 x 1.5Gbps, it is optimal for applications requiring efficient video stream management and consolidation.
The Dynamic PhotoDetector (DPD) by ActLight specifically designed for smartphone applications marks a considerable advancement in mobile light sensing technology. This sensor is crafted with enhanced sensitivity and efficiency, capable of adjusting its operational parameters dynamically based on ambient light conditions. It ensures the optimum performance of smartphone features reliant on light sensing, such as automatic screen brightness adjustment and camera functionalities. Notably, the DPD achieves this while maintaining a lower power consumption profile than conventional alternatives, which is a significant advantage for today's power-hungry smartphones that demand long battery life. Its state-of-the-art design encapsulates high-performance metrics in a small, cost-effective package, allowing manufacturers to integrate it into devices without substantial adjustments in design and costs. This technology not only improves user experience by providing smoother, more responsive control over light-related smartphone features but also supports the burgeoning trend towards more eco-friendly, energy-efficient consumer electronics, reducing the overall energy footprint of modern mobile devices.
The MXL-DS-LVDS is a high performance 4-channel LVDS Deserializer implemented using digital CMOS technology. Both the serial and parallel data are organized into four channels. The parallel data can be 7 or 10 bits wide per channel. The input clock is 25MHz to 165MHz. The De-serializer is highly integrated and requires no external components. Great care was taken to insure matching between the Data and Clock channels to maximize the deserializer margin. The circuit is designed in a modular fashion and desensitized to process variations. This facilitates process migration, and results in a robust design.
Analog Bits' I/O solutions offer highly efficient differential clocking and crystal oscillator IPs with customizable options for die-to-die connectivity. These technologies are optimized to utilize minimal transistors while ensuring the highest quality of signal transmission. Demonstrating proven silicon performance at 5nm and developments at 3nm, the company's I/O solutions are at the forefront of innovation, meeting high-volume production demands across top-tier fab facilities. These products are tailored to specifically address customer requirements, ensuring optimal operation with precision in signal integrity and low power usage, offering users flexibility in implementation across systems.
Silicon Creations' Bi-Directional LVDS Interfaces are engineered to offer high-speed data transmission with exceptional signal integrity. These interfaces are designed to complement FPGA-to-ASIC conversions and include broad compatibility with industry standards like FPD-Link and Camera-Link. Operating efficiently over processes from 90nm to 12nm, the LVDS interfaces achieve data rates exceeding 3Gbps using advanced phase alignment techniques. A standout feature of this IP is its capability to handle independent LVCMOS input and output functions while maintaining high compatibility with TIA/EIA644A standards. The bi-directional nature allows for seamless data flow in chip-to-chip communications, essential for modern integrated circuits requiring high data throughput. The design is further refined with trimmable on-die termination, enhancing signal integrity during operations. The LVDS interfaces are versatile and highly programmable, meeting bespoke application needs with ease. The interfaces ensure robust error rate performance across varying phase selections, making them ideal for video data applications, controllers, and other high-speed data interfaces where reliability and performance are paramount.
The Satellite Navigation SoC Integration solution offers a seamless method to embed satellite navigation capabilities within a System on Chip (SoC). This solution effectively integrates GPS, GLONASS, SBAS, and Galileo channels, along with independent fast search engines for each navigation system, enabling a robust and comprehensive navigation system. Because of its silicon-verified nature and VHDL library-based design, it ensures ease of integration and compatibility with various platforms. Notably, this IP was among the first to be integrated with open hardware architecture such as RISC-V, bolstering its adaptability and performance. The navigation IP features advanced signal processing capabilities that are platform independent, supporting a high update rate that can reach up to 1000 Hz. This high performance is complemented by a user-friendly API, making it accessible for developers to implement in various applications. Its versatility is further demonstrated through the support of a wide range of communication protocols and its ability to work seamlessly with other software services like OpenStreetMaps. This solution is optimal for developers looking to enhance their SoC with precise and reliable satellite navigation functionalities. It is particularly beneficial in modern applications requiring high accuracy and reliability, offering comprehensive features that facilitate a range of applications beyond traditional GPS functions. The integration of this technology enables devices to perform at unprecedented levels of efficiency and accuracy in location-based applications.
The 1394b PHY IP Core delivers a robust hardware implementation of the AS5643 PHY layer, ensuring comprehensive interoperability and performance for high-speed data applications. This core facilitates communication through standard PHY-Link interfaces, emphasizing reliability, low latency, and efficient data exchanges critical for mission-critical operations. Designed to integrate seamlessly into existing systems, the 1394b PHY Core empowers communication networks with a resilient framework to handle extensive data flows. It plays a vital role in avionic environments, where high reliability and efficiency are non-negotiable for performance. Its operational excellence and flexibility make the 1394b PHY Core an indispensable asset for a wide range of aerospace applications that demand high-speed communication, serving as a cornerstone for data integrity and synchronization across networks.
The second-generation MIPITM SVRPlus-8L-F is a high performance serial video receiver built for FPGAs. Complying with CSI2 revision 2.0 and DPHY revision 1.2 standards, it supports 8 lanes and 16 virtual channels, offering efficient communication with 12Gbps data throughput. This receiver comes with features like 4 pixel output per clock, calibration support, and communication error statistics, making it suitable for high-speed video transmission and processing applications.
Advinno's SerDes (Serializer/Deserializer) technology facilitates the efficient conversion of data between serial and parallel interfaces. This critical component is designed to support high-speed data transmission, making it an integral part of modern communication infrastructure, including data centers and telecommunication systems. The SerDes solution provided by Advinno offers impressive bandwidth capabilities, ensuring seamless data transfer across substantial distances without loss of integrity. This technology supports error correction techniques that enhance reliability and data integrity in demanding environments. Suitable for high-performance systems, Advinno's SerDes integrates seamlessly into a variety of applications, from server interconnects to network switches, reinforcing the company's commitment to innovation and reliability in data communication technologies.
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