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All IPs > Interface Controller & PHY > AMBA AHB / APB/ AXI > AMBA APB Target

AMBA APB Target

From Agnisys, inc.

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Description

Advanced Peripheral Bus (APB) is one of the Advanced Microcontroller Bus Architecture (AMBA) family protocols. It is a low-cost interface that is designed for low power consumption and interface simplicity. Unlike AHB, it is a non-pipelined protocol for connecting low-bandwidth peripherals. Mostly used to link external peripherals to the SOC. Every APB transfer requires at least two clock cycles (SETUP Cycle and ACCESS Cycle) to finish. The APB interface is designed for accessing the programmable control registers of peripheral devices. The APB protocol has two independent data buses, one for read data and one for write data. The buses can be 8, 16, or 32 bits wide. The read and write data buses must have the same width. Data transfers cannot occur concurrently because the read data and write data buses do not have their own individual handshake signals.

Deliverables
Soft IP
  • Synthesizable RTL
  • Verilog integration testbench
  • Datasheet
  • Hardware user guide
  • IDesignSpec tool to configure
Features
  • Wait state
  • Error reporting
  • Transaction protection
  • Sparse data transfer
  • Flopped and non-flopped
  • Synchronous or asynchronous reset type
  • APB 4 / APB3
Foundries & Process Nodes
Foundry Process Nodes
All Foundries All Process Nodes
Tech Specs
Class Value
Categories Interface Controller & PHY > AMBA AHB / APB/ AXI
Availability All Countries & Regions
Applications
  • AI
  • Mobile
  • Autonomous Technology
  • Research & Science and Engineering Services
  • Semiconductor Industry
  • Military & Aerospace
  • Information & Technology
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