All IPs > Multimedia > H.265
The Multimedia > H.265 category features semiconductor IPs specifically designed for optimizing High-Efficiency Video Coding (HEVC) technology. H.265, a successor to H.264, is renowned for doubling the data compression ratio compared to its predecessor while maintaining the same level of video quality. This allows developers to deliver ultra-high-definition video content at significantly reduced bandwidths and storage requirements, making it an essential technology in today's data-driven multimedia landscape.
In this category, you will find a range of H.265 semiconductor IPs aimed at facilitating the efficient encoding and decoding of video streams. These IPs are highly sought after by industries looking to integrate 4K and 8K video content, such as in smart televisions, streaming devices, video conferencing systems, and mobile devices. By implementing H.265 semiconductor IPs, companies can ensure their products offer superb visual experiences while optimizing performance and minimizing power consumption.
The products available in the H.265 semiconductor IP category are designed to support a variety of applications beyond standard video playback and streaming. They are integral in enabling next-generation technologies such as virtual reality (VR) and augmented reality (AR), where seamless, high-resolution video streaming is crucial for immersive user experiences. Additionally, these IPs provide robust support for live broadcasting solutions, cloud video storage, and advanced surveillance systems, showcasing their versatility across numerous technology sectors.
Overall, the H.265 semiconductor IP offerings from Silicon Hub empower developers with the tools needed to meet escalating consumer expectations for high-quality video performance. Whether your focus is on improving end-user video experiences or optimizing backend video processing systems, H.265 IPs provide the foundational technology to achieve these goals, all while adhering to stringent industry standards for efficiency and quality. Explore our comprehensive collection to find the IP solution that best suits your multimedia product development needs.
aiSim 5 is at the forefront of automotive simulation, providing a comprehensive environment for the validation and verification of ADAS and AD systems. This innovative simulator integrates AI and physics-based digital twin technology, creating an adaptable and realistic testing ground that accommodates diverse and challenging environmental scenarios. It leverages advanced sensor simulation capabilities to reproduce high fidelity data critical for testing and development. The simulator's architecture is designed for modularity, allowing seamless integration with existing systems through C++ and Python APIs. This facilitates a wide range of testing scenarios while ensuring compliance with ISO 26262 ASIL-D standards, which is a critical requirement for automotive industry trust. aiSim 5 offers developers significant improvements in testing efficiency, allowing for runtime performance adjustments with deterministic outcomes. Some key features of aiSim 5 include the ability to simulate varied weather conditions with real-time adaptable environments, a substantial library of 3D assets, and built-in domain randomization features through aiFab for synthetic data generation. Additionally, its innovative rendering engine, aiSim AIR, enhances simulation realism while optimizing computational resources. This tool serves as an ideal solution for companies looking to push the boundaries of ADAS and AD testing and deployment.
The H.264 FPGA Encoder and CODEC Micro Footprint Cores are versatile, ITAR-compliant solutions providing high-performance video compression tailored for FPGAs. These H.264 cores leverage industry-leading technology to offer 1080p60 H.264 Baseline support in a compact design, presenting one of the fastest and smallest FPGA cores available. Customizable features allow for unique pixel depths and resolutions, with particular configurations including an encoder, CODEC, and I-Frame only encoder options, making this IP adaptable to varied video processing needs. Designed with precision, these cores introduce significant latency improvements, such as achieving 1ms latency at 1080p30. This capability not only enhances real-time video processing but also optimizes integration with existing electronic systems. Licensing options are flexible, offering a cost-effective evaluation license to accommodate different project scopes and needs. Customization possibilities further extend to unique resolution and pixel depth requirements, supporting diverse application needs in fields like surveillance, broadcasting, and multimedia solutions. The core’s design ensures it can seamlessly integrate into a variety of platforms, including challenging and sophisticated FPGA applications, all while keeping development timelines and budgets in focus.
High-resolution Image Processing IP Performance 4K60p@400MHz (600MHz for display interface) Features Support various color format : YUV420, YUV422, YUV444, and RGB Up-/Down-scaler x1/8~x8 : selectable scaler algorithm with Bi-cubic and Lanczos Two scalers, connected to DRAM and display/direct I/F respectively, operating at different ratios at the same time (configurable to one scaler option) Color space conversion : YUV2RGB and RGB2YUV, coefficient downloadable Optional features Crop and digital zoom : scaling on cropped region Flip : horizontal and vertical 3rd Party interfaces: such as AFBC v1.2 and PVRIC v4 (support output only) Interface Display Interface : 3 channels for components with vertical/horizontal sync signal (ITU-R BT.601 compatible) Direct Interface (optional feature) : On-the-fly interface based on ready-valid protocol Support CF10 (Chips&Media’s Frame buffer compression) for Chips&Media video codec Support AFBC v1.2 and PVRIC v4 (optional feature) for output of MAPI
The TW330 distortion correction IP is tailored for use in applications requiring dynamic image transformations, such as VR headsets and automotive HUDs. Utilizing GPU-powered technologies, it offers real-time coordinate transformations, distortion corrections, and other modifications up to a resolution of 16K x 16K in both RGB and YUV formats. This IP is crucial for enhancing visual accuracy and display adaptability across varied markets.
The 4K Video Scaler by Zipcores is tailored for providing high-quality digital scaling solutions suitable for 4K/UHD content. Harnessing state-of-the-art processing technology, this scaler ensures crisp image quality even at high resolutions, without the need for complex external memory setups. Designed for integration into mid-range FPGA and SoC platforms, the scaler supports dual pixels per clock and operates with an effective pixel clock rate of 600 MHz. This capability is crucial for systems in need of high-definition video processing without additional memory overhead. The simple AXI4-stream input/output interfaces of the 4K Video Scaler make it compatible across a range of designs, facilitating easy deployment in various multimedia projects. It is the ideal choice for applications focused on delivering superior video quality, such as broadcasting equipment and high-end consumer electronics.
Designed for smaller scale transformations, the TW220/240 IP handles tasks such as distortion correction, scaling, and rotation for images up to 4K x 4K resolution. It supports RGB and YUV formats, offering vital capabilities for applications needing precision in image processing at lower resolutions. Its applications span from consumer digital products to professional imaging equipment.
The JPEG Encoder for Image Compression is a sophisticated IP core designed to support machine vision applications, offered by Section5. It is developed for integration in standard FPGAs, facilitating a cost-effective and efficient image processing solution. Capable of handling pixel bit depths up to 12 bits, this encoder provides high-quality image compression suitable for various multimedia applications. This IP core supports a diverse range of configurations, including the L1 pipeline for monochrome images and the L2 dual-pipe for high-quality YUV422 encoding. The JPEG Encoder also includes a higher pixel clock variant, L2H, that can accommodate up to 200 MHz for specific platforms. Its deployment capabilities include UDP/Ethernet streaming solutions compliant with RFC 2435 standards, enhancing its applicability in networked systems. Supported by extensive simulation models, Section5’s JPEG Encoder ensures high performance and reliability in deployment. Available reference designs and receiver software streamline the integration process across Linux and Windows platforms, facilitating seamless implementation in varying environments.
The H.265 HEVC Decoder System from Korusys stands out as a high-performance standalone FPGA solution for decoding video efficiently. Adhering to the ITU-T H.265 standard, this decoder supports ultra-low latency decoding for streams up to 4kp60. This makes it ideal for cutting-edge video applications demanding high-definition quality and performance. Available as a packaged offering with the High Performance FPGA PCIe Accelerator Card, it delivers comprehensive video decoding services with exceptional speed and quality.
HEVC/H.265 Main/Main10/ Main Still Picture Profile @L5.2 AVC/H.264 BP/CBP/MP/HP/HP10 @L5.2 Capable of encoding up to 8K ((8192x4096) A 32-bit AMBA3 APB bus for host CPU system control 128-bit AMBA3 AXI for data transfer (Optionally, additional secondary AXI) Latency tolerance Low power consumption Programmability Configurable IP Multi-instances Frame buffer compression (CFrame) Rotation & Mirroring Bit-depth & chroma sub-sample conversion Background detection 3DNR Lambda table QP Map Custom mode decision, etc.
Video Codec Standard AV1: Main/High profile @ L6 Main tier 50Mbps Professional profile except 12-bit @ L6 Main tier 50Mbps Mono/YUV420/YUV422/YUV444 8-/10-bit HEVC/H.265: Main/Main 10/Main 4:2:2 10 profile @ L6 High tier Main 4:4:4/Main 4:4:4 10 profile @ L6 High tier (Only support 4:2:0 coding tools, high precision weighted prediction, and chroma QP offset list) AVC/H.264: Baseline/Constrained Baseline/Main/High/High10 profile @ L6 High 10 Intra/High 4:2:2/High 4:2:2 Intra profile with frame_mbs_only_flag = 1 @ L6 High 4:4:4 Predictive/High 4:4:4 Intra/CAVLC 4:4:4 Intra profile @ L6 with: frame_mbs_only_flag = 1 bit_depth_luma ≤ 10 bit_depth_chroma ≤ 10 frame_mbs_only_flag = 1 and qpprime_y_zero_transform_bypass_flag = 0 VP9 (Decoder only): Profile 0 and Profile 2 (12-bit not supported), YUV420 8/10-bit Performance 4K120fps@500MHz with a dual-core 4K240fps@1GHz or 8K60fps@1GHz with a dual-core Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit depth and YUV format conversion of the source picture Rotate/Mirror Down-scaler Crop Encoder Features I/P/B picture coding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer (optional AXI can be used to alleviate bandwidth usage.)
Allegro DVT’s HEVC/H.265 Encoder is designed to excel in video compression, efficiently reducing bandwidth while maintaining superior video quality. This encoder facilitates the processing of 4K and higher resolutions, making it instrumental for next-generation broadcasting and video streaming services. The core advantage of this encoder lies in its ability to deliver high compression rates without sacrificing video clarity. Integrated with cutting-edge algorithms, it supports various bit rates and frame rates, enabling it to dynamically manage encoding tasks across different video formats seamlessly. With its emphasis on high dynamic range (HDR) and wide color gamuts, the HEVC/H.265 Encoder is particularly suitable for applications that demand top-tier video quality, such as professional video production and live streaming platforms.
The IPMX Core is a cutting-edge solution for leveraging the latest AV-over-IP standards within professional AV systems. By adopting the open specification IPMX protocol, Nextera Video enables seamless communication over IP networks, transforming the efficiency of media transport globally. Its foundation on proven standards like SMPTE ST 2110 and NMOS enhances its interoperability and scalability. Designed for versatile video and audio integration, the IPMX Core supports both compressed and uncompressed media, providing flexibility across a spectrum of resolutions up to 8K. This adaptability caters to diverse media landscapes, accommodating different frame rates, color spaces, and sample rates, while maintaining low latency and high-quality delivery. Nextera’s IPMX Core stands at the forefront of AV-over-IP technology, offering essential features like encrypted data transport, asynchronous video support, and industry-standard NMOS control. This makes it a formidable choice for any organization seeking to future-proof its AV infrastructure through robust IP technologies that meet rigorous professional standards.
HEVC/H.265 - Main/Main10 Profile @L5.1 AVC/H.264 - BP/CBP/MP/HP/HP10 Profile @ L5.2 Capable of decoding up to 4K60fps (8192x4096) A 32-bit APB bus and 128-bit AMBA3 AXI buses (w/ additional secondary AXI) Burst Write Back Map converter Low delay Low power consumption Configurable IP Latency tolerance Programmability Multi-instances Frame buffer compression (CFrame) Secondary AXI interfaces Downscaler (on-the-fly mode)
The DVB-Satellite Modulator is a high-performance modulator core designed to adhere to DVB-S, DSNG, DVB-S2, and DVB-S2X satellite forward-link specifications. This versatile modulator core is engineered for both broadcasting and interactive applications, accommodating a variety of modulation schemes including (A)PSK. Its robust framework is capable of delivering efficient and reliable operations in challenging satellite communication environments. The modulator's design prioritizes support for advanced satellite communication standards, ensuring its place in future-ready satellite systems.
MPEG-H Audio System enhances TV and virtual reality experiences by providing immersive and interactive audio. Capable of delivering high-quality sound, it supports personalized audio experiences where users can adjust audio elements such as dialogue and music levels. This adaptability revolutionizes how audiences interact with media, offering a customized experience that was previously unavailable. It's increasingly being adopted in broadcasting and virtual environments, ensuring compatibility with current and next-gen platforms.
Video Codec Standard HEVC: Main/Main Still Picture profile @ L5.1 High tier AVC: Baseline/Constrained Baseline/Main/High profiles @ L5.2 Performance 4K60fps@500MHz Max resolution: 8192 x 4096 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Multi-instances Frame-buffer compression (CFrame) In-loop filter Rotation & Mirroring Bit depth & chroma sample format conversion Lossless coding Background coding MapConverter 3DNR, etc. Interface 32-bit AMBA3 APB bus 128-bit AMBA3 AXI buses Primary AXI interface and an optional secondary AXI interface
The MIPITM V-NLM-01 is a specialized non-local mean image noise reduction product designed to enhance image quality through sophisticated noise reduction techniques. This hardware core features a parameterized search-window size and adjustable bits per pixel, ensuring a high degree of customization and efficiency. Supporting HDMI with resolutions up to 2048×1080 at 30 to 60 fps, it is ideally suited for applications requiring image enhancement and processing.
The DVB-S2 Modulator is engineered to accommodate both DVB-S2 and DVB-S2X satellite forward-link specifications. This high-performance modulator core supports (A)PSK modulation schemes and is particularly suitable for both broadcasting and interactive applications. Its design is focused on delivering advanced functionalities while ensuring compliance with dynamic satellite communication standards. This makes it well-suited for a variety of professional and commercial telecommunications applications. The modulator is ideal for delivering superior broadcast experiences with increased efficiency and reliability.
Video Codec Standard HEVC/H.265: Main profile @ L5.1 High tier AVC/H.264: Baseline/Constrained Baseline/Main/High profile @ L5.2 Performance 4K60fps@500MHz Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit depth and YUV format conversion of the source picture Encoder Features I/P picture coding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer (Optional AXI can be used to alleviate bandwidth usage.)
The HEVC Decoder from VYUsync Design Solutions is a top-tier video decoder built for high performance. It complies with HEVC/H.265 standards, providing up to Main 12 422 Profile compatibility. The HEVC Decoder is specially designed for deployment on a wide variety of target FPGAs. Its capability to handle complex video data efficiently makes it ideal for high-definition video streaming applications, ensuring seamless video playback and advanced video processing. This decoder is flexible, scalable, and tailored to meet the rigorous demands of modern video applications, whether they're for broadcasting, professional video recording, or any high-demand video processing role. Focused on maintaining superior color fidelity, the HEVC Decoder supports the 4:4:4 color format, accommodating larger bit depths to ensure refined and nuanced color reproduction. This makes it exceptionally suited for applications in fields that demand high visual fidelity such as professional film production and medical imaging. The decoder’s design assures low latency, enhancing the responsiveness and effectiveness of visual data transmission, which is particularly critical when real-time processing is necessary. The HEVC Decoder is an invaluable component in mission-critical environments. Its robust performance ensures that it can reliably transport and decode video streams even in high-pressure situations. This decoder is also an asset for companies looking to enhance their current video processing capabilities, offering a highly efficient, field-proven IP that can be integrated seamlessly into existing systems.
The DXT GPU is specifically designed to deliver robust graphics capabilities on mobile devices, providing the perfect foundation for applications that demand high performance alongside power efficiency. Leveraging advanced ray tracing capabilities, it brings desktop-level rendering quality to portable devices, enhancing user experiences in gaming, AR, and VR settings without compromising battery life.
Video Codec Standard HEVC: Main/Main10 profile @ L6 High tier AVC: Baseline/Constrained Baseline/Main/High/High 10 profile @ L6 (Interlaced coding tools are not supported) Performance 4K120fps@500MHz or 8K60fps@1GHz Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit depth and YUV format conversion of the source picture Encoder Features I/P/B picture encoding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer *Optional AXI can be used to alleviate bandwidth usage
Focused on meeting the ETSI DVB-CID carrier identification standard (EN103129), the DVB-CID Modulator integrates both modulation and channel coding functionalities into a single cohesive core. This integration is aimed at addressing specific carrier identification requirements within satellite communication systems. By streamlining these processes, the modulator enhances operational efficiencies while ensuring adherence to key industry standards. The DVB-CID Modulator effectively supports sophisticated satellite communication systems demanding reliable carrier identification capabilities.
The v-MP6000UDX Visual Processing Unit is a powerhouse of the Videantis portfolio, offering extensive capabilities for handling deep learning, computer vision, and video coding across a singular architecture. This unit brings prowess in processing tasks that require real-time performance and energy efficiency, making it pivotal for next-generation intelligent devices. Designed to support multiple computational requirements, the v-MP6000UDX processes deep learning models efficiently, acting as a unified platform that negates the need for disparate hardware accelerators. This processor's architecture is optimized for running complete neural networks swiftly and at low power, facilitating applications that demand rapid computing power with minimal energy constraints. Boasting a sophisticated memory hierarchy and high-bandwidth interfaces, the processor ensures efficient data handling and processing. Its enhanced memory architecture paired with a network-on-chip design fosters an environment where high-performance computations are achieved seamlessly. This makes the v-MP6000UDX suitable for deployment in complex systems such as autonomous vehicles, mobile technology, and industrial automation, where proficient data processing and precision are critical. Incorporating the latest design principles, the v-MP6000UDX unit integrates seamlessly into devices that require extensive video processing capabilities, benefiting from a vast library of codecs and support for emerging standards in video compression. This processing unit is indispensable for businesses aiming to enhance their product offerings with cutting-edge technology.
Video Codec Standard AV1: Main profile @ L5.1 HEVC: Main/Main10 profile, Main/Main 10 Still Picture profile @ L5.1 High tier AVC: Baseline/Constrained Baseline/Main/High/High 10 profile @ L5.2 (Interlaced coding tools are not supported) Performance 4K60fps@500MHz Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit depth and YUV format conversion of the source picture Encoder Features I/P/B picture encoding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer * Optional AXI can be used to alleviate bandwidth usage
Video Codec Standard HEVC: Main/Main Still Picture profile @ L5.1 High tier AVC: Baseline/Constrained Baseline/Main/High profiles @ L5.2 Performance 4K60fps@500MHz Max resolution: 8192 x 4096 Min resolution: 256 x 128 Bit depth: 8-bit Features Multi-instances Frame-buffer compression (CFrame) In-loop filter Rotation & Mirroring Bit depth & chroma sample format conversion Lossless coding Background coding Down-scaler (On-the-fly mode) MapConverter 3DNR, etc. Interface 32-bit AMBA3 APB bus 128-bit AMBA3 AXI buses Primary AXI interface and an optional secondary AXI interface
The AVC/H.264 Decoder from Allegro DVT delivers a robust decoding solution for high-definition video content, supporting the widely adopted H.264 format. This decoder is engineered to handle significant data rates efficiently, ensuring minimal power usage and optimal processing performance in various applications, from broadcasting to online streaming services. Characterized by its adaptability, the decoder copes with diverse protocol stacks, making it a reliable choice for industries requiring seamless video transmission. It decodes video content with high precision and fidelity, providing viewers with an enhanced visual experience without compromising on speed or accuracy. The AVC/H.264 Decoder is an ideal component for systems demanding efficient video decoding capabilities while supporting multiple resolutions and frame rates, ensuring it meets the diverse needs of today’s multimedia applications.
Supported standards for Decoder ISO/IEC23008-2 HEVC/H.265, ITU-T Rec. H.265 Main/Main10 Profile L5.1 AVC/H.264 BP/CBP/MP/HP/HP10 Profile @ L5.2 AVS2 Main/Main10 Profile @L8.0.60 Main performance 4K(3840x2160) 60fps @ 450MHz Max. resolution: 8192x4096 Features Frame buffer compression (CFrame) Embedded Post-processing (w/Down-scaler) Low delay Low power consumption Latency tolerance Interface AMBA 32-bit APB interface for Host CPU AMBA 128-bit AXI interface for the external memory
Video Codec Standard HEVC/H.265: Main profile @ L5.1 High tier AVC/H.264: Baseline/Constrained Baseline/Main/High profile @ L5.2 Performance 4K60fps@500MHz with a single-core Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit depth and YUV format conversion of the source picture Encoder Features I/P/B picture coding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer (Optional AXI can be used to alleviate bandwidth usage.)
Brief specification HEVC/H.265 Main/Main10 Profile @L5.1 AV1 Main Profile @ L5.1 VP9 Profile 0/ Profile 2 @L5.1 AVC/H.264 BP/CBP/MP/HP/HP10 Profile @ L5.2 AVS2 Main/Main10 Profile @L8.0.60 Main performance 4K(3840x2160) 60fps @ 450MHz Max. resolution: 8192x4096 System I/F A 32-bit APB bus and 128-bit AMBA3 AXI buses (w/additional Secondary AXI) Burst Write Back (BWB) Features Frame buffer compression (CFrame) Embedded Post-processing (w/Down-scaler) Low delay Low power consumption Latency tolerance
Video Codec Standard AV1: Main profile @ L5.1 Main tier 50Mbps HEVC/H.265: Main/Main 10 profile @ L5.1 High tier AVC/H.264: Baseline/Constrained Baseline/Main/High/High10 profile @ L5.2 (Interlaced coding tools are not supported.) VP9 (Decoder only): Profile 0 and Profile 2 (12-bit not supported) Performance 4K60fps@500MHz with a single-core Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit depth and YUV format conversion of the source picture Encoder Features I/P/B picture coding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer (Optional AXI can be used to alleviate bandwidth usage.)
The H.265 Codec from XtremeSilica delivers advanced video compression technology suitable for modern digital video applications. It enables efficient streaming and storage by significantly reducing bandwidth requirements, while maintaining high visual quality. Ideal for video broadcasting, streaming services, and mobile video applications, this codec supports high-resolution video formats, enhancing viewing experiences on a variety of platforms. Its enhancement over previous codecs ensures more efficient processing and lower data costs, facilitating HD and UHD content proliferation.
Video Codec Standard AV1: Main profile @ L6 High tier HEVC/H.265: Main/Main10 profile @ L6 High tier AVC/H.264: Baseline/Constrained Baseline/Main/High/High 10 profile @ L6 Performance 4K120fps@500MHz with a dual-core 4K240fps@1GHz or 8K60fps@1GHz with a dual-core Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit depth and YUV format conversion of the source picture Encoder Features I/P/B picture coding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer (Optional AXI can be used to alleviate bandwidth usage.)
Video Codec Standard HEVC: Main/Main Still Picture profile @ L5.1 High tier AVC: Baseline/Constrained Baseline/Main/High profiles @ L5.2 Performance 4K60fps@500MHz Max resolution: 8192 x 4096 Min resolution: 256 x 128 Bit depth: 8-bit Features Multi-instances Frame-buffer compression (CFrame) In-loop filter Rotation & Mirroring Bit depth & chroma sample format conversion Lossless coding Background coding 3DNR, etc. Interface 32-bit AMBA3 APB bus 128-bit AMBA3 AXI buses Primary AXI interface and an optional secondary AXI interface
Video Codec Standard AV1: Main profile @ L6 Main tier 50Mbps HEVC/H.265: Main/Main10 profile @ L6 High tier AVC/H.264: Baseline/Constrained Baseline/Main/High/High 10 profile @ L6 VP9 (Decoder only): Profile 0 and Profile 2 (12-bit not supported) Performance 4K120fps@500MHz with a dual-core 4K240fps@1GHz or 8K60fps@1GHz with a dual-core Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit depth and YUV format conversion of the source picture Encoder Features I/P/B picture coding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer (Optional AXI can be used to alleviate bandwidth usage.)
Decoding/Encoding Tools Support Extended Sequential ISO/IEC 10918-1 JPEG compliance Support one or three color components Three components in a scan (interleaved only) 8-bit and 12-bit samples for each component Support 4:2:0, 4:2:2, 4:4:0, 4:4:4 and 4:0:0 color formats Max. six 8x8 blocks in one MCU Support NV12/NV16/NV24 (CbCr Interleaved), NV21/NV61/NV42 (CrCb Interleaved) Support from 16 x 16 to 32K x 32K (32,768 x 32,768) image size Packed mode is supported 12-bit PPM format is supported Value-added Features Partial mode for encoding and decoding On-the-fly rotator/mirror ROI(Region of Interest) for decoding On-the-fly downsampler for decoding Color format converting for decoding Performance Decode up to 290M pix/s for 4:2:0 color format Encode up to 290M pix/s for 4:2:0 color format Operating clock frequency: 200MHz Ease of integration AMBA 32-bit APB (w/ PREADY) interface for communication with a host processor AMBA 64-bit AXI interface for the external memory
HEVC/H.265 Main/Main10 Profile @L5.1 AVC/H.264 BP/CBP/MP/HP/HP10 Profile @ L5.2 VP9 Profile 0/Profile 2 (HBD) AVS2 Main10 Profile @L8.0.60 Capable of decoding up to 4Kp60 (8192x4096) A 32-bit APB bus and 128-bit AMBA3 AXI buses (w/ additional secondary AXI) Burst Write Back Map converter Low delay Low power consumption Configurable IP Latency tolerance Programmability Multi-instances Frame buffer compression (CFrame) Downscaler (on-the-fly mode)
The TicoXS FPGA/ASIC IP Cores deliver a ground-breaking video compression standard known as JPEG XS. This technology is designed to handle visually lossless compression with little to no latency, perfectly suitable for real-time video transmission. TicoXS achieves unparalleled image quality and consistent performance due to its lightweight compression mechanisms, particularly beneficial for transmitting large volumes of video data efficiently. With its design suited for both FPGA and ASIC, TicoXS can operate robustly across various hardware platforms including Xilinx and Intel FPGAs. The IP cores support a wide spectrum of resolutions, from HD up to 10K, with flexibility in color space and bit depth which includes RGB, YUV, and more. This compatibility ensures that TicoXS cores can deliver real-time processing with remarkably low gate count and memory usage, tailored for high-speed content delivery systems. TicoXS is integral for applications that demand high-resolution outputs, such as broadcast, live production, and wireless video. The IP cores facilitate encoding and decoding of high-quality video streams, enabling seamless IP workflows. With added features such as adjustable compression rates and options for lossy and lossless modes, TicoXS provides ideal solutions for scenarios requiring streamlined data handling and pristine image quality in fast-paced media environments.
H.264, MVC, VP8, MPEG-1/2/4, VC-1, AVS, AVS+, H.263, Sorenson Decoding and encoding support at 1080p 60fps Supported standards for Decoder ISO/IEC 14496-10 AVC/H.264 BP/MP/HP@L4.2 ISO/IEC 14496-10/5 MVC Stereo High Profile@L4.1 ISO/IEC 14496-2 MPEG-4 SP,ASP@L6 SMPTE 421M-2006 VC-1 SP/MP/AP@L3 ISO/IEC 13818-2 MPEG-2 MP@HL ITU-T H.263(Annex I,J,K,T) AVS Jizhun @L6.2 AVS+ Guangdian @L6.2 On2 VP8 Sorenson Spark Theora Supported standards for Encoder ISO/IEC 14496-10 AVC/H.264 BP/MP/HP@L4.2 ISO/IEC 14496-10/5 MVC Stereo High Profile@L4.1 ISO/IEC 14496-2 MPEG-4 SP@L6 ITU-T H.263(Annex J,K,T) Supported Max. Resolution Supports up to 2048x2048 resolution Performance Single-stream H.264 HD(1920x1080p) 30fps decoding at <133MHz core clock H.264 HD(1920x1080p) 60fps decoding at <266MHz core clock H.264 HD(1920x1080p) 30fps encoding at <133MHz core clock H.264 HD(1920x1080p) 60fps encoding at <266MHz core clock Multi-stream Dual H.264 HD(1920x1080p) 30fps decoding at <266MHz core clock Dual H.264 HD(1920x1080p) 30fps encoding at <266MHz core clock 6SD/D1(NTSC&PAL) 30fps decoding at <133MHz core clock Full HD(1080p) encoding and decoding at <266MHz core clock Encoding Tools Selective [+/-64,+/-48] Quarter-pel and half-pel accuracy motion estimation using a full- search algorithm Flexible bit-rate control CBR VBR Fixed QP CABAC/CAVLC for AVC/H.264 Built-in pre- rotation/mirroring function 90xn degree rotation Vertical/horizontal mirroring Decoding Tools CABAC/CAVLC for AVC/H.264 MPEG-4 AC/DC prediction AVC/H.264 intra-prediction In-loop deblocking filter for H.264, H.263, and AVS Overlapped smoothing filter for VC-1 Built-in post-processing function 90xn degree rotation Vertical/horizontal mirroring De-ringing De-blocking filter for MPEG-2/4 Interface AMBA 32-bit APB interface for Host CPU AMBA 64-bit AXI interface for the external memory
The CXM GPU is designed for utmost efficiency and versatility, catering to a range of devices from wearable technology to smart home systems. Known for its compact design and low power consumption, it still provides significant computing power and rendering capabilities. This makes it a perfect fit for industrial applications where space and energy efficiency are crucial.
Video Codec Standard AV1: Main Profile @ L5.1 Performance 4K60fps@500MHz Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit-depth and YUV format conversion of the source picture Encoder Features I/P/B picture coding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer * Optional AXI can be used to alleviate bandwidth usage
Video Codec Standard HEVC/H.265: Main/Main 10 profile @ L6 High tier AVC/H.264: Baseline/Constrained Baseline/Main/High/High 10 profile @ L6 Performance 4K120fps@500MHz or 8K30fps@500MHz with a dual-core 4K240fps@1GHz or 8K60fps@1GHz with a dual-core Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit-depth and YUV format conversion of the source picture Encoder Features I/P/B picture coding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer (optional AXI can be used to alleviate bandwidth usage.)
This cutting-edge video decoder by Atria Logic focuses on delivering high-quality Ultra High Definition (UHD) content with low latency. The H.264 UHD Hi422 Intra Video Decoder is engineered to support the Hi422 profile at level 5.1, permitting intricate color detailing through its 10-bit YUV 4:2:2 format. Designed for real-time applications, it is particularly beneficial for medical imaging, broadcast, and industrial scenarios requiring crisp and precise video playback. With an architecture that minimizes latency to sub-frame levels, this decoder ensures consistent performance, crucial for mission-critical applications. Integrated with an efficient resource utilization model, the decoder facilitates a smooth video experience on platforms such as the Xilinx Zynq-7000, making it versatile across FPGA and ASIC integrations.
Aimed at providing high-quality video encoding with minimal latency, the H.264 UHD Hi422 Intra Video Encoder surpasses industrial standards by supporting 4K video encoding suited for multiple high-demand applications. Its design excellence lies in handling 10-bit YUV 4:2:2 content seamlessly, ensuring sharp color contrasts and reducing gradient banding, making it ideal for medical, broadcast, and enterprise use. The encoder excels in maintaining low latency, meeting crucial performance needs in dynamic environments such as live news broadcasting and real-time video streaming. Utilizing the Xilinx Zynq-7000 architecture allows for reduced resource consumption while ensuring top-tier video quality and efficient IP streaming.
H.264, MVC, VP8, MPEG-1/2/4, VC-1, AVS, AVS+, H.263, and Sorenson decoder HW IP for 2Kp60, 4:2:0 Standards AVC/H.264 BP/CBP/MP/HP L.4.1 Max: 1920x1088; Min: 16x16 MVC SHP L.4.1 Max: 1920x1088; Min: 16x16 MPEG-4 SP/ASP L.5 Max: 1920x1088; Min: 16x16 H.263 Profile 3 Max: 1920x1088; Min: 16x16 VC-1 SP/MP/AP L.3 Max: 1920x1088 or 2048x1024 Min: 16x16 MPEG-1/2 MP L.high Max: 1920x1088; Min: 16x16 Sorenson Spark Max: 1920x1088; Min: 16x16 VP8 WebM/WebP Max: 1920x1088; Min: 16x16 Theora Max: 1920x1088; Min: 16x16 AVS Jizhun/Guangdian L6.2 Max: 1920x1088; Min: 16x16 Features Frame buffer compression (CFrame) Low delay decoding Configurable IP Programmability Low power consumption Frame-based processing Multi-instances Latency tolerance Burst Write Back Down-scaler (on-the-fly mode) Map converter MPEG-2/4 De-ringing Built-in de-blocking filter A 32-bit AMBA3 APB bus and 64-bit AMBA3 AXI buses (w/additional Secondary AXI buses)
The Digital Video Scaler from Zipcores is crafted for high-definition video processing, offering dynamic resolution scaling capabilities. This core is optimized for upscaling and downscaling digital video content, ensuring the preservation of image quality across various display mediums and formats. Designed to operate efficiently on mid-range FPGAs, it supports a 600 MHz effective pixel clock rate, providing high throughput video processing solutions. The scaler eliminates the need for additional frame buffer or external memory, facilitating a straightforward integration into existing systems with minimal impact on system resources. Intended for applications demanding high-quality visual output, such as home entertainment systems and professional multimedia devices, this scaler maintains pristine video clarity and ensures compatibility with both standard and high-definition graphical interfaces.
VISENGI's Bayer To RGB Converter is a bilinear interpolation hardware IP core designed to transform Bayer format pixel data into full-color RGB output. This intricate process involves interpolating missing color components at each pixel location using neighboring data, ensuring vibrant and true-to-life color replication. Capable of handling extremely high throughput, the converter facilitates one RGB pixel per cycle output with notable minimal latency. The core can be configured to support various Bayer sensor pixel bit widths, sensor signaling modes, and end-output pixel bit widths, lending it impressive flexibility across diverse applications. Equipped to handle images of unlimited sizes, the converter seamlessly integrates into existing systems using dual clock regions, thereby supporting different input and output clock logistics. Beyond this, it offers configurations that cater to resource-critical environments, optimizing logic use and adapting to specific operational constraints, making it an invaluable tool for modern imaging solutions.
The v-MP4000UDX Visual Processing Unit by Videantis is a formidable processing solution designed to meet the demands of modern deep learning and computer vision applications. This unit integrates key functionalities of image and signal processing with enhanced capabilities for video coding. Its architecture is designed to handle various data-intensive tasks on a single platform, reducing the complexity involved in developing and integrating such functionalities into embedded systems. Equipped with a unified architecture, the v-MP4000UDX ensures all embedded processing activities take place without requiring additional hardware or extensive power resources. This integration allows for streamlined workflows that keep power usage and costs to a minimum. It supports tasks like neural network computation, making it ideal for devices that require advanced visual processing such as automotive systems, mobile devices, and professional-grade equipment. The v-MP4000UDX Visual Processing Unit excels at processing high volumes of data efficiently. It is recognized for its ability to support a range of image processing functions, while also ensuring advanced video codec standards are maintained. This makes it an excellent choice for high-performance applications that demand low latency and high-quality output. The flexibility and power efficiency of this processing unit affirm its suitability for a wide array of professionals seeking reliable and cutting-edge technology solutions.
The Mali-C78AE is designed to achieve high-level image processing, catering primarily to industrial and automotive settings where precision in visual data capture is critical. It represents a significant leap in enabling advanced driver assistance systems (ADAS) and autonomous vehicle technology. Its structure is optimized for real-time processing, with high-speed data throughput and sophisticated image processing algorithms that support clear, high-quality image outputs under varying lighting conditions. This processor ensures reliable, fast image recognition and processing, which is vital for safety and navigation in automated systems. Incorporating error detection and correction mechanisms, the Mali-C78AE is highly resilient, reducing the risk of failure and ensuring consistent performance. With its robust security and processing capabilities, it is well-suited for use in smart vehicles and other precision-requiring environments.
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