All IPs > Wireline Communication
Wireline Communication semiconductor IPs are critical components in the semiconductor industry, playing a vital role in enabling efficient data transmission across fixed networks. They are designed to optimize the performance of data transfer over physical media like copper cables, fiber optics, or hybrid systems. Given the growing demand for faster and more reliable data transmission, these IPs are indispensable in the development of network infrastructure and communication devices.
Products within this category cover a wide array of technologies essential for different communication protocols. For instance, Ethernet IPs are fundamental for creating network interfaces capable of high-speed data exchange, contributing to the performance of local and wide-area networks. The Fibre Channel IPs are specifically tailored for storage area networks, providing high-speed, lossless data transmission which is crucial for data-intensive applications in enterprise environments.
Additionally, this category includes Error Correction/Detection IPs, critical for maintaining data integrity during transmission by identifying and rectifying errors without needing retransmission. Our portfolio also comprises IPs for Modulation/Demodulation which play a key role in preparing data for transmission and ensuring it is correctly interpreted upon receipt. Other pivotal subcategories include ATM/Utopia, which aid in asynchronous transfer mode communications, and CEI, which contribute to high-speed chip-to-chip and board-to-board communications.
Overall, Wireline Communication semiconductor IPs facilitate the development of robust and efficient communication solutions across various industries. Whether for building telecommunication infrastructure or advancing next-generation networking devices, these IPs are central to achieving high performance, scalability, and reliability in wireline communication networks.
Designed for high-performance applications, the Metis AIPU PCIe AI Accelerator Card by Axelera AI offers powerful AI processing capabilities in a PCIe card format. This card is equipped with the Metis AI Processing Unit, capable of delivering up to 214 TOPS, making it ideal for intensive AI tasks and vision applications that require substantial computational power. With support for the Voyager SDK, this card ensures seamless integration and rapid deployment of AI models, helping developers leverage existing infrastructures efficiently. It's tailored for applications that demand robust AI processing like high-resolution video analysis and real-time object detection, handling complex networks with ease. Highlighted for its performance in ResNet-50 processing, which it can execute at a rate of up to 3,200 frames per second, the PCIe AI Accelerator Card perfectly meets the needs of cutting-edge AI applications. The software stack enhances the developer experience, simplifying the scaling of AI workloads while maintaining cost-effectiveness and energy efficiency for enterprise-grade solutions.
Alphawave Semi's 1G to 224G SerDes stands as a cornerstone in high-speed connectivity applications. This versatile SerDes solution supports a broad data rate range and multiple signaling schemes, such as PAM2, PAM4, PAM6, and PAM8, which adapt seamlessly to a variety of industry protocols and standards. Designed with the future of connectivity in mind, this intellectual property is critical for systems requiring robust and reliable data transmission across numerous networking environments. Notably, the 1G to 224G SerDes is engineered to deliver unparalleled performance, offering low latency and minimal power consumption. Its application is widespread in data center infrastructures, telecommunications, automotive systems, and beyond, providing the backbone for next-generation data processing and transmission needs. By integrating this SerDes, users can expect to enhance communication speed and efficiency, vital for maintaining competitive advantage in a rapidly evolving market. The ability to adapt to cutting-edge technologies, like AI and 5G, further underscores its versatility. This SerDes IP enables seamless integration of digital processing units with minimal interference, thus fostering robust system interconnections essential for high-performance computing environments.
Panmnesia's CXL 3.1 Switch is an integral component designed to facilitate high-speed, low-latency data transfers across multiple connected devices. It is architected to manage resource allocation seamlessly in AI and high-performance computing environments, supporting broad bandwidth, robust data throughput, and efficient power consumption, creating a cohesive foundation for scalable AI infrastructures. Its integration with advanced protocols ensures high system compatibility.
The Low Density Parity Check (LDPC) codes are powerful, capacity approaching channel codes and have exceptional error correction capabilities. The high degree of parallelism that they offer enables efficient, high throughput hardware architectures. The ntLDPC_WiFi6 IP Core is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes and is fully compliant with IEEE 802.11 n/ac/ax standard. The Quasi-Cyclic LDPC codes are based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that they offer high throughput at low implementation complexity. The ntLDPC_WiFi6 decoder IP Core may optionally implement one of two approximations of the log-domain LDPC iterative decoding algorithm (Belief propagation) known as either Layered Normalized Offset Min-Sum Algorithm or Layered Lambda-min Algorithm. Selecting between the two algorithms presents a decoding performance .vs. system resources utilization trade-off. The core is highly reconfigurable and fully compliant to the IEEE 802.11 n/ac/ax Wi-Fi4, Wi-Fi5 and Wi-Fi 6 standards. The ntLDPC_WiFi6 encoder IP implements a 81-bit parallel systematic LDPC encoder. An off-line profiling Matlab script processes the original matrices and produces a set of constants that are associated with the matrix and hardcoded in the RTL encoder.
Designed to cater to high-performance networking needs, this offload engine integrates multiple functionalities including TCP offloading, MAC, PCIe, and host interface in one low-latency package. It enables a complete bypass of the host CPU processing, drastically reducing the load and enhancing data throughput. The solution boasts an ultra-low latency of 77 ns, ensuring robust performance suited for critical applications that demand high-speed data processing. The architecture of this offload engine supports a vast number of concurrent TCP and UDP sessions, offering a consistent latency and impressive data transfer rate per session. By offloading network processing tasks, this solution frees up CPU resources, thus achieving efficient operation and lower power consumption. It is particularly advantageous for deployment in data-intensive environments such as cloud computing infrastructures and modern data centers. Equipped with dual-10G ports and advanced features like enterprise-class reliability and scalability, it has been widely adopted for its capability to execute networking tasks efficiently while consuming minimal resources. This engine integrates architecture that is designed to be immune to network jitter, providing a seamless networking experience across multiple ports.
The Jotunn8 AI Accelerator represents a pioneering approach in AI inference chip technology, designed to cater to the demanding needs of contemporary data centers. Its architecture is optimized for high-speed deployment of AI models, combining rapid data processing capabilities with cost-effectiveness and energy efficiency. By integrating features such as ultra-low latency and substantial throughput capacity, it supports real-time applications like chatbots and fraud detection that require immediate data processing and agile responses. The chip's impressive performance per watt metric ensures a lower operational cost, making it a viable option for scalable AI operations that demand both efficiency and sustainability. By reducing power consumption, Jotunn8 not only minimizes expenditure but also contributes to a reduced carbon footprint, aligning with the global move towards greener technology solutions. These attributes make Jotunn8 highly suitable for applications where energy considerations and environmental impact are paramount. Additionally, Jotunn8 offers flexibility in memory performance, allowing for the integration of complexity in AI models without compromising on speed or efficiency. The design emphasizes robustness in handling large-scale AI services, catering to the new challenges posed by expanding data needs and varied application environments. Jotunn8 is not simply about enhancing inference speed; it proposes a new baseline for scalable AI operations, making it a foundational element for future-proof AI infrastructure.
Time-Triggered Ethernet (TTEthernet) is a cutting-edge data communication solution tailored for aviation and space sectors requiring dual fault-tolerance and redundancy. Critically designed to support environments with high safety-criticality, TTEthernet embodies an evolutionary step in Ethernet communication by integrating deterministic behavior with conventional Ethernet benefits. This blend of technologies facilitates the transfer of data with precision timing, ensuring that all communications occur as scheduled—a vital feature for mission-critical operations. TTEthernet is particularly advantageous in applications requiring high levels of data integrity and latency control. Its deployment across triple-redundant network architectures ensures that even in case of component failures, the network continues to function seamlessly. Such redundancy is necessary in scenarios like human space missions, where data loss or delay is not an option. TTTech's TTEthernet offerings, which also include ASIC designs, meet the European Cooperation for Space Standardization (ECSS) standards, reinforcing their reliability and suitability for the most demanding applications. Supporting both end systems and more intricate system-on-chip designs, this technology synchronizes all data flow to maintain continuity and consistency throughout the network infrastructure.
RaiderChip's GenAI v1 is a pioneering hardware-based generative AI accelerator, designed to perform local inference at the Edge. This technology integrates optimally with on-premises servers and embedded devices, offering substantial benefits in privacy, performance, and energy efficiency over traditional hybrid AI solutions. The design of the GenAI v1 NPU streamlines the process of executing large language models by embedding them directly onto the hardware, eliminating the need for external components like CPUs or internet connections. With its ability to support complex models such as the Llama 3.2 with 4-bit quantization on LPDDR4 memory, the GenAI v1 achieves unprecedented efficiency in AI token processing, coupled with energy savings and reduced latency. What sets GenAI v1 apart is its scalability and cost-effectiveness, significantly outperforming competitive solutions such as Intel Gaudi 2, Nvidia's cloud GPUs, and Google's cloud TPUs in terms of memory efficiency. This solution maximizes the number of tokens generated per unit of memory bandwidth, thus addressing one of the primary limitations in generative AI workflow. Furthermore, the adept memory usage of GenAI v1 reduces the dependency on costly memory types like HBM, opening the door to more affordable alternatives without diminishing processing capabilities. With a target-agnostic approach, RaiderChip ensures the GenAI v1 can be adapted to various FPGAs and ASICs, offering configuration flexibility that allows users to balance performance with hardware costs. Its compatibility with a wide range of transformers-based models, including proprietary modifications, ensures GenAI v1's robust placement across sectors requiring high-speed processing, like finance, medical diagnostics, and autonomous systems. RaiderChip's innovation with GenAI v1 focuses on supporting both vanilla and quantized AI models, ensuring high computation speeds necessary for real-time applications without compromising accuracy. This capability underpins their strategic vision of enabling versatile and sustainable AI solutions across industries. By prioritizing integration ease and operational independence, RaiderChip provides a tangible edge in applying generative AI effectively and widely.
The ARINC 818 Product Suite is a comprehensive collection of tools and resources designed to support the full development lifecycle for ARINC 818 enabled equipment. This suite assists in the implementation and testing of ARINC 818 protocols, which are crucial for systems that require high-performance video and data transmission, such as in avionics and defense applications. The product suite is built to facilitate not only the development and qualification but also the simulation of ARINC 818 products, ensuring effective integration into mission-critical environments. The suite’s tools include development software and Implementer's guides, enabling seamless access to ARINC 818 capabilities.
The ntLDPC_G98042 (17664,14592) IP Core is defined in IEEE 802.3ca-2020, it is used by ITU-T G.9804.2-09.2021 standard document and it is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes. These LDPC codes are based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that they offer high throughput at low implementation complexity. The ntLDPCΕ_G98042 encoder IP implements a 256-bit parallel systematic LDPC encoder. The Generator LDPC Matrix is calculated off-line, compressed and stored in ROM. It is partitioned to 12 layers and each layer, when multiplied by the 14592 payload block, produces 256 parity bits. The multiplier architecture may be parameterized before synthesis to generate multiple multiplier instances [1:4,6], in order to effectively process multiple layers in parallel and improve the IP throughput rate. Shortened blocks are supported with granularity of 128-bit boundaries and 384 or 512 parity bits puncturing is also optionally supported. The ntLDPCD_G98042 decoder IP Core may optionally implement one of two approximations of the log-domain LDPC iterative decoding algorithm (Belief propagation) known as either Layered Offset Min-Sum Algorithm (OMS) or Layered Lambda-min Algorithm (LMIN). Selecting between the two algorithms presents a decoding performance vs. system resources utilization trade-off. The OMS algorithm is chosen for this implementation, given the high code rate of the Parity Check Matrix (PCM). The ntLDPCD_G98042 decoder IP implements a 256-bit parallel systematic LDPC layered decoder. Each layer corresponds to Z=256 expanded rows of the original LDPC matrix. Each layer element corresponds to the active ZxZ shifted identity sub-matrices within the layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit, in order to update the layers’ LLR estimates and extrinsic information iteratively until the required number of decoding iterations has been run. The decoder IP also features a powerful optional syndrome check early termination (ET) criterion, to maintain identical error correction performance, while significantly increasing its throughput rate and/or reducing hardware cost. Additionally it reports how many decoding iterations have been performed when ET is activated, for system performance observation and calibration purposes. A top level architecture deployment wrapper allows to expand the parallelism degree of the decoder before synthesis, effec-tively implementing a trade-off between utilized area and throughput rate. Finally a simple, yet robust, flow control handshaking mechanism is included in both IPs, which is used to communicate the IPs availability to adjacent system components at 128-bit parallel bus interface. This logic is easily portable into any communication protocol, like AXI4 stream IF.
**Ceva-PentaG2** is a complete IP platform for implementing a wide range of user-equipment and IoT cellular modems. The platform includes a variety of DSPs, modem hardware modules, software libraries, and simulation tools. Capabilities of the Ceva-PentaG2 include New Radio (NR) physical layer design ranging across all 3GPP profiles from RedCap IoT and mMTC, through eMBB up to ultra-reliable low-latency communications (URLLC). The platform has two base configurations. Ceva-PentaG2 Max emphasizes performance and scalability for enhanced mobile broadband (eMBB) and future proofing design for next generation 5G-Advanced releases. Ceva-PentaG2 Lite emphasizes extreme energy and area efficiency for lower-throughput applications such as LTE Cat 1, RedCap, and optimized cellular IoT applications. The PentaG2 platform comprises a set of Ceva DSP cores, optimized fixed-function hardware accelerators, and proven, optimized software modules. By using this platform, designers can implement optimized, hardware-accelerated processing chains for all main modem functions. In the selection process, designers can tune their design for any point across a huge space of area, power consumption, latency, throughput, and channel counts. Solutions can fit applications ranging from powerful eMBB for mobile and Fixed Wireless Access (FWA) devices to connected vehicles, cellular IoT modules, and even smart watches. System-C models in Ceva’s Virtual Platform Simulator (VPS) aid architectural exploration and system tuning, while an FPGA-based emulation kit speeds SoC integration. [**Learn more about Ceva-PentaG2 solution>**](https://www.ceva-ip.com/product/ceva-pentag2/?utm_source=silicon_hub&utm_medium=ip_listing&utm_campaign=ceva_pentag2_page)
EW6181 is an IP solution crafted for applications demanding extensive integration levels, offering flexibility by being licensable in various forms such as RTL, gate-level netlist, or GDS. Its design methodology focuses on delivering the lowest possible power consumption within the smallest footprint. The EW6181 effectively extends battery life for tags and modules due to its efficient component count and optimized Bill of Materials (BoM). Additionally, it is backed by robust firmware ensuring highly accurate and reliable location tracking while offering support and upgrades. The IP is particularly suitable for challenging application environments where precision and power efficiency are paramount, making it adaptable across different technology nodes given the availability of its RF frontend.
The ePHY-5616 delivers data rates from 1 to 56Gbps across technology nodes of 16nm and 12nm. Designed for a diverse range of applications, this product offers superior BER and low latency, making it ideal for enterprise equipment like routers, switches, and network interface cards. The ePHY-5616 employs a highly configurable DSP-based receiver architecture designed to manage various insertion loss scenarios, from 10dB up to over 35dB. This ensures robust and reliable data transfer across multiple setups.
Ethernet MAC 10M/100M/1G/2.5G IP is a solution that enables the host to communicate data using the IEEE 802.3 standard for 10M, 100M, 1G, 2.5G speeds and is suited for use in networking equipment such as switches and routers. The Client-side interface for the IP is AXI-S and the Ethernet MAC IP comes with GMII, RGMII or MII interfaces on the PHY side. The Ethernet MAC 10M/100M/1G/2.5G IP features a compact and low latency solution, it is highly configurable and can optionally include IEEE 1588 Timestamping Unit (TSU). The Silicon agnostic Ethernet MAC IP, suitable for ASICs and FPGAs, is prepared for easy integration with Ethernet PCS 10M/ 100M/1G/2.5G IP from Comcores.
The GenAI v1-Q from RaiderChip brings forth a specialized focus on quantized AI operations, reducing memory requirements significantly while maintaining impressive precision and speed. This innovative accelerator is engineered to execute large language models in real-time, utilizing advanced quantization techniques such as Q4_K and Q5_K, thereby enhancing AI inference efficiency especially in memory-constrained environments. By offering a 276% boost in processing speed alongside a 75% reduction in memory footprint, GenAI v1-Q empowers developers to integrate advanced AI capabilities into smaller, less powerful devices without sacrificing operational quality. This makes it particularly advantageous for applications demanding swift response times and low latency, including real-time translation, autonomous navigation, and responsive customer interactions. The GenAI v1-Q diverges from conventional AI solutions by functioning independently, free from external network or cloud auxiliaries. Its design harmonizes superior computational performance with scalability, allowing seamless adaptation across variegated hardware platforms including FPGAs and ASIC implementations. This flexibility is crucial for tailoring performance parameters like model scale, inference velocity, and power consumption to meet exacting user specifications effectively. RaiderChip's GenAI v1-Q addresses crucial AI industry needs with its ability to manage multiple transformer-based models and confidential data securely on-premises. This opens doors for its application in sensitive areas such as defense, healthcare, and financial services, where confidentiality and rapid processing are paramount. With GenAI v1-Q, RaiderChip underscores its commitment to advancing AI solutions that are both environmentally sustainable and economically viable.
The HOTLink II Product Suite constitutes a range of resources specifically tailored for systems utilizing HOTLink II™ technology. This suite is engineered to manage high-speed video and data communication in environments where reliability and precision are paramount. It is ideal for applications in aerospace where maintaining high data integrity is critical. The suite provides robust solutions for both the development and operational stages, enhancing system performance. With its extensive support for different phases of product lifecycle management, the HOTLink II suite ensures that products meet the high standards required for mission-critical military and industrial applications.
The ntLDPC_5GNR Base Graph Encoder IP Core is defined in 3GPP TS 38.212 standard document and it is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes. The specification defines two sets of LDPC Base Graphs and their respective derived Parity Check Matrices. Each Base Graph can be combined with 8 sets of lifting sizes (Zc) in a total of 51 different lifting sizes. This way by using the 2 Base Graphs, the 5G NR specification defines up to 102 possible distinct LDPC modes of operation to select from, for optimum decoding performance, depending on target application code block size and code rate (using the additional rate matching module features). For Base Graph 1 we have LDPC(N=66xZc,K=22xZc) sized code blocks, while for Base Graph 2 we have LDPC(N=50xZc,K=[6,8,9,10]xZc) sized code blocks. The ntLDPCE_5GNR Encoder IP implements a multi-parallel systematic LDPC encoder. Parallelism depends on the selected lifting sizes subsets chosen for implementation. Shortened blocks are supported with granularity at lifting size Zc-bit boundaries. Customizable modes generation is also supported beyond the scope of the 5G-NR specification with features such as: “flat parity bits puncturing instead of Rate Matching Bit Selection”, “maintaining the first 2xZc payload bits instead of eliminating it before transmission”, etc. The ntLDPCD_5GNR decoder IP implements a maximum lifting size of Zc_MAX-bit parallel systematic LDPC layered decoder. Each layer corresponds to Zc_MAX expanded rows of the original LDPC matrix. Each layer element corresponds to the active ZcxZc shifted identity sub-matrices within the layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit, in order to update the layers LLR estimates and extrinsic information iteratively until the required number of decoding iterations has been run. The decoder IP also features a powerful optional early termination (ET) criterion, to maintain practically equivalent error correction performance, while significantly increasing its throughput rate and/or reducing hardware cost. Additionally it reports how many decoding iterations have been performed when ET is activated, for system performance observation and calibration purposes. Finally a simple, yet robust, flow control handshaking mechanism is included in both IPs, which is used to communicate the IPs availability to adjacent system components. This logic is easily portable into any communication protocol, like AXI4 stream IF.
The Flexibilis Ethernet Switch (FES) is an advanced Layer 2 Ethernet switch IP tailored for high data throughput and time-sensitive applications. It features a multi-gigabit forwarding engine that can handle 10/100/1000 Mbps speeds across its ports. Designed for integration into FPGA environments, FES serves exceptionally well in scenarios demanding dynamic traffic management and precise time synchronization. FES supports advanced clock synchronization via the IEEE 1588 protocol, ensuring sub-microsecond accuracy, making it suitable for high-precision applications in sectors like power utilities and telecommunications. The switch combines this with packet prioritization and VLAN tagging functionalities, allowing for efficient network traffic segmentation and Quality of Service (QoS) management. The switch's versatile design includes support for various physical interfaces, such as MII/GMII and optional SGMII/RGMII adapters, making it suitable for deployment in varied network setups. FES offers a robust framework for developing comprehensive network solutions that require high availability and precise timing control, addressing the complex needs of modern industrial and utility applications.
The Ultra-Low Latency 10G Ethernet MAC from Chevin Technology is designed to deliver exceptional speed and efficiency for cutting-edge FPGA applications. Its primary focus is on reducing latency to the bare minimum while maintaining a high data throughput. This Ethernet MAC is universally compatible with Intel and AMD FPGA platforms, offering seamless adaptation to various projects. This solution is especially advantageous for environments where near-instantaneous data transmission is a necessity. Ideal for applications in high-frequency trading, telecommunications, and advanced scientific instrumentation, the Ultra-Low Latency 10G Ethernet MAC ensures that data integrity is preserved even at high speeds. Chevin Technology's meticulous in-house testing and development processes guarantee that this IP core meets stringent quality and performance standards. It offers a scalable, all-hardware architecture that slashes the usual implementation time, allowing more resources to be dedicated to expanding functionality and securing additional data pathways.
The pPLL03F-GF22FDX is a sophisticated all-digital fractional-N PLL optimized for performance computing applications using GlobalFoundries 22FDX technology. This PLL is engineered for environments with rigorous timing requirements, offering low jitter performance of less than 10 picoseconds RMS at operational frequencies as high as 4GHz. Compact and power-efficient, it typically occupies less than 0.01 square millimeters and consumes under 5 milliwatts of power. The architecture of the pPLL03F-GF22FDX is built on Perceptia's advanced second-generation digital PLL technology, which provides consistent performance across various processes, regardless of PVT conditions. This design is particularly well-suited to applications where multiple clock domains are present, each controlled by its dedicated PLL, thanks to integrated power supply regulation that simplifies system design and power sharing. Integration into complex SoC designs is seamless, supported by comprehensive deliverables that include models and views necessary for modern backend design flows. The adaptable nature of this PLL allows it to be configured as either an integer-N or fractional-N PLL, offering flexibility in aligning system-level input and output clock frequencies. Clients are also offered extensive customization and integration support, ensuring optimal fit and functionality in diverse applications.
The Time-Triggered Protocol (TTP) stands out as a robust framework for ensuring synchronous communication in embedded control systems. Developed to meet stringent aerospace industry criteria, TTP offers a high degree of reliability with its fault-tolerant configuration, integral to maintaining synchrony across various systems. This technology excels in environments where timing precision and data integrity are critical, facilitating accurate information exchange across diverse subsystems. TTTech’s TTP implementation adheres to the SAE AS6003 standard, making it a trusted component among industry leaders. As part of its wide-ranging applications, this protocol enhances system communication within commercial avionic solutions, providing dependable real-time data handling that ensures system stability. Beyond aviation, TTP's applications can also extend into the energy sector, demonstrating its versatility and robustness. Characterized by its deterministic nature, TTP provides a framework where every operation is scheduled, leading to predictable data flow without unscheduled interruptions. Its suitability for field-programmable gate arrays (FPGAs) allows for easy adaptation into existing infrastructures, making it a versatile tool for companies aiming to upgrade their communication systems without a complete overhaul. For engineers and developers, TTP provides a dependable foundation that streamlines the integration process while safeguarding communication integrity.
Convolutional FEC codes are very popular because of their powerful error correction capability and are especially suited for correcting random errors. The most effective decoding method for these codes is the soft decision Viterbi algorithm. ntVIT core is a high performance, fully configurable convolutional FEC core, comprised of a 1/N convolutional encoder, a variable code rate puncturer/depuncturer and a soft input Viterbi decoder. Depending on the application, the core can be configured for specific code parameters requirements. The highly configurable architecture makes it ideal for a wide range of applications. The convolutional encoder maps 1 input bit to N encoded bits, to generate a rate 1/N encoded bitstream. A puncturer can be optionally used to derive higher code rates from the 1/N mother code rate. On the encoder side, the puncturer deletes certain number of bits in the encoded data stream according to a user defined puncturing pattern which indicates the deleting bit positions. On the decoder side, the depuncturer inserts a-priori-known data at the positions and flags to the Viterbi decoder these bits positions as erasures. The Viterbi decoder uses a maximum-likelihood detection recursive process to cor-rect errors in the data stream. The Viterbi input data stream can be composed of hard or soft bits. Soft decision achieves a 2 to 3dB in-crease in coding gain over hard-decision decoding. Data can be received continuously or with gaps.
The Ethernet Real-Time Publish-Subscribe (RTPS) IP Core offers a thorough hardware implementation of the Ethernet RTPS protocol, which is utilized for real-time communication in Ethernet networks. Its architecture supports efficient and deterministic data transfer, crucial in environments that demand reliable and high-speed data exchanges. The IP core is particularly beneficial within applications that require consistent communication and reduced latency, fostering robust network infrastructures.
Credo's SerDes PHY solutions are pivotal in enabling high-performance interconnects for custom ASICs and advanced signal processing applications. Specifically engineered to balance performance with power efficiency, these solutions leverage unique, patented DSP architectures that can be implemented using mature process nodes, thereby maintaining cost efficiency without compromising on quality. The design flexibility allows the seamless integration of SerDes PHY into various ASIC platforms, making it ideal for complex digital signal processing and AI tasks. Credo’s SerDes PHYs are available as both licensed IP and chiplets to cater to a broad spectrum of customer needs. These solutions are also adaptable, capable of accommodating a range of signaling, from 112G to 56G, in various modes like PAM4 and NRZ. The architecture is further configured to support diverse operating conditions, ensuring compatibility across different fabrication technologies and design scenarios. The adaptability of SerDes PHY makes it highly suitable for integration into multiple platforms such as Multi-Chip Modules (MCM) and 2.5D interposers. This characteristic simplifies the design process for high-speed interconnects and assists in overcoming conventional barriers associated with the same-process logic and SerDes integration. As a result, Credo enables more accessible and economically viable solutions for pioneering ASIC designs that demand robust performance and scalability.
The Digital Radio (GDR) from GIRD Systems is an advanced software-defined radio (SDR) platform that offers extensive flexibility and adaptability. It is characterized by its multi-channel capabilities and high-speed signal processing resources, allowing it to meet a diverse range of system requirements. Built on a core single board module, this radio can be configured for both embedded and standalone operations, supporting a wide frequency range. The GDR can operate with either one or two independent transceivers, with options for full or half duplex configurations. It supports single channel setups as well as multiple-input multiple-output (MIMO) configurations, providing significant adaptability in communication scenarios. This flexibility makes it an ideal choice for systems that require rapid reconfiguration or scalability. Known for its robust construction, the GDR is designed to address challenging signal processing needs in congested environments, making it suitable for a variety of applications. Whether used in defense, communications, or electronic warfare, the GDR's ability to seamlessly switch configurations ensures it meets the evolving demands of modern communications technology.
ntLDPC_SDAOCT IP implements a 5G-NR Base Graph 1 systematic Encoder/Decoder based on Quasi-Cyclic LDPC Codes (QC-LDPC), with lifting size Zc=384 and Information Block Size 8448 bits. The implementation is based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that it offers high throughput at low implementation complexity. The ntLDPCE_SDAOCT Encoder IP implements a systematic LDPC Zc=384 encoder. Input and Output may be selected to be 32-bit or 128-bits per clock cycle prior to synthesis, while internal operations are 384-bits parallel per clock cycle. Depending on code rate, the respective amount of parity bits are generated and the first 2xZc=768 payload bits are discarded. There are 5 code rate modes of operation available (8448,8448)-bypass, (9984,8448)-0.8462, (11136,8448)-0.7586, (12672,8448)-0.6667 and (16896,8448)-0.5. The ntLDPCD_SDAOCT Base Graph Decoder IP may optionally implement one of two approximations of the log-domain LDPC iterative decoding algorithm (Belief propagation) known as either Layered Min-Sum Algorithm (MS) or Layered Lambda-min Algorithm (LMIN). Variations of Layered MS available are Offset Min-Sum (OMS), Normalized Min-Sum (NMS), and Normalized Offset Min-Sum (NOMS). Selecting between these algorithms presents a decoding performance vs. system resources utilization trade-off. The ntLDPCD_SDAOCT decoder IP implements a Zc=384 parallel systematic LDPC layered decoder. Each layer corresponds to Zc=384 expanded rows of the original LDPC matrix. Each layer element corresponds to the active ZcxZc shifted identity submatrices within the layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit, in order to update the layers LLR estimates and extrinsic information iteratively until the required number of decoding iterations has been run. The decoder IP also features a powerful optional early termination (ET) criterion, to maintain practically equivalent error correction performance, while significantly increasing its throughput rate and/or reducing hardware cost. Additionally it reports how many decoding iterations have been performed when ET is activated, for system performance observation and calibration purposes. Finally a simple, yet robust, flow control handshaking mechanism is included in both IPs, which is used to communicate the IPs availability to adjacent system components. This logic is easily portable into any communication protocol, like AXI4 stream IF.
The Digital PreDistortion (DPD) Solution from Systems4Silicon is a comprehensive adaptive technology aimed at improving the efficiency of RF power amplifiers. It is designed to maximize amplifier performance by allowing operation in the non-linear region while significantly reducing distortion. The solution is highly scalable, allowing for resource optimization across bandwidth, performance, and multiple antenna configurations. It is technology-agnostic, supporting various transistor technologies such as LDMOS and GaN, and can be adapted to different amplifier topologies including Doherty configurations. Benefits of the DPD technology include achieving over 50% efficiency improvements when utilized alongside the latest GaN devices, with amplifier distortion improvements of over 45 dB. This IP also supports multi-carrier and multi-standard transmissions, covering a broad array of standards such as 3G, 4G, 5G, DVB, and many more. It is compliant with the O-RAN standard for 7-2x deployments, making it a versatile solution for modern wireless communication systems. Systems4Silicon's DPD solution includes comprehensive integration and performance analysis tools, backed by expert support from experienced radio systems engineers. Designed for both FPGA/SoC and ASIC platforms, it provides a low resource footprint while ensuring maximum efficiency across diverse applications.
TT-Ascalon™ is a versatile RISC-V CPU core developed by Tenstorrent, emphasizing the utility of open standards to meet a diverse array of computing needs. Built to be highly configurable, TT-Ascalon™ allows for the inclusion of 2 to 8 cores per cluster complemented by a customizable L2 cache. This architecture caters to clients seeking a tailored processing solution without the limitations tied to proprietary systems. With support for CHI.E and AXI5-LITE interfaces, TT-Ascalon™ ensures robust connectivity while maintaining system integrity and performance density. Its security capabilities are premised on equivalent RISC-V primitives, ensuring a reliable and trusted environment for operations involving sensitive data. Tenstorrent’s engineering prowess, evident in TT-Ascalon™, has been shaped by experienced personnel from renowned tech giants. This IP is meant to align with various performance targets, suited for complex computational tasks that demand flexibility and efficiency in design.
The DisplayPort 1.4 core by Parretto offers a comprehensive solution for implementing DisplayPort functionalities in electronic designs. This IP supports both source (DPTX) and sink (DPRX) configurations, making it a versatile choice for any DisplayPort application. It operates at link rates of 1.62, 2.7, 5.4, and 8.1 Gbps, including embedded DisplayPort rates, and supports 1, 2, and 4 DP lanes. The IP core is built with adaptability in mind, featuring native video and AXI stream video interfaces. It supports both Single Stream Transport (SST) and Multi Stream Transport (MST) modes, accommodating diverse video streaming needs. With dual and quad pixels per clock transmission, it can deliver up to 10-bit video in various colorspaces such as RGB, YCbCr 4:4:4, YCbCr 4:2:2, and YCbCr 4:2:0. Additionally, the DisplayPort 1.4 IP core includes a secondary data packet interface for audio and metadata transport, enhancing multimedia performance. It comes with an accessible Video Toolbox that includes a timing generator, test pattern generator, and video clock recovery feature. Parretto provides full source code access, ensuring customizable integration and increased product reliability.
RapidGPT is PrimisAI's flagship product, a cutting-edge generative AI-based Electronic Design Automation (EDA) tool designed to streamline and revolutionize hardware design. By employing an intuitive natural language interface, RapidGPT enhances productivity for hardware designers, allowing them to communicate their ideas effortlessly in Verilog code. This tool not only accelerates the entire design process, guiding engineers from conceptualization to the final bitstream or GDSII stage, but also brings third-party IP integration capabilities to the table. RapidGPT empowers users by offering features like AutoReview, an AI-based HDL auditor, and AutoComment, which generates intelligent comments for HDL files. This enriches the documentation process and ensures clarity in design communication. The tool further personalizes user experiences by customizing AI-powered project documentation with AutoDoc, building on the unique design practices and methodologies of each engineer. PrimisAI's RapidGPT isn't just an incremental improvement but a monumental leap in AI-driven EDA technology, tailored to address both individual designers and larger companies' needs. Its extensive feature set, combined with options for tailored enterprise solutions like on-premise deployments and specialized support, positions RapidGPT as a versatile ally in hardware innovation.
The High-Speed SerDes designed for chiplets by EXTOLL represents a pinnacle in data transfer technologies. This high-performance SerDes is specifically crafted to support the latest chiplet technologies by enabling rapid data movement across chip boundaries. Its implementation ensures minimal latency, critical for time-sensitive applications, all the while maintaining a structure that is easy to integrate within various semiconductor designs. This SerDes offers unparalleled flexibility and adaptability for users seeking high-speed connectivity within chiplet environments. It supports a wide range of mainstream process nodes, thus ensuring compatibility with a diverse array of design requirements. Moreover, its architecture is optimized for energy efficiency, reducing the overall power consumption of systems which is crucial in today’s power-conscious technological landscape. EXTOLL’s High-Speed SerDes is not only about performance but also about reliability and scalability. As systems require more data and increased processing power, maintaining data integrity becomes a mission-critical requirement. This SerDes is engineered to provide robust error correction and data integrity, thus ensuring high standards of reliability while supporting the data bandwidth needs of modern, complex semiconductor applications.
Tyr AI Processor Family is engineered to bring unprecedented processing capabilities to Edge AI applications, where real-time, localized data processing is crucial. Unlike traditional cloud-based AI solutions, Edge AI facilitated by Tyr operates directly at the site of data generation, thereby minimizing latency and reducing the need for extensive data transfers to central data centers. This processor family stands out in its ability to empower devices to deliver instant insights, which is critical in time-sensitive operations like autonomous driving or industrial automation. The innovative design of the Tyr family ensures enhanced privacy and compliance, as data processing stays on the device, mitigating the risks associated with data exposure. By doing so, it supports stringent requirements for privacy while also reducing bandwidth utilization. This makes it particularly advantageous in settings like healthcare or environments with limited connectivity, where maintaining data integrity and efficiency is crucial. Designed for flexibility and sustainability, the Tyr AI processors are adept at balancing computing power with energy consumption, thus enabling the integration of multi-modal inputs and outputs efficiently. Their performance nears data center levels, yet they are built to consume significantly less energy, making them a cost-effective solution for implementing AI capabilities across various edge computing environments.
The Network Protocol Accelerator Platform (NPAP) is engineered to accelerate network protocol processing and offload tasks at speeds reaching up to 100 Gbps when implemented on FPGAs, and beyond in ASICs. This platform offers patented and patent-pending technologies that provide significant performance boosts, aiding in efficient network management. With its support for multiple protocols like TCP, UDP, and IP, it meets the demands of modern networking environments effectively, ensuring low latency and high throughput solutions for critical infrastructure. NPAP facilitates the construction of function accelerator cards (FACs) that support 10/25/50/100G speeds, effectively handling intense data workloads. The stunning capabilities of NPAP make it an indispensable tool for businesses needing to process vast amounts of data with precision and speed, thereby greatly enhancing network operations. Moreover, the NPAP emphasizes flexibility by allowing integration with a variety of network setups. Its capability to streamline data transfer with minimal delay supports modern computational demands, paving the way for optimized digital communication in diverse industries.
The EZiD211, also known as Oxford-2, is a leading-edge demodulator and modulator developed by EASii IC to facilitate advanced satellite communications. It embodies a sophisticated DVB-S2X wideband tuner capable of supporting LEO, MEO, and GEO satellites, integrating proprietary features like Beam Hopping, VLSNR, and Super Frame applications. With EZiD211 at the helm, satellite communications undergo a transformation in efficiency and capacity, addressing both current and future demands for fixed data infrastructures, mobility, IoT, and M2M applications. Its technological forefront facilitates seamless operations in varied European space programs, validated by its full production readiness. EZiD211's design offers a unique capability to manage complex satellite links, enhance performance, and ensure robust and reliable data transmission. EASii IC provides comprehensive support through evaluation boards and samples, allowing smooth integration and testing to meet evolving satellite communication standards.
The High PHY Accelerators from AccelerComm are a collection of signal processing cores designed for ASIC, FPGA, and SoC applications, primarily focused on boosting 5G NR communications. These accelerators incorporate proprietary algorithms that allow users to attain the highest levels of throughput, efficiency, and power savings. These accelerator cores are engineered to facilitate seamless integration into existing systems, significantly improving spectral efficiency through advanced processing techniques. The use of patented algorithms allows for overcoming system noise and interference, delivering superior performance for complex wireless communication networks. Moreover, these accelerators excel at minimizing latency and resource consumption, providing an optimal balance between high performance and low power requirements. Recognized for their flexibility, these accelerators support scalable architectures, customizable for various deployment scenarios. This versatility ensures operators and developers can adapt solutions to fit small, cost-sensitive applications or larger enterprise demands, enhancing the ability to handle high data volumes with integrity and reliability.
The Ncore Cache Coherent Interconnect from Arteris is engineered to overcome challenges associated with multicore SoC designs. It delivers high-bandwidth, low-latency interconnect fabric enhancing communication efficiency across various SoC components and multiple dies. Designed to ensure reliable performance and scalability, this coherent NoC addresses complex tasks by implementing heterogeneous coherency, and it is scalable from small embedded systems to extensive multi-die designs. Ncore promotes effective cache management, providing full coherency for processors and I/O coherency for accelerators. It supports various coherency protocols including CHI-E and ACE, and comes with ISO 26262 certification, meeting stringent safety standards in automotive environments. The inherent AMBA support allows seamless integration with existing and new SoC infrastructures, enhancing data handling efficiency. By offering automated generation of diagnostic analysis and fault modes, Ncore aids developers in creating secure systems ready for advanced automotive and AI applications, thereby accelerating their time-to-market. Its configurability and extensive protocol support position it as a trusted choice for industries requiring flexible and robust system integration solutions.
The FCM1401 is a 14GHz CMOS Power Amplifier tailored for Ku-band applications, operating over a frequency range of 12.4 to 16 GHz. This amplifier exhibits a gain of 22 dB and a saturated output power (Psat) of 19.24 dBm, ensuring optimal performance with a power-added efficiency (PAE) of 47%. The architecture enables reduction in battery consumption and heat output, making it ideal for satellite and telecom applications. Its small silicon footprint facilitates integration in space-constrained environments.
Chevin Technology's 10G Ethernet MAC and PCS solution is engineered to deliver premium data transfer speeds, ideal for high-performance FPGAs. Its compact all-logic architecture eliminates the need for external CPUs or software, minimizing complexity and enhancing efficiency. This IP achieves excellent link utilization and minimal latency, ensuring seamless integration into FPGA projects with ample room for additional design logic. The architecture supports sustained high throughput rates, making it particularly suited for demanding applications such as data storage and industrial imaging. With its proven performance and reliability, the 10G Ethernet MAC and PCS are trusted across numerous industries, including defense and scientific research. Its power-efficient design contributes to reduced energy consumption, a critical factor in modern FPGA designs. Moreover, this solution offers flexibility through its technology-agnostic approach, capable of functioning across a wide range of FPGA families from leading manufacturers like Intel and AMD. Clients appreciate the secure, high-speed connectivity this IP provides, coupled with Chevin Technology’s commitment to expert support and seamless customization capabilities.
AccelerComm offers an innovative LDPC solution specifically for 5G NR systems, pushing the boundaries of performance with its advanced block-parallel and row-parallel architectures. This sophisticated solution enhances data channel performance by utilizing a combination of scalability, high throughput, and low latency to maintain optimal communication systems. The LDPC solution effectively addresses standard 5G data channels, achieving substantive gains in resource utilization efficiency. By improving the already stringent latency specifications to support numerology 4, the solution ensures comprehensive code and transport block processing capabilities. It also upholds IEEE standards, providing a compliant pathway for high reliability and operational efficiency. Designed for integration across multiple platforms, including ASIC, FPGA, and software form factors, LDPC’s flexibility allows for deployment in a range of network conditions. Its open standard software interfaces make it easily adaptable, presenting a robust and versatile framework for companies to enhance their 5G network communication protocols with minimal effort.
The ntRSC_DP1.4 IP core is compliant with Display Port 1.4 standard as published by Video Electronics Standards Association (VESA) for use in DSC (Display Stream Compression) technology. It is based on Reed-Solomon RS(254,250), 10 bit symbols, forward error correction code, where the codeword block consists of 250 information symbols and 4 RS parity symbols. The ntRSC_DP1.4 FEC IP Core ensures error resilient / glitch-free compressed video transport (DSC) to external displays. The implementation is very low latency, high speed with a simple interface for easy integration in SoC applications.
Dyumnin's RISCV SoC is a versatile platform centered around a 64-bit quad-core server-class RISCV CPU, offering extensive subsystems, including AI/ML, automotive, multimedia, memory, cryptographic, and communication systems. This test chip can be reviewed in an FPGA format, ensuring adaptability and extensive testing possibilities. The AI/ML subsystem is particularly noteworthy due to its custom CPU configuration paired with a tensor flow unit, accelerating AI operations significantly. This adaptability lends itself to innovations in artificial intelligence, setting it apart in the competitive landscape of processors. Additionally, the automotive subsystem caters robustly to the needs of the automotive sector with CAN, CAN-FD, and SafeSPI IPs, all designed to enhance systems connectivity within vehicles. Moreover, the multimedia subsystem boasts a complete range of IPs to support HDMI, Display Port, MIPI, and more, facilitating rich audio and visual experiences across devices.
Algo-Logic's FPGA Pre-Trade Risk Check is tailored for financial entities needing to assess risk in real-time before trade execution. This product implements risk assessment algorithms on FPGAs, enabling checks to be performed at the speeds necessary to keep pace with high-frequency trading. The integration on FPGA hardware ensures that pre-trade risk checks do not become bottlenecks and contribute to maintaining compliance with regulations while minimizing the latency typically associated with software-based checks.
The AST 500 and AST GNSS-RF are multifaceted SOC and RF solutions designed for GNSS applications. They support a wide array of constellations such as GPS, GLONASS, NavIC, and others, in multiple frequency bands, enhancing navigation performance. These ICs integrate features like secure boots and data encryption, facilitating robust security measures crucial for sensitive data. The AST GNSS-RF is equipped with capabilities for L1, L2, L5, and S band reception, catering to high-fidelity signal requirements across various applications. The support for dual-band reception ensures that ionosphere errors are minimized, offering exceptional positioning accuracy.
The High Speed Data Bus (HSDB) IP Core by New Wave Design provides a comprehensive physical (PHY) and MAC layer hardware implementation. It is engineered to deliver full-rate data throughput, facilitating seamless integration into network infrastructures. With a particular focus on compatibility, it features a design that aligns with F-22 interface standards, ensuring smooth application within related military avionics systems. This core is central to maintaining robust and high-speed data transmission in demanding environments.
Polar coding, a relatively recent addition to the 5G NR suite of technologies, is embraced by AccelerComm through their unique design that facilitates higher degrees of parallel processing. This advancement ensures operational efficiency and minimizes resource usage, thereby improving system robustness and throughput in 5G NR control channels. By employing a patented architecture, Polar coding exhibits flexibility and scalability, key to supporting high-performance 5G requirements. The reduced burden on hardware resources enables it to deliver superior BLER performance, crucial for meeting the stringent demands of modern telecommunications standards. Delivering across a spectrum of platforms, whether hardware-based like ASIC and FPGA or software-driven, Polar coding maintains a high degree of integration ease. This allows rapid deployment and alignment with existing infrastructure, ensuring seamless communication and data integrity in a wide array of network scenarios.
ntRSD core implements a time-domain Reed-Solomon decoding algorithm. The core is parameterized in terms of bits per symbol, maximum codeword length and maximum number of parity symbols. It also supports varying on the fly shortened codes. Therefore any desirable code-rate can be easily achieved rendering the decoder ideal for fully adaptive FEC applications. ntRSD core supports erasure decoding thus doubling its error correction capability. The core also supports continuous or burst decoding. The implementation is very low latency, high speed with a simple interface for easy integration in SoC applications.
A trailblazer in high-speed rail connectivity, LightningBlu offers a groundbreaking, track-to-train multi-gigabit mmWave solution. This technology is renowned for its seamless integration with train networks, providing stable and fast connections crucial for high-speed transport. LightningBlu operates efficiently over a rail-friendly frequency range from 57-71 GHz and delivers an impressive data throughput of up to 3.5 Gbps. The system comprises both trackside and train-top nodes, each featuring innovative two-sector radios to ensure continuous, dynamic connection between the train and the trackside infrastructure. The design includes components qualified for rugged rail environments, promising extended service life and low maintenance needs. The solution significantly boosts operational efficiency for rail networks, being deployed in key infrastructures like South Western Railways and Caltrain in Silicon Valley. Versatile and resilient, LightningBlu adapts to varied complexities found in high-speed transport contexts. It communicates data faster than 5G while maintaining lower power consumption than traditional mobile networks, ensuring a superior commuter experience through its reliability and speed.
CLOP Technologies' 60GHz Wireless Solution offers businesses an impressive alternative to traditional networking systems. Leveraging the IEEE 802.11ad WiFi standard and Wireless Gigabit Alliance MAC/PHY specifications, this solution achieves a peak data rate of up to 4.6Gbps. This makes it particularly suited for applications that require significant bandwidth, such as real-time, uncompressed HD video streaming and high-speed data transfers — operations that are notably quicker compared to current WiFi systems. The solution is engineered to support 802.11ad IP networking, providing a platform for IP-based applications like peer-to-peer data transfer and serving as a router or access point. Its architecture includes a USB 3.0 host interface and mechanisms for RF impairment compensation, ensuring both ease of access for host compatibility and robust performance even under high data rate operations. Operating on a frequency band ranging from 57GHz to 66GHz, the wireless solution utilizes modulation modes such as BPSK, QPSK, and 16QAM. It incorporates forward error correction (FEC) with LDPC codes, providing various coding rates for enhanced data integrity. Furthermore, the system boasts AES-128 hardware security, with quality of service maintained through IEEE 802.11e standards.
The iCan PicoPop® is a miniaturized system on module (SOM) based on the Xilinx Zynq UltraScale+ Multi-Processor System-on-Chip (MPSoC). This advanced module is designed to handle sophisticated signal processing tasks, making it particularly suited for aeronautic embedded systems that require high-performance video processing capabilities. The module leverages the powerful architecture of the Zynq MPSoC, providing a robust platform for developing cutting-edge avionics and defense solutions. With its compact form factor, the iCan PicoPop® SOM offers unparalleled flexibility and performance, allowing it to seamlessly integrate into various system architectures. The high level of integration offered by the Zynq UltraScale+ MPSoC aids in simplifying the design process while reducing system latency and power consumption, providing a highly efficient solution for demanding applications. Additionally, the iCan PicoPop® supports advanced functionalities through its integration of programmable logic, multi-core processing, and high-speed connectivity options, making it ideal for developing next-generation applications in video processing and other complex avionics functions. Its modular design also allows for easy customization, enabling developers to tailor the system to meet specific performance and functionality needs, ensuring optimal adaptability for intricate aerospace environments. Overall, the iCan PicoPop® demonstrates a remarkable blend of high-performance computing capabilities and adaptable configurations, making it a valuable asset in the development of high-tech avionics solutions designed to withstand rigorous operational demands in aviation and defense.
The ADQ35 is a high-performance digitizer that features dual-channel capabilities, providing a 12-bit resolution at an impressive 10 GSPS sampling rate. It is designed to meet demanding requirements for data acquisition, capable of streaming data at a throughput of 14 Gbyte/s. Equipped with up to a 3 GHz input bandwidth, it ensures precise signal capture and processing, making it ideal for a range of complex applications. This digitizer is optimized for scenarios requiring rapid data transfer and high fidelity in digital signal processing. Additionally, the ADQ35's architecture supports both single and dual-channel operations, adding versatility and adaptability in various operational setups. Its robust design supports pulse detection optimization, enhancing its effective resolution to an equivalent of 16-bit ENOB, thus delivering better signal integrity and improved measurement accuracy. Predominantly used in high-fidelity applications, it represents the pinnacle of Teledyne SP Devices’ dedication to precision engineering. The ADQ35 is also portable, providing an efficient solution for dynamic field operations while maintaining uncompromised data acquisition performance. This adaptability makes it a preferred choice for environments that require quick deployment and reliable results. Its integration within a system is facilitated by user-friendly software, enhancing usability while maintaining top-tier performance metrics.
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