All IPs > Wireline Communication
Wireline Communication semiconductor IPs are critical components in the semiconductor industry, playing a vital role in enabling efficient data transmission across fixed networks. They are designed to optimize the performance of data transfer over physical media like copper cables, fiber optics, or hybrid systems. Given the growing demand for faster and more reliable data transmission, these IPs are indispensable in the development of network infrastructure and communication devices.
Products within this category cover a wide array of technologies essential for different communication protocols. For instance, Ethernet IPs are fundamental for creating network interfaces capable of high-speed data exchange, contributing to the performance of local and wide-area networks. The Fibre Channel IPs are specifically tailored for storage area networks, providing high-speed, lossless data transmission which is crucial for data-intensive applications in enterprise environments.
Additionally, this category includes Error Correction/Detection IPs, critical for maintaining data integrity during transmission by identifying and rectifying errors without needing retransmission. Our portfolio also comprises IPs for Modulation/Demodulation which play a key role in preparing data for transmission and ensuring it is correctly interpreted upon receipt. Other pivotal subcategories include ATM/Utopia, which aid in asynchronous transfer mode communications, and CEI, which contribute to high-speed chip-to-chip and board-to-board communications.
Overall, Wireline Communication semiconductor IPs facilitate the development of robust and efficient communication solutions across various industries. Whether for building telecommunication infrastructure or advancing next-generation networking devices, these IPs are central to achieving high performance, scalability, and reliability in wireline communication networks.
The CXL 3.1 Switch by Panmnesia is a high-tech solution designed to manage diverse CXL devices within a cache-coherent system, minimizing latency through its proprietary low-latency CXL IP. This switch supports a scalable and flexible architecture, offering multi-level switching and port-based routing capabilities that allow expansive system configurations to meet various application demands. It is engineered to connect system devices such as CPUs, GPUs, and memory modules, ideal for constructing large-scale systems tailored to specific needs.
The Low Density Parity Check (LDPC) codes are powerful, capacity approaching channel codes and have exceptional error correction capabilities. The high degree of parallelism that they offer enables efficient, high throughput hardware architectures. The ntLDPC_WiFi6 IP Core is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes and is fully compliant with IEEE 802.11 n/ac/ax standard. The Quasi-Cyclic LDPC codes are based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that they offer high throughput at low implementation complexity. The ntLDPC_WiFi6 decoder IP Core may optionally implement one of two approximations of the log-domain LDPC iterative decoding algorithm (Belief propagation) known as either Layered Normalized Offset Min-Sum Algorithm or Layered Lambda-min Algorithm. Selecting between the two algorithms presents a decoding performance .vs. system resources utilization trade-off. The core is highly reconfigurable and fully compliant to the IEEE 802.11 n/ac/ax Wi-Fi4, Wi-Fi5 and Wi-Fi 6 standards. The ntLDPC_WiFi6 encoder IP implements a 81-bit parallel systematic LDPC encoder. An off-line profiling Matlab script processes the original matrices and produces a set of constants that are associated with the matrix and hardcoded in the RTL encoder.
RaiderChip's GenAI v1 is a pioneering hardware-based generative AI accelerator, designed to perform local inference at the Edge. This technology integrates optimally with on-premises servers and embedded devices, offering substantial benefits in privacy, performance, and energy efficiency over traditional hybrid AI solutions. The design of the GenAI v1 NPU streamlines the process of executing large language models by embedding them directly onto the hardware, eliminating the need for external components like CPUs or internet connections. With its ability to support complex models such as the Llama 3.2 with 4-bit quantization on LPDDR4 memory, the GenAI v1 achieves unprecedented efficiency in AI token processing, coupled with energy savings and reduced latency. What sets GenAI v1 apart is its scalability and cost-effectiveness, significantly outperforming competitive solutions such as Intel Gaudi 2, Nvidia's cloud GPUs, and Google's cloud TPUs in terms of memory efficiency. This solution maximizes the number of tokens generated per unit of memory bandwidth, thus addressing one of the primary limitations in generative AI workflow. Furthermore, the adept memory usage of GenAI v1 reduces the dependency on costly memory types like HBM, opening the door to more affordable alternatives without diminishing processing capabilities. With a target-agnostic approach, RaiderChip ensures the GenAI v1 can be adapted to various FPGAs and ASICs, offering configuration flexibility that allows users to balance performance with hardware costs. Its compatibility with a wide range of transformers-based models, including proprietary modifications, ensures GenAI v1's robust placement across sectors requiring high-speed processing, like finance, medical diagnostics, and autonomous systems. RaiderChip's innovation with GenAI v1 focuses on supporting both vanilla and quantized AI models, ensuring high computation speeds necessary for real-time applications without compromising accuracy. This capability underpins their strategic vision of enabling versatile and sustainable AI solutions across industries. By prioritizing integration ease and operational independence, RaiderChip provides a tangible edge in applying generative AI effectively and widely.
The CT25205 is a comprehensive digital controller designed for 10BASE-T1S Ethernet applications, providing seamless integration with Ethernet MACs and offering essential PMA, PCS, and PLCA Reconciliation Sublayer components. Crafted in Verilog 2005 HDL, this core is fully synthesizable on standard cells and FPGA systems, ensuring versatile deployment in various network architectures. The IP also supports PLCA RS, enabling advanced Ethernet features without the need for additional MAC extensions. It's developed to function with the OPEN Alliance 10BASE-T1S PMD interface, making it a robust solution for modern Ethernet-based systems.
The Jotunn8 represents a leap in AI inference technology, delivering unmatched efficiency for modern data centers. This chip is engineered to manage AI model deployments with lightning-fast execution, at minimal cost and high scalability. It ensures optimal performance by balancing high throughput and low latency, while being extremely power-efficient, which significantly lowers operational costs and supports sustainable infrastructures. The Jotunn8 is designed to unlock the full capacity of AI investments by providing a high-performance platform that enhances the delivery and impact of AI models across applications. It is particularly suitable for real-time applications such as chatbots, fraud detection, and search engines, where ultra-low latency and very high throughput are critical. Power efficiency is a major emphasis of the Jotunn8, optimizing performance per watt to control energy as a substantial operational expense. Its architecture allows for flexible memory allocation ensuring seamless adaptability across varied applications, providing a robust foundation for scalable AI operations. This solution is aimed at enhancing business competitiveness by supporting large-scale model deployment and infrastructure optimization.
Time-Triggered Ethernet (TTE) combines the robustness of Ethernet technology with the precision of time-triggered communication. Designed for critical applications that demand reliability and synchronized communication, TTE finds its place in aerospace and industrial sectors. TTE operates by affording secure, deterministic data transmission over Ethernet networks. It achieves this by dedicating specific time slots for high-priority traffic, ensuring latency and jitter are minimized. This segregation allows time-sensitive data to safely coexist with traditional Ethernet traffic, without sacrificing normal network operations. The protocol's architecture underlies a mixed-criticality networking environment, supporting integration with standard Ethernet devices. TTE's scheduling mechanism guarantees timely delivery of critical messages, crucial in environments where even microsecond delays can impact overall system performance. Its application ensures Ethernet networks meet the stringent requirements of real-time operations synonymous with safety-critical systems.
The 10G TCP Offload Engine (TOE) is a specialized hardware solution designed to alleviate CPU loads by handling TCP/IP traffic directly. Particularly useful in high-speed network environments, this offload engine ensures that servers can maintain optimal performance levels by significantly reducing the computational load associated with TCP processing. This TOE implementation offers low latency operation and supports a broad range of network protocols, making it an ideal fit for data centers and enterprise network settings. It ensures high throughput with minimal packet loss, which is crucial for applications like video streaming and large file transfers where data integrity and speed are paramount. Built with scalability in mind, the TOE can manage multiple connections concurrently, providing consistent performance even as network demands grow. The integration with existing network infrastructure is seamless, making it a cost-effective upgrade for enhancing network efficiency and reducing bottlenecks.
The HOTLink II Product Suite is another remarkable offering from Great River Technology. Built to complement their ARINC 818 suite, HOTLink II provides an integrated framework for crafting high-performance digital data links. This suite ensures seamless, secure, and reliable data transmission over fiber or copper cables across various platforms. Developed with a focus on flexibility and functionality, the HOTLink II capabilities enhance system integrators' ability to deploy effective communication solutions within aircraft and other demanding environments. The emphasis on robust, low-latency data transfer makes it an ideal choice for real-time applications where precision and reliability are paramount. Broad compatibility is a hallmark of HOTLink II, facilitating integration into diverse infrastructures. Backed by Great River Technology's expertise and support, customers are empowered to advance their system communication capabilities efficiently and cost-effectively.
The ntLDPC_G98042 (17664,14592) IP Core is defined in IEEE 802.3ca-2020, it is used by ITU-T G.9804.2-09.2021 standard document and it is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes. These LDPC codes are based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that they offer high throughput at low implementation complexity. The ntLDPCΕ_G98042 encoder IP implements a 256-bit parallel systematic LDPC encoder. The Generator LDPC Matrix is calculated off-line, compressed and stored in ROM. It is partitioned to 12 layers and each layer, when multiplied by the 14592 payload block, produces 256 parity bits. The multiplier architecture may be parameterized before synthesis to generate multiple multiplier instances [1:4,6], in order to effectively process multiple layers in parallel and improve the IP throughput rate. Shortened blocks are supported with granularity of 128-bit boundaries and 384 or 512 parity bits puncturing is also optionally supported. The ntLDPCD_G98042 decoder IP Core may optionally implement one of two approximations of the log-domain LDPC iterative decoding algorithm (Belief propagation) known as either Layered Offset Min-Sum Algorithm (OMS) or Layered Lambda-min Algorithm (LMIN). Selecting between the two algorithms presents a decoding performance vs. system resources utilization trade-off. The OMS algorithm is chosen for this implementation, given the high code rate of the Parity Check Matrix (PCM). The ntLDPCD_G98042 decoder IP implements a 256-bit parallel systematic LDPC layered decoder. Each layer corresponds to Z=256 expanded rows of the original LDPC matrix. Each layer element corresponds to the active ZxZ shifted identity sub-matrices within the layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit, in order to update the layers’ LLR estimates and extrinsic information iteratively until the required number of decoding iterations has been run. The decoder IP also features a powerful optional syndrome check early termination (ET) criterion, to maintain identical error correction performance, while significantly increasing its throughput rate and/or reducing hardware cost. Additionally it reports how many decoding iterations have been performed when ET is activated, for system performance observation and calibration purposes. A top level architecture deployment wrapper allows to expand the parallelism degree of the decoder before synthesis, effec-tively implementing a trade-off between utilized area and throughput rate. Finally a simple, yet robust, flow control handshaking mechanism is included in both IPs, which is used to communicate the IPs availability to adjacent system components at 128-bit parallel bus interface. This logic is easily portable into any communication protocol, like AXI4 stream IF.
The ePHY-5616 is a high-performance SerDes solution from eTopus, designed for versatile use across enterprise, data center, and 5G applications. Operating efficiently at data rates from 1 to 56 Gbps, this product exploits advanced DSP techniques for superior signal integrity and robustness. It accommodates wide insertion loss ranges of 10dB to over 35dB, thus ensuring reliable performance in challenging communication environments. Its architecture supports direct optical drives and quad/octal configurations, making it ideal for network interface cards, routers, and high-speed switches in a data center setup. The embedded DSP architecture is developed with eTopus's proprietary algorithms, which enable rapid SerDes tuning and performance optimization. The ePHY-5616 is also characterized by its low Bit Error Rate (BER), ensuring data reliability and integrity. Moreover, it supports multiple protocols, including Ethernet and PCIe, enhancing its integration potential in modern broadband networks.
EW6181 is an IP solution crafted for applications demanding extensive integration levels, offering flexibility by being licensable in various forms such as RTL, gate-level netlist, or GDS. Its design methodology focuses on delivering the lowest possible power consumption within the smallest footprint. The EW6181 effectively extends battery life for tags and modules due to its efficient component count and optimized Bill of Materials (BoM). Additionally, it is backed by robust firmware ensuring highly accurate and reliable location tracking while offering support and upgrades. The IP is particularly suitable for challenging application environments where precision and power efficiency are paramount, making it adaptable across different technology nodes given the availability of its RF frontend.
The 10G TCP Offload Engine with MAC and PCIe interface is engineered for ultra-low latency environments, serving as a robust solution for efficient data transmission in high-speed networks. By offloading TCP processing from the host CPU, it significantly reduces processing demands, enabling data centers and network infrastructures to streamline operations and enhance throughput. This offload engine demonstrates impressive scalability, supporting a variety of session capacities with consistent, minimal latency. Implemented using advanced architecture techniques, this offload engine offers a comprehensive TCP stack with MAC interface capabilities, ensuring seamless data flow across network devices. Its hardware-centric design further eliminates system bottlenecks, delivering high bandwidth and reliable data transmission even under high-load conditions. The PCIe integration allows for rapid, efficient communication within network systems, improving overall data handling efficiency. This solution is designed to minimize jitter and operates effectively in various network setups, making it ideal for cloud computing, large-scale data centers, and other demanding environments. Its robust configuration options and support for multiple sessions simultaneously make it a versatile choice for enterprises looking to maximize their network performance while reducing overhead costs.
The 1G to 224G SerDes is a state-of-the-art SerDes solution designed for applications requiring a wide array of data rates and signaling schemes. Supporting speeds from 1 Gbps up to an impressive 224 Gbps, this SerDes IP caters to multiple industry standard protocols such as Ethernet, PCIe, and CXL. The flexibility of this SerDes allows for integration into a wide range of devices, from data centers to network switches, where high data throughput and reliability are crucial.\n\nAt its core, this SerDes IP utilizes advanced modulation schemes including PAM2 (also known as NRZ), PAM4, and even more advanced techniques like PAM6 and PAM8. This flexibility in modulation ensures that the IP can adapt to different signal integrity requirements and channel conditions, making it an ideal choice for high-performance computing environments.\n\nMoreover, the 1G to 224G SerDes is engineered to deliver leading-edge performance with minimal power consumption, maintaining connectivity efficiency across various operational spectrums. Its robust design ensures that signal integrity is preserved, reducing bit error rates significantly, which is critical in maintaining the reliability of high-speed networks.
The CT25203 serves as a critical analog front-end for 10BASE-T1S Ethernet systems, working in conjunction with other Canova Tech IP like the CT25205 digital core for a complete solution. This product is engineered to align with the stringent OA TC14 specification, allowing seamless communication over standard 3-pin interfaces commonly used in automotive and industrial Ethernet networks. Its high-voltage process technology ensures optimal electromagnetic compatibility, critical for maintaining performance in challenging environments.
The Ethernet Real-Time Publish-Subscribe (RTPS) IP Core presents a complete hardware-based solution for the Ethernet RTPS protocol, enhancing real-time data distribution across complex network settings. Designed to meet the demands of high-performance environments, this core ensures minimal latency in data transfers, maintaining the integrity and synchronization essential for time-sensitive operations. The RTPS core supports intricate network systems demanding reliability and speed, making it indispensable in communication infrastructures where real-time data dissemination is paramount. Its robust design ensures adaptability and seamless integration into existing Ethernet platforms, empowering mission-critical operations with reliable data flow capabilities. The RTPS solution is vital for defense and aerospace industries that rely on expedited and accurate data exchanges, supporting agile and responsive decision-making processes.
The ntLDPC_5GNR Base Graph Encoder IP Core is defined in 3GPP TS 38.212 standard document and it is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes. The specification defines two sets of LDPC Base Graphs and their respective derived Parity Check Matrices. Each Base Graph can be combined with 8 sets of lifting sizes (Zc) in a total of 51 different lifting sizes. This way by using the 2 Base Graphs, the 5G NR specification defines up to 102 possible distinct LDPC modes of operation to select from, for optimum decoding performance, depending on target application code block size and code rate (using the additional rate matching module features). For Base Graph 1 we have LDPC(N=66xZc,K=22xZc) sized code blocks, while for Base Graph 2 we have LDPC(N=50xZc,K=[6,8,9,10]xZc) sized code blocks. The ntLDPCE_5GNR Encoder IP implements a multi-parallel systematic LDPC encoder. Parallelism depends on the selected lifting sizes subsets chosen for implementation. Shortened blocks are supported with granularity at lifting size Zc-bit boundaries. Customizable modes generation is also supported beyond the scope of the 5G-NR specification with features such as: “flat parity bits puncturing instead of Rate Matching Bit Selection”, “maintaining the first 2xZc payload bits instead of eliminating it before transmission”, etc. The ntLDPCD_5GNR decoder IP implements a maximum lifting size of Zc_MAX-bit parallel systematic LDPC layered decoder. Each layer corresponds to Zc_MAX expanded rows of the original LDPC matrix. Each layer element corresponds to the active ZcxZc shifted identity sub-matrices within the layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit, in order to update the layers LLR estimates and extrinsic information iteratively until the required number of decoding iterations has been run. The decoder IP also features a powerful optional early termination (ET) criterion, to maintain practically equivalent error correction performance, while significantly increasing its throughput rate and/or reducing hardware cost. Additionally it reports how many decoding iterations have been performed when ET is activated, for system performance observation and calibration purposes. Finally a simple, yet robust, flow control handshaking mechanism is included in both IPs, which is used to communicate the IPs availability to adjacent system components. This logic is easily portable into any communication protocol, like AXI4 stream IF.
The Ultra-Low Latency 10G Ethernet MAC from Chevin Technology is tailored for environments where speed and minimal delay are critical. Designed with a focus on reducing latency, this IP core enables high-frequency traders and ultra-fast data acquisition systems to operate with unparalleled efficiency. By using advanced algorithms and streamlined architecture, it achieves extremely low latencies, contributing to faster processing and decision-making. This Ethernet MAC supports full 10 Gbps bandwidth and operates efficiently across a varied range of data-intensive applications. It remains highly customizable, allowing integration with a variety of protocols and applications, thus catering to specific project needs without compromising on speed or performance. As a result, this MAC is particularly suited to sectors where time is of the essence, such as financial services, automated trading systems, and real-time data streaming. Chevin Technology also provides extensive support and documentation to ensure that users can achieve the best possible results from this advanced IP.
The Nerve IIoT Platform is a comprehensive solution for machine builders, offering cloud-managed edge computing capabilities. This innovative platform delivers high levels of openness, security, flexibility, and real-time data handling, enabling businesses to embark on their digital transformation journeys. Nerve's architecture allows for seamless integration with a variety of hardware devices, from basic gateways to advanced IPCs, ensuring scalability and operational efficiency across different industrial settings. Nerve facilitates the collection, processing, and analysis of machine data in real-time, which is crucial for optimizing production and enhancing operational efficiency. By providing robust remote management functionalities, businesses can efficiently handle device operations and application deployments from any location. This capacity to manage data flows between the factory floor and the cloud transitions enterprises into a new era of digital management, thereby minimizing costs and maximizing productivity. The platform also supports multiple cloud environments, empowering businesses to select their preferred cloud service while maintaining operational continuity. With its secure, IEC 62443-4-1 certified infrastructure, Nerve ensures that both data and applications remain protected from cyber threats. Its integration of open technologies, such as Docker and virtual machines, further facilitates rapid implementation and prototyping, enabling businesses to adapt swiftly to ever-changing demands.
The ntRSC_DP1.4 IP core is compliant with Display Port 1.4 standard as published by Video Electronics Standards Association (VESA) for use in DSC (Display Stream Compression) technology. It is based on Reed-Solomon RS(254,250), 10 bit symbols, forward error correction code, where the codeword block consists of 250 information symbols and 4 RS parity symbols. The ntRSC_DP1.4 FEC IP Core ensures error resilient / glitch-free compressed video transport (DSC) to external displays. The implementation is very low latency, high speed with a simple interface for easy integration in SoC applications.
Convolutional FEC codes are very popular because of their powerful error correction capability and are especially suited for correcting random errors. The most effective decoding method for these codes is the soft decision Viterbi algorithm. ntVIT core is a high performance, fully configurable convolutional FEC core, comprised of a 1/N convolutional encoder, a variable code rate puncturer/depuncturer and a soft input Viterbi decoder. Depending on the application, the core can be configured for specific code parameters requirements. The highly configurable architecture makes it ideal for a wide range of applications. The convolutional encoder maps 1 input bit to N encoded bits, to generate a rate 1/N encoded bitstream. A puncturer can be optionally used to derive higher code rates from the 1/N mother code rate. On the encoder side, the puncturer deletes certain number of bits in the encoded data stream according to a user defined puncturing pattern which indicates the deleting bit positions. On the decoder side, the depuncturer inserts a-priori-known data at the positions and flags to the Viterbi decoder these bits positions as erasures. The Viterbi decoder uses a maximum-likelihood detection recursive process to cor-rect errors in the data stream. The Viterbi input data stream can be composed of hard or soft bits. Soft decision achieves a 2 to 3dB in-crease in coding gain over hard-decision decoding. Data can be received continuously or with gaps.
The Flexibilis Ethernet Switch (FES) is a versatile Ethernet Layer-2 switch IP designed to deliver high-speed, reliable packet forwarding across a network. With triple-speed ranging from 10 Mbps to 1 Gbps, FES supports full-duplex Ethernet interfaces, enhancing data transfer efficiency and network performance. Its design emphasizes seamless integration within programmable hardware environments, complying with IEEE1588v2 standards for time synchronization. FES is engineered for scalability, offering configurations that range from 3-port to 12-port setups, thereby providing flexibility in supporting various network sizes and applications. It includes support for a variety of interface types, such as MII, GMII, and others, enhancing its compatibility with diverse network setups. As part of its robust feature set, FES incorporates packet filtering and Virtual LAN (VLAN) tagging for optimized traffic management. This switch IP core is adept at handling the demands of high-availability networks, with advanced memory management features that prevent resource bottlenecks. By minimizing latency and maximizing throughput, FES is ideal for applications that require reliable communication such as industrial automation and telecommunication networks, reinforcing Flexibilis' reputation for delivering resilient and high-performing network solutions.
The GenAI v1-Q from RaiderChip brings forth a specialized focus on quantized AI operations, reducing memory requirements significantly while maintaining impressive precision and speed. This innovative accelerator is engineered to execute large language models in real-time, utilizing advanced quantization techniques such as Q4_K and Q5_K, thereby enhancing AI inference efficiency especially in memory-constrained environments. By offering a 276% boost in processing speed alongside a 75% reduction in memory footprint, GenAI v1-Q empowers developers to integrate advanced AI capabilities into smaller, less powerful devices without sacrificing operational quality. This makes it particularly advantageous for applications demanding swift response times and low latency, including real-time translation, autonomous navigation, and responsive customer interactions. The GenAI v1-Q diverges from conventional AI solutions by functioning independently, free from external network or cloud auxiliaries. Its design harmonizes superior computational performance with scalability, allowing seamless adaptation across variegated hardware platforms including FPGAs and ASIC implementations. This flexibility is crucial for tailoring performance parameters like model scale, inference velocity, and power consumption to meet exacting user specifications effectively. RaiderChip's GenAI v1-Q addresses crucial AI industry needs with its ability to manage multiple transformer-based models and confidential data securely on-premises. This opens doors for its application in sensitive areas such as defense, healthcare, and financial services, where confidentiality and rapid processing are paramount. With GenAI v1-Q, RaiderChip underscores its commitment to advancing AI solutions that are both environmentally sustainable and economically viable.
The Dual-Drive™ Power Amplifier FCM1401 exemplifies advanced engineering in power amplification, designed specifically for extreme efficiency in wireless communication devices. Operating at a center frequency of 14 GHz, it boasts a sophisticated architecture that minimizes silicon area while enhancing performance metrics. One of the standout features of the FCM1401 is its impressive core drain efficiency, which reaches up to 62%, offering significant power savings and extended battery life for end users. Such efficiencies are particularly crucial in mobile devices, where power remains a critical resource. Moreover, this power amplifier features a dual-stage design to facilitate better signal strength and lower transmission losses. With an optimally configured supply voltage range, the FCM1401 performs without efficiency bottlenecking, crucial for systems with constrained power budgets. Its meticulous construction results in an efficiency at device output around 70%, allowing it to outperform competitors across various metrics. These enhancements not only make the FCM1401 ideal for mobile and satellite communications but also align perfectly with initiatives to lower telecommunication costs through energy-efficient technology. Supported by a drain efficiency that peaks even under full load conditions, Falcomm’s FCM1401 assures users of reliability under diverse operational scenarios. The assurance of minimal loss in complex QAM scenarios further underscores its potential for diverse communication applications. This exemplary power amplifier serves as a testament to Falcomm's commitment to innovation, combining unprecedented efficiency with practical applications in everyday technology.
AccelerComm's LDPC solution stands out for its innovative design that marries block-parallel and row-parallel architectures to deliver peak performance and efficiency. Primarily designed for 5G NR use cases, this product supports both data and control channels, proving its versatility across different communication requirements. With a focus on maximizing throughput and minimizing latency, the LDPC decoder is optimized for various hardware formats, including ASIC, FPGA, and software implementations. It supports a wide range of configurations, allowing it to adapt to specific performance requirements across applications. This LDPC solution has been rigorously validated against IEEE standards and offers enhanced error correction capabilities within a compact design. By reducing resource demands while improving overall communication reliability, it exemplifies AccelerComm's commitment to leading-edge technological solutions.
AccelerComm's High PHY Accelerators provide a suite of IP cores designed to boost signal processing capabilities for 5G New Radio applications. Integrating patented high-performance algorithms, this library of accelerators ensures peak throughput and efficiency, facilitating robust signal processing across ASIC, FPGA, and SoC platforms. These accelerators are characterized by their ability to significantly reduce latency and improve spectral efficiency, making them indispensable in high-demand environments. By supporting a wide array of features, including high-throughput modulation/demodulation and sophisticated error correction techniques, the accelerators empower systems to handle intricate data transmission with precision. Moreover, these accelerators seamlessly integrate with existing hardware platforms, offering a versatile solution for enhancing signal processing in diverse network scenarios. Their robust design and functionality reflect AccelerComm's commitment to driving innovation in communication technologies.
Credo's SerDes PHY solutions are designed to meet the demands of modern data communication platforms, facilitating high-speed data transfer across varied interface standards. These PHYs leverage Credo's proprietary mixed-signal DSP design principles to deliver enhanced signal integrity and reduced power consumption in high-density environments. SerDes PHY enables seamless integration into custom ASICs, offering support for data rates up to 112G PAM4 per lane, suitable for a wide range of applications from data centers to telecommunications. The inclusion of advanced error correction and signal conditioning technologies within the PHY helps improve reliability and system robustness, accommodating the increasing demands for bandwidth in today's digital ecosystems. These PHY solutions support a variety of signaling standards, including NRZ and PAM4, to optimize performance across different operational scenarios. Credo's focus on adaptability and energy efficiency ensures that their SerDes PHYs are not only cutting-edge in performance but also sustainable in energy usage, aligning with the industry's shift towards greener technology solutions.
The SMPTE ST 2110 suite allows for professional media transport over IP networks. It supports a wide range of sub-standards designed to handle uncompressed active video, PCM audio, and ancillary data. These cores offer flexibility and efficiency, allowing media broadcasts to integrate seamlessly across IP networks. The modular structure provides an implementation that minimizes resource usage while maximizing operational capability. Designed for both broadcast and professional AV industries, the SMPTE ST 2110 cores facilitate the transition from SDI to IP by efficiently handling various media components. They can operate in both gateway and synthetic essence modes, thereby broadening application use cases. The cores are crafted to conform with deterministic networking needs, supporting functionalities like traffic shaping and time synchronization, adhering to the exacting standards of SMPTE sections 10 through 40. These cores offer full interoperability, tested in Joint Taskforce on Networked Media (JT-NM) programs, and have shown perfect compatibility with multiple vendor equipment. The SMPTE ST 2110 cores streamline the architecture of your IP-enabled systems, enhancing both the reliability and scalability of media operations.
The 10G Ethernet MAC and PCS from Chevin Technology is a powerful and flexible core designed for efficient data transfer in high-end FPGAs. Engineered to handle up to 10 Gbps, this IP core is ideal for applications requiring fast and reliable connectivity, such as data centers and telecommunications. Its architecture is compact, ensuring minimal resource usage on the FPGA, thus providing room for additional custom designs. This MAC and PCS combination supports a broad range of features, including full duplex operation and a variety of Ethernet frames, making it suitable for integration into complex network systems. By offering both MAC and PCS layers, it provides a comprehensive solution that simplifies the integration process while ensuring robust performance. Additionally, Chevin Technology’s Ethernet cores are built to maximize throughput and maintain low latency, delivering a consistently high performance across different environments. The cores are versatile, adaptable to different FPGA platforms from major vendors, ensuring seamless integration into any project.
The Network Protocol Accelerator Platform (NPAP) by Missing Link Electronics is engineered to significantly enhance network protocol processing. This platform leverages MLE's innovative patented and patent-pending technologies to boost the speed of data transmission within FPGAs, achieving impressive rates of up to 100 Gbps. The NPAP provides a robust, efficient solution for offloading processing tasks, leading to superior networking efficiency. MLE's NPAP facilitates multiple high-speed connections and can manage large volumes of data effectively, incorporating support for a variety of network protocols. The design ensures that users benefit from reduced latency and improved data throughput, making it an ideal choice for network-intensive applications. MLE’s expertise in integrating high-performance networking capabilities into FPGA environments comes to the forefront with this product, providing users with a dependable tool for optimizing their network infrastructures.
Polar encoding and decoding for 5G NR leverages AccelerComm's expertise in creating sophisticated IP that reduces resource and memory demands while delivering superior BLER performance. This solution, selected for 5G NR control channels, utilizes PC- and CRC-aided SCL polar decoding techniques to achieve high error correction accuracy. The polar IP is fully compliant with 3GPP NR standards, encompassing the entire encoding and decoding chain required for seamless integration. It offers high levels of parallel processing and scalability, making it suitable for diverse applications, from simple to complex data transmission systems. With its configurable design, the Polar IP allows adjustments in decoder list size to best fit specific BLER and PPA requirements. This flexibility, combined with its efficient integration capabilities, underscores its role as a critical enabler of efficient, high-performance wireless communication solutions.
Intilop's UDP Offload Engine (UOE) is engineered to optimize data throughput and minimize latencies in network communications by offloading UDP protocol processing from the host CPU. This hardware solution delivers enhanced network efficiency, particularly suitable for environments where UDP traffic is predominant, such as streaming media, gaming, and VoIP applications. The UOE facilitates fast packet processing, allowing network devices to achieve greater bandwidth utilization without increasing CPU load. Its architecture supports a large number of concurrent sessions, ensuring consistent performance across various network conditions. By handling UDP traffic independently, the engine reduces the workload on network servers, improving overall system responsiveness. Integration of this UOE into existing systems is straightforward, providing an immediate performance boost with minimal configuration required. This adaptability makes it an ideal choice for enterprises looking to enhance their network operations without extensive infrastructure changes.
The ASPER sensor operates at a 79GHz frequency, making it a sophisticated module for automotive applications like parking assistance. This short-range radar sensor boasts a coverage of 180 degrees with a superior detection range that extends beyond other conventional technology, such as ultrasonic systems. Its application in vehicle systems allows for enhanced features, including rear and front collision warning, blind spot detection, and more. ASPER is designed to detect low-lying objects and maintain accurate function in adverse weather conditions like fog or rain, making it a versatile component for comprehensive vehicle safety and awareness systems.
The Time-Triggered Protocol (TTP) is an advanced communication protocol designed to enable high-reliability data transmission in embedded systems. It is widely used in mission-critical environments such as aerospace and automotive industries, where it supports deterministic message delivery. By ensuring precise time coordination across various control units, TTP helps enhance system stability and predictability, which are essential for real-time operations. TTP operates on a time-triggered architecture that divides time into fixed-length intervals, known as communication slots. These slots are assigned to specific tasks, enabling precise scheduling of messages and eliminating the possibility of data collision. This deterministic approach is crucial for systems that require high levels of safety and fault tolerance, allowing them to operate effectively under stringent conditions. Moreover, TTP supports fault isolation and recovery mechanisms that significantly improve system reliability. Its ability to detect and manage faults without operator intervention is key in maintaining continuous system operations. Deployment is also simplified by its modular structure, which allows seamless integration into existing networks.
The eSi-Comms suite is a versatile toolset designed for enabling sophisticated communication functionalities in integrated circuits. Known for its high degree of parameterization, this communication IP adapts to various industry standards, effectively facilitating connectivity across a range of applications. Built to support modern wireless and wireline standards like Wi-Fi, Li-Fi, LTE, and DVB, eSi-Comms demonstrates a balance between adaptability and high performance, suiting dynamic communication environments. It facilitates robust network communications, ensuring seamless data exchange and reliable connectivity in demanding scenarios. EnSilica's focus on optimized resource usage allows eSi-Comms to deliver top-tier communication capabilities with minimized power consumption, a crucial feature in portable and battery-operated devices. Furthermore, its integration ability ensures that it aligns with diverse system architectures, enhancing interoperability across different technology ecosystems.
The FC Upper Layer Protocol (ULP) provides a hardware-based solution for implementing FC-AE-RDMA or FC-AV standards, designed for seamless full-network stack integration. This IP solution ensures rigorous buffer mapping, delivering advanced DMA controllers and message chain engines that streamline data integrity management processes. As it aligns with F-18 and F-15 compatible interface modes, it is particularly suited for high-demand aviation data management applications where precision and performance are pivotal. The ULP IP core offers enhanced control over fiber channel-based communication infrastructures, promoting superior data processing capabilities tailored to intricate defense systems. The dependable handling of protocol processes underpins the core's design, offering the ideal balance of accuracy and efficiency needed in today's highly dynamic communication landscapes. With consistent reliability and integration ease, it represents a culmination of mastery in fiber channel data solutions tailored for military applications.
Ethernet MAC 10M/100M/1G/2.5G IP is a solution that enables the host to communicate data using the IEEE 802.3 standard for 10M, 100M, 1G, 2.5G speeds and is suited for use in networking equipment such as switches and routers. The Client-side interface for the IP is AXI-S and the Ethernet MAC IP comes with GMII, RGMII or MII interfaces on the PHY side. The Ethernet MAC 10M/100M/1G/2.5G IP features a compact and low latency solution, it is highly configurable and can optionally include IEEE 1588 Timestamping Unit (TSU). The Silicon agnostic Ethernet MAC IP, suitable for ASICs and FPGAs, is prepared for easy integration with Ethernet PCS 10M/ 100M/1G/2.5G IP from Comcores.
Ubi.cloud is a breakthrough geolocation solution designed to offload GPS and Wi-Fi computing tasks to the cloud effectively. This innovation results in significantly smaller, more efficient geolocation devices, ideal for IoT tracking applications. By reducing the size and energy consumption of the hardware, Ubi.cloud provides organizations with the ability to deploy diverse tracking solutions across their operations. It supports global GPS positioning for outdoor use and Wi-Fi for indoor urban tracking, making it versatile for various needs. Designed to minimize the inherent power and size issues of traditional GNSS modules, Ubi.cloud leverages advanced embedded technologies like UbiGNSS and UbiWIFI. These allow for remarkable on-time performance improvements compared to traditional setups, drastically cutting down receiver chipset consumption and boosting battery life. With Ubi.cloud, businesses can integrate cutting-edge geolocation capabilities into their devices using a pay-as-you-go model or life-time licenses, ensuring flexibility in application. This makes it ideal for asset tracking of unpowered devices, fitting into existing systems seamlessly or being part of new innovative designs.
The High Speed Data Bus (HSDB) solution offers a comprehensive hardware implementation for the HSDB's PHY and MAC layers. Designed to facilitate seamless integration into high-speed data transfer environments, this component ensures reliable communication within F-22 compatible systems. Its easy-to-integrate frame interface supports rapid deployment in complex aerospace applications, making it invaluable for organizations seeking robust data transmission solutions in mission-critical scenarios. By focusing on delivering superior bandwidth operations, this core supports stringent performance standards for high-speed data usage, essential in modern aerospace and defense settings. The HSDB IP Core prioritizes seamless communications with minimal latency, catering specifically to real-time applications. Its architecture is engineered for adaptability and high-speed operations, meeting the rigorous demands presented by intricate military communications systems. Overall, the HSDB solution represents a pinnacle of high-precision engineering, tailor-made for defense-related data operations.
The PCS2100 is Palma Ceia SemiDesign's innovative solution specifically engineered for IoT communication within Wi-Fi HaLow networks. This single modem chip is designed for client-side applications, essential for creating a robust IoT ecosystem as envisioned under the IEEE 802.11ah specification. The PCS2100 is integral in enhancing network span owing to its operational capability in sub-gigahertz frequencies, extending communication range up to a kilometer. Characterized by low power consumption and efficient data handling, the PCS2100 stands out in environments demanding scalable throughput and long-lasting operational life. Its architectural design supports advanced features like Target Wake Time (TWT) and Resource Allocation Windowing (RAW), allowing fine-tuned control of device activity to significantly conserve energy in demanding IoT applications. The PCS2100's support for narrow-band transmission, coupled with sophisticated modulation schemes, gives it a performance edge in sensor-intensive environments. This makes it ideal for applications that require continuous connectivity and efficient data streaming, such as surveillance systems or industrial monitoring. Its comprehensive interface options further enhance its integration and deployment flexibility in various IoT settings.
The ntLDPC_8023CA (17664,14592) IP Core is defined in IEEE 802.3ca-2020 standard document and it is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes. These LDPC codes are based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that they offer high throughput at low implementation complexity. The ntLDPCE_8023CA encoder IP implements a 256-bit parallel systematic LDPC encoder. The Generator LDPC Matrix is calculated off-line, compressed and stored in ROM. It is partitioned to 12 layers and each layer when multiplied by the 14592 payload block pro-duces 256 parity bits. The multiplier architecture may be parameterized before synthesis to generate multiple multiplier instances [1 to 6], in order to effectively process multiple layers in parallel and improve the IP throughput rate. Shortened blocks are supported with granularity of 128-bit boundaries and 384 or 512 parity bits puncturing is also optionally supported. The ntLDPCD_8023CA decoder IP Core may optionally implement one of two approximations of the log-domain LDPC iterative decoding algorithm (Belief propagation) known as either Layered Offset Min-Sum Algorithm (OMS) or Layered Lambda-min Algorithm (LMIN). Selecting between the two algorithms presents a decoding performance vs system resources utilization trade-off. The OMS algorithm is chosen for this implementation, given the high code rate of the Parity Check Matrix (PCM). The ntLDPCD_8023CA decoder IP implements a 256-bit parallel systematic LDPC layered decoder. Each layer corresponds to Z=256 expanded rows of the original LDPC matrix. Each layer element corresponds to the active ZxZ shifted identity sub-matrices within the layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit, in order to update the layers LLR estimates and extrinsic information iteratively until the required number of decoding iterations has been run. The decoder IP also features a powerful optional early termination (ET) criterion, to maintain practically equivalent error correction performance, while significantly increasing its throughput rate and/or reducing hardware cost. Additionally it reports how many decoding iterations have been performed when ET is activated, for system performance observation and calibration purposes. Finally a simple, yet robust, flow control handshaking mechanism is included in both IPs, which is used to communicate the IPs availability to adjacent system components. This logic is easily portable into any communication protocol, like AXI4 stream IF.
The FC Anonymous Subscriber Messaging (ASM) IP Core offers a full-network stack hardware implementation of FC-AE-ASM, tailored to enable hardware-based label lookup, DMA controllers, and message chain engines, optimizing defense communication processes. Specifically engineered for F-35 system compatibility, the ASM core ensures seamless integration and reliable data flow management across intricate aviation systems. By providing real-time processing efficiency and robust communication controls, it addresses complex data interactions inherent in military-grade communication channels, ensuring high precision and execution reliability. This core empowers operational frameworks with advanced data management potency, ensuring that mission-critical messaging systems operate smoothly and efficiently. The ASM IP reflects a commitment to excellence in communication integrity and operation reliability, serving as a crucial component for integrated defense communication infrastructures.
ArrayNav is a groundbreaking GNSS solution utilizing patented adaptive antenna technology, crafted to provide automotive Advanced Driver-Assistance Systems (ADAS) with unprecedented precision and capacity. By employing multiple antennas, ArrayNav substantially enhances sensitivity and coverage through increased antenna gain, mitigates multipath fading with antenna diversity, and offers superior interference and jamming rejection capabilities. This advancement leads to greater accuracy in open environments and markedly better functionality within urban settings, often challenging due to signal interference. It is designed to serve both standalone and cloud-dependent use cases, thereby granting broad application flexibility.
The nxFeed Market Data System is an FPGA-based feed handler that revolutionizes market data processing by using hardware to enhance speed and efficiency. By normalizing data feeds into a simple and consistent API, nxFeed significantly reduces the server resources and latency associated with data handling. This system is especially beneficial for electronic trading applications requiring synchronized and fast market data updates. Designed to integrate easily into existing systems, nxFeed offers both local PCIe delivery and UDP multicast for distributed applications, allowing for flexibility in deployment. Its robust API ensures that integration can be achieved rapidly, often within a week, without the need for dedicated FPGA hardware during development. The system offers a central management structure with tools for latency statistics and live monitoring. With nxFeed, developers can focus on core business logic while the system handles complex feed arbitration, decoding, and normalization. It's particularly useful for firms looking to develop proprietary trading algorithms or manage volatile exchange feeds. The solution supports up to 250,000 symbols per card, making it an ideal choice for high-demand trading environments.
The HOTLink II solution is a fully implemented hardware layer 2 design specifically intended for handling high-speed interface communications. It effectively supports full-rate, half-rate, and quarter-rate operations, as per standards set for such technological interfaces. Tailored for F-18 compatible environments, this IP provides frame interface integration ease, which is critical for successful deployment in high-frequency operational settings. The core's engineering sophistication is evident in its steadfast processing capabilities and adaptability to diverse aviation communication needs. Designed to offer sustainable and efficient data processing, the HOTLink II ensures minimal disruptions, promoting fluid operation within its designated applications. As an industry standard solution, its precision aligns with substantial aerospace demands, guaranteeing optimal performance even under demanding conditions. Organizations deploying this core can expect significant enhancements in data throughput efficiency and streamlined communication processes crucial to operational success in aviation platforms.
Arteris's Ncore Cache Coherent Interconnect IP addresses the complex challenges of multi-core ASIC development, offering a scalable, highly configurable solution for coherent network-on-chip designs. This IP supports multiple protocols, including Arm and RISC-V, and is engineered to comply with ISO 26262 for safety-critical applications. Ncore enables seamless communication and cache coherence across varied processor cores, enhancing performance while meeting stringent functional safety standards. Its capability to automate Fault Modes Effects and Diagnostic Analysis (FMEDA) further simplifies safety compliance, proving its value in advanced SoCs where reliability and high throughput are critical.
The VIDIO 12G SDI FMC Daughter Card represents the forefront of broadcast video technology, equipped to meet high-definition requirements for the modern market. Specifically designed for integration with both AMD/Xilinx and Intel/Altera devices, this card supports resolutions up to 4K, making it ideal for video and IP development on compatible development boards. This design features the latest chip technology from Texas Instruments, incorporating full-size BNC and SFP+ configurations for comprehensive SDI or IP functionalities. Unlike similar products, its ease of use is inherent, with no additional software configuration needed to begin operations. Globally trusted and field-tested for reliability, the VIDIO SDI FMC card is manufactured in the USA, ensuring premium quality and performance metrics. Its durability and affordability provide a nimble platform for developing the next generation of 4K and Video over IP products.
Dyumnin Semiconductors' RISCV SoC is a robust solution built around a 64-bit quad-core server-class RISC-V CPU, designed to meet advanced computing demands. This chip is modular, allowing for the inclusion of various subsystems tailored to specific applications. It integrates a sophisticated AI/ML subsystem that features an AI accelerator tightly coupled with a TensorFlow unit, streamlining AI operations and enhancing their efficiency. The SoC supports a multimedia subsystem equipped with IP for HDMI, Display Port, and MIPI, as well as camera and graphic accelerators for comprehensive multimedia processing capabilities. Additionally, the memory subsystem includes interfaces for DDR, MMC, ONFI, NorFlash, and SD/SDIO, ensuring compatibility with a wide range of memory technologies available in the market. This versatility makes it a suitable choice for devices requiring robust data storage and retrieval capabilities. To address automotive and communication needs, the chip's automotive subsystem provides connectivity through CAN, CAN-FD, and SafeSPI IPs, while the communication subsystem supports popular protocols like PCIe, Ethernet, USB, SPI, I2C, and UART. The configurable nature of this SoC allows for the adaptation of its capabilities to meet specific end-user requirements, making it a highly flexible tool for diverse applications.
Secure Protocol Engines offer high-performance IP blocks designed to enhance network and security processing capabilities. These engines support critical operations like cryptographic functions, dramatically offloading the central processing units within SoCs. They ensure secure communication channels for embedded systems by seamlessly integrating into existing security frameworks, thereby bolstering the system's defense mechanisms against potential cyber threats.
Digital PreDistortion (DPD) technology is pivotal for enhancing the efficiency of RF power amplifiers. Systems4Silicon's DPD offering, known as FlexDPD, is a comprehensive adaptive linearization subsystem. This solution is vendor-independent, allowing for seamless compilation whether targeting ASICs, FPGAs, or SoC platforms. It is engineered to boost radio transmission efficiency dramatically.\n\nFlexDPD is adaptable to evolving market needs, supporting multi-standard, multi-carrier wireless systems like 5G and O-RAN networks. Its field-proven scalability ensures it can manage transmission bandwidths exceeding 1 GHz, making it apt for various applications with high data throughput demands. The technology has been crafted to align with the growing complexity and performance expectations of modern wireless networks.\n\nThe solution enhances the power efficiency by effectively linearizing amplifiers, thus mitigating distortions and optimizing output. It ensures systems run at optimal power levels, crucial for energy savings and overall operational efficiency within high-frequency communication environments. Systems4Silicon provides extensive support services, ensuring smooth implementation and ongoing optimization for FlexDPD users.
The RWM6050 Baseband Modem is a cutting-edge component designed for high-efficiency wireless communications, ideally suited for dense data transmission environments. This modem acts as a fundamental building block within Blu Wireless's product portfolio, enabling seamless integration into various network architectures. Focusing on addressing the needs of complex wireless systems, the RWM6050 optimizes data flow and enhances connectivity capabilities within mmWave deployments. Technical proficiency is at the core of RWM6050's design, targeting high-speed data processing and signal integrity. It supports multiple communication standards, ensuring compatibility and flexibility in diverse operational settings. The modem's architecture is crafted to manage substantial data payloads effectively, fostering reliable, high-bandwidth communication across different sectors, including telecommunications and IoT applications. The RWM6050 is engineered to simplify the setup of communication networks and improve performance in crowded signal environments. Its robust design not only accommodates the challenges posed by demanding applications but also anticipates future advancements within wireless communication technologies. The modem provides a scalable yet efficient solution that meets the industry's evolving requirements.
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