All IPs > Wireline Communication
Wireline Communication semiconductor IPs are critical components in the semiconductor industry, playing a vital role in enabling efficient data transmission across fixed networks. They are designed to optimize the performance of data transfer over physical media like copper cables, fiber optics, or hybrid systems. Given the growing demand for faster and more reliable data transmission, these IPs are indispensable in the development of network infrastructure and communication devices.
Products within this category cover a wide array of technologies essential for different communication protocols. For instance, Ethernet IPs are fundamental for creating network interfaces capable of high-speed data exchange, contributing to the performance of local and wide-area networks. The Fibre Channel IPs are specifically tailored for storage area networks, providing high-speed, lossless data transmission which is crucial for data-intensive applications in enterprise environments.
Additionally, this category includes Error Correction/Detection IPs, critical for maintaining data integrity during transmission by identifying and rectifying errors without needing retransmission. Our portfolio also comprises IPs for Modulation/Demodulation which play a key role in preparing data for transmission and ensuring it is correctly interpreted upon receipt. Other pivotal subcategories include ATM/Utopia, which aid in asynchronous transfer mode communications, and CEI, which contribute to high-speed chip-to-chip and board-to-board communications.
Overall, Wireline Communication semiconductor IPs facilitate the development of robust and efficient communication solutions across various industries. Whether for building telecommunication infrastructure or advancing next-generation networking devices, these IPs are central to achieving high performance, scalability, and reliability in wireline communication networks.
The Low Density Parity Check (LDPC) codes are powerful, capacity approaching channel codes and have exceptional error correction capabilities. The high degree of parallelism that they offer enables efficient, high throughput hardware architectures. The ntLDPC_WiFi6 IP Core is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes and is fully compliant with IEEE 802.11 n/ac/ax standard. The Quasi-Cyclic LDPC codes are based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that they offer high throughput at low implementation complexity. The ntLDPC_WiFi6 decoder IP Core may optionally implement one of two approximations of the log-domain LDPC iterative decoding algorithm (Belief propagation) known as either Layered Normalized Offset Min-Sum Algorithm or Layered Lambda-min Algorithm. Selecting between the two algorithms presents a decoding performance .vs. system resources utilization trade-off. The core is highly reconfigurable and fully compliant to the IEEE 802.11 n/ac/ax Wi-Fi4, Wi-Fi5 and Wi-Fi 6 standards. The ntLDPC_WiFi6 encoder IP implements a 81-bit parallel systematic LDPC encoder. An off-line profiling Matlab script processes the original matrices and produces a set of constants that are associated with the matrix and hardcoded in the RTL encoder.
The ADQ35 digitizer is designed for high-throughput applications, featuring a dual-channel configuration capable of achieving a sampling rate up to 10 GSPS. This 12-bit digitizer is tailored for applications that require simultaneous data streams and efficient high-speed data transfer, making it ideal for use in advanced signal analysis.
The CXL 3.1 Switch by Panmnesia is a high-performance solution facilitating flexible and scalable inter-device connectivity. Designed for data centers and HPC systems, this switch supports extensive device integration, including memory, CPUs, and accelerators, thanks to its advanced connectivity features. The switch's design allows for complex networking configurations, promoting efficient resource utilization while ensuring low-latency communication between connected devices. It stands as an essential component in disaggregated compute environments, driving down latency and operational costs.
RaiderChip's GenAI v1 is a pioneering hardware-based generative AI accelerator, designed to perform local inference at the Edge. This technology integrates optimally with on-premises servers and embedded devices, offering substantial benefits in privacy, performance, and energy efficiency over traditional hybrid AI solutions. The design of the GenAI v1 NPU streamlines the process of executing large language models by embedding them directly onto the hardware, eliminating the need for external components like CPUs or internet connections. With its ability to support complex models such as the Llama 3.2 with 4-bit quantization on LPDDR4 memory, the GenAI v1 achieves unprecedented efficiency in AI token processing, coupled with energy savings and reduced latency. What sets GenAI v1 apart is its scalability and cost-effectiveness, significantly outperforming competitive solutions such as Intel Gaudi 2, Nvidia's cloud GPUs, and Google's cloud TPUs in terms of memory efficiency. This solution maximizes the number of tokens generated per unit of memory bandwidth, thus addressing one of the primary limitations in generative AI workflow. Furthermore, the adept memory usage of GenAI v1 reduces the dependency on costly memory types like HBM, opening the door to more affordable alternatives without diminishing processing capabilities. With a target-agnostic approach, RaiderChip ensures the GenAI v1 can be adapted to various FPGAs and ASICs, offering configuration flexibility that allows users to balance performance with hardware costs. Its compatibility with a wide range of transformers-based models, including proprietary modifications, ensures GenAI v1's robust placement across sectors requiring high-speed processing, like finance, medical diagnostics, and autonomous systems. RaiderChip's innovation with GenAI v1 focuses on supporting both vanilla and quantized AI models, ensuring high computation speeds necessary for real-time applications without compromising accuracy. This capability underpins their strategic vision of enabling versatile and sustainable AI solutions across industries. By prioritizing integration ease and operational independence, RaiderChip provides a tangible edge in applying generative AI effectively and widely.
The CT25205 is a comprehensive digital core designed for IEEE 802.3cg® 10BASE-T1S Ethernet applications, incorporating the Physical Medium Attachment (PMA), Physical Coding Sublayer (PCS), and Physical Layer Coordination (PLCA) Reconciliation Sublayers. Written in Verilog 2005 HDL, this IP core is versatile enough to be implemented in standard cells and FPGA systems. It interfaces seamlessly with IEEE Ethernet MACs through a Media Independent Interface (MII), and the PLCA RS supports legacy MACs, enhancing functionality without additional extensions. The PMA is compatible with OPEN Alliance 10BASE-T1S PMD, perfect for Zonal Gateways and MCUs in advanced network architectures.
This high-powered TCP Offload Engine aims to deliver superior efficiency by offloading TCP processing from the CPU. By integrating a MAC interface, it reduces processing latencies and broadens throughput, thereby optimizing network operations substantially. This IP suite maintains rapid data processing speeds and addresses a broad array of network optimization needs for today's high-demand environments. Optimized for high-speed networking environments, the TOE offers unprecedented latency reduction through its hardware-accelerated design. The integration of a refined MAC interface plays a crucial role in translating packet data into usable formats swiftly, a crucial factor in enhancing overall system performance, particularly in data-intensive industries. This technology’s edge lies in its ability to seamlessly deliver full data transfer acceleration. Its design caters to enterprises that prioritize low-processing overheads and need to maximize network efficiency without the traditional constraints of higher CPU usage. Thus, Intilop's 10G TCP Offload Engine represents a benchmark in high-performance data handling systems.
The ePHY-5616 is a high-performance SerDes solution from eTopus, designed for versatile use across enterprise, data center, and 5G applications. Operating efficiently at data rates from 1 to 56 Gbps, this product exploits advanced DSP techniques for superior signal integrity and robustness. It accommodates wide insertion loss ranges of 10dB to over 35dB, thus ensuring reliable performance in challenging communication environments. Its architecture supports direct optical drives and quad/octal configurations, making it ideal for network interface cards, routers, and high-speed switches in a data center setup. The embedded DSP architecture is developed with eTopus's proprietary algorithms, which enable rapid SerDes tuning and performance optimization. The ePHY-5616 is also characterized by its low Bit Error Rate (BER), ensuring data reliability and integrity. Moreover, it supports multiple protocols, including Ethernet and PCIe, enhancing its integration potential in modern broadband networks.
The Ethernet Real-Time Publish-Subscribe (RTPS) IP Core provides an all-encompassing solution for Ethernet-based RTPS protocols, ensuring efficient network data management and publication in real-time systems. This IP core supports crucial applications in environments where time-sensitive communication is paramount. Ideal for industrial and aerospace settings, the core manages data transactions with precision, leveraging real-time processing and minimal latency to ensure seamless data exchange. By facilitating controlled and secure communication network streams, the core optimally handles various multi-subscriber environments. With its highly dependable architecture, the RTPS IP Core integrates easily into existing systems, providing scalability and adaptability for evolving network requirements. This capability makes it indispensable for systems demanding high reliability and rapid information exchange across distributed networks.
The ntLDPC_G98042 (17664,14592) IP Core is defined in IEEE 802.3ca-2020, it is used by ITU-T G.9804.2-09.2021 standard document and it is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes. These LDPC codes are based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that they offer high throughput at low implementation complexity. The ntLDPCΕ_G98042 encoder IP implements a 256-bit parallel systematic LDPC encoder. The Generator LDPC Matrix is calculated off-line, compressed and stored in ROM. It is partitioned to 12 layers and each layer, when multiplied by the 14592 payload block, produces 256 parity bits. The multiplier architecture may be parameterized before synthesis to generate multiple multiplier instances [1:4,6], in order to effectively process multiple layers in parallel and improve the IP throughput rate. Shortened blocks are supported with granularity of 128-bit boundaries and 384 or 512 parity bits puncturing is also optionally supported. The ntLDPCD_G98042 decoder IP Core may optionally implement one of two approximations of the log-domain LDPC iterative decoding algorithm (Belief propagation) known as either Layered Offset Min-Sum Algorithm (OMS) or Layered Lambda-min Algorithm (LMIN). Selecting between the two algorithms presents a decoding performance vs. system resources utilization trade-off. The OMS algorithm is chosen for this implementation, given the high code rate of the Parity Check Matrix (PCM). The ntLDPCD_G98042 decoder IP implements a 256-bit parallel systematic LDPC layered decoder. Each layer corresponds to Z=256 expanded rows of the original LDPC matrix. Each layer element corresponds to the active ZxZ shifted identity sub-matrices within the layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit, in order to update the layers’ LLR estimates and extrinsic information iteratively until the required number of decoding iterations has been run. The decoder IP also features a powerful optional syndrome check early termination (ET) criterion, to maintain identical error correction performance, while significantly increasing its throughput rate and/or reducing hardware cost. Additionally it reports how many decoding iterations have been performed when ET is activated, for system performance observation and calibration purposes. A top level architecture deployment wrapper allows to expand the parallelism degree of the decoder before synthesis, effec-tively implementing a trade-off between utilized area and throughput rate. Finally a simple, yet robust, flow control handshaking mechanism is included in both IPs, which is used to communicate the IPs availability to adjacent system components at 128-bit parallel bus interface. This logic is easily portable into any communication protocol, like AXI4 stream IF.
The HOTLink II Product Suite is another remarkable offering from Great River Technology. Built to complement their ARINC 818 suite, HOTLink II provides an integrated framework for crafting high-performance digital data links. This suite ensures seamless, secure, and reliable data transmission over fiber or copper cables across various platforms. Developed with a focus on flexibility and functionality, the HOTLink II capabilities enhance system integrators' ability to deploy effective communication solutions within aircraft and other demanding environments. The emphasis on robust, low-latency data transfer makes it an ideal choice for real-time applications where precision and reliability are paramount. Broad compatibility is a hallmark of HOTLink II, facilitating integration into diverse infrastructures. Backed by Great River Technology's expertise and support, customers are empowered to advance their system communication capabilities efficiently and cost-effectively.
The ntRSC_DP1.4 IP core is compliant with Display Port 1.4 standard as published by Video Electronics Standards Association (VESA) for use in DSC (Display Stream Compression) technology. It is based on Reed-Solomon RS(254,250), 10 bit symbols, forward error correction code, where the codeword block consists of 250 information symbols and 4 RS parity symbols. The ntRSC_DP1.4 FEC IP Core ensures error resilient / glitch-free compressed video transport (DSC) to external displays. The implementation is very low latency, high speed with a simple interface for easy integration in SoC applications.
Designed for applications that require extremely low communication delays, this ultra-low latency Ethernet MAC supports a data rate of 10G. With a round trip in the nanoseconds range, this core is perfect for high-speed communications where timing is critical. The efficient use of FPGA resources allows for additional design logic to be integrated, maximizing the chip's potential.
Designed for 10BASE-T1S applications, the CT25203 serves as an essential analog front-end component of Ethernet transceivers. This IP component helps connect host controllers and switches by implementing a 3-pin interface compliant with the OA TC14 specification. It ensures high EMC performance thanks to its compact 8-pin design and manufacturing on high-voltage process technology. Particularly suited for automotive and industrial use, this IP core demonstrates versatility, offering robust communication with minimal footprint.
Chevin Technology offers an Ethernet MAC and PCS solution designed to simplify the integration of Ethernet protocols like TCP/IP and UDP with FPGAs. This IP supports bandwidths of 10G to 100G and features low latency to ensure quick communication times. With a focus on minimal FPGA resource use, it's engineered with a small footprint to fit many cores on a single chip, reducing complexity and cost. Cut-through and store-and-forward modes are available to provide custom solutions based on the workload requirements.
The EW6181 is a cutting-edge multi-GNSS silicon solution offering the lowest power consumption and high sensitivity for exemplary accuracy across a myriad of navigation applications. This GNSS chip is adept at processing signals from numerous satellite systems including GPS L1, Glonass, BeiDou, Galileo, and several augmentation systems like SBAS. The integrated chip comprises an RF frontend, a digital baseband processor, and an ARM microcontroller dedicated to operating the firmware, allowing for flexible integration across devices needing efficient power usage. Designed with a built-in DC-DC converter and LDOs, the EW6181 silicon streamlines its bill of materials, making it perfect for battery-powered devices, providing extended operational life without compromising on performance. By incorporating patent-protected algorithms, the EW6181 achieves a remarkably compact footprint while delivering superior performance characteristics. Especially suited for dynamic applications such as action cameras and wearables, its antenna diversity capabilities ensure exceptional connectivity and positioning fidelity. Moreover, by enabling cloud functionality, the EW6181 pushes boundaries in power efficiency and accuracy, catering to connected environments where greater precision is paramount.
The NaviSoC by ChipCraft is a highly integrated GNSS system-on-chip (SoC) designed to bring navigation technologies to a single die. Combining a GNSS receiver with an application processor, the NaviSoC delivers unmatched precision in a dependable, scalable, and cost-effective package. Designed for minimal energy consumption, it caters to cutting-edge applications in location-based services (LBS), the Internet of Things (IoT), and autonomous systems like UAVs and drones. This innovative product facilitates a wide range of customizations, adaptable to varied market needs. Whether the application involves precise lane-level navigation or asset tracking and management, the NaviSoC meets and exceeds market expectations by offering enhanced security and reliability, essential for synchronization and smart agricultural processes. Its compact design, which maintains high efficiency and flexibility, ensures that clients can tailor their systems to exact specifications without compromise. NaviSoC stands as a testament to ChipCraft's pioneering approach to GNSS technologies.
AccelerComm presents the Polar encoding and decoding suite for the 3GPP NR, featuring a comprehensive chain that enables quick integration and minimizes additional developmental efforts. This advanced IP utilizes PC and CRC-aided SCL decoding methods to deliver uncompromising error correction performance, adeptly handling the intricacies of 5G applications.\n\nThe Polar IP supports an extensive range of block sizes, tightly integrating each component to optimize performance while reducing latency and resource use. Its flexibility is further highlighted by its highly configurable parameters, which allow users to tailor its implementation to specific performance demands and power efficiency expectations.\n\nBy offering support for prevalent FPGA platforms like AMD and Intel, alongside ASIC optimizations, this Polar solution is a versatile option for developers seeking robust and integral solutions for burgeoning 5G networks. With ease of integration and superior performance metrics, it remains a leading solution in comprehensive 5G data processing.
The 8b/10 Decoder from Roa Logic is a comprehensive implementation of the well-known 8b10b line coding scheme, utilized for achieving DC-balance and bounded disparity during serial data transmission. This system is essential for maintaining synchronization between data and clock signals, thus utilized in high-speed data transmission protocols to enable reliable data recovery. This decoder efficiently translates 10-bit encoded symbols into 8-bit data while continuously monitoring for bit errors. It adeptly recognizes and processes special comma characters, with intrinsic functionality for identifying K28.5 symbols widely used across many data communication standards. The architecture of the 8b/10 Decoder allows for cascading to support 16b20b decoding, expanding its utility in complex serial communication systems. Its design is fully synthesizable, making it versatile across different technology platforms. Roa Logic supports developers with easily accessible documentation and source materials available on GitHub, fostering straightforward adoption and integration into modern data transmission systems.
The ntLDPC_8023CA (17664,14592) IP Core is defined in IEEE 802.3ca-2020 standard document and it is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes. These LDPC codes are based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that they offer high throughput at low implementation complexity. The ntLDPCE_8023CA encoder IP implements a 256-bit parallel systematic LDPC encoder. The Generator LDPC Matrix is calculated off-line, compressed and stored in ROM. It is partitioned to 12 layers and each layer when multiplied by the 14592 payload block pro-duces 256 parity bits. The multiplier architecture may be parameterized before synthesis to generate multiple multiplier instances [1 to 6], in order to effectively process multiple layers in parallel and improve the IP throughput rate. Shortened blocks are supported with granularity of 128-bit boundaries and 384 or 512 parity bits puncturing is also optionally supported. The ntLDPCD_8023CA decoder IP Core may optionally implement one of two approximations of the log-domain LDPC iterative decoding algorithm (Belief propagation) known as either Layered Offset Min-Sum Algorithm (OMS) or Layered Lambda-min Algorithm (LMIN). Selecting between the two algorithms presents a decoding performance vs system resources utilization trade-off. The OMS algorithm is chosen for this implementation, given the high code rate of the Parity Check Matrix (PCM). The ntLDPCD_8023CA decoder IP implements a 256-bit parallel systematic LDPC layered decoder. Each layer corresponds to Z=256 expanded rows of the original LDPC matrix. Each layer element corresponds to the active ZxZ shifted identity sub-matrices within the layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit, in order to update the layers LLR estimates and extrinsic information iteratively until the required number of decoding iterations has been run. The decoder IP also features a powerful optional early termination (ET) criterion, to maintain practically equivalent error correction performance, while significantly increasing its throughput rate and/or reducing hardware cost. Additionally it reports how many decoding iterations have been performed when ET is activated, for system performance observation and calibration purposes. Finally a simple, yet robust, flow control handshaking mechanism is included in both IPs, which is used to communicate the IPs availability to adjacent system components. This logic is easily portable into any communication protocol, like AXI4 stream IF.
eTopus's ePHY-11207 stands out in their SerDes lineup by achieving data rates up to 112 Gbps, a leap forward for scenarios demanding ultra-high bandwidth and low-latency communication. Constructed on a 7nm platform, this product is tailored for state-of-the-art applications in both enterprise and advanced data center environments. The architecture of the ePHY-11207 is conducive to handling extensive insertion loss ranges and high-sensitivity demands typical of contemporary optical and copper interconnects. Its adaptability is further enhanced by embedded proprietary DSP algorithms that permit fine-tuning of performance in sub-millisecond timeframes, a feature that assures operational stability even amidst jitter-inducing environments. In addition to backing numerous protocols such as Ethernet and PCIe, the ePHY-11207's low BER and extensive diagnostic capabilities make it a prime candidate for rapid deployment in high-density network settings. Such versatility not only supports robust infrastructure but also enhances overall throughput efficiency.
The eSi-Comms IP suite provides a highly adaptable OFDM-based MODEM and DFE portfolio, crucial for facilitating communications-oriented ASIC designs. This IP offers adept handling of many air interface standards in use today, making it ideal for 4G, 5G, Wi-Fi, and other wireless applications. The suite includes advanced DSP algorithms for ensuring robust links under various conditions, using a core design that is highly configurable to the specific needs of high-performance communication systems. Notably, it supports synchronization, equalization, and channel decoding, boasting features like BPSK to 1024-QAM demodulation and multi-antenna processing.
The Jotunn8 is engineered to redefine performance standards for AI datacenter inference, supporting prominent large language models. Standing as a fully programmable and algorithm-agnostic tool, it supports any algorithm, any host processor, and can execute generative AI like GPT-4 or Llama3 with unparalleled efficiency. The system excels in delivering cost-effective solutions, offering high throughput up to 3.2 petaflops (dense) without relying on CUDA, thus simplifying scalability and deployment. Optimized for cloud and on-premise configurations, Jotunn8 ensures maximum utility by integrating 16 cores and a high-level programming interface. Its innovative architecture addresses conventional processing bottlenecks, allowing constant data availability at each processing unit. With the potential to operate large and complex models at reduced query costs, this accelerator maintains performance while consuming less power, making it the preferred choice for advanced AI tasks. The Jotunn8's hardware extends beyond AI-specific applications to general processing (GP) functionalities, showcasing its agility. By automatically selecting the most suitable processing paths layer-by-layer, it optimizes both latency and power consumption. This provides its users with a flexible platform that supports the deployment of vast AI models under efficient resource utilization strategies. This product's configuration includes power peak consumption of 180W and an impressive 192 GB on-chip memory, accommodating sophisticated AI workloads with ease. It aligns closely with theoretical limits for implementation efficiency, accentuating VSORA's commitment to high-performance computational capabilities.
Time-Triggered Ethernet (TTEthernet) represents a significant advancement in network technology by integrating time-triggered communication over standard Ethernet infrastructures. This technology is designed to meet the stringent real-time requirements of aerospace and industrial applications, offering deterministic data transfer alongside regular Ethernet traffic within a shared network. TTEthernet delivers seamless synchronization across all network devices, ensuring that time-critical data packets are processed with precise timing. This capability is essential for applications where simultaneous actions from multiple systems require tight coordination, such as flight control systems or automated industrial processes. The protocol's compatibility with existing Ethernet environments allows for easy integration into current systems, reducing costs associated with network infrastructure upgrades. TTEthernet also enhances network reliability through redundant data paths and failover mechanisms, which guarantee continuous operation even in the event of link failures. As a result, TTEthernet provides a future-proof solution for managing both regular and mission-critical data streams within a single unified network environment. Its capacity to support various operational modes makes it an attractive choice for industries pursuing high standards of safety and efficiency.
Convolutional FEC codes are very popular because of their powerful error correction capability and are especially suited for correcting random errors. The most effective decoding method for these codes is the soft decision Viterbi algorithm. ntVIT core is a high performance, fully configurable convolutional FEC core, comprised of a 1/N convolutional encoder, a variable code rate puncturer/depuncturer and a soft input Viterbi decoder. Depending on the application, the core can be configured for specific code parameters requirements. The highly configurable architecture makes it ideal for a wide range of applications. The convolutional encoder maps 1 input bit to N encoded bits, to generate a rate 1/N encoded bitstream. A puncturer can be optionally used to derive higher code rates from the 1/N mother code rate. On the encoder side, the puncturer deletes certain number of bits in the encoded data stream according to a user defined puncturing pattern which indicates the deleting bit positions. On the decoder side, the depuncturer inserts a-priori-known data at the positions and flags to the Viterbi decoder these bits positions as erasures. The Viterbi decoder uses a maximum-likelihood detection recursive process to cor-rect errors in the data stream. The Viterbi input data stream can be composed of hard or soft bits. Soft decision achieves a 2 to 3dB in-crease in coding gain over hard-decision decoding. Data can be received continuously or with gaps.
ASPER is an advanced 79 GHz mmWave radar offering expansive 180-degree field coverage, designed to excel in park assist solutions. This radar module replaces traditional ultrasonic systems with improved accuracy, capable of extended detection ranges from 5 cm to 100 meters. Its adaptability across various vehicle classes makes it ideal for applications in automotive, transportation, and industrial environments, delivering unparalleled performance even in adverse conditions.
The GenAI v1-Q from RaiderChip brings forth a specialized focus on quantized AI operations, reducing memory requirements significantly while maintaining impressive precision and speed. This innovative accelerator is engineered to execute large language models in real-time, utilizing advanced quantization techniques such as Q4_K and Q5_K, thereby enhancing AI inference efficiency especially in memory-constrained environments. By offering a 276% boost in processing speed alongside a 75% reduction in memory footprint, GenAI v1-Q empowers developers to integrate advanced AI capabilities into smaller, less powerful devices without sacrificing operational quality. This makes it particularly advantageous for applications demanding swift response times and low latency, including real-time translation, autonomous navigation, and responsive customer interactions. The GenAI v1-Q diverges from conventional AI solutions by functioning independently, free from external network or cloud auxiliaries. Its design harmonizes superior computational performance with scalability, allowing seamless adaptation across variegated hardware platforms including FPGAs and ASIC implementations. This flexibility is crucial for tailoring performance parameters like model scale, inference velocity, and power consumption to meet exacting user specifications effectively. RaiderChip's GenAI v1-Q addresses crucial AI industry needs with its ability to manage multiple transformer-based models and confidential data securely on-premises. This opens doors for its application in sensitive areas such as defense, healthcare, and financial services, where confidentiality and rapid processing are paramount. With GenAI v1-Q, RaiderChip underscores its commitment to advancing AI solutions that are both environmentally sustainable and economically viable.
The UDP Offload Engine is crafted to amplify data transmission by reducing CPU intervention in the data communication process. Specifically tailored for systems requiring accelerated UDP packet handling, this IP effectively boosts performance in applications needing minimized jitter and maximum throughput efficiencies without burdening the central processor. This offload engine is a critical component in environments where data flows need to be expedited, such as high-volume streaming and real-time communication applications. Its architecture supports extensive session management and high packet rates, maintaining efficiency and reliability in large-scale network deployments. By offloading UDP processes, it streamlines data pathways which, in turn, reduces computational delays, enhancing overall system dynamics. The seamless integration that the UOE offers makes it a preferred choice for organizations looking to enhance their networking stack while reducing operational costs due to its reduced dependency on traditional CPU processes.
The Tyr Superchip is engineered to tackle the most daunting computational challenges in edge AI, autonomous driving, and decentralized AIoT applications. It merges AI and DSP functionalities into a single, unified processing unit capable of real-time data management and processing. This all-encompassing chip solution handles vast amounts of sensor data necessary for complete autonomous driving and supports rapid AI computing at the edge. One of the key challenges it addresses is providing massive compute power combined with low-latency outputs, achieving what traditional architectures cannot in terms of energy efficiency and speed. Tyr chips are surrounded by robust safety protocols, being ISO26262 and ASIL-D ready, making them ideally suited for the critical standards required in automotive systems. Designed with high programmability, the Tyr Superchip accommodates the fast-evolving needs of AI algorithms and supports modern software-defined vehicles. Its low power consumption, under 50W for higher-end tasks, paired with a small silicon footprint, ensures it meets eco-friendly demands while staying cost-effective. VSORA’s Superchip is a testament to their innovative prowess, promising unmatched efficiency in processing real-time data streams. By providing both power and processing agility, it effectively supports the future of mobility and AI-driven automation, reinforcing VSORA’s position as a forward-thinking leader in semiconductor technology.
The FC Upper Layer Protocol (ULP) IP Core offers a complete hardware solution for managing upper-layer protocol tasks associated with Fibre Channel systems. By implementing full network stack protocols, this core provides hardware-based buffer mapping, DMA control, and message management, making it integral to F-18 and F-15 compatible systems. Designed for aerospace applications, the core ensures seamless data flow and robust connection management across multiple system nodes. These features enable it to cope with the demands of modern aircraft systems, where data throughput and real-time processing are critical. Available with various mode configurations, the FC ULP IP Core is adaptable to a range of deployments, facilitating efficient and high-speed networking. Its integrated design optimizes the communication framework, reducing processor load and enhancing overall system performance in complex mission-critical environments.
The High Speed Data Bus (HSDB) IP Core offers a comprehensive solution for implementing physical (PHY) and media access control (MAC) layer functionalities for high-speed communication systems. It seamlessly integrates into a variety of systems, providing a complete frame interface that is easy to embed into existing platforms. Designed with compatibility in mind, this core meets F-22 interface standards, ensuring it can be implemented in a wide range of military and aerospace systems. This IP core supports high data rates and is optimized for low latency communication, making it ideal for real-time applications. Its design focuses on robustness and reliability, ensuring consistent data transmission even in demanding environments. Additionally, its flexible architecture allows for customization and scalability according to specific project requirements, enhancing its adaptability to various system designs. With its extensive compliance and versatility, the HSDB IP Core serves as an essential component in systems requiring high performance and precision. By streamlining the integration process and minimizing hardware footprint, it facilitates efficient communication in complex embedded systems.
This engine features ultra-low latency FPGA IP, providing a robust TCP Offload in networking systems. The integration includes MAC, PCIe, and Host Interface, ensuring sector-leading performance with minimal latency. Built on a background of efficient data transfer protocols, the system enhances throughput while reducing CPU overhead, which is particularly advantageous for high-frequency trading or real-time applications. Characterized by its ultra-low latency capabilities, the IP facilitates enhanced data handling that allows for immediate processing, making it ideal for data-heavy environments like data centers and financial services. The integration of a MAC interface alongside PCIe provides a cohesive solution that rapidly processes network traffic, addressing both data-heavy and computationally demanding tasks. Designed for environments demanding reduced latency, this IP underscores Intilop's commitment to cutting-edge data solutions. It accommodates concurrent sessions with high-speed data throughputs, thereby minimizing the computational load on conventional processing units and achieving execution speeds that are unparalleled in the market.
Flexibilis Ethernet Switch (FES) is engineered as a triple-speed Ethernet Layer 2 switch IP, capable of gigabit forwarding on each port. Its design ensures compatibility with IEEEv2's end-to-end transparent clock, enhancing clock information reliability across expansive networks. FES provides flexible connectivity options, supporting various Media Independent Interfaces and optional adapters for different interfaces, enabling seamless integration with host systems and external PHY devices. The switch's core is a multi-gigabit forwarding engine supporting up to twelve full-duplex gigabit Ethernet ports, employing Weighted Random Early Detection to prioritize critical data streams during congestion. Additional features like VLAN tagging, packet filtering, and PTP synchronization further solidify FES's credentials for robust, high-availability Ethernet communications.
Secure Protocol Engines from Secure-IC are designed to enhance network and security processing in data centers by offloading heavy computational tasks. These engines feature some of the industry's fastest SSL/TLS handshaking capabilities, paired with ultra-high-performance MACsec and IPsec processing. By managing demanding network tasks, Secure Protocol Engines enable data centers to optimize resources and improve system performance significantly. As data transmission and sensitive information exchange become increasingly common, these engines provide crucial support in maintaining robust security measures against interception and unauthorized access. The Secure Protocol Engines are optimized to integrate seamlessly with existing infrastructures, ensuring minimized impact on overall system efficiency and maximizing throughput and security.
The FC Anonymous Subscriber Messaging (ASM) IP Core provides a comprehensive hardware stack solution for FC-AE-ASM implementations, enabling efficient data transactions in high-demand communication environments. This IP core incorporates hardware-based label lookup, DMA control, and message chain engines tailored for compatibility with F-35 systems. Ideal for defense and aerospace industries, the ASM IP Core optimizes data flow between system nodes, ensuring security and accuracy in transactions. By functioning as a powerful network communication manager, the core plays a critical role in supporting avionics systems where high-speed, real-time data handling is paramount. With its focused architecture on optimizing message traffic and reducing communication overhead, this IP core enhances system performance by streamlining packet management and data dissemination across complex aerospace environments. Its robust design accommodates aggressive datahandling requirements essential for advanced system operations.
The LDPC solution by AccelerComm is meticulously optimized for the 5G NR standard, ensuring superior efficiency and performance. This encoder and decoder IP triumphantly addresses the pivotal needs of the 5G network by combining maximal hardware efficiency with enhanced power efficiency. It is adeptly designed to fulfill the rigorous throughput and error correction targets outlined by 3GPP standards.\n\nIntended for integration into both FPGA and ASIC environments, the LDPC IP is highly configurable, providing numerous settings to cater to a broad array of applications. Its capability to support maximum data rates while minimizing latency makes it an indispensable element in advanced communication infrastructures.\n\nWith enhanced BLER performance and an innovative design that outstrips generic LDPC solutions, this implementation significantly reduces latency and resource utilization. Offering low power consumption and half the energy per bit compared to competitors, it provides a balanced approach to meeting both diverse operational demands and stringent power budgets.
The ADQ35-WB RF digitizer is crafted for high-performance data acquisition with versatility at its core. It offers users a dual-channel capability with an impressive sample rate of up to 10 GSPS, and it extends its performance with a usable analog bandwidth reaching 9 GHz. This makes it a formidable option for professionals demanding precision and accuracy in RF signal digitization.
The FCM1401 is part of Falcomm's line of advanced Dual-Drive™ power amplifiers designed to enhance efficiency in wireless applications. Engineered for operation at a center frequency of 14 GHz, this two-stage power amplifier maximizes energy use while maintaining exceptional performance standards. Its innovative design includes CMOS SOI platform integration, boasting world-class efficiencies unmatched by conventional solutions in the market. The technology also comes with alternative options across other silicon platforms like GaAs, GaN, and SiGe, providing versatile application potential. This power amplifier achieves remarkable efficiency levels; a two-stage power-added efficiency (PAE) of 56% and a drain efficiency nearing 70%. The design also incorporates a 0.5x reduction in silicon area without degrading overall capabilities. The FCM1401 supports a broad range of applications from telecommunications to space communications, helping to lower operational costs while enhancing signal strength. Moreover, the amplifier’s robust design allows it to operate across a supply voltage between 1.6V to 2.0V without any loss in efficiency, ensuring stable performance under diverse conditions. With such specifications, the FCM1401 proves an ideal candidate for integrative use in advanced wireless communication infrastructures, offering substantial battery life improvements and energy savings to connected devices.
AccelerComm's High PHY Accelerators offer an impressive portfolio of IP accelerators tailored for 5G NR, enhancing O-RAN deployments with advanced signal processing capabilities. These accelerators emphasize maximum throughput and minimal power and latency, leveraging scalable technology for ASIC, FPGA, and SoC applications.\n\nCentral to these accelerators are patented high-performance signal processing algorithms, which enhance throughput significantly, making them crucial in scenarios demanding rapid data processing and low latency. The offering is ideal for improving the speed and efficiency of high-demand networks, reinforced by extensive research led by industry experts from Southampton University.\n\nMoreover, the accelerators encompass a wide variety of signal processing techniques such as LDPC and advanced equalization, to optimize the entire data transmission process. The result is a remarkable boost in spectral efficiency and overall network performance, making these accelerators indispensable for cutting-edge wireless technologies and their future-forward deployments.
The ntLDPC_5GNR Base Graph Encoder IP Core is defined in 3GPP TS 38.212 standard document and it is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes. The specification defines two sets of LDPC Base Graphs and their respective derived Parity Check Matrices. Each Base Graph can be combined with 8 sets of lifting sizes (Zc) in a total of 51 different lifting sizes. This way by using the 2 Base Graphs, the 5G NR specification defines up to 102 possible distinct LDPC modes of operation to select from, for optimum decoding performance, depending on target application code block size and code rate (using the additional rate matching module features). For Base Graph 1 we have LDPC(N=66xZc,K=22xZc) sized code blocks, while for Base Graph 2 we have LDPC(N=50xZc,K=[6,8,9,10]xZc) sized code blocks. The ntLDPCE_5GNR Encoder IP implements a multi-parallel systematic LDPC encoder. Parallelism depends on the selected lifting sizes subsets chosen for implementation. Shortened blocks are supported with granularity at lifting size Zc-bit boundaries. Customizable modes generation is also supported beyond the scope of the 5G-NR specification with features such as: “flat parity bits puncturing instead of Rate Matching Bit Selection”, “maintaining the first 2xZc payload bits instead of eliminating it before transmission”, etc. The ntLDPCD_5GNR decoder IP implements a maximum lifting size of Zc_MAX-bit parallel systematic LDPC layered decoder. Each layer corresponds to Zc_MAX expanded rows of the original LDPC matrix. Each layer element corresponds to the active ZcxZc shifted identity sub-matrices within the layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit, in order to update the layers LLR estimates and extrinsic information iteratively until the required number of decoding iterations has been run. The decoder IP also features a powerful optional early termination (ET) criterion, to maintain practically equivalent error correction performance, while significantly increasing its throughput rate and/or reducing hardware cost. Additionally it reports how many decoding iterations have been performed when ET is activated, for system performance observation and calibration purposes. Finally a simple, yet robust, flow control handshaking mechanism is included in both IPs, which is used to communicate the IPs availability to adjacent system components. This logic is easily portable into any communication protocol, like AXI4 stream IF.
InnoSilicon's 56G SerDes Solution is crafted to address the growing need for high-bandwidth data transmission in data centers, telecommunications, and enterprise network infrastructures. SerDes, or Serializer/Deserializer technology, is crucial for enhancing data throughput and reducing latency, making it ideal for high-speed network operations. Designed to support multiple protocols including PCIe, Ethernet, and beyond, the 56G SerDes solution provides flexibility and robustness required by modern communication systems. Its high data rates allow for rapid data exchange that meets the demands of high-performance computing environments. This makes it an essential component in systems requiring extensive data processing capabilities. The architecture of the 56G SerDes combines low power consumption with high throughput, making it suitable for applications that require energy efficiency without compromising on speed. Its design incorporates advanced signal processing techniques to maintain data integrity, offering a reliable solution that scales with the requirements of evolving technologies.
APIX3 represents the latest evolution in high-speed data transmission modules, engineered specifically for automotive infotainment and cockpit architectures. Designed to interface seamlessly within vehicle IT landscapes, it supports transmissions up to 12 Gbps using shielded or quad twisted pair cables. APIX3 offers unique capabilities like multiple video stream handling on a single connection and supports advanced diagnostics, including cable health checks for predictive maintenance. This technology is backward compatible with APIX2, enhancing modular flexibility across previous and new vehicle designs. With support for UHD automotive display resolutions, APIX3 ensures all-in-one connectivity solutions for complex exterior and interior automotive systems. The APIX3 modules enable comprehensive networking through various serial interface protocols and are positioned as go-to solutions for future-proofing in-car data systems. Each channel within APIX3 is fine-tuned for specific needs, from video data handling to full-duplex telecommunications. Additionally, APIX3 supports Ethernet connectivity for seamless integration into the larger automotive communication network. Thanks to its efficient design, APIX3 provides stability and enhanced bandwidth support, delivering robust performance suited for both entry-level and high-end automotive systems.
The HOTLink II IP Core is a highly sophisticated implementation of layer 2 hardware for High-Speed Interconnect (HSI) systems. It provides a comprehensive and robust platform for data communication, ensuring seamless integration into systems through an intuitive frame interface. The core is compatible with various operational rates, including full-rate, half-rate, and quarter-rate, as explicitly specified by the associated standard. Engineered for compatibility with F-18 interface requirements, the HOTLink II IP Core enhances system reliability and efficiency. It empowers engineers to achieve reliable high-speed data links necessary for modern defense and aerospace applications. This core is designed to operate under diverse conditions, providing resilient support for complex networking needs. The HOTLink II IP Core stands out with its ease of integration and operational flexibility, making it invaluable for enterprises looking to enhance high-speed data communication capabilities. With its robust design, it can handle intensive demand cycles, ensuring uninterrupted performance even in critical environments.
Terminus Circuits' SerDes PHY caters to diverse market needs, from networking and data storage to enterprise-level routers and industrial applications. It enables seamless data rate configurations, supporting multiple standards like PCI Express Gen1 to Gen4, USB3.1, and more. The PHY is engineered to deliver high speed and low power while maintaining stringent control over channel characteristics through adaptive equalization techniques. Its broad compatibility with different protocols and data rates makes it a highly versatile solution in complex system integrations.
The BlueLynx Chiplet Interconnect is a sophisticated die-to-die interconnect solution that offers industry-leading performance and flexibility for both advanced and conventional packaging applications. As an adaptable subsystem, BlueLynx supports the integration of Universal Chiplet Interconnect Express (UCIe) as well as Bunch of Wires (BoW) standards, facilitating high bandwidth capabilities essential for contemporary chip designs.\n\nBlueLynx IP emphasizes seamless connectivity to on-die buses and network-on-chip (NoCs) using standards such as AMBA, AXI, and ACE among others, thereby accelerating the design process from system-on-chip (SoC) architectures to chiplet-based designs. This innovative approach not only allows for faster deployment but also mitigates development risks through a predictable and silicon-friendly design process with comprehensive support for rapid first-pass silicon success.\n\nWith BlueLynx, designers can take advantage of a highly optimized performance per watt, offering customizable configurations tailored to specific application needs across various markets like AI, high-performance computing, and mobile technologies. The IP is crafted to deliver outstanding bandwidth density and energy efficiency, bridging the requirements of advanced nodal technologies with compatibility across several foundries, ensuring extensive applicability and cost-effectiveness for diverse semiconductor solutions.
The FC Link Layer (LL) IP Core delivers a complete implementation of Fibre Channel's layer protocols, encompassing both FC-1 and FC-2 layers. This IP core plays an essential role in facilitating high-performance network solutions, providing reliable data transmission and integrity across diverse communication systems. Designed primarily for aerospace and defense applications, this core ensures accurate data handling and synchronization by managing communications across various system interfaces. It enhances system compatibility and adaptability, ensuring compliance with industry standards and facilitating advanced networking capabilities. The FC LL IP Core's robust design and seamless integration mechanics make it an ideal choice for environments demanding high data throughput and minimal latency. It assures top-tier reliability in network communications focused on mission-critical operations in a variety of challenging conditions.
The JPEG Encoder offered by section5 is a highly efficient image compression solution suitable for standard Field Programmable Gate Arrays (FPGAs). This encoder facilitates machine vision systems by providing robust JPEG and motion JPEG encoding capabilities. It is designed to work with pixel depths up to 12 bits and supports dual-channel operations for high-quality image processing, such as 1280x720 at 60 frames per second.\n\nGiven its adaptability, this JPEG Encoder is applicable for high-speed, low-latency video streaming applications, making it ideal for real-time image capture. It achieves this through its sophisticated low-latency design, capable of synchronous operation without external RAM, merely relying on the FPGA and Ethernet Phy components.\n\nThe encoder further extends its functionality through integrated streaming solutions compatible with both Windows and Linux platforms. This is facilitated using embedded GStreamer applications that ensure stable, lossless transmission even over high bandwidths. For developers, the JPEG IP offers comprehensive simulation models and support for custom application integration, assuring seamless deployment in various hardware environments.
PCS2100 is a modem chip specifically crafted for Wi-Fi HaLow IoT applications, part of Palma Ceia's lineup designed according to IEEE 802.11ah standard. This chip empowers IoT devices by ensuring effective long-range communication over low power networks, essential for smart networks scaling up extensive regions. It functions over sub-gigahertz bands, distinguishing itself by enabling communication extending up to 1 kilometer. This expansive reach, combined with the high-density network support, makes the PCS2100 exceptionally suitable for smart city infrastructures and industrial IoT networks. The chip's architecture allows it to operate over 755 to 928 MHz bands with great efficiency, abiding to different regional regulations. Enhanced by protocols that minimize power use, such as Target Wake Time, this chip ensures long battery life in IoT deployments, pivotal for resource-heavy setups like smart manufacturing. The PCS2100 includes robust security protocols, supporting WPA3 Personal and others, to ensure secure data transmission across device connections.
The 100G Transponder CAUI-10 facilitates seamless optical-to-electrical signal conversion, doubling as an efficient intermediary in high-capacity network systems. These transponders are invaluable for telecommunications setups that demand high data rates and extended reach, providing the necessary tools to manage complex digital signal demands.
Designed for advanced network diagnostics, the 10G Universal Network Probe enables comprehensive traffic monitoring and analysis across OTN and other high-capacity networks. This probe offers versatile compatibility, ensuring streamlined integration into existing infrastructure, a critical function for maintaining high-speed data transmission fidelity and efficiency.
The ADQ7DC stands out with its high-resolution 14-bit digitization capability, providing users with a single or dual-channel configuration for enhanced flexibility. Its formidable 10 GSPS sampling speed offers compelling performance for applications requiring high fidelity data conversion, allowing for intricate RF signal capture and analysis.
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