All IPs > Network on Chip
Network on Chip (NoC) semiconductor IP is a pivotal element in the design and development of highly integrated electronic systems and chips. As devices become more complex and contain multiple processing units, effective communication through reliable interconnections is crucial. NoC IPs provide a scalable and efficient way to connect various intellectual properties (IPs) within a system on chip (SoC), enabling improved data transfer, performance, and power efficiency.
In modern multicore processor architectures, the traditional bus-based communication faces challenges with scalability, latency, and energy consumption. NoC IPs address these issues by offering packet-based communication paradigms, which are structured like networks to efficiently manage data flow between cores, memory controllers, and peripheral interfaces. This technology is vital for a range of applications including data centers, mobile processors, automotive systems, and beyond. It not only helps in breaking the bandwidth bottleneck but also enhances the overall performance of the system.
A detailed exploration of the Network on Chip category reveals various types of IPs designed to cater to different specific needs, including low-latency networks, high-bandwidth connections, and power-conserving interfaces. Developers and designers can choose from pre-verified solutions by leading vendors, ensuring reliability and reducing time to market. Functionalities offered by these IP solutions might include advanced routing algorithms, traffic prioritization, security features, and error correction mechanisms.
Furthermore, semiconductor IPs in the Network on Chip category are continuously evolving to support emerging technologies such as AI, IoT, and 5G. This makes NoC IPs not only a fundamental infrastructure element but also a key enabler of future technological advancements. Companies seeking to develop state-of-the-art, fully integrated SoCs will find the NoC IP category indispensable in constructing efficient and robust systems capable of meeting current and future demands.
Akida Neural Processor IP by BrainChip serves as a pivotal technology asset for enhancing edge AI capabilities. This IP core is specifically designed to process neural network tasks with a focus on extreme efficiency and power management, making it an ideal choice for battery-powered and small-footprint devices. By utilizing neuromorphic principles, the Akida Neural Processor ensures that only the most relevant computations are prioritized, which translates to substantial energy savings while maintaining high processing speeds. This IP's compatibility with diverse data types and its ability to form multi-layer neural networks make it versatile for a wide range of industries including automotive, consumer electronics, and healthcare. Furthermore, its capability for on-device learning, without network dependency, contributes to improved device autonomy and security, making the Akida Neural Processor an integral component for next-gen intelligent systems. Companies adopting this IP can expect enhanced AI functionality with reduced development overheads, enabling quicker time-to-market for innovative AI solutions.
The Akida 2nd Generation continues BrainChip's legacy of low-power, high-efficiency AI processing at the edge. This iteration of the Akida platform introduces expanded support for various data precisions, including 8-, 4-, and 1-bit weights and activations, which enhance computational flexibility and efficiency. Its architecture is significantly optimized for both spatial and temporal data processing, serving applications that demand high precision and rapid response times such as robotics, advanced driver-assistance systems (ADAS), and consumer electronics. The Akida 2nd Generation's event-based processing model greatly reduces unnecessary operations, focusing on real-time event detection and response, which is vital for applications requiring immediate feedback. Furthermore, its sophisticated on-chip learning capabilities allow adaptation to new tasks with minimal data, fostering more robust AI models that can be personalized to specific use cases without extensive retraining. As industries continue to migrate towards AI-powered solutions, the Akida 2nd Generation provides a compelling proposition with its improved performance metrics and lower power consumption profile.
The Coherent Network-on-Chip (NOC) from SkyeChip is crafted to provide an efficient and scalable interconnect solution for systems requiring memory coherence. Designed to support ACE4, ACE5, and CHI protocols, this NOC is structured to handle data transfers in multi-core systems while minimizing routing congestion. Operating at frequencies up to 2GHz, this network solution excels in achieving high-frequency timing closure, essential for the demands of modern compute architectures. The NOC integrates SkyeChip's Home Agent and is compatible with other proprietary coherence handlers, making it a versatile choice for diverse systems. It also features support for source synchronous and synchronous clocking methodologies, enabling flexible deployment in various technological frameworks. Seamless integration with SkyeChip's Non-Coherent NOC facilitates partitioned system designs, providing a holistic approach to interconnect architecture. This coherent NOC is perfect for complex applications where bandwidth, routing efficiency, and coherent data handling are key.
EXTOLL's Universal Chiplet Interconnect Express (UCIe) is a cutting-edge solution designed to meet the evolving needs of chip-to-chip communication. UCIe enables seamless data exchange between chiplets, fostering a new era of modular and scalable processor designs. This technology is especially vital for applications requiring high bandwidth and low latency in data transfer between different chip components. Built to support heterogeneous integration, UCIe offers superior scalability and is compatible with a variety of process nodes, enabling easy adaptation to different technological requirements. This ensures that system architects can achieve optimal performance without compromising on design flexibility or efficiency. Furthermore, UCIe's design philosophy is centered around maintaining ultra-low power consumption, aligning with modern demands for energy-efficient technology. Through EXTOLL’s UCIe, developers have the capability to build versatile and multi-functional platforms that are more robust than ever. This interconnect technology not only facilitates communications between chips but enhances the overall architecture, paving the way for future innovations in chiplet systems.
The Chimera GPNPU from Quadric is engineered to meet the diverse needs of modern AI applications, bridging the gap between traditional processing and advanced AI model requirements. It's a fully licensable processor, designed to deliver high AI inference performance while eliminating the complexity of traditional multi-core systems. The GPNPU boasts an exceptional ability to execute various AI models, including classical backbones, state-of-the-art transformers, and large language models, all within a single execution pipeline.\n\nOne of the core strengths of the Chimera GPNPU is its unified architecture that integrates matrix, vector, and scalar processing capabilities. This singular design approach allows developers to manage complex tasks such as AI inference and data-parallel processing without resorting to multiple tools or artificial partitioning between processors. Users can expect heightened productivity thanks to its modeless operation, which is fully programmable and efficiently executes C++ code alongside AI graph code.\n\nIn terms of versatility and application potential, the Chimera GPNPU is adaptable across different market segments. It's available in various configurations to suit specific performance needs, from single-core designs to multi-core clusters capable of delivering up to 864 TOPS. This scalability, combined with future-proof programmability, ensures that the Chimera GPNPU not only addresses current AI challenges but also accommodates the ever-evolving landscape of cognitive computing requirements.
SkyeChip's Non-Coherent Network-on-Chip (NOC) is a solution optimized for performance and area efficiency, significantly reducing silicon wire utilization. Designed to operate at high frequencies up to 2GHz, this NOC is engineered to facilitate efficient data communication across ICs while minimizing routing congestion. It supports a range of protocols, including AXI4, AXI5, and proprietary protocols, providing flexibility in integration. The architecture is tailored to ease timing closure at high frequencies and supports both synchronous and source-synchronous clocking topologies. It is equipped to bridge 2.5D and 3D die-to-die interfaces, making it suitable for advanced system partitioning and component interconnects. Moreover, the network seamlessly integrates with SkyeChip's Coherent NOC, offering a cohesive solution for systems that require both coherent and non-coherent data transfers. Its scalability and robust design make it a prime choice for applications that demand high bandwidth with efficient area utilization, catering to the needs of modern processing environments that are space-constrained yet performance-driven.
The NuLink Die-to-Die PHY for Standard Packaging represents Eliyan's cornerstone technology, engineered to harness the power of standard packaging for die-to-die interconnects. This technology circumvents the limitations of advanced packaging by providing superior performance and power efficiencies traditionally associated only with high-end solutions. Designed to support multiple standards, such as UCIe and BoW, the NuLink D2D PHY is an ideal solution for applications requiring high bandwidth and low latency without the cost and complexity of silicon interposers or silicon bridges. In practical terms, the NuLink D2D PHY enables chiplets to achieve unprecedented bandwidth and power efficiency, allowing for increased flexibility in chiplet configurations. It supports a diverse range of substrates, providing advantages in thermal management, production cycle, and cost-effectiveness. The technology's ability to split a Network on Chip (NoC) across multiple chiplets, while maintaining performance integrity, makes it invaluable in ASIC designs. Eliyan's NuLink D2D PHY is particularly beneficial for systems requiring physical separation between high-performance ASICs and heat-sensitive components. By delivering interposer-like bandwidth and power in standard organic or laminate packages, this product ensures optimal system performance across varied applications, including those in AI, data processing, and high-speed computing.
The ePHY-5616 delivers data rates from 1 to 56Gbps across technology nodes of 16nm and 12nm. Designed for a diverse range of applications, this product offers superior BER and low latency, making it ideal for enterprise equipment like routers, switches, and network interface cards. The ePHY-5616 employs a highly configurable DSP-based receiver architecture designed to manage various insertion loss scenarios, from 10dB up to over 35dB. This ensures robust and reliable data transfer across multiple setups.
aiSim 5 represents a pivotal advancement in the simulation of automated driving systems, facilitating realistic and efficient validation of ADAS and autonomous driving components. Designed to exceed conventional expectations, aiSim 5 combines high-fidelity sensor and environment simulation with an AI-based digital twin concept to deliver unparalleled simulation accuracy and realism. It is the first simulator to be certified at ISO 26262 ASIL-D level, offering users the utmost industry trust.\n\nThe simulated environments are rooted in physics-based sensor data and cover a wide spectrum of operational design domains, including urban areas and highways. This ensures the simulation tests AD systems under diverse and challenging conditions, such as adverse weather events. aiSim 5's modular architecture supports easy integration with existing systems, leveraging open APIs to ensure seamless incorporation into various testing and continuous integration pipelines.\n\nNotably, aiSim 5 incorporates aiFab's domain randomization to create extensive synthetic data, mirroring real-world variances. This feature assists in identifying edge cases, allowing developers to test system responsiveness in rare but critical scenarios. By turning the spotlight on multi-sensor simulation and synthetic data generation, aiSim 5 acts as a powerful tool to accelerate the development lifecycle of ADAS and AD technologies, fostering innovation and development efficiency.\n\nThrough its intuitive graphical interface, aiSim 5 democratizes access to high-performance simulations, supporting operating systems like Microsoft Windows and Linux Ubuntu. This flexibility, coupled with the tool’s compatibility with numerous standards such as OpenSCENARIO and FMI, makes aiSim an essential component for automotive simulation projects striving for precision and agility.
The High-Speed SerDes designed for chiplets by EXTOLL represents a pinnacle in data transfer technologies. This high-performance SerDes is specifically crafted to support the latest chiplet technologies by enabling rapid data movement across chip boundaries. Its implementation ensures minimal latency, critical for time-sensitive applications, all the while maintaining a structure that is easy to integrate within various semiconductor designs. This SerDes offers unparalleled flexibility and adaptability for users seeking high-speed connectivity within chiplet environments. It supports a wide range of mainstream process nodes, thus ensuring compatibility with a diverse array of design requirements. Moreover, its architecture is optimized for energy efficiency, reducing the overall power consumption of systems which is crucial in today’s power-conscious technological landscape. EXTOLL’s High-Speed SerDes is not only about performance but also about reliability and scalability. As systems require more data and increased processing power, maintaining data integrity becomes a mission-critical requirement. This SerDes is engineered to provide robust error correction and data integrity, thus ensuring high standards of reliability while supporting the data bandwidth needs of modern, complex semiconductor applications.
The Hyperspectral Imaging System developed by Imec is a revolutionary tool for capturing and analyzing light across a wide range of wavelengths. This system is particularly valuable for applications requiring detailed spectral analysis, such as agricultural inspection, environmental monitoring, and medical diagnostics. By capturing hundreds of narrow spectral bands, the system provides a comprehensive spectral profile of the subject, enabling precise identification of materials and substances. What sets Imec's Hyperspectral Imaging System apart is its ability to integrate seamlessly into existing devices, allowing for versatile use across various industries. The compact and efficient design ensures that it can be deployed in field conditions, offering real-time analysis capabilities that are crucial for immediate decision-making processes. The Hyperspectral Imaging System is designed with cutting-edge CMOS technology, ensuring high sensitivity and accuracy. This integration with CMOS technology not only enhances the performance but also ensures that the system is cost-effective and accessible to a broader range of applications and markets. As hyperspectral imaging continues to evolve, Imec's system stands as a leader in the field, providing unmatched resolution and reliability.
The Network on Chip (NOC-X) offered by EXTOLL is designed to support complex system architectures by providing a high-performance interconnect fabric within a chip. This technology is vital for balancing the load and efficiently managing data traffic between different components within a chip, ensuring system cohesiveness and efficiency. NOC-X enhances data throughput and reduces the latency issues commonly associated with traditional bus-based interconnects. Its design is optimized to provide dynamic bandwidth allocation and efficient route management, which are crucial for applications with rigorous data exchange demands, such as in AI and complex processor arrays. By deploying NOC-X, developers can achieve a fine-tuned orchestration of data pathways, improving the overall efficiency and performance of their designs. This network design simplifies scaling for extensive systems and provides a backbone for integrating advanced features with minimal overhead, accommodating the continuous evolution and expansion of semiconductor functionalities.
The Ncore Cache Coherent Interconnect from Arteris is engineered to overcome challenges associated with multicore SoC designs. It delivers high-bandwidth, low-latency interconnect fabric enhancing communication efficiency across various SoC components and multiple dies. Designed to ensure reliable performance and scalability, this coherent NoC addresses complex tasks by implementing heterogeneous coherency, and it is scalable from small embedded systems to extensive multi-die designs. Ncore promotes effective cache management, providing full coherency for processors and I/O coherency for accelerators. It supports various coherency protocols including CHI-E and ACE, and comes with ISO 26262 certification, meeting stringent safety standards in automotive environments. The inherent AMBA support allows seamless integration with existing and new SoC infrastructures, enhancing data handling efficiency. By offering automated generation of diagnostic analysis and fault modes, Ncore aids developers in creating secure systems ready for advanced automotive and AI applications, thereby accelerating their time-to-market. Its configurability and extensive protocol support position it as a trusted choice for industries requiring flexible and robust system integration solutions.
ISPido represents a fully configurable RTL Image Signal Processing Pipeline, adhering to the AMBA AXI4 standards and tailored through the AXI4-LITE protocol for seamless integration with systems such as RISC-V. This advanced pipeline supports a variety of image processing functions like defective pixel correction, color filter interpolation using the Malvar-Cutler algorithm, and auto-white balance, among others. Designed to handle resolutions up to 7680x7680, ISPido provides compatibility for both 4K and 8K video systems, with support for 8, 10, or 12-bit depth inputs. Each module within this pipeline can be fine-tuned to fit specific requirements, making it a versatile choice for adapting to various imaging needs. The architecture's compatibility with flexible standards ensures robust performance and adaptability in diverse applications, from consumer electronics to professional-grade imaging solutions. Through its compact design, ISPido optimizes area and energy efficiency, providing high-quality image processing while keeping hardware demands low. This makes it suitable for battery-operated devices where power efficiency is crucial, without sacrificing the processing power needed for high-resolution outputs.
Packetcraft's Bluetooth LE Audio Solutions offer a full suite of host, controller, and LC3 components optimized for seamless transition to Bluetooth LE Audio. The platform supports Auracast broadcast audio and True Wireless Stereo (TWS), making it adaptable to prevalent chipsets and providing flexibility to product companies. The modular design facilitates simplified integration, ensuring companies can leverage advanced audio capabilities in a variety of applications. As Bluetooth audio technology evolves, Packetcraft remains at the leading edge, offering industry-leading solutions that cater to modern audio requirements.
FlexWay Interconnect caters to the demands of cost-effective, low-power applications, particularly within the Internet of Things (IoT) edge devices and microcontrollers. It is designed as an entry-level network-on-chip IP, emphasizing simplicity without compromising on the dynamic communication needs essential for embedded System-on-Chip projects. This system supports a wide range of configurations and efficiently manages dataflow within small to medium-scale SoCs. Through its intuitive user interface and support for various protocols including AMBA, FlexWay simplifies design processes while maintaining efficient on-chip communication. The IP is equipped with advanced power management features, ensuring great performance with low energy constraints, making it well-suited for battery-operated devices. FlexWay maintains system integrity through robust verification and debugging support, which minimizes errors and accelerates time to market. By combining flexibility in topologies and robust supporting tools, it allows developers to tailor solutions to specific application needs efficiently.
Tensix Neo is an AI-focused semiconductor solution from Tenstorrent that capitalizes on the robustness of RISC-V architecture. This IP is crafted to enhance the efficiency of both AI training and inference processes, making it a vital tool for entities needing scalable AI solutions without hefty power demands. With Tensix Neo, developers can rest assured of the silicon-proven reliability that backs its architecture, facilitating a smooth integration into existing AI platforms. The IP embraces the flexibility and customization needed for advanced AI workloads, optimizing resources and yielding results with high performance per watt. As the demand for adaptable AI solutions grows, Tensix Neo offers a future-proof platform that can accommodate rapid advancements and complex deployments in machine learning applications. By providing developers with tested and verified infrastructure, Tensix Neo stands as a benchmark in AI IP development.
UTTUNGA is a high-performance PCIe accelerator card, purpose-built to amplify HPC and AI tasks through its integration with the TUNGA SoC. It effectively harnesses the power of multi-core RISC-V technology combined with Posit arithmetic, offering significant enhancements in computation efficiency and memory optimization. Designed to be compatible with a broad range of server architectures, including x86, ARM, and PowerPC, UTTUNGA elevates system capabilities, particularly in precision computing applications. The UTTUNGA card operates by implementing foundational arithmetic operations in Posit configurations, supporting multiple bit-width formats for diverse processing needs. This flexibility is further complemented by a pool of programmable FPGA gates, optimized for scenarios demanding real-time adaptability and cloud computing acceleration. These gates facilitate the acceleration of complex tasks and aid in the effortless management of non-standard data types essential for advanced AI processing and cryptographic applications. By leveraging a seamless integration process, UTTUNGA eliminates the need for data copying in host memory, thus ensuring efficient utilization of resources. It also provides support for well-known scientific libraries, enabling easy adoption for legacy systems while fostering a modern computing environment. UTTUNGA stands as a testament to the profound impact of advancing arithmetic standards like Posit, paving the way for a transformation in computational practices across industries.
The BlueLynx Chiplet Interconnect is a sophisticated die-to-die interconnect solution that offers industry-leading performance and flexibility for both advanced and conventional packaging applications. As an adaptable subsystem, BlueLynx supports the integration of Universal Chiplet Interconnect Express (UCIe) as well as Bunch of Wires (BoW) standards, facilitating high bandwidth capabilities essential for contemporary chip designs.\n\nBlueLynx IP emphasizes seamless connectivity to on-die buses and network-on-chip (NoCs) using standards such as AMBA, AXI, and ACE among others, thereby accelerating the design process from system-on-chip (SoC) architectures to chiplet-based designs. This innovative approach not only allows for faster deployment but also mitigates development risks through a predictable and silicon-friendly design process with comprehensive support for rapid first-pass silicon success.\n\nWith BlueLynx, designers can take advantage of a highly optimized performance per watt, offering customizable configurations tailored to specific application needs across various markets like AI, high-performance computing, and mobile technologies. The IP is crafted to deliver outstanding bandwidth density and energy efficiency, bridging the requirements of advanced nodal technologies with compatibility across several foundries, ensuring extensive applicability and cost-effectiveness for diverse semiconductor solutions.
Thermal oxide, often referred to as SiO2, is an essential film used in creating various semiconductor devices, ranging from simple to complex structures. This dielectric film is created by oxidizing silicon wafers under controlled conditions using high-purity, low-defect silicon substrates. This process produces a high-quality oxide layer that serves two main purposes: it acts as a field oxide to electrically insulate different layers, such as polysilicon or metal, from the silicon substrate, and as a gate oxide essential for device function. The thermal oxidation process occurs in furnaces set between 800°C to 1050°C. Utilizing high-purity steam and oxygen, the growth of thermal oxide is meticulously controlled, offering batch thickness uniformity of ±5% and within-wafer uniformity of ±3%. With different techniques used for growth, dry oxidation results in slower growth, higher density, and increased breakdown voltage, whereas wet oxidation allows faster growth, even at lower temperatures, facilitating the formation of thicker oxides. NanoSILICON, Inc. is equipped with state-of-the-art horizontal furnaces that manage such high-precision oxidation processes. These furnaces, due to their durable quartz construction, ensure stability and defect-free production. Additionally, the processing equipment, like the Nanometrics 210, inspects film thickness and uniformity using advanced optical reflection techniques, guaranteeing a high standard of production. With these capabilities, NanoSILICON Inc. supports a diverse range of wafer sizes and materials, ensuring superior quality oxide films that meet specific needs for your semiconductor designs.
The NoC Bus Interconnect by OPENEDGES is a sophisticated solution for modern semiconductor designs, providing efficient on-chip communication. This network-on-chip (NoC) architecture facilitates communication between different IP blocks within a chip, significantly enhancing data flow and reducing bottlenecks compared to traditional bus systems. This interconnect solution is designed to provide high bandwidth and low latency, supporting various data transmission protocols. It's built to be highly scalable, accommodating growing demands in complex system-on-chip (SoC) designs. The flexibility in configuration allows it to support varied application needs, making it a versatile choice for high-performance computing, data centers, and AI applications. Besides its performance advantages, the NoC Bus Interconnect offers features that ensure optimal power management, which is crucial for maintaining efficiency in energy-sensitive applications. By intelligently managing data paths and utilizing advanced buffering techniques, it effectively minimizes power usage while maximizing throughput.
The Complete 5G NR Physical Layer solution by AccelerComm is designed to provide exceptional performance for demanding applications in O-RAN and satellite networks. This all-encompassing solution integrates high-accuracy signal processing technology, ensuring optimal link performance and efficient power usage. The physical layer is inherently flexible, allowing performance optimizations tailored to meet specific requirements of specialized network applications. This solution navigates the complex real-world dynamics involved in high-performance network scenarios, including both terrestrial and space-based communications. By leveraging advanced algorithms and architectures, the 5G physical layer supports customizable configurations, leading to power and area efficiency improvements. Through interoperability with multiple hardware platforms, it maximizes the performance of 5G networks, enhancing the user experience by minimizing latency and maximizing throughput. Delivered as openly-licensable intellectual property, the 5G NR Physical Layer can function across a wide range of platforms, such as ARM software and FPGA, ensuring broad compatibility. This strategic approach facilitates quicker project advancements through seamless integration and testing processes on multiple development boards, thereby reducing project risks effectively.
The Satellite Navigation SoC Integration offering by GNSS Sensor Ltd is a comprehensive solution designed to integrate sophisticated satellite navigation capabilities into System-on-Chip (SoC) architectures. It utilizes GNSS Sensor's proprietary VHDL library, which includes modules like the configurable GNSS engine, Fast Search Engine for satellite systems, and more, optimized for maximum CPU independence and flexibility. This SoC integration supports various satellite navigation systems like GPS, Glonass, and Galileo, with efficient hardware designs that allow it to process signals across multiple frequency bands. The solution emphasizes reduced development costs and streamlining the navigation module integration process. Leveraging FPGA platforms, GNSS Sensor's solution integrates intricate RF front-end components, allowing for a robust and adaptable GNSS receiver development. The system-on-chip solution ensures high performance, with features like firmware stored on ROM blocks, obviating the need for external memory.
SEMIFIVE's SoC Platform provides a comprehensive solution for rapid system-on-chip (SoC) development, tailoring these designs to various key applications. Leveraging purpose-built silicon-proven IPs and optimized design methodologies, it enables lower cost, minimized risk, and swift turnaround times. The platform employs a Domain-Specific Architecture, utilizing pre-configured and verified IP pools, making the integration and development process significantly faster and less complex. This platform is equipped with hardware/software prototypes that ensure customers can bring their ideas to fruition with less overhead and enhanced efficiency. It features technical highlights like the SiFive quad-core U74 RISC-V processor, LPDDR4x memory interfaces, and cutting-edge peripheral interfaces including PCIe Gen4, facilitating various applications ranging from AI inference to big data analytics and vision processing. Customers benefit from significantly reduced non-recurring engineering (NRE) costs and time-to-market durations that are up to 50% lower than the industry average. This framework maximizes design and verification component reusability, therefore reducing engineering risks. Its silicon-proven design ensures reliability and offers a variety of engagement models to cater to the unique needs of different projects.
Specializing in Network-on-Chip (NoC)-based SoC integration, this IP leverages coherent and non-coherent NoC subsystems, crucial for building scalable multi-chip solutions. By integrating several NoC platforms, it offers a robust framework for developing SoCs with enhanced connectivity and performance.
IC Manage's IP Central Management System is an advanced platform designed to streamline the management of semiconductor IPs. This system is engineered to consolidate all IPs—both internal and external—into a comprehensive, searchable catalog, enhancing accessibility and security across a company's design teams. It addresses the complexities of IP reuse and integration, facilitating a more structured and efficient approach to leveraging IP assets. IP Central stands out by supporting seamless information dissemination and access control, crucial for optimizing design workflows and maximizing IP utility. It empowers organizations to effectively catalog their IP portfolios, integrating them into an enterprise-wide repository that is easily accessible yet tightly secure. This feature is particularly beneficial for design teams striving to balance diverse historical designs and methodologies in their projects. Moreover, the platform is instrumental in establishing a global IP catalog, a strategic advantage for companies looking to enhance the value of their IPs. By fostering a culture of organized and secure IP sharing, IP Central aids in reducing development time, costs while increasing reliability and design accuracy. This tool is a critical component for companies aiming to capitalize on their IP investments through improved management and deployment.
FlexNoC Interconnect is renowned for its ability to enable developers to create high-throughput, physically aware network-on-chip (NoC) solutions quicker than traditional methods. Integrated with physical awareness technology, it significantly reduces interconnect area and power consumption, giving place and route teams a superior starting point. By leveraging source-synchronous communications and virtual channels, FlexNoC supports vast chip paths, streamlining the process and enhancing performance. Facilitated by a set of intuitive underlying algorithms, FlexNoC helps construct any topology, thus addressing diverse SoC demands ranging from small to large-scale applications. This flexibility allows for substantial bandwidth, efficiently managing on-chip data flow and facilitating quick access to off-chip memory. Through its rapid installation capabilities and integrated physical awareness, it provides a five times faster resolution cycle time compared to manual approaches. FlexNoC's unique efficiencies contribute to market differentiation by optimizing cache coherence, communication fluidity, and comprehensive integration, thus accelerating product time-to-market. Its implementation in ASIC design ensures combined performance optimization, scalability, and system integration, meeting the rigorous demands of modern computing technologies, particularly in automotive, consumer electronics, and industry sectors.
IC Manage offers the Envision Real-Time Analytics Platform as a cutting-edge tool for semiconductor companies looking to analyze design and verification progress. This platform provides visual insights on extensive data sets, leveraging big data technology to offer near-real-time reports that aid efficient decision-making processes. Envision's capabilities extend to tracking millions of data points across massive datasets, providing clear visibility into the design lifecycle's various stages. This comprehensive overview enables design teams to identify trends, predict performance issues, and optimize their workflows to ensure timely project completion. Its ability to analyze vast quantities of data and provide actionable insights is invaluable for companies focusing on efficient design verification. Moreover, the platform's advanced analytics improve collaboration by offering consistent, transparent, and up-to-date information to all stakeholders. It enhances the ability to respond swiftly to potential design challenges, reducing bottlenecks, increasing accuracy, and improving overall efficiency. These features make Envision a critical asset for companies aiming to remain at the forefront of technology innovation.
The Xinglian-500 interconnect fabric is a crucial component for systems requiring robust data flow management and high throughput. It facilitates seamless communication within multi-core CPU and SoC architectures, providing cache coherence and efficient data handling across channels. Designed to support a wide variety of systems, the Xinglian-500 ensures consistent performance across different layers, helping to optimize data parallelism and workload distribution. This interconnect fabric is central to systems that must maintain a high level of data integrity and synchronization. An innovation by StarFive, it is tailored to support growing demands in SoC design and multi-core CPU development. The Xinglian-500’s flexibility and scalability make it an ideal choice for state-of-the-art computing frameworks and a key player in advancing integrated circuit architectures.
iNoCulator is an innovative solution designed to expedite the development of flexible and configurable Network-on-Chips (NoCs). This comprehensive platform supports NoC creation from initial concepts to system architecture, culminating in RTL simulation, emulation, and implementation. Notable for its user-friendly editing tools, iNoCulator offers complete configuration flexibility and integrates fully with existing EDA environments. This makes it an ideal choice for designers needing seamless and efficient NoC development processes. Its adaptability not only enhances the speed and efficiency of SoC architectures but also significantly reduces time-to-market.
The Concrete Surface Layer Degradation Detection System is designed to monitor and evaluate the condition of concrete surfaces, identifying degradation stages with high precision. It leverages advanced sensor technologies and data analysis to detect surface anomalies that might indicate structural weaknesses or aging, crucial for infrastructure maintenance. Using state-of-the-art imaging and scanning techniques, this system can identify defects that are invisible to the naked eye, enabling early intervention and repair to prevent further damage. This proactive approach to infrastructure management ensures safety and extends the lifespan of concrete structures by providing timely information necessary for maintenance planning. The system's accuracy in degradation detection makes it invaluable for various applications, including bridges, highways, and building maintenance. By integrating IoT capabilities, the system allows for automated data gathering and analysis, providing engineers and maintenance teams with actionable insights for improved decision-making.
ZIA Stereo Vision is designed to offer superior depth perception and object detection by employing advanced stereo vision algorithms. This system enhances the capabilities of autonomous vehicles and drones, providing precise imaging for real-time decision-making applications. Built with a focus on accuracy and computational efficiency, it supports a range of stereoscopic camera systems, enabling better navigation and environmental interaction.
The IMG B-Series is designed to provide scalable performance across a diverse range of markets, from set-top boxes to high-end desktop applications. Its architecture allows for customization, offering options from low-area configurations to powerful multi-core solutions that enhance multitasking capabilities. Equipped with Imagination's innovative multi-core GPU technology, the B-Series enables developers to boost performance or enhance multitasking flexibility according to the device requirements. This adaptability is particularly advantageous for products demanding varying levels of compute power and energy efficiency. Targeting both consumer and industrial applications, its power-efficient design supports prolonged device use without compromising on graphical output quality. The B-Series underscores Imagination’s commitment to providing flexible solutions that meet the evolving needs of modern computing.
Atrevido is a versatile 64-bit out-of-order execution RISC-V processor core known for its high performance in demanding AI and HPC applications. The core is capable of handling a wide range of tasks with a design that supports 2/3/4-wide execution paths, ensuring optimal throughput. Included within Atrevido's capabilities are integrated vector and tensor units, which deliver comprehensive acceleration for AI and machine learning tasks without latency penalties. Equipped with Gazzillion Misses™ technology, Atrevido efficiently manages memory bottlenecks, supporting up to 128 simultaneous memory requests. This enhancement is critical for handling large datasets typical in AI and high-performance computing. Designed for Linux environments, it supports multiprocessing with extensive interfaces such as AXI and CHI for high-bandwidth requirements. With customizable elements including vector specifications and cache configurations, Atrevido is engineered for precision and flexibility. Whether you are developing key-value stores, engaging in AI inference, or conducting complex data analysis, Atrevido's robust architecture is designed to provide highly efficient and rapid computational capabilities.
StarFive introduces the Xinglian-700, a high-performance interconnect fabric designed to deliver exceptional scalability and performance for complex processor networks. Ideal for multi-core CPUs and advanced SoCs, this component assures the necessary bandwidth and cache coherence for sophisticated data processing. The Xinglian-700 builds on StarFive's expertise in creating highly scalable fabrics, ensuring that each processor in the network communicates effectively, minimizing latency, and improving data throughput. The robustness of this interconnect supports expansive configurations, making it a preferred choice for enterprises needing high-level integration and scalability. its adaptability, the Xinglian-700 revolutionizes interconnect architectures by offering easily configurable options suitable for a wide variety of applications-from data centers requiring massive processing capabilities to consumer electronics needing efficiency and speed.
IQonIC Works’ Intelligent Sensor and Power Management Platform (ISP) provides an all-encompassing solution for the development of sensor-based, intelligent, embedded applications. The platform emphasizes key areas like power management, energy harvesting, sensor interfacing, and processing, utilizing a rich variety of design building blocks and pre-assembled, validated sub-systems. By offering this suite as an integrated platform, IQonIC Works ensures that projects aimed at developing new ASICs or improving existing designs can maintain budget and time constraints more typical of derivative projects. The ISP expands the scope of possibilities in diverse applications, especially those associated with IoT, by delivering modular and scalable design tools. Additionally, the ISP supports various MCU cores and I/O IP configurations, allowing solutions to be tailored to specific application requirements. It integrates easily with other design blocks, providing the flexibility needed to accommodate additional features such as communication and security, making it an invaluable resource for advanced IoT and sensor applications.
The UCIe Chiplet Interconnect solution is a high-speed interface designed for efficient chip-to-chip and die-to-die communications within a SoC platform. This innovative interconnect adopts state-of-the-art technology to offer cross-chip bridging with support for AXI and CHI interfaces, ensuring seamless data transfer and integration between different chiplets. With the ever-growing complexity of SoC designs, the UCIe Chiplet Interconnect ensures scalability and flexibility, adapting to a range of system configurations and technical requirements. It allows for a higher degree of customization, enabling developers to tailor the interconnect to fit specific design goals and application demands. Beyond mere connectivity, the UCIe solution provides enhancements in power efficiency, reducing system power requirements while maintaining high data throughput. This solution is ideal for a wide range of applications, including high-performance computing and data centers, where it significantly optimizes the performance and connectivity of multi-chip systems.
Metis is an innovative solution by Xpeedic focusing on the challenges of 2.5D and 3D IC packaging, two critical technology fronts in modern semiconductor manufacturing. This tool addresses the complexities involved in these advanced packaging techniques, facilitating the design and analysis processes to ensure products meet high-performance and reliability standards. As semiconductor devices become increasingly complex, Metis supports the intricate interconnect and integration solutions required by today's cutting-edge electronics. By leveraging Metis, engineers can simulate the thermal, mechanical, and electrical behaviors of IC packages, identifying potential issues early in the design phase. This capability is vital in maintaining the integrity and functionality of densely packed chips. Furthermore, the tool supports co-design efforts, allowing teams to synchronize their work on various design aspects, leading to more efficient and innovative end products. Metis' seamless integration with other Xpeedic tools enables it to play a pivotal role in the multiscale simulation ecosystem. The collaborative environment it fosters helps minimize iterations and enhances the integration quality of semiconductor packages, ensuring that products are robust and performant. This positions Metis as a cornerstone solution for companies looking to advance their 2.5D and 3D packaging capabilities.
The Processor System IP from Akeana is an extensive array of IP blocks designed to accelerate the development and integration of processor systems. This suite includes a compute coherence block (CCB), interconnect fabrics, and other essential system components to support scalable and customizable SOC designs. These components help in seamlessly connecting multiple processors, ensuring coherence and robust data management across systems. This IP suite is integral for those looking to construct comprehensive solutions without compromising flexibility. It enables advanced interrupt handling and memory management, vital for complex systems that demand high synchronization and precise control. Akeana provides architecture support with both coherent and non-coherent interconnects, facilitating a complete multi-core integration according to specific requirements. Customers are empowered to blend these system IP blocks into their designs, enhancing performance and reliability. The flexible nature of this offering makes it ideal for processors aiming for advanced configurations, delivering scalability and performance demanded by modern applications in environments such as cloud computing and edge systems.
The Stellar Packet Classification Platform offers an advanced solution for complex packet processing and network management by leveraging cutting-edge classification techniques. Designed to efficiently handle ultra-high search performance, Stellar excels in implementing comprehensive Access Control List (ACL) rules and Longest Prefix Match (LPM) methods. This sophisticated IP is capable of executing hundreds of millions of lookups per second, ensuring seamless processing within demanding networking environments. Ideally suited for high-reliability systems such as 5G User Plane Function (UPF) and network firewalls, Stellar provides robust security measures against threats like Distributed Denial of Service (DDoS) attacks. With capabilities extending from IPV4/6 address lookups to real-time routing, Stellar effectively supports extensive application bandwidths and complex rule integrations. Live updates ensure that the platform remains responsive to dynamic network scenarios, maintaining optimal system performance and integrity.
Channel Sounding is the latest advancement in Bluetooth technology, offering high-precision distance measurement and location capabilities. This innovative technology provides a wide range of applications and competitive use cases, suited for environments requiring accurate spatial awareness. With Channel Sounding, users can achieve enhanced accuracy in measuring distances, making it ideal for automotive, industrial, and consumer electronics applications. Available as part of Packetcraft's suite, this solution represents the future of Bluetooth’s role in distance-based measurement technologies.
The H-Series PHY is a premier high-bandwidth memory (HBM) PHY solution, serving as a standard for graphics and high-performance computing applications. Its architecture supports both HBM2 and HBM2E, delivering an impressive bandwidth density that meets the rigorous demands of modern computing systems. This IP core ensures low latency and efficient power consumption, optimizing performance for applications such as graphics processing, data centers, and networking. A comprehensive ecosystem supports the integration of H-Series PHY, including Design Acceleration Kits that offer design optimization tools and reference floor plans, tailored to streamline the product development process.
The NC-NoC offers an advanced, configurable NoC solution that is both scalable and physically aware. It is designed to accommodate multiple clocking schemes, making it suitable for a wide range of applications not requiring coherency. This solution is compatible with various protocols such as AXI4/3, AHB, APB, and AXI-lite, with bus widths ranging from 32 to 2048 bits. Its layered architecture facilitates seamless integration into diverse SoC environments, providing a robust framework for efficient data routing and high system performance. The NC-NoC stands out for its capacity to support complex, multi-protocol operations, delivering reliable and high-speed interconnectivity within SoCs.
FlexGen Smart Network-on-Chip (NoC) leverages advanced AI-driven heuristics to revolutionize SoC design by automating NoC topology generation, significantly enhancing productivity. This innovative IP aims to maximize engineering efficiency through minimal manual intervention, achieving a tenfold increase in productivity compared to traditional methods. Dedicated to large-scale automotive, data center, and industrial electronics, FlexGen utilizes intelligent algorithms to optimize wire length and power efficiency, enabling faster design iterations and greater design exploration for complex systems. The AI-based insights facilitate automatic timing closure assistance, ensuring that designs are both accurate and optimal. FlexGen enhances performance by employing streamlined network interfaces, reducing latency, and improving power efficiency, all critical in the fast-paced SoC environment. By promoting faster product cycles and higher yield, it empowers developers to navigate design complexities effectively, ensuring a competitive advantage in the rapidly evolving semiconductor landscape.
C-NoC represents a major advancement in coherent NoC technology, scheduled for release in the second half of 2023. It supports an array of topologies, including mesh, grid, and torus, and incorporates on-chip L3 cache to reduce latency significantly. This solution is engineered to support multiple protocols such as CHI, AXI4/3, AXI-lite, ACE, and ACE-lite, with adaptability to bus widths from 32 to 2048 bits. C-NoC's versatile design makes it a powerful option for systems that require coherence and high-speed data processing. The integration of robust caching mechanisms ensures optimized data flow and enhanced system efficiency, making it a valuable addition for sophisticated SoC designs.
MIPS Sense Data Movement Engines are specialized for handling data flows in high-demand environments such as AI-driven data centers and industrial networking infrastructures. These engines are crafted to efficiently process and integrate sensor data, a critical component in platforms that rely on real-time data to make informed decisions. The data movement engines facilitate seamless communication protocols including TSN and EtherCAT, supporting turnkey solutions for quick adoption and deployment. This compatibility is crucial for systems that require rapid data transfer and integration to function optimally, such as those in autonomous manufacturing systems and AI datacenters. Designed to handle gigabytes of data per second, the Sense engines improve throughput and reliability, making them essential in advanced environments where high-speed data processing is a necessity. The combination of these engines with MIPS' multithreading and functional safety options provides increased reliability and performance, ensuring that the data movement infrastructure is robust and efficient.
KMX 100G UDPIP Core implements UDP/IP protocol hardware stack that achieves high-speed communication over a LAN or a point-to-point connection, which is ideal to offload systems from demanding tasks of UDP/IP encapsulation and to enable media streaming in both FPGA and RISC designs. The core supports ARP request, reply and manages 32-entry ARP cache. ICMP ping reply is included. The core provides DHCP client engine, which can get an IP address from external DHCP servers. The 100G UDPIP Core implements V3 IGMP membership Query/Report messaging. IP jumbo packets are supported as well as UDP port number filters and VLAN. IP/UDP checksum generation and validation are implemented. They can be enabled or disabled. The MDIO bus access to external device via AXI4-Lite bus is included. The IP raw packets are supported in both TX and RX. IP fragmentation and TCP protocol hardware stack companion core are available on demand. The core supports 32 RX channels and 32 TX channels. Each of the RX channels can be configured and associated with any of five RX ports. Each of the TX channels can be used to send IP packets on any of five TX Ports. The core connects to user logic through Control write Interface and Control Read Interface of AXI4-Lite buses; five RX Dedicated Ports of AXI4-Stream buses and five TX Dedicated Ports of AXI4-Stream buses. The core connects to 100G MAC module through AXI4-Stream bus. KMX 100G MAC and PCS cores are available to KMX customers.
The H-Series Controller complements the HBM PHY by managing data transfer and memory operations with precision. Designed for high-performance scenarios, it is integral to managing high throughput demands while maintaining system efficiency. This controller interfaces seamlessly with MEMTECH's HBM PHY, utilizing advanced schedulers and error correction capabilities to enhance reliability and throughput. Its robust feature set, optimized for today’s intensive computing environments, makes it indispensable for high-demand sectors like AI, machine learning, and graphics processing.
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