All IPs > Network on Chip
Network on Chip (NoC) semiconductor IP is a pivotal element in the design and development of highly integrated electronic systems and chips. As devices become more complex and contain multiple processing units, effective communication through reliable interconnections is crucial. NoC IPs provide a scalable and efficient way to connect various intellectual properties (IPs) within a system on chip (SoC), enabling improved data transfer, performance, and power efficiency.
In modern multicore processor architectures, the traditional bus-based communication faces challenges with scalability, latency, and energy consumption. NoC IPs address these issues by offering packet-based communication paradigms, which are structured like networks to efficiently manage data flow between cores, memory controllers, and peripheral interfaces. This technology is vital for a range of applications including data centers, mobile processors, automotive systems, and beyond. It not only helps in breaking the bandwidth bottleneck but also enhances the overall performance of the system.
A detailed exploration of the Network on Chip category reveals various types of IPs designed to cater to different specific needs, including low-latency networks, high-bandwidth connections, and power-conserving interfaces. Developers and designers can choose from pre-verified solutions by leading vendors, ensuring reliability and reducing time to market. Functionalities offered by these IP solutions might include advanced routing algorithms, traffic prioritization, security features, and error correction mechanisms.
Furthermore, semiconductor IPs in the Network on Chip category are continuously evolving to support emerging technologies such as AI, IoT, and 5G. This makes NoC IPs not only a fundamental infrastructure element but also a key enabler of future technological advancements. Companies seeking to develop state-of-the-art, fully integrated SoCs will find the NoC IP category indispensable in constructing efficient and robust systems capable of meeting current and future demands.
The Akida Neural Processor IP by BrainChip is a versatile AI solution that melds neural processing capabilities with scalable digital architecture, delivering high performance with minimal power consumption. At its core, this processor is engineered using principles from neuromorphic computing to address the demands of AI workloads with precision and speed. By enabling efficient computations with sparse data, the Akida Neural Processor optimizes sparse data, weights, and activations, making it especially suitable for AI applications that demand real-time processing with low latency. It provides a flexible solution for implementing neural networks with varying complexities and is adaptable to a wide array of use cases from audio processing to visual recognition. The IP core’s configurable framework supports the execution of complex neural models on edge devices, effectively running sophisticated neural algorithms like Convolutional Neural Networks (CNNs) without the need for complementary computing resources. This standalone operation capability reduces dependency on external CPUs, driving down power consumption and liberating devices from constant network connections.
The Akida 2nd Generation processor further advances BrainChip's AI capabilities with enhanced programmability and efficiency for complex neural network operations. Building on the principles of its predecessor, this generation is optimized for 8-, 4-, and 1-bit weights and activations, offering more robust activation functions and support for advanced temporal and spatial neural networks. A standout feature of the Akida 2nd Generation is its enhanced teaching capability, which includes learning directly on the chip. This enables the system to perform one-shot and few-shot learning, significantly boosting its ability to adapt to new tasks without extensive reprogramming. Its architecture supports more sophisticated machine learning models such as Convolutional Neural Networks (CNNs) and Spatio-Temporal Event-Based Neural Networks, optimizing them for energy-efficient application at the edge. The processor's design reduces the necessity for host CPU involvement, thus minimizing communication overhead and conserving energy. This makes it particularly suitable for real-time data processing applications where quick and efficient data handling is crucial. With event-based hardware that accelerates processing, the Akida 2nd Generation is designed for scalability, providing flexible solutions across a wide range of AI-driven tasks.
The Coherent Network-on-Chip (NOC) provides scalable, area-efficient interconnect solutions, specifically optimized for memory-coherent systems. This innovation supports ACE4, ACE5, and CHI protocols, integrating seamlessly within complex many-core architectures to efficiently manage routing congestion. It operates at frequencies up to 2GHz, aiding in achieving high frequency timing closures required by modern semiconductor designs. The Coherent NOC works in tandem with SkyeChip's Home Agent while being swappable with proprietary coherency handlers for flexible system architecture designs. This technology also supports both source synchronous and synchronous clocking topologies, promoting continuous interconnect adaptability within diverse environments. Its versatility extends to seamless integration with SkyeChip's Non-Coherent NOC, providing modular interconnect solutions for comprehensive IC design projects.
Chimera GPNPU provides a groundbreaking architecture, melding the efficiency of neural processing units with the flexibility and programmability of processors. It supports a full range of AI and machine learning workloads autonomously, eliminating the need for supplementary CPUs or GPUs. The processor is future-ready, equipped to handle new and emerging AI models with ease, thanks to its C++ programmability. What makes Chimera stand out is its ability to manage a diverse array of workloads within a singular processor framework that combines matrix, vector, and scalar operations. This harmonization ensures maximum performance for applications across various market sectors, such as automotive, mobile devices, and network edge systems. These capabilities are designed to streamline the AI development process and facilitate high-performance inference tasks, crucial for modern gadget ecosystems. The architecture is fully synthesizable, allowing it to be implemented in any process technology, from current to advanced nodes, adjusting to desired performance targets. The adoption of a hybrid Von Neuman and 2D SIMD matrix design supports a broad suite of DSP operations, providing a comprehensive toolkit for complex graph and AI-related processing.
The NuLink Die-to-Die PHY for Standard Packaging represents Eliyan's cornerstone technology, engineered to harness the power of standard packaging for die-to-die interconnects. This technology circumvents the limitations of advanced packaging by providing superior performance and power efficiencies traditionally associated only with high-end solutions. Designed to support multiple standards, such as UCIe and BoW, the NuLink D2D PHY is an ideal solution for applications requiring high bandwidth and low latency without the cost and complexity of silicon interposers or silicon bridges. In practical terms, the NuLink D2D PHY enables chiplets to achieve unprecedented bandwidth and power efficiency, allowing for increased flexibility in chiplet configurations. It supports a diverse range of substrates, providing advantages in thermal management, production cycle, and cost-effectiveness. The technology's ability to split a Network on Chip (NoC) across multiple chiplets, while maintaining performance integrity, makes it invaluable in ASIC designs. Eliyan's NuLink D2D PHY is particularly beneficial for systems requiring physical separation between high-performance ASICs and heat-sensitive components. By delivering interposer-like bandwidth and power in standard organic or laminate packages, this product ensures optimal system performance across varied applications, including those in AI, data processing, and high-speed computing.
The Non-Coherent Network-on-Chip (NOC) offers a performance-centric interconnect solution designed to optimize bandwidth and latency while minimizing silicon wire utilization. This results in power and area-efficient IC designs. It supports a wide range of protocols including AXI4, AXI5, and APB, along with proprietary protocols, ensuring compatibility across various system architectures. This NOC is crafted for high frequency operation, handling up to 2GHz across source synchronous and synchronous clocking topologies. It has been architected to significantly reduce routing congestion, thus facilitating easier high-frequency timing closure in complex multi-core systems. Furthermore, it seamlessly integrates with SkyeChip’s Coherent NOC, enabling efficient interconnect systems suitable for hybrid configurations. The NOC is also compatible with 2.5D and 3D die-to-die NOC bridging, providing comprehensive scalability for advanced semiconductor solutions.
The ePHY-5616 delivers data rates from 1 to 56Gbps across technology nodes of 16nm and 12nm. Designed for a diverse range of applications, this product offers superior BER and low latency, making it ideal for enterprise equipment like routers, switches, and network interface cards. The ePHY-5616 employs a highly configurable DSP-based receiver architecture designed to manage various insertion loss scenarios, from 10dB up to over 35dB. This ensures robust and reliable data transfer across multiple setups.
Dillon Engineering's 2D FFT core delivers robust performance for transforming two-dimensional data sets into the frequency domain with high precision and efficiency. By leveraging both internal and external memory between dual FFT engines, this core optimizes the data processing pipeline, ensuring fast and reliable results even as data complexity increases. Ideal for applications that handle image processing and data matrix transformations, the 2D FFT core navigates data bandwidth constraints with ease, maintaining throughput even for larger data sets. This core's design maximizes data accuracy and minimizes processing delays, crucial for applications requiring precise image recognition and analysis. Thanks to the adaptable nature provided by Dillon's ParaCore Architect, this IP core is easily customized for various FPGA and ASIC environments. Its flexibility and robust processing capabilities make the 2D FFT core a key component for cutting-edge applications in fields where data translation and processing are critical.
The Hyperspectral Imaging System by Imec enables detailed spectral imaging by capturing data across multiple wavelengths. This technology is pivotal for applications requiring precise material composition analysis and object identification, such as in agriculture and environmental monitoring. The system uses a compact and integrated design making it adaptable and efficient for various uses. Imec's hyperspectral imaging technology paves the way for advancements in remote sensing, where it can provide critical insights into land usage and resource management. Its high spectral resolution coupled with Imec's cutting-edge integration methods allows users to discern more nuanced differences in material compositions, fostering innovation across sectors. Engineered for flexibility, this imaging system boasts features that support rapid data analysis and integration into larger systems. Its robust design ensures it can withstand challenging operational conditions, making it a reliable choice for continuous and demanding applications.
The Ncore Cache Coherent Interconnect from Arteris provides a quintessential solution for handling multi-core SoC design complications, facilitating heterogeneous coherency and efficient caching. It is distinguished by its high throughput, ensuring reliable and high-performance system-on-chips (SoCs). Ncore's configurable fabric offers designers the ability to establish a multi-die, multi-protocol coherent interconnect where emerge cutting-edge technologies like RISC-V can seamlessly integrate. This IP’s adaptability and scalable design unlock broader performance trajectories, whether for small embedded systems or extensive multi-billion transistor architectures. Ncore's strength lies in its ability to offer ISO 26262 ASIL D readiness, enabling designers to adhere to stringent automotive safety standards. Furthermore, its coupling with Magillem™ automation enhances the potential for rapid IP integration, simplifying multi-die designs and compressing development timelines. In addressing modern computational demands, Ncore is reinforced by robust quality of service parameters, secure power management, and seamless integration capabilities, making it an imperative asset in constructing scalable system architectures. By streamlining memory operations and optimizing data flow, it provides bandwidth that supports both high-end automotive and complex consumer electronics, fostering innovation and market excellence.
Packetcraft's Bluetooth LE Audio Solutions offer a full suite of host, controller, and LC3 components optimized for seamless transition to Bluetooth LE Audio. The platform supports Auracast broadcast audio and True Wireless Stereo (TWS), making it adaptable to prevalent chipsets and providing flexibility to product companies. The modular design facilitates simplified integration, ensuring companies can leverage advanced audio capabilities in a variety of applications. As Bluetooth audio technology evolves, Packetcraft remains at the leading edge, offering industry-leading solutions that cater to modern audio requirements.
ISPido represents a fully configurable RTL Image Signal Processing Pipeline, adhering to the AMBA AXI4 standards and tailored through the AXI4-LITE protocol for seamless integration with systems such as RISC-V. This advanced pipeline supports a variety of image processing functions like defective pixel correction, color filter interpolation using the Malvar-Cutler algorithm, and auto-white balance, among others. Designed to handle resolutions up to 7680x7680, ISPido provides compatibility for both 4K and 8K video systems, with support for 8, 10, or 12-bit depth inputs. Each module within this pipeline can be fine-tuned to fit specific requirements, making it a versatile choice for adapting to various imaging needs. The architecture's compatibility with flexible standards ensures robust performance and adaptability in diverse applications, from consumer electronics to professional-grade imaging solutions. Through its compact design, ISPido optimizes area and energy efficiency, providing high-quality image processing while keeping hardware demands low. This makes it suitable for battery-operated devices where power efficiency is crucial, without sacrificing the processing power needed for high-resolution outputs.
FlexWay Interconnect is tailored for developers aiming to integrate scalable, low-power network-on-chip (NoC) solutions into IoT edge devices and microcontroller units (MCUs). It is celebrated for its adaptability in small to medium-scale designs, facilitating efficient interconnect setup with uncomplicated, cost-effective elements. Equipped to handle expansive bandwidth demands with limited power use, FlexWay capitalizes on Arteris’ advanced algorithms and graphical interfaces for optimal chip architecture design. By supporting multi-clock, voltage, and power domains with integrated clock gating, the IP maintains thorough power management across different configurations. It is engineered to easily adapt to various protocols, promising easy integration with existing systems without sacrificing performance. FlexWay’s intelligent design offers considerable flexibility, making it a prime choice for industries grappling with significant on-chip communication demands. By simplifying the design process and ensuring energy-efficient data management, this IP is integral for bringing cutting-edge IoT applications to fruition swiftly and cost-effectively.
Network on Chip (NOC-X) provides an advanced framework that orchestrates efficient communication across intricate semiconductor systems. It forms the backbone of complex data transfer within a chip or between chiplets, ensuring that the system's various components interact efficiently. The design of NOC-X prioritizes both power efficiency and high throughput, making it capable of meeting the demands of large-scale chip architectures. By embedding this technology, systems can enhance their computational ability while maintaining a balance in energy consumption, a critical factor in modern design. Its implementation facilitates improved system scalability and reliability. This makes NOC-X an essential feature in the development of cutting-edge semiconductor solutions, capable of sustaining advancements in processing capabilities and integrating seamlessly with other interconnect technologies.
aiSim 5 represents a leap forward in automotive simulation technology, underpinning the complex validation processes needed for modern autonomous driving systems. Certified to ISO26262 ASIL-D, this simulator is designed to handle the demanding requirements of advanced driver-assistance systems (ADAS) and autonomous driving technologies. By utilizing AI-driven digital twin creation and sophisticated sensor modeling, aiSim ensures high fidelity in simulations, enabling developers to conduct virtual tests across diverse scenarios that replicate real-world conditions. Featuring a physics-based rendering engine, aiSim allows for the precise simulation of varied environmental conditions like rain, fog, and sunshine, as well as complex sensor configurations. Its open architecture and modular design facilitate easy integration into existing development pipelines, ensuring compatibility with a wide range of testing and development frameworks. The simulator's deterministic simulation capabilities provide reliability and repeatability, which are crucial for validating safety-critical automotive functions. The robust architecture of aiSim extends its utility beyond basic simulations, offering tools such as aiFab for scenario randomization, which helps in exposing edge cases that may not be encountered in typical testing environments. Moreover, its ability to produce synthetic data for training improves the robustness of ADAS systems. With aiSim, the development cycle shortens significantly, allowing automotive manufacturers to bring innovative products to market more efficiently.
UTTUNGA is a high-performance PCIe accelerator card, purpose-built to amplify HPC and AI tasks through its integration with the TUNGA SoC. It effectively harnesses the power of multi-core RISC-V technology combined with Posit arithmetic, offering significant enhancements in computation efficiency and memory optimization. Designed to be compatible with a broad range of server architectures, including x86, ARM, and PowerPC, UTTUNGA elevates system capabilities, particularly in precision computing applications. The UTTUNGA card operates by implementing foundational arithmetic operations in Posit configurations, supporting multiple bit-width formats for diverse processing needs. This flexibility is further complemented by a pool of programmable FPGA gates, optimized for scenarios demanding real-time adaptability and cloud computing acceleration. These gates facilitate the acceleration of complex tasks and aid in the effortless management of non-standard data types essential for advanced AI processing and cryptographic applications. By leveraging a seamless integration process, UTTUNGA eliminates the need for data copying in host memory, thus ensuring efficient utilization of resources. It also provides support for well-known scientific libraries, enabling easy adoption for legacy systems while fostering a modern computing environment. UTTUNGA stands as a testament to the profound impact of advancing arithmetic standards like Posit, paving the way for a transformation in computational practices across industries.
Tensix Neo represents a transformative leap in enhancing AI computational efficiency, specifically designed to empower developers working on sophisticated AI networks and applications. Built around a Network-on-Chip (NoC) framework, Tensix Neo optimizes performance-per-watt, a critical factor for AI processing. It supports multiple precision formats to adapt to diverse AI workloads efficiently, allowing seamless integration with existing models and enabling scalability. Careful design ensures that Tensix Neo delivers consistent high performance across varied AI tasks, from image recognition algorithms to advanced analytics, making it an essential component in the AI development toolkit. Its capability to connect with an expanding library of AI models allows developers to leverage its full potential across multiple cutting-edge applications. This synthesis of performance and efficiency makes Tensix Neo a vital player in fields requiring high adaptability and rapid processing, such as autonomous vehicles, smart devices, and dynamic data centers. Moreover, the compatibility of Tensix Neo with Tenstorrent's other solutions underscores its importance as a flexible and powerful processing core. Designed with the contemporary developer in mind, Tensix Neo integrates seamlessly with open-source resources and tools, ensuring that developers have the support and flexibility needed to meet the challenges of tomorrow's AI solutions.
The BlueLynx Chiplet Interconnect is a sophisticated die-to-die interconnect solution that offers industry-leading performance and flexibility for both advanced and conventional packaging applications. As an adaptable subsystem, BlueLynx supports the integration of Universal Chiplet Interconnect Express (UCIe) as well as Bunch of Wires (BoW) standards, facilitating high bandwidth capabilities essential for contemporary chip designs.\n\nBlueLynx IP emphasizes seamless connectivity to on-die buses and network-on-chip (NoCs) using standards such as AMBA, AXI, and ACE among others, thereby accelerating the design process from system-on-chip (SoC) architectures to chiplet-based designs. This innovative approach not only allows for faster deployment but also mitigates development risks through a predictable and silicon-friendly design process with comprehensive support for rapid first-pass silicon success.\n\nWith BlueLynx, designers can take advantage of a highly optimized performance per watt, offering customizable configurations tailored to specific application needs across various markets like AI, high-performance computing, and mobile technologies. The IP is crafted to deliver outstanding bandwidth density and energy efficiency, bridging the requirements of advanced nodal technologies with compatibility across several foundries, ensuring extensive applicability and cost-effectiveness for diverse semiconductor solutions.
The UltraLong FFT core from Dillon Engineering offers exceptional performance for applications requiring extensive sequence lengths. This core utilizes external memory in coordination with dual FFT engines to facilitate high throughput. While it typically hinges on memory bandwidth for its speed, the UltraLong FFT effectively processes lengthy data sequences in a streamlined manner. This core is characterized by its medium to high-speed capabilities and is an excellent choice for applications where external memory can be leveraged to support processing requirements. Its architecture allows for flexible design implementation, ensuring seamless integration with existing systems, and is particularly well-suited for advanced signal processing applications in both FPGA and ASIC environments. With Dillon's ParaCore Architect tool, customization and re-targeting of the IP core towards any technology are straightforward, offering maximum adaptability. This FFT solution stands out for its capacity to manage complex data tasks, making it an ideal fit for cutting-edge technologies demanding extensive data length processing efficiency.
The NoC Bus Interconnect by OPENEDGES is a sophisticated solution for modern semiconductor designs, providing efficient on-chip communication. This network-on-chip (NoC) architecture facilitates communication between different IP blocks within a chip, significantly enhancing data flow and reducing bottlenecks compared to traditional bus systems. This interconnect solution is designed to provide high bandwidth and low latency, supporting various data transmission protocols. It's built to be highly scalable, accommodating growing demands in complex system-on-chip (SoC) designs. The flexibility in configuration allows it to support varied application needs, making it a versatile choice for high-performance computing, data centers, and AI applications. Besides its performance advantages, the NoC Bus Interconnect offers features that ensure optimal power management, which is crucial for maintaining efficiency in energy-sensitive applications. By intelligently managing data paths and utilizing advanced buffering techniques, it effectively minimizes power usage while maximizing throughput.
Our SoC Platform is designed to accelerate the development of custom silicon products. Built with domain-specific architecture, it provides rapid and streamlined SoC design using silicon-proven IPs. The platform offers lower costs and reduced risks associated with prototyping and manufacturing, ensuring a quicker turnaround. Users benefit from pre-configured and verified IP pools, enabling faster bring-up of hardware and software. Designed for flexible applications, it supports a range of use cases from AI inference to IoT, helping companies achieve up to 50% faster time-to-market compared to industry standards.
The Satellite Navigation SoC Integration offering by GNSS Sensor Ltd is a comprehensive solution designed to integrate sophisticated satellite navigation capabilities into System-on-Chip (SoC) architectures. It utilizes GNSS Sensor's proprietary VHDL library, which includes modules like the configurable GNSS engine, Fast Search Engine for satellite systems, and more, optimized for maximum CPU independence and flexibility. This SoC integration supports various satellite navigation systems like GPS, Glonass, and Galileo, with efficient hardware designs that allow it to process signals across multiple frequency bands. The solution emphasizes reduced development costs and streamlining the navigation module integration process. Leveraging FPGA platforms, GNSS Sensor's solution integrates intricate RF front-end components, allowing for a robust and adaptable GNSS receiver development. The system-on-chip solution ensures high performance, with features like firmware stored on ROM blocks, obviating the need for external memory.
Thermal oxide, often referred to as SiO2, is an essential film used in creating various semiconductor devices, ranging from simple to complex structures. This dielectric film is created by oxidizing silicon wafers under controlled conditions using high-purity, low-defect silicon substrates. This process produces a high-quality oxide layer that serves two main purposes: it acts as a field oxide to electrically insulate different layers, such as polysilicon or metal, from the silicon substrate, and as a gate oxide essential for device function. The thermal oxidation process occurs in furnaces set between 800°C to 1050°C. Utilizing high-purity steam and oxygen, the growth of thermal oxide is meticulously controlled, offering batch thickness uniformity of ±5% and within-wafer uniformity of ±3%. With different techniques used for growth, dry oxidation results in slower growth, higher density, and increased breakdown voltage, whereas wet oxidation allows faster growth, even at lower temperatures, facilitating the formation of thicker oxides. NanoSILICON, Inc. is equipped with state-of-the-art horizontal furnaces that manage such high-precision oxidation processes. These furnaces, due to their durable quartz construction, ensure stability and defect-free production. Additionally, the processing equipment, like the Nanometrics 210, inspects film thickness and uniformity using advanced optical reflection techniques, guaranteeing a high standard of production. With these capabilities, NanoSILICON Inc. supports a diverse range of wafer sizes and materials, ensuring superior quality oxide films that meet specific needs for your semiconductor designs.
The Complete 5G NR Physical Layer solution by AccelerComm is designed to provide exceptional performance for demanding applications in O-RAN and satellite networks. This all-encompassing solution integrates high-accuracy signal processing technology, ensuring optimal link performance and efficient power usage. The physical layer is inherently flexible, allowing performance optimizations tailored to meet specific requirements of specialized network applications. This solution navigates the complex real-world dynamics involved in high-performance network scenarios, including both terrestrial and space-based communications. By leveraging advanced algorithms and architectures, the 5G physical layer supports customizable configurations, leading to power and area efficiency improvements. Through interoperability with multiple hardware platforms, it maximizes the performance of 5G networks, enhancing the user experience by minimizing latency and maximizing throughput. Delivered as openly-licensable intellectual property, the 5G NR Physical Layer can function across a wide range of platforms, such as ARM software and FPGA, ensuring broad compatibility. This strategic approach facilitates quicker project advancements through seamless integration and testing processes on multiple development boards, thereby reducing project risks effectively.
The Pipelined FFT core by Dillon Engineering is engineered to support continuous data streams with its ranked pipelined architecture. This design accommodates efficient data processing with minimal memory requirement, making it an exceptional option for ongoing signal processing tasks requiring low latency. This architecture utilizes a single butterfly per rank, optimizing the processing capability for applications where minimal memory footprint and consistent throughput are paramount. The Pipelined FFT stands as a streamlined solution for real-time digital signal processing, ensuring data accuracy and swift computations without the need for significant storage or delay operations. Dillon's ParaCore Architect allows for seamless adaptation of this IP core across a wide range of hardware platforms, ensuring its applicability to both FPGA and ASIC designs. Its versatile nature accommodates rapid design shifts, making the Pipelined FFT a preferred choice for projects requiring quick and efficient data stream processing.
The FlexNoC Interconnect is engineered as a physically-aware network-on-chip (NoC) IP that serves as the backbone of semiconductor solutions in high-demand markets. It assists SoC developers in creating quick, reliable network setups with minimal power consumption. By incorporating top-grade algorithms and a user-friendly interface, FlexNoC facilitates flexible and efficient interconnect designs for both small and large-scale SoCs. Featuring robust support for comprehensive topologies, FlexNoC is highly advantageous in navigating the complexities of long interchip pathways using virtual channels and synchronous communications. It supports multi-channel memory such as HBMx, ensuring outstanding bandwidth and seamless off-chip memory access. The IP’s physical awareness advances timing closure processes and reduces interconnect area, contributing to reduced power usage and enhanced scalability. Designed for wide application across automotive, consumer electronics, and industrial sectors, FlexNoC offers standard protocol interoperability and advanced power management with state-of-the-art security measures. The IP’s ability to maintain high frequencies and lower latencies while ensuring compact die areas makes it indispensable for projects aiming for time-efficient delivery and market distinction.
IC Manage's IP Central Management System is an advanced platform designed to streamline the management of semiconductor IPs. This system is engineered to consolidate all IPs—both internal and external—into a comprehensive, searchable catalog, enhancing accessibility and security across a company's design teams. It addresses the complexities of IP reuse and integration, facilitating a more structured and efficient approach to leveraging IP assets. IP Central stands out by supporting seamless information dissemination and access control, crucial for optimizing design workflows and maximizing IP utility. It empowers organizations to effectively catalog their IP portfolios, integrating them into an enterprise-wide repository that is easily accessible yet tightly secure. This feature is particularly beneficial for design teams striving to balance diverse historical designs and methodologies in their projects. Moreover, the platform is instrumental in establishing a global IP catalog, a strategic advantage for companies looking to enhance the value of their IPs. By fostering a culture of organized and secure IP sharing, IP Central aids in reducing development time, costs while increasing reliability and design accuracy. This tool is a critical component for companies aiming to capitalize on their IP investments through improved management and deployment.
Specializing in Network-on-Chip (NoC)-based SoC integration, this IP leverages coherent and non-coherent NoC subsystems, crucial for building scalable multi-chip solutions. By integrating several NoC platforms, it offers a robust framework for developing SoCs with enhanced connectivity and performance.
The Xinglian-500, StarFive's pioneering interconnect fabric IP, integrates advanced design for enhancing system performance through consistency in memory access across multiple core CPUs. It's ideal for constructing multi-core CPUs and SoCs by offering cache coherence properties. This fabric IP is critical for maintaining system efficiency and scalability, supporting the development of complex and demanding SoC architectures.
ZIA SV represents a state-of-the-art stereo vision IP core geared towards precise distance measurement through stereo imaging, critical for applications involving autonomous navigation and distance sensing. By harnessing images from dual cameras, ZIA SV utilizes semi-global matching (SGM) algorithms to accurately estimate disparities and distances. The core is optimized through various pre- and post-processing techniques to enhance performance and precision. These processes include alignment, stereo rectification, sub-pixel interpolation, and disparity image denoising, ensuring unparalleled accuracy in distance estimation. Equipped with a scalable architecture, DMP’s ZIA SV supports integration with AMBA AXI4 interface, ensuring compatibility with numerous processor architectures. The versatility and precision of this IP make it suitable for use in robots and drones requiring advanced stereo vision capabilities.
iNoCulator is an innovative solution designed to expedite the development of flexible and configurable Network-on-Chips (NoCs). This comprehensive platform supports NoC creation from initial concepts to system architecture, culminating in RTL simulation, emulation, and implementation. Notable for its user-friendly editing tools, iNoCulator offers complete configuration flexibility and integrates fully with existing EDA environments. This makes it an ideal choice for designers needing seamless and efficient NoC development processes. Its adaptability not only enhances the speed and efficiency of SoC architectures but also significantly reduces time-to-market.
The Concrete Surface Layer Degradation Detection System is an advanced tool engineered to evaluate the integrity of concrete structures. Ideal for use in construction and civil engineering, this system offers precise monitoring capabilities for assessing the degradation levels of concrete surfaces. Through its use of state-of-the-art sensors and data processing algorithms, the system provides real-time insights into the structural health of buildings and infrastructure. By detecting early signs of degradation, it helps in planning maintenance and reducing potential repair costs.
Dillon Engineering's Mixed Radix FFT core stands out for its capacity to handle non-power-of-two FFT operations efficiently. Using combinations of radix-2, 3, 5, and 7, this IP core is tailored to optimize processing length flexibility, providing solutions for a broad array of applications and data sizes beyond typical limits. This core excels in delivering medium-speed performance with a balanced need for memory and logic resources. It is ideal for applications that require adaptable lengths and quick processing adaptation, particularly when constraints on traditional FFT lengths are present. By facilitating various configurations, the Mixed Radix FFT core ensures optimized performance across diverse FFT needs. With Dillon's ParaCore Architect enabling technology re-targeting and customization, this core is suitable for both FPGA and ASIC environments. It provides a formidable solution for advanced signal processing, offering enhanced flexibility and utility in tackling complex FFT requirements.
IC Manage offers the Envision Real-Time Analytics Platform as a cutting-edge tool for semiconductor companies looking to analyze design and verification progress. This platform provides visual insights on extensive data sets, leveraging big data technology to offer near-real-time reports that aid efficient decision-making processes. Envision's capabilities extend to tracking millions of data points across massive datasets, providing clear visibility into the design lifecycle's various stages. This comprehensive overview enables design teams to identify trends, predict performance issues, and optimize their workflows to ensure timely project completion. Its ability to analyze vast quantities of data and provide actionable insights is invaluable for companies focusing on efficient design verification. Moreover, the platform's advanced analytics improve collaboration by offering consistent, transparent, and up-to-date information to all stakeholders. It enhances the ability to respond swiftly to potential design challenges, reducing bottlenecks, increasing accuracy, and improving overall efficiency. These features make Envision a critical asset for companies aiming to remain at the forefront of technology innovation.
The IMG B-Series GPUs are designed to deliver scalability across various markets, from low-area set-top box solutions to high-performance desktop environments. This GPU series introduces innovative multi-core technology that enhances both performance and multitasking capabilities. Imagination's B-Series GPUs support advanced rendering techniques, providing high-quality graphics output suitable for a diverse range of consumer electronics and automotive applications, ensuring robust performance even under demanding conditions.
Dillon Engineering's Load Unload FFT core is designed to optimize input and output handling in FFT operations, allowing for efficient buffering and data arrangement. This core features a robust design that caters to both simple and complex data arrangements, facilitating streamlined FFT processes by managing data in natural order without the additional complexity of shuffling. It boasts fast data handling capabilities, making it ideal for environments that require swift data throughput alongside FFT processing. The Load Unload FFT is particularly effective in situations where consistent high-speed performance is necessary, aiding in reducing bottlenecks during data-intensive operations. Adaptable to various FPGA and ASIC technologies through Dillon's state-of-the-art ParaCore Architect, this core integrates effortlessly into existing systems, offering a customizable approach to data handling in FFT pipelines. By ensuring efficient data management, Dillon's Load Unload FFT contributes to enhancing overall system efficiency and robustness.
The 40G MAC/PCS ULL serves as an ultra-low latency IP core that extends the capabilities of traditional FPGA applications by offering substantial data throughput improvements. It focuses on maintaining low-latency characteristics crucial for high-speed data environments, particularly suited for competitive financial market engagements. Built around a 40G MAC/PCS framework, this product ensures swift data transitions across 40 Gigabit Ethernet, optimizing the path for data flow and reducing time delay significantly. The architecture supports critical data processing tasks, providing users with an advanced tool for maintaining competitive edges in rapid market fluctuations. The 40G MAC/PCS ULL is embedded as part of the nxFramework, enabling seamless integration with Enyx’s range of FPGA development tools. This IP core empowers financial institutions to leverage high-speed trading capabilities, ensuring that their processing frameworks meet the rigorous demands of contemporary trading environments.
The LDACS-1 and LDACS-2 Physical Layer IPs are designed to offer robust solutions for communication systems. Leveraging the power of MATLAB for initial design and simulation, these IPs can be seamlessly converted into Verilog as per project demands. Their flexibility allows for adaptation to various requirements, ensuring they can address differing specifications for telecommunications projects effectively. These IP cores serve as an essential component for developers leveraging advanced algorithmic designs in FPGA environments. By providing a comprehensive solution for the physical layer operations of L-band Digital Aeronautical Communication Systems (LDACS), these cores facilitate a transition toward more efficient and reliable communication systems. Their implementation supports real-time processing capabilities essential for aeronautical communication, ensuring enhanced performance and reliability. Moreover, the adaptability of these IPs makes them a preferred choice for those needing tailor-made solutions in the aeronautical comms field. Developers benefit from the cores' optimized resource utilization, which ensures they can efficiently manage power and processing loads while maintaining high standards of communication integrity and throughput.
The Parallel FFT core from Dillon Engineering exemplifies high-speed data processing with its dual-core design, enabling simultaneous FFT computations. By utilizing two distinct FFT cores aligned in series, this architecture enhances processing speed and efficiency through the management of shuffle memory situated between the cores. Uniquely suited for applications demanding rapid data analysis and processing, Parallel FFT leverages advanced input/output buffering to maintain order and efficiency in data throughput. The architecture extends practical data lengths significantly, supporting up to 2K or 4K points, thus amplifying its utility in high-performance environments. With the adaptability to various technologies provided by Dillon's ParaCore Architect, this core ensures seamless integration into both FPGA and ASIC designs. It simplifies the design process by allowing for immediate reconfiguration to meet specific technological demands, fostering a versatile solution for enhanced data processing requirements.
The Xinglian-700 is a highly scalable and efficient interconnect fabric IP developed by StarFive that offers excellent support for building expansive CPU and SoC architectures. Its design ensures memory consistency and offers high performance, making it suitable for sophisticated multi-core and SoC designs. This interconnect fabric is engineered to accommodate and synchronize a wide array of CPU cores, providing high-level integration solutions for modern electronic systems.
The 5G ORAN Base Station is set to transform mobile networking by significantly enhancing wireless data capacity and opening up new opportunities for innovative wireless applications. This technology promises to exceed previous limitations by supporting a vast amount of data through increased efficiency, facilitating the expansion of wireless connectivity solutions in diverse environments. With its capability to handle high-speed data transmissions efficiently, the 5G ORAN Base Station is particularly suitable for industries seeking to leverage wireless technology for expansive, high-demand applications. It supports the integration of various critical infrastructure components, ensuring consistent and reliable performance in real-time data processing situations. This base station's architecture also supports future enhancements and scalability in evolving network environments. Primarily used in applications that require large-scale data transmission and robust connectivity, the 5G ORAN Base Station is ideal for industries ranging from telecommunications to advanced data analytics. Its adaptability allows it to cater to specific needs in any given environment, making it a versatile solution for modern wireless communication challenges.
The 10G MAC/PCS ULL is a specialized ultra-low latency IP core specifically designed for high-performance FPGA applications. This core is optimized for providing rapid data throughput with minimal latency, characteristics highly sought in environments where timing is critical, such as financial trading systems. Featuring a 10G MAC/PCS architecture, this product is essential for applications needing high-speed data transfer and processing, ensuring minimal delay between input and output signals. The design is carefully crafted to deliver robust functionality over a 10 Gigabit Ethernet, maintaining integrity and reliability throughout its operations. This IP core is exclusive to the nxFramework, allowing users to exploit these tools to build advanced trading solutions. The application of the 10G MAC/PCS ULL in FPGA development enables users to achieve superior performance metrics, crucial for high-frequency trading solutions that demand immediate data processing and transmission capabilities.
Semidynamics offers the Atrevido core, a cutting-edge 64-bit RISC-V processor designed for high-performance computing environments. The core supports out-of-order execution, enhancing processing efficiency by allowing multiple instructions to be executed simultaneously. This flexibility enables the Atrevido processor to excel in demanding AI and HPC applications, providing an efficient solution for tasks such as inference, key-value stores, and sparse data processing. An integral feature of the Atrevido core is its support for vector and tensor capabilities. These units are seamlessly integrated within the core to provide scalable AI acceleration without incurring latency penalties. This makes the Atrevido core an optimal choice for industries looking to incorporate AI workloads seamlessly into their computing systems. The Atrevido core also benefits from the Gazzillion Misses™ technology, which improves memory access performance by handling a high number of simultaneous memory requests, reducing bottlenecks. Compatibility with AXI and CHI interfaces further enhances its utility in multiprocessor configurations, making it a robust, versatile option for advanced computing needs.
The Stellar Packet Classification Platform is specifically designed for ultra-high-speed search performance within FPGA environments. It manages lookup operations using complex Access Control List (ACL) and Longest Prefix Match (LPM) rules, making it an ideal solution for scenarios requiring rigorous data filtering and sorting. This platform enables hundreds of millions of lookup operations per second, adaptable to data rates stretching from 25Gbps to over 1Tbps, handling millions of intricate rules with the capacity for live updates. This scalability ensures that the platform can meet the needs of current and future network enhancements, especially as demand for high reliability and speed grows. Feature-rich, the Stellar platform facilitates extensive key matching, allowing up to 480-bit keys to be processed, ensuring effective handling of vast knowledge sets in high-speed environments. It supports functions critical to maintaining robust and efficient data routing and security protocols, helping to safeguard infrastructures from threats and optimizing data packet handling. Perfect for applications that demand precise data routing and protection, such as IPv4/6 address lookups, network firewalls, and anti-DDoS measures. The Stellar Platform's adaptability makes it a preferred choice for emerging technologies and capabilities in evolving network setups like 5G networks and beyond.
Channel Sounding is the latest advancement in Bluetooth technology, offering high-precision distance measurement and location capabilities. This innovative technology provides a wide range of applications and competitive use cases, suited for environments requiring accurate spatial awareness. With Channel Sounding, users can achieve enhanced accuracy in measuring distances, making it ideal for automotive, industrial, and consumer electronics applications. Available as part of Packetcraft's suite, this solution represents the future of Bluetooth’s role in distance-based measurement technologies.
Akeana’s Processor System combines a rich suite of component IP blocks into a comprehensive solution aimed at streamlining processor system development. This includes enhanced IP modules such as compute coherence blocks, interrupt controllers, input-output memory management units (IOMMU), and interconnect fabrics that support both coherent and non-coherent communication. The system IP provides a flexible and scalable solution for integrating varied processing cores, ensuring optimal performance and reliability. It supports sophisticated system design, allowing the assembly of customized solutions that align with specific application requirements. This is particularly valuable for developers seeking effective system integration strategies. Enhanced by compatibility with industry standard interfaces, Akeana’s Processor System facilitates seamless connection and expansion options, highlighting the company’s focus on providing full-stack solutions. With this level of integration and support, developers can achieve faster deployment and reduced project risks, thereby gaining a competitive edge in dynamic technology markets.
Truechip’s NoC Crossbar Silicon IP is designed to support diverse protocols at both the master and slave port interfaces while offering physical address conversion across the network-on-chip (NoC). This sophisticated IP accommodates phase-shifted frequencies specifically tailored for each master and slave port, thereby optimizing data transfer efficiency and system synchronization. It offers a plethora of configurability options, including programmable registers and port priority adjustments, providing tailored solutions for complex systems. The NoC Crossbar Silicon IP integrates seamlessly into an array of industry-standard bus protocols, including ARM AHB and AXI, SiFive TileLink, among others, ensuring compatibility with custom configurations tailored to specific application needs. Its design leverages a robust and customizable architecture, allowing easy scalability and adaptability to evolving project demands. Localization of access type configurations enhances security and privilege management across slave ports, ensuring reliable and secure data transactions.
The NC-NoC offers an advanced, configurable NoC solution that is both scalable and physically aware. It is designed to accommodate multiple clocking schemes, making it suitable for a wide range of applications not requiring coherency. This solution is compatible with various protocols such as AXI4/3, AHB, APB, and AXI-lite, with bus widths ranging from 32 to 2048 bits. Its layered architecture facilitates seamless integration into diverse SoC environments, providing a robust framework for efficient data routing and high system performance. The NC-NoC stands out for its capacity to support complex, multi-protocol operations, delivering reliable and high-speed interconnectivity within SoCs.
FlexGen represents the pinnacle of smart NoC IP design, crafted with an advanced AI-driven framework that automates topology generation, optimizing SoC design processes. By harnessing machine learning, FlexGen drastically enhances productivity, providing a tenfold increase in NoC design efficiency over traditional methods. The IP significantly reduces latency and minimizes power consumption through intelligent wire length reduction. FlexGen’s applicability spans across the automotive, data center, and industrial electronics sectors, cementing its role in accelerating the time-to-market for complex systems-on-chip. Its sophisticated architecture empowers designers with expert-level outcomes while cutting down manual intervention, allowing comprehensive exploration of design alternatives within shorter timelines. Embedded with efficient routing algorithms, FlexGen curtails congestion, fostering improved silicon area during physical design phases. This IP not only excels in adaptive design by offering up to 30% reduction in wire lengths, but also integrates systematically with other IPs for coherent and non-coherent procedures. Designers benefit from enhanced transport of data within SoCs, making FlexGen a cornerstone for ventures aiming to amalgamate performance with efficiency.
The 32G UCIe PHY from GUC is tailored to support high-speed universal chiplet interconnect express protocols. This IP is designed to meet the demanding needs of high-throughput, low-latency communication within and across chips, forming a backbone for next-generation semiconductor infrastructures. With its robust architecture, it ensures seamless data flow, critical for applications in AI, data analytics, and high-performance computing. Built to optimize system performance, the 32G UCIe PHY boosts connectivity between integrated circuits, enhancing system bandwidth and reducing power consumption. This high-speed interface facilitates rapid prototyping and integration in hyper-connected environments, paving the way for advancements in semiconductor technologies. Its advanced design minimizes electromagnetic interference, ensuring data integrity and communication stability. GUC's 32G UCIe PHY is compatible with cutting-edge process nodes, enabling developers to harness its potential across various applications. By providing high-speed data channels, it becomes integral to fostering innovation and supporting the dynamic needs of modern computing and networking solutions.
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