All IPs > Graphic & Peripheral
Graphic & Peripheral Semiconductor IPs are critical components in the design and development of electronics that require efficient and robust control over multimedia and peripheral functions. This category of semiconductor IP encompasses a wide array of technologies used to manage and optimize graphics rendering, audio processing, data communication, and peripheral interfaces in electronic devices such as computers, smartphones, tablets, and other smart gadgets.
In this vivid category, you'll find a variety of subcategories tailored to specific functionalities. For instance, the Graphics Processing Unit (GPU) semiconductor IPs are pivotal for rendering images and video, essential in gaming, virtual reality, and professional content creation. Audio Controllers handle sound processing, ensuring crisp and seamless audio output, crucial for devices prioritizing high-quality sound delivery.
Other key components in the Graphic & Peripheral category include Peripheral Controllers, which facilitate the integration of various input/output devices, enhancing the device's interactivity and user experience. DMA Controllers are responsible for moving data efficiently between memory and peripherals, minimizing the CPU load. These IPs enhance overall system performance by ensuring that data flow is smooth and uninterrupted.
From Clock Generators that synchronize the entire system's operations to Interrupt Controllers managing priority tasks, each semiconductor IP in this category plays a unique role in ensuring that electronic devices operate at peak efficiency. By exploring these subcategories, companies and developers can find the precise semiconductors needed to support cutting-edge multimedia and peripheral technologies in their next product launch.
The KL730 AI SoC is a state-of-the-art chip incorporating Kneron's third-generation reconfigurable NPU architecture, delivering unmatched computational power with capabilities reaching up to 8 TOPS. This chip's architecture is optimized for the latest CNN network models and performs exceptionally well in transformer-based applications, reducing DDR bandwidth requirements substantially. Furthermore, it supports advanced video processing functions, capable of handling 4K 60FPS outputs with superior image handling features like noise reduction and wide dynamic range support. Applications can range from intelligent security systems to autonomous vehicles and commercial robotics.
Overview: The UCIe IP supports multiple protocols (CXL/PCIe/Streaming) to connect chiplets, reducing overall development cycles for IPs and SOCs. With flexible application and PHY interfaces, The UCIe IP is ideal for SOCs and chiplets. Key Features:  Supports UCIe 1.0 Specification  Supports CXL 2.0 and CXL 3.0 Specifications  Supports PCIe Gen6 Specification  Supports PCIe Gen5 and older versions of PCIe specifications  Supports single and two-stack modules  Supports CXL 2.0 68Byte flit mode with Fallback mode for PCIe non-flit mode transfers  Supports CXL 3.0 256Byte flit mode  Supports PCIe Gen6 flit mode  Configurable up to 64-lane configuration for Advanced UCIe modules and 16 lanes for Standard UCIe modules  Supports sideband and Mainband signals  Supports Lane repair handling  Data to clock point training and eye width sweep support from transmitter and receiver ends  UCIe controller can work as Downstream or Upstream  Main Band Lane reversal supported  Dynamic sense of normal and redundant clock and data lines activation  UCIe enumeration through DVSEC  Error logging and reporting supported  Error injection supported through Register programming  RDI/FDI PM entry, Exit, Abort flows supported  Dynamic clock gang at adapter supported Configurable Options:  Maximum link width (x1, x2, x4, x8, x16)  MPS (128B to 4KB)  MRRS (128B to 4KB)  Transmit retry/Receive buffer size  Number of Virtual Channels  L1 PM substate support  Optional Capability Features can be Configured  Number of PF/VFDMA configurable Options  AXI MAX payload size Variations  Multiple CPI Interfaces (Configurable)  Cache/memory configurable  Type 0/1/2 device configurable
Overview: The Expanded Serial Peripheral Interface (xSPI) Master/Slave controller offers high data throughput, low signal count, and limited backward compatibility with legacy SPI devices. It is designed to connect xSPI Master/Slave devices in computing, automotive, Internet of Things, embedded systems, and mobile processors to various peripherals such as non-volatile memories, graphics peripherals, networking devices, FPGAs, and sensor devices. Key Features:  Compliance with JEDEC standard JESD251 eXpanded SPI for Non-Volatile Memory Devices, Version 1.0  Support for Single master and multiple slaves per interface port  Single Data Rate (SDR) and Double Data Rate (DDR) support  Source synchronous clocking  Deep Power Down (DPD) enter and exit commands  Eight IO ports in standard, expandable based on system requirements  Optional Data Strobe (DS) for write masking  bit wide SDR transfer support  Profile 1.0 Commands for non-volatile memory device management  Profile 2.0 Commands for read or write data for various slave devices Applications:  Consumer Electronics  Defense & Aerospace  Virtual Reality  Augmented Reality  Medical  Biometrics  Automotive Devices  Sensor Devices
Our Expanded Serial Peripheral Interface (JESD251) Master controller features a low signal count and high data bandwidth, making it ideal for use in computing, automotive, Internet of Things, embedded systems, and mobile system processors. It connects multiple sources of Serial Peripheral Interface (xSPI) slave devices, including nonvolatile memories, graphics peripherals, networking peripherals, FPGAs, and sensor devices. Features • Compliant with JEDEC standard JESD251 expanded Serial Peripheral Interface (xSPI) for Non-Volatile Memory Devices, Version 1.0. • Supports a single master and multiple slaves per interface port. • Supports Single Data Rate and Double Data Rate. • Supports source synchronous clocking. • Supports data transfer rates up to: o 400MT/s (200MHz Clock) o 333MT/s (167MHz Clock) o 266MT/s (133MHz Clock) o 200MT/s (100MHz Clock) • Supports Deep Power Down (DPD) enter and exit commands. • Standard support for eight IO ports, with the possibility to increase IO ports based on system performance requirements. • Optional support for Data Strobe (DS) for writemasking. • Supports 1-bit wide SDR transfer. • Supports Profile 1.0 commands to manage nonvolatile memory devices. • Supports Profile 2.0 commands to read or writedata for any type of slave device. • Compatible with non-volatile memory arrays such as NOR Flash, NAND Flash, FRAM, and nvSRAM. • Compatible with volatile memory arrays such as SRAM, PSRAM, and DRAM. • Supports register-mapped input/output functions. • Supports programmable function devices such as FPGAs. Application • Consumer Electronics. • Defence & Aerospace. • Virtual Reality. • Augmented Reality. • Medical. • Biometrics (Fingerprints, etc). • Automotive Devices. • Sensor Devices. Deliverables • Verilog Source code. • User Guide. • IP Integration Guide. • Run and Synthesis script. • Encrypted Verification Testbench Environment. • Basic Test-suite.
The ADQ35 digitizer is designed for high-throughput applications, featuring a dual-channel configuration capable of achieving a sampling rate up to 10 GSPS. This 12-bit digitizer is tailored for applications that require simultaneous data streams and efficient high-speed data transfer, making it ideal for use in advanced signal analysis.
Overview: The Multi-Protocol Accelerator IP is a versatile technology designed to support low latency and high bandwidth accelerators for efficient CPU-to-device and CPU-to-memory communication. It also enables switching for fan-out to connect more devices, memory pooling for increased memory utilization efficiency, and provides memory capacity with support for hot-plug, security enhancements, persistent memory support, and memory error reporting. Key Features:  CXL 3.0 Support: Compliant with CXL spec V3.X/V2.X  PCIe Compatibility: Supports PCIe spec 6.0/5.0  CPI Interface: Support for CPI Interface  AXI Interface: Configurable AXI master, AXI slave  Bus Support: PIPE/FLEX bus, Lane x1,x2,x4,x8,x16  Protocol Support: Gen3, Gen4, Gen5 & Gen6, Fallback Mode  Register Checks: Configuration and Memory Mapped registers  Dual Mode: Supports Dual Mode operation  Transfer Support: HBR/PBR & LOpt Transfers, Standard Cache and Mem Transfers  CXL Support: Can function as both CXL host and device  Data Transfer: Supports Standard IO, 68Byte Flit, and 256Byte Flit Transfers  FlexBus Features: FlexBus Link Features, ARB/MUX, ARB/MUX Bypass  Optimization: Latency Optimization, Credit Return Forcing, Empty Flits (Latency Optimized)  Power Management: Supports Power Management features  Enhancements: CXL IDE, RAS Features, Poison & Viral Handling, MLD/SLD  Testing: Compliance Testing and Error Scenarios support
Our Expanded Serial Peripheral Interface (JESD251) Slave controller offers high data throughput, low signal count, and limited backward compatibility with legacy Serial Peripheral Interface (SPI) devices. It is used to connect xSPI Master devices in computing, automotive, Internet of Things, embedded systems, and mobile system processors to non-volatile memories, graphics peripherals, networking peripherals, FPGAs, and sensor devices. Features • Compliant with JEDEC standard JESD251 expanded Serial Peripheral Interface (xSPI) for Non-Volatile Memory Devices, Version 1.0. • Supports Single Data Rate (SDR) and Double Data Rate (DDR). • Supports source synchronous clocking. • Supports data transfer rates up to: o 400MT/s (200MHz Clock) o 333MT/s (167MHz Clock) o 266MT/s (133MHz Clock) o 200MT/s (100MHz Clock) • Supports Deep Power Down (DPD) enter and exit commands. • Standard support for eight IO ports, with the possibility to increase IO ports based on system performance requirements. • Optional support for Data Strobe (DS) for timing reference. • Supports 1-bit wide SDR transfer. • Supports Profile 1.0 commands to manage nonvolatile memory devices. • Supports Profile 2.0 commands for reading or writing data for any type of slave device. • Compatible with non-volatile memory arrays such as NOR Flash, NAND Flash, FRAM, and nvSRAM. • Compatible with volatile memory arrays such as SRAM, PSRAM, and DRAM. • Supports register-mapped input/output functions. • Supports programmable function devices such as FPGAs. Application • Consumer Electronics. • Defence & Aerospace. • Virtual Reality. • Augmented Reality. • Medical. • Biometrics (Fingerprints, etc). • Automotive Devices. • Sensor Devices. Deliverables • Verilog Source code. • User Guide. • IP Integration Guide. • Run and Synthesis script. • Encrypted Verification Testbench Environment. • Basic Test-suite.
Overview: PCIe Gen6 is a high-speed, layered protocol interconnect interface supporting speeds up to 64GT/s, featuring multi-lanes and links. The Transport, Data Link, and Physical layers specified in the PCIe specification are implemented, along with PIPE interface logic connecting to PHY and AXI Bridging logic for application connectivity. Specifications:  Supports PCIe Gen 6 and Pipe 5.X Specifications  Core supports Flit and non-Flit Mode  Lane Configurations: X16, X8, X4, X2, X1  AXI MM and Streaming supported  Supports Gen1 to Gen6 modes  Data rate support of 2.5 GT/s, 5 GT/s, 8 GT/s, 16 GT/s, 32 GT/s, 64 GT/s  PAM support when operating at 64GT/s  Encoding/Decoding Support: 8b/10b, 128b/130b, 1b/1b  Supports SerDes and non-SerDes architecture  Optional DMA support as plugin module  Support for alternate negotiation protocol  Can operate as an endpoint or root complex  Lane polarity control through register  Lane de-skew supported  Support for L1 states and L0P  Support for SKP OS add/removal and SRIS mode  No equalization support through configuration  Deemphasis negotiation support at 5GT/s  Supports EI inferences in all modes  Supports PTM, OBFF, MSI, MSIX, Power management, and all message formats
Silicon Creations delivers precision LC-PLLs designed for ultra-low jitter applications requiring high-end performance. These LC-tank PLLs are equipped with advanced digital architectures supporting wide frequency tuning capabilities, primarily suited for converter and PHY applications. They ensure exceptional jitter performance, maintaining values well below 300fs RMS. The LC-PLLs from Silicon Creations are characterized by their capacity to handle fractional-N operations, with active noise cancellation features allowing for clean signal synthesis free of unwanted spurs. This architecture leads to significant power efficiencies, with some IPs consuming less than 10mW. Their low footprint and high frequency integrative capabilities enable seamless deployments across various chip designs, creating a perfect balance between performance and size. Particular strength lies in these PLLs' ability to meet stringent PCIe6 reference clocking requirements. With programmable loop bandwidth and an impressive tuning range, they offer designers a powerful toolset for achieving precise signal control within cramped system on chip environments. These products highlight Silicon Creations’ commitment to providing industry-leading performance and reliability in semiconductor design.
Silicon Creations' Free Running Oscillators provide dependable timing solutions for a range of applications such as watchdog timers and core clock generators in low-power systems. These oscillators, crafted with compactness and efficiency in mind, support a gamut of processes from 65nm to the latest 3nm technologies. These oscillators excel in low power consumption, often requiring less than 30µW during operation. Their robust design ensures they deliver high precision over a temperature range from -40°C to 125°C with supply voltage variabilities factored in. The simplicity in design negates the need for external components, promoting easier integration and reduced overall system complexity. Precise tuning capabilities allow for accuracy levels up to ±1.5% after process trimming, ensuring outstanding performance in volatile environmental conditions. This level of reliability makes them ideal for integration into various consumer electronics, automotive controls, and other precision-demanding applications where space and power constraints are critical.
eSi-Connect delivers a comprehensive suite of AMBA-compliant peripheral IPs, designed to streamline connectivity in SoC designs. This suite includes a range of interface controllers, memory controllers, and standard I/O components like UART, SPI, I2C, and much more. Designed with integration flexibility in mind, these components utilize the AMBA AXI, AHB, and APB protocols to ensure seamless communication across different modules within a chip. Each peripheral is equipped with low-level software drivers, enhancing their deployment in real-time environments and alleviating integration and development burdens from engineers.
The AI Camera Module from Altek Corporation is a testament to their prowess in integrating complex imaging technologies. With substantial expertise in lens design and an adeptness for soft-hard integration capabilities, Altek partners with top global brands to supply a variety of AI-driven cameras. These cameras meet diverse customer demands in AI+IoT differentiation, edge computing, and high-resolution image requisites of 2K to 4K quality. This module's ability to seamlessly engage with the latest AI algorithms makes it ideal for smart environments requiring real-time data analysis and decision-making capabilities.
Silicon Creations' Analog Glue solutions provide essential analog functionalities to complete custom SoC designs seamlessly. These functional blocks, which constitute buffer and bandgap reference circuits, are vital for seamless on-chip clock distribution and ensure low-jitter operations. Analog Glue includes crucial components such as power-on reset (POR) generators and bridging circuits to support various protocols and interfaces within SoCs. These supplementary macros are crafted to complement existing PLLs and facilities like SerDes, securing reliable signal transmission under varied operating circumstances. Serving as the unsung heroes of chip integration, these Analog Glue functions mitigate the inevitable risks of complex SoC designs, supporting efficient design flows and effective population of chip real estate. Thus, by emphasizing critical system coherency, they enhance overall component functionality, providing a stable infrastructure upon which additional system insights can be leveraged.
RaiderChip's GenAI v1 is a pioneering hardware-based generative AI accelerator, designed to perform local inference at the Edge. This technology integrates optimally with on-premises servers and embedded devices, offering substantial benefits in privacy, performance, and energy efficiency over traditional hybrid AI solutions. The design of the GenAI v1 NPU streamlines the process of executing large language models by embedding them directly onto the hardware, eliminating the need for external components like CPUs or internet connections. With its ability to support complex models such as the Llama 3.2 with 4-bit quantization on LPDDR4 memory, the GenAI v1 achieves unprecedented efficiency in AI token processing, coupled with energy savings and reduced latency. What sets GenAI v1 apart is its scalability and cost-effectiveness, significantly outperforming competitive solutions such as Intel Gaudi 2, Nvidia's cloud GPUs, and Google's cloud TPUs in terms of memory efficiency. This solution maximizes the number of tokens generated per unit of memory bandwidth, thus addressing one of the primary limitations in generative AI workflow. Furthermore, the adept memory usage of GenAI v1 reduces the dependency on costly memory types like HBM, opening the door to more affordable alternatives without diminishing processing capabilities. With a target-agnostic approach, RaiderChip ensures the GenAI v1 can be adapted to various FPGAs and ASICs, offering configuration flexibility that allows users to balance performance with hardware costs. Its compatibility with a wide range of transformers-based models, including proprietary modifications, ensures GenAI v1's robust placement across sectors requiring high-speed processing, like finance, medical diagnostics, and autonomous systems. RaiderChip's innovation with GenAI v1 focuses on supporting both vanilla and quantized AI models, ensuring high computation speeds necessary for real-time applications without compromising accuracy. This capability underpins their strategic vision of enabling versatile and sustainable AI solutions across industries. By prioritizing integration ease and operational independence, RaiderChip provides a tangible edge in applying generative AI effectively and widely.
The Mixed-Signal CODEC by Archband integrates advanced audio and voice processing capabilities, designed to deliver high-fidelity sound in a compact form. This technology supports applications across various audio devices, ensuring quality performance even at low power consumption levels. With its ability to handle both mono and stereo channels, it is perfectly suited for modern audio systems.
The AHB-Lite Multilayer Switch by Roa Logic is engineered to provide a high-performance, low-latency interconnect fabric for systems employing numerous AHB-Lite bus masters and slaves. This IP core enables configurations that support virtually unlimited bus connections, facilitated by slave-side arbitration for each slave port, thereby eliminating the need for individual bus masters to implement arbitration logic. A standout feature of this switch is its use of priority and round-robin based arbitration methods to efficiently manage multiple bus requests. Typically achieving arbitration within a single clock cycle, this design ensures minimal delay in data transfer across the network, promoting seamless communication in complex systems. With a fully parameterized architecture, it allows for the customization of bus interfaces to meet specific design needs, ensuring compatibility and optimal performance across varied configurations. Complete source code and comprehensive documentation are made available through Roa Logic’s GitHub repository, providing developers with the resources needed for successful integration and deployment.
The AHB-Lite Timer from Roa Logic is a versatile and fully parameterized soft IP designed to implement multiple timers as per the specifications laid out in the RISC-V Privileged 1.9.1 specification. This timer core interfaces through a well-compliant AHB-Lite Slave interface, allowing seamless integration into systems requiring precise timing functionalities. Offering extensive configurability, the IP allows users to define the number of timers, address and data widths, as well as the time base, which is derived from the AHB-Lite bus clock, scaled down according to programmable values. This flexibility supports a range of applications requiring accurate time tracking. Ideal for various embedded applications where timing precision is paramount, the AHB-Lite Timer features a single interrupt output that triggers when any enabled timer is activated. Developers can access detailed resources including source code and documentation from Roa Logic’s GitHub repository, ensuring an easy setup and integration process.
As the SoC that placed Kneron on the map, the KL520 AI SoC continues to enable sophisticated edge AI processing. It integrates dual ARM Cortex M4 CPUs, ideally serving as an AI co-processor for products like smart home systems and electronic devices. It supports an array of 3D sensor technologies including structured light and time-of-flight cameras, which broadens its application in devices striving for autonomous functionalities. Particularly noteworthy is its ability to maximize power savings, making it feasible to power some devices on low-voltage battery setups for extended operational periods. This combination of size and power efficiency has seen the chip integrated into numerous consumer product lines.
The Ring PLLs offered by Silicon Creations illustrate a versatile clocking solution, well-suited for numerous frequency generation tasks within integrated circuit designs. Known for their general-purpose and specialized applications, these PLLs are crafted to serve a massive array of industries. Their high configurability makes them applicable for diverse synthesis needs, acting as the backbone for multiple clocking strategies across different environments. Silicon Creations' Ring PLLs epitomize high integration with functions tailored for low jitter and precision clock generation, suitable for battery-operated devices and systems demanding high accuracy. Applications span from general clocking to precise Audio Codecs and SerDes configurations requiring dedicated performance metrics. The Ring PLL architecture achieves best-in-class long-term and period jitter performance with both integer and fractional modes available. Designed to support high volumes of frequencies with minimal footprint, these PLLs aid in efficient space allocation within system designs. Their use of silicon-proven architectures and modern validation methodologies assure customers of high reliability and quick integration into existing SoC designs, emphasizing low risk and high reward configurations.
The GH310 is specialized GPU IP tailored for 2D sprite graphics with an emphasis on high pixel processing capabilities. It achieves minimal gate count, ensuring it occupies less silicon area while delivering robust graphic outputs. Designed to handle large volumes of sprite graphics efficiently, the GH310 is perfect for applications requiring rapid rendering and minimal hardware overhead. This makes it favorable for systems where space and power savings are crucial yet high-quality graphics are needed. Its architecture allows for optimized performance tailored for specific graphical needs, translating into a resource-efficient solution for developers seeking to integrate intricate graphical features in their products without excessive resource consumption.
Silicon Creations crafts highly reliable LVDS interfaces designed to meet diverse application needs, going from bi-directional I/Os to specialized uni-directional configurations. Spanning process compatibilities from 90nm CMOS to advanced 7nm FinFET, these interfaces are a cornerstone for high-speed data communication systems, thriving particularly in video data transmission and chip-to-chip communications. Supporting robust data rates over multiple channels, the LVDS Interfaces guarantee flexible programmability and protocol compatibility with standards such as FPD-Link and Camera-Link. They capitalize on proven PLL and CDR architectures for superior signal integrity and error-free data transfers. Operating efficiently in various technology nodes, they remain highly effective across collaborative chipset environments. The interfaces are fortified with adaptable features like dynamic phase alignment to stabilize data sequences and on-die termination options for superior signal integrity. Their proven record places them as a critical enabler in applications where consistent high-speed data transfer is paramount, demonstrating Silicon Creations’ prowess in delivering industry-leading communication solutions.
Archband's PDM-to-PCM Converter is a versatile module designed to facilitate digital audio transformation. By converting Pulse Density Modulated audio signals into Pulse Code Modulated signals, this converter enhances audio clarity and fidelity in modern digital interfaces. It suits applications where efficient data streaming and noise reduction are critical, such as in high-quality audio devices and communications technology.
The Ethernet Real-Time Publish-Subscribe (RTPS) IP Core provides an all-encompassing solution for Ethernet-based RTPS protocols, ensuring efficient network data management and publication in real-time systems. This IP core supports crucial applications in environments where time-sensitive communication is paramount. Ideal for industrial and aerospace settings, the core manages data transactions with precision, leveraging real-time processing and minimal latency to ensure seamless data exchange. By facilitating controlled and secure communication network streams, the core optimally handles various multi-subscriber environments. With its highly dependable architecture, the RTPS IP Core integrates easily into existing systems, providing scalability and adaptability for evolving network requirements. This capability makes it indispensable for systems demanding high reliability and rapid information exchange across distributed networks.
The Aries fgOTN processor family is engineered according to the ITU-T G.709.20 fgOTN standard. This line of processors handles a variety of signals, including E1/T1, FE/GE, and STM1/STM4, effectively monitoring and managing alarms and performance metrics. Aries processors excel at fine-grain traffic aggregation, efficiently channeling fgODUflex traffic across OTN lines to support Ethernet, SDH, PDH client services. Their capacity to map signals to fgODUflex containers, which are then multiplexed into higher order OTN signals, demonstrates their versatility and efficiency. By allowing cascaded configurations with other Aries devices or Apodis processors, Aries products optimize traffic routes through OTN infrastructures, positioning them as essential components in optical networking and next-generation access scenarios.
This ultra-compact and high-speed H.264 core is engineered for FPGA platforms, boasting industry-leading size and performance. Capable of providing 1080p60 H.264 Baseline support, it accommodates various customization needs, including different pixel depths and resolutions. The core is particularly noted for its minimal latency of less than 1ms at 1080p30, a significant advantage over competitors. Its flexibility allows integration with a range of FPGA systems, ensuring efficient compression without compromising on speed or size. In one versatile package, users have access to a comprehensive set of encoding features including variable and fixed bit-rate options. The core facilitates simultaneous processing of multiple video streams, adapting to various compression ratios and frame types (I and P frames). Its support for advanced video input formats and compliance with ITAR guidelines make it a robust choice for both military and civilian applications. Moreover, the availability of low-cost evaluation licenses invites experimentation and custom adaptation, promoting broad application and ease of integration in diverse projects. These cores are especially optimized for low power consumption, drawing minimal resources in contrast to other market offerings due to their efficient FPGA design architecture. They include a suite of enhanced features such as an AXI wrapper for simple system integration and significantly reduced Block RAM requirements. Embedded systems benefit from its synchronous design and wide support for auxiliary functions like simultaneous stream encoding, making it a versatile addition to complex signal processing environments.
The Chimera GPNPU by Quadric redefines AI computing on devices by combining processor flexibility with NPU efficiency. Tailored for on-device AI, it tackles significant machine learning inference challenges faced by SoC developers. This licensable processor scales massively offering performance from 1 to 864 TOPs. One of its standout features is the ability to execute matrix, vector, and scalar code in a single pipeline, essentially merging the functionalities of NPUs, DSPs, and CPUs into a single core. Developers can easily incorporate new ML networks such as vision transformers and large language models without the typical overhead of partitioning tasks across multiple processors. The Chimera GPNPU is entirely code-driven, empowering developers to optimize their models throughout a device's lifecycle. Its architecture allows for future-proof flexibility, handling newer AI workloads as they emerge without necessitating hardware changes. In terms of memory efficiency, the Chimera architecture is notable for its compiler-driven DMA management and support for multiple levels of data storage. Its rich instruction set optimizes both 8-bit integer operations and complex DSP tasks, providing full support for C++ coded projects. Furthermore, the Chimera GPNPU integrates AXI Interfaces for efficient memory handling and configurable L2 memory to minimize off-chip access, crucial for maintaining low power dissipation.
The GV380 is a compact and powerful GPU IP designed to handle complex vector graphics with ease. This OpenVG 1.1 compliant GPU leverages a fourth generation architecture that minimizes CPU load while maximizing pixel performance in vector processing. The IP is ideal for embedded systems needing enhanced 2D graphics performance. It can seamlessly integrate with digital cameras and similar devices to render high-quality graphics without burdening the central processing unit. This efficiency is crucial in environments where processing capacity and battery life are valued. By offering substantial gains in pixel processing through innovative architectural improvements, the GV380 enables richer graphics and smoother interactions in embedded applications, supporting enhanced user experiences.
The HOTLink II Product Suite is another remarkable offering from Great River Technology. Built to complement their ARINC 818 suite, HOTLink II provides an integrated framework for crafting high-performance digital data links. This suite ensures seamless, secure, and reliable data transmission over fiber or copper cables across various platforms. Developed with a focus on flexibility and functionality, the HOTLink II capabilities enhance system integrators' ability to deploy effective communication solutions within aircraft and other demanding environments. The emphasis on robust, low-latency data transfer makes it an ideal choice for real-time applications where precision and reliability are paramount. Broad compatibility is a hallmark of HOTLink II, facilitating integration into diverse infrastructures. Backed by Great River Technology's expertise and support, customers are empowered to advance their system communication capabilities efficiently and cost-effectively.
DisplayPort and Embedded DisplayPort (eDP) IP by Silicon Library enables advanced digital display connectivity, offering superior video performance and enhanced sound. Designed to serve high-resolution displays, this IP supports next-gen display protocols, delivering robust signal quality and efficient energy use.
The KL630 AI SoC represents Kneron's sophisticated approach to AI processing, boasting an architecture that accommodates Int4 precision and transformers, making it incredibly adept in delivering performance efficiency alongside energy conservation. This chip shines in contexts demanding high computational intensity such as city surveillance and autonomous operation. It sports an ARM Cortex A5 CPU and a specialized NPU with 1 eTOPS computational power at Int4 precision. Suitable for running diverse AI applications, the KL630 is optimized for seamless operation in edge AI devices, providing comprehensive support for industry-standard AI frameworks and displaying superior image processing capabilities.
Specially designed for performance computing and complex system-on-chips (SoCs), the pPLL03F-GF22FDX is a Fractional-N PLL optimized for low-jitter applications in GF's 22FDX technology. The PLL caters to high-specificity clocking requirements, driving critical components like ADCs/DACs with moderate signal-to-noise ratio needs. Its architecture allows flexibility in multi-domain SoC environments, maintaining low power consumption under 5mW and occupying minimal die space. This second-generation digital PLL capitalizes on Perceptia's robust technology, ensuring stable performance across a wide array of environments. Easily integrated into existing SoC frameworks, pPLL03F-GF22FDX provides precise clock frequency modulation in both integer and fractional modes, aligning system requirements with input-output clock frequency combinations. This adaptability is crucial for refining complex digital systems. Availability in multiple technologies exemplifies its versatility, suitable for integrating in various technology nodes beyond GlobalFoundries, including options from Samsung, TSMC, and UMC. With its compact design and ability to meet critical timing requirements, the pPLL03F-GF22FDX is an ideal choice for performance-focused digital applications where reliability and flexibility are paramount.
Vantablack S-VIS Space Coating is engineered for use in space-qualified applications, excelling in suppressing stray light in optical systems. This coating is highly regarded for its ability to offer extremely high spectrally flat absorption, extending from the ultraviolet through to the near-millimeter wavelengths. Such attributes make it a superior choice for space missions, where light pollution from celestial bodies is a paramount challenge. Designed to withstand the harsh conditions of space, Vantablack S-VIS improves the effectiveness of baffles and calibration systems by reducing both the size and weight of the instrument package. This not only enhances the optical performance but also contributes to cost savings in manufacturing and deployment. The coating has been tested rigorously to ensure it withstands the environmental extremes experienced in space, including thermal stability and resistance to outgassing. For over a decade, Vantablack S-VIS has demonstrated flawless performance in low Earth orbit, particularly on dual star-trackers on disaster monitoring satellites. Its reliability has been proven through numerous successful implementations, including its deployment on the International Space Station. These achievements underscore Surrey NanoSystems' leadership in advanced coating technologies for aerospace applications.
The DB9000AXI Display Controller is designed to handle a vast range of display resolutions for LCD and OLED panels. It supports standard configurations from 320x240 pixels to Full HD at 1920x1080 pixels, with advanced setups accommodating 4K and even 8K resolutions. This flexibility allows it to drive displays via on-chip AMBA interconnects, linking frame buffer memory and processing units. Moreover, it incorporates sophisticated capabilities like overlay windows and hardware cursors, ideal for applications requiring high precision and functionality. Built to align with the AXI protocol, the controller is optimized for performance, ensuring high throughput for demanding graphic operations. Its versatile nature suits it to multiple applications, ranging from consumer electronics to sophisticated medical and industrial monitors. The added advantages of reduced CPU burden and enhanced visual rendering make it a compelling choice for high-end display solutions. Additionally, the DB9000AXI supports optional features tailored to specific requirements, including alpha blending and color space conversion. These advanced functions ensure top-tier visual fidelity and are vital for modern, immersive viewing experiences. Paired with Linux drivers and extensive verification suites, the DB9000AXI is a future-proof solution for robust display management needs.
The xcore.ai platform from XMOS is engineered to revolutionize the scope of intelligent IoT by offering a powerful yet cost-efficient solution that combines high-performance AI processing with flexible I/O and DSP capabilities. At its heart, xcore.ai boasts a multi-threaded architecture with 16 logical cores divided across two processor tiles, each equipped with substantial SRAM and a vector processing unit. This setup ensures seamless execution of integer and floating-point operations while facilitating high-speed communication between multiple xcore.ai systems, allowing for scalable deployments in varied applications. One of the standout features of xcore.ai is its software-defined I/O, enabling deterministic processing and precise timing accuracy, which is crucial for time-sensitive applications. It integrates embedded PHYs for various interfaces such as MIPI, USB, and LPDDR, enhancing its adaptability in meeting custom application needs. The device's clock frequency can be adjusted to optimize power consumption, affirming its cost-effectiveness for IoT solutions demanding high efficiency. The platform's DSP and AI performances are equally impressive. The 32-bit floating-point pipeline can deliver up to 1600 MFLOPS with additional block floating point capabilities, accommodating complex arithmetic computations and FFT operations essential for audio and vision processing. Its AI performance reaches peaks of 51.2 GMACC/s for 8-bit operations, maintaining substantial throughput even under intensive AI workloads, making xcore.ai an ideal candidate for AI-enhanced IoT device creation.
SkyeChip's High-Speed PLL is engineered to provide robust clock generation capabilities in diverse technical environments. Geared for high-frequency applications, this phase-locked loop exhibits a broad input frequency range from 100Mhz to 350Mhz and can achieve an output frequency scaling from 300MHz to 3.2GHz. The design yields significant flexibility, supporting various division and modulation schemes that extend operational range and efficiency. Integral components are engineered for optimal power consumption, ensuring that even at maximum output frequencies, the PLL remains energy-efficient, making it especially suitable for power-sensitive applications across numerous electronic domains.
The Platform-Level Interrupt Controller (PLIC) from Roa Logic is a highly adaptable interrupt management system, crafted in accordance with the RISC-V Privileged v1.10 specification. This core seamlessly integrates with AHB-Lite, supporting a wide range of interrupt sources and targets. It provides a robust foundation for managing complex interrupt architectures, essential in modern embedded systems. The PLIC core is meticulously designed for configurability, offering custom parameters for address and data widths, as well as the capacity to set unique priority levels per interrupt source. It includes features like programmable priority thresholds and an interrupt pending queue, allowing for tailored performance to meet the specific needs of an application. This controller ensures efficient handling of interrupt masking using a priority threshold system, further enabling sophisticated event management in multi-tasking environments. With comprehensive documentation and source code available through Roa Logic's GitHub, the PLIC is an accessible solution for developers looking to integrate reliable interrupt control in their RISC-V based systems.
The Apodis family of Optical Transport Network processors adheres to ITU-T standards, offering a comprehensive suite for signal termination, processing, and multiplexing. Designed to handle both SONET/SDH and Ethernet client services, these processors map signals to Optical Transport Network (OTN), empowering versatile any-port, any-service configurations. Apodis processors are notable for their capacity to support up to 16 client ports and four 10G OTN line ports, delivering bandwidth scalability up to 40G, crucial for wireless backhaul and fronthaul deployments. With a robust, non-blocking OTN switching fabric, Apodis facilitates seamless client-to-line and line-to-line connections while optimally managing network bandwidth. This adaptability makes the Apodis processors an ideal choice for next-generation access networks and optical infrastructures.
The AXI4 DMA Controller by Digital Blocks is engineered to facilitate efficient data transfers within hardware configurations, offering multi-channel support ranging from 1 to 16 channels. This makes it adaptable for varying data throughput needs, whether for small data packets or extensive data transfers. It features independent read and write controllers for each channel, supporting both scatter and gather linked-list transactions, ensuring maximum efficiency. Designed with the AMBA AXI protocol in mind, this DMA controller ensures seamless integration with other system components, making it ideal for high-performance computing tasks that require substantial data movement. The ability of users to program burst lengths and manage 4K boundary crossings enhances its adaptability for different application scenarios, from network systems to complex AV processing. The controller also allows for a high degree of customization to accommodate specific needs. Options to tailor features can help systems minimize silicon area while managing licensing costs effectively. Software compilation is further streamlined by the extensive suite of provided specification documents and test benches, guaranteeing reliable performance across diverse operational environments.
The DisplayPort Transmitter is a highly advanced solution designed to seamlessly transmit high-definition audio and video data between devices. It adheres to the latest VESA standards, ensuring it can handle DisplayPort 1.4 and 2.1 specifications with ease. The transmitter is engineered to support a plethora of audio interfaces including I2S, SPDIF, and DMA, making it highly adaptable to a wide range of consumer and professional audio-visual equipment. With features focused on AV sync and timing recovery, it ensures smooth and uninterrupted data flow even in the most demanding applications. This transmitter is particularly beneficial for those wishing to integrate top-of-the-line audio and video synchronization within their projects, offering customizable sound settings that can accommodate unique user requirements. It's robust enough to be used across industry sectors, from high-end consumer electronics like gaming consoles and home theater systems to professional equipment used in broadcast and video wall displays. Moreover, the DisplayPort Transmitter's architecture facilitates seamless integration into existing FPGA and ASIC systems without a hitch in performance. Comprehensive compliance testing ensures that it is compatible with a wide base of devices and technologies, making it a dependable choice for developers looking to provide comprehensive DisplayPort solutions. Whether it's enhancing consumer electronics or powering complex industry-specific systems, the DisplayPort Transmitter is built to deliver exemplary performance.
Clock generation solutions from Analog Circuit Works are engineered to pair seamlessly with other IP products, enhancing the functionality and performance of integrated systems. Their offerings focus on providing consistent, reliable clock signals that are essential for synchronizing complex digital circuits, thus playing a pivotal role in maintaining efficient system operation. These solutions cater to varying clock frequencies, tailored to fit a diverse set of process technologies. Analog Circuit Works capitalizes on their ability to design optimized clock circuits that cater to both high-frequency and optimized low-frequency operations, ensuring that they meet specific design requirements while facilitating smoother integration into diverse application environments. The clock generation IP serves as a backbone for ensuring operational timing precision within devices, providing foundational support that enhances the overall synchronization and performance of intricate electronic systems. This reliability and adaptability make these solutions vital in complex electronics where time-sensitive operations are critical.
SkyeChip's Configurable I/O module offers a versatile interface supporting high-speed signaling up to 3.2 GT/s. This component is compatible with several I/O standards including LVDS, HCSL, POD, and various CMOS levels, providing broad application utility in modern digital systems. Tailored for ease of integration into diverse electronic architectures, its configuration capabilities allow for precise adaptation to specific design needs, enhancing system performance and interoperability. This flexibility opens avenues for its utilization across numerous sectors, including telecommunications and general electronic device manufacturers.
Dolphin Technology's I/O products encompass a vast selection of interface IPs known for their high-performance capabilities. These I/O components are designed to complement various process technologies, ensuring reliability and efficiency in applications ranging from core limited designs to flip-chip utilizations. The product range includes standard I/O, high-speed I/O, and specialty interface I/O that can be customized for specific design requirements. The portfolio comprises various specialized I/Os like High Voltage Tolerant GPIO, LVDS Tx/Rx, and several DDR and SD IO variations, each built to meet demanding design specifications. Dolphin Technology’s offerings are fully equipped with compilers that allow for customization, ensuring each I/O library can be tailored to address process and chip-specific needs, thereby delivering optimal performance and versatility. These I/O solutions are available in multiple forms, including inline styles and flip-chip arrangements, which assist in the efficient use of space and signal integrity in complex semiconductor designs. The capability to integrate with different technology levels further broadens the applicability of these products, making them suitable for a diverse set of industry requirements.
The ARINC 818 Streaming IP Core is engineered to deliver real-time streaming conversion between a pixel data bus and an ARINC 818 formatted Fibre Channel (FC) serial data stream, or vice versa. This core is pivotal in applications where precision and timing are critical, providing efficient data handling for high-resolution display systems commonly used in avionics. Tailored for flexibility, this IP core supports bidirectional conversion, which provides seamless integration into existing infrastructure, enhancing both legacy systems and new installations. By handling ARINC 818 formatted FC data, it ensures consistent and accurate data synchronization, making it ideal for mission-critical aerospace applications. This IP core excels in environments requiring advanced data processing and synchronization. Its design minimizes latency while maximizing throughput, ensuring high-quality transmission and reception of visual data. The ARINC 818 Streaming IP Core is a vital asset in enhancing the performance and reliability of communication and display systems in complex aerospace technologies.
DolphinWare IPs is a versatile portfolio of intellectual property solutions that enable efficient SoC design. This collection includes various control logic components such as FIFO, arbiter, and arithmetic components like math operators and converters. In addition, the logic components span counters, registers, and multiplexers, providing essential functionalities for diverse industrial applications. The IPs in this lineup are meticulously designed to ensure data integrity, supported by robust verification IPs for AXI4, APB, SD4.0, and more. This comprehensive suite meets the stringent demands of modern electronic designs, facilitating seamless integration into existing design paradigms. Beyond their broad functionality, DolphinWare’s offerings are fundamental to applications requiring specific control logic and data integrity solutions, making them indispensable for enterprises looking to modernize or expand their product offerings while ensuring compliance with industry standards.
The Orion MFH IP Cores are designed for optimal performance in 4G mobile fronthaul networks, compliant with the ITU-T specifications for CPRI signal multiplexing. They adeptly handle various CPRI options, ranging from 2.4576 Gbps to 12.16512 Gbps, ensuring high compatibility and performance. Featuring both muxponder and transponder configurations, Orion cores facilitate the efficient mapping and transport of CPRI signals via Optical Transport Network infrastructures, ideal for modern telecommunications frameworks. Their advanced capabilities enable telecommunications providers to enhance their network reliability and service delivery, adapting seamlessly to different fronthaul scenarios.
The PLL12G, serving as a Clock Multiplication Unit, is engineered to generate clock outputs in the 8.5GHz to 11.3GHz range, complementing a host of transceiver standards like 10GbE and OC-192. It operates with low power consumption, courtesy of IBM's 65nm process, making it suitable for various clocking modes crucial in phase-locked loop systems. Its diverse functionality ensures it's integral to telecommunications infrastructures where multiple clocking modes, including FEC support, are required.
iWave Global introduces the ARINC 818 Switch, a pivotal component in the management and routing of video data within avionics systems. Designed for applications that require efficient video data distribution and management, the switch is optimized for performance in environments with stringent data handling requirements. The switch's architecture supports a high level of bandwidth, allowing for the smooth routing of multiple video streams in real-time. Its design includes advanced features that ensure low-latency, error-free data transfer, integral to maintaining the integrity and reliability of video data in critical applications. Featuring robust interoperability characteristics, the ARINC 818 Switch easily integrates into existing systems, facilitating modular expansion and adaptability to new technological standards. It is indispensable for any aerospace project that involves complex video data management, providing a stable platform for video data routing and switching.
The GenAI v1-Q from RaiderChip brings forth a specialized focus on quantized AI operations, reducing memory requirements significantly while maintaining impressive precision and speed. This innovative accelerator is engineered to execute large language models in real-time, utilizing advanced quantization techniques such as Q4_K and Q5_K, thereby enhancing AI inference efficiency especially in memory-constrained environments. By offering a 276% boost in processing speed alongside a 75% reduction in memory footprint, GenAI v1-Q empowers developers to integrate advanced AI capabilities into smaller, less powerful devices without sacrificing operational quality. This makes it particularly advantageous for applications demanding swift response times and low latency, including real-time translation, autonomous navigation, and responsive customer interactions. The GenAI v1-Q diverges from conventional AI solutions by functioning independently, free from external network or cloud auxiliaries. Its design harmonizes superior computational performance with scalability, allowing seamless adaptation across variegated hardware platforms including FPGAs and ASIC implementations. This flexibility is crucial for tailoring performance parameters like model scale, inference velocity, and power consumption to meet exacting user specifications effectively. RaiderChip's GenAI v1-Q addresses crucial AI industry needs with its ability to manage multiple transformer-based models and confidential data securely on-premises. This opens doors for its application in sensitive areas such as defense, healthcare, and financial services, where confidentiality and rapid processing are paramount. With GenAI v1-Q, RaiderChip underscores its commitment to advancing AI solutions that are both environmentally sustainable and economically viable.
GSHARK is a high-performance GPU IP designed to accelerate graphics on embedded devices. Known for its extreme power efficiency and seamless integration, this GPU IP significantly reduces CPU load, making it ideal for use in devices like digital cameras and automotive systems. Its remarkable track record of over one hundred million shipments underscores its reliability and performance. Engineered with TAKUMI's proprietary architecture, GSHARK integrates advanced rendering capabilities. This architecture supports real-time, on-the-fly graphics processing similar to that found in PCs, smartphones, and gaming consoles, ensuring a rich user experience and efficient graphics applications. This IP excels in environments where power consumption and performance balance are crucial. GSHARK is at the forefront of embedded graphics solutions, providing significant improvements in processing speed while maintaining low energy usage. Its architecture easily handles demanding graphics rendering tasks, adding considerable value to any embedded system it is integrated into.
ISPido on VIP Board is a customized runtime solution tailored for Lattice Semiconductors’ Video Interface Platform (VIP) board. This setup enables real-time image processing and provides flexibility for both automated configuration and manual control through a menu interface. Users can adjust settings via histogram readings, select gamma tables, and apply convolutional filters to achieve optimal image quality. Equipped with key components like the CrossLink VIP input bridge board and ECP5 VIP Processor with ECP5-85 FPGA, this solution supports dual image sensors to produce a 1920x1080p HDMI output. The platform enables dynamic runtime calibration, providing users with interface options for active parameter adjustments, ensuring that image settings are fine-tuned for various applications. This system is particularly advantageous for developers and engineers looking to integrate sophisticated image processing capabilities into their devices. Its runtime flexibility and comprehensive set of features make it a valuable tool for prototyping and deploying scalable imaging solutions.
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