All IPs > Graphic & Peripheral
Graphic & Peripheral Semiconductor IPs are critical components in the design and development of electronics that require efficient and robust control over multimedia and peripheral functions. This category of semiconductor IP encompasses a wide array of technologies used to manage and optimize graphics rendering, audio processing, data communication, and peripheral interfaces in electronic devices such as computers, smartphones, tablets, and other smart gadgets.
In this vivid category, you'll find a variety of subcategories tailored to specific functionalities. For instance, the Graphics Processing Unit (GPU) semiconductor IPs are pivotal for rendering images and video, essential in gaming, virtual reality, and professional content creation. Audio Controllers handle sound processing, ensuring crisp and seamless audio output, crucial for devices prioritizing high-quality sound delivery.
Other key components in the Graphic & Peripheral category include Peripheral Controllers, which facilitate the integration of various input/output devices, enhancing the device's interactivity and user experience. DMA Controllers are responsible for moving data efficiently between memory and peripherals, minimizing the CPU load. These IPs enhance overall system performance by ensuring that data flow is smooth and uninterrupted.
From Clock Generators that synchronize the entire system's operations to Interrupt Controllers managing priority tasks, each semiconductor IP in this category plays a unique role in ensuring that electronic devices operate at peak efficiency. By exploring these subcategories, companies and developers can find the precise semiconductors needed to support cutting-edge multimedia and peripheral technologies in their next product launch.
The KL730 is a sophisticated AI System on Chip (SoC) that embodies Kneron's third-generation reconfigurable NPU architecture. This SoC delivers a substantial 8 TOPS of computing power, designed to efficiently handle CNN network architectures and transformer applications. Its innovative NPU architecture significantly optimizes DDR bandwidth, providing powerful video processing capabilities, including supporting 4K resolution at 60 FPS. Furthermore, the KL730 demonstrates formidable performance in noise reduction and low-light imaging, positioning it as a versatile solution for intelligent security, video conferencing, and autonomous applications.
Overview: The UCIe IP supports multiple protocols (CXL/PCIe/Streaming) to connect chiplets, reducing overall development cycles for IPs and SOCs. With flexible application and PHY interfaces, The UCIe IP is ideal for SOCs and chiplets. Key Features:  Supports UCIe 1.0 Specification  Supports CXL 2.0 and CXL 3.0 Specifications  Supports PCIe Gen6 Specification  Supports PCIe Gen5 and older versions of PCIe specifications  Supports single and two-stack modules  Supports CXL 2.0 68Byte flit mode with Fallback mode for PCIe non-flit mode transfers  Supports CXL 3.0 256Byte flit mode  Supports PCIe Gen6 flit mode  Configurable up to 64-lane configuration for Advanced UCIe modules and 16 lanes for Standard UCIe modules  Supports sideband and Mainband signals  Supports Lane repair handling  Data to clock point training and eye width sweep support from transmitter and receiver ends  UCIe controller can work as Downstream or Upstream  Main Band Lane reversal supported  Dynamic sense of normal and redundant clock and data lines activation  UCIe enumeration through DVSEC  Error logging and reporting supported  Error injection supported through Register programming  RDI/FDI PM entry, Exit, Abort flows supported  Dynamic clock gang at adapter supported Configurable Options:  Maximum link width (x1, x2, x4, x8, x16)  MPS (128B to 4KB)  MRRS (128B to 4KB)  Transmit retry/Receive buffer size  Number of Virtual Channels  L1 PM substate support  Optional Capability Features can be Configured  Number of PF/VFDMA configurable Options  AXI MAX payload size Variations  Multiple CPI Interfaces (Configurable)  Cache/memory configurable  Type 0/1/2 device configurable
Overview: The Expanded Serial Peripheral Interface (xSPI) Master/Slave controller offers high data throughput, low signal count, and limited backward compatibility with legacy SPI devices. It is designed to connect xSPI Master/Slave devices in computing, automotive, Internet of Things, embedded systems, and mobile processors to various peripherals such as non-volatile memories, graphics peripherals, networking devices, FPGAs, and sensor devices. Key Features:  Compliance with JEDEC standard JESD251 eXpanded SPI for Non-Volatile Memory Devices, Version 1.0  Support for Single master and multiple slaves per interface port  Single Data Rate (SDR) and Double Data Rate (DDR) support  Source synchronous clocking  Deep Power Down (DPD) enter and exit commands  Eight IO ports in standard, expandable based on system requirements  Optional Data Strobe (DS) for write masking  bit wide SDR transfer support  Profile 1.0 Commands for non-volatile memory device management  Profile 2.0 Commands for read or write data for various slave devices Applications:  Consumer Electronics  Defense & Aerospace  Virtual Reality  Augmented Reality  Medical  Biometrics  Automotive Devices  Sensor Devices
Our Expanded Serial Peripheral Interface (JESD251) Master controller features a low signal count and high data bandwidth, making it ideal for use in computing, automotive, Internet of Things, embedded systems, and mobile system processors. It connects multiple sources of Serial Peripheral Interface (xSPI) slave devices, including nonvolatile memories, graphics peripherals, networking peripherals, FPGAs, and sensor devices. Features • Compliant with JEDEC standard JESD251 expanded Serial Peripheral Interface (xSPI) for Non-Volatile Memory Devices, Version 1.0. • Supports a single master and multiple slaves per interface port. • Supports Single Data Rate and Double Data Rate. • Supports source synchronous clocking. • Supports data transfer rates up to: o 400MT/s (200MHz Clock) o 333MT/s (167MHz Clock) o 266MT/s (133MHz Clock) o 200MT/s (100MHz Clock) • Supports Deep Power Down (DPD) enter and exit commands. • Standard support for eight IO ports, with the possibility to increase IO ports based on system performance requirements. • Optional support for Data Strobe (DS) for writemasking. • Supports 1-bit wide SDR transfer. • Supports Profile 1.0 commands to manage nonvolatile memory devices. • Supports Profile 2.0 commands to read or writedata for any type of slave device. • Compatible with non-volatile memory arrays such as NOR Flash, NAND Flash, FRAM, and nvSRAM. • Compatible with volatile memory arrays such as SRAM, PSRAM, and DRAM. • Supports register-mapped input/output functions. • Supports programmable function devices such as FPGAs. Application • Consumer Electronics. • Defence & Aerospace. • Virtual Reality. • Augmented Reality. • Medical. • Biometrics (Fingerprints, etc). • Automotive Devices. • Sensor Devices. Deliverables • Verilog Source code. • User Guide. • IP Integration Guide. • Run and Synthesis script. • Encrypted Verification Testbench Environment. • Basic Test-suite.
The AI Camera Module by Altek Corporation exemplifies cutting-edge image capture technology, integrating both hardware and software to deliver high-quality, intelligent imaging solutions. This module is built on robust AI frameworks allowing it to adapt and optimize image processing based on specific application needs. It finds use in areas where high-resolution and real-time processing are essential, such as security systems and automotive industries.<br/><br/>Equipped with versatile imaging sensors, the AI Camera Module ensures excellent picture quality even in challenging lighting conditions, thanks to its AI-driven image enhancement algorithms. It supports edge computing, which reduces latency and enhances the speed of image analysis, thus providing timely insights and data processing right on the device itself.<br/><br/>This camera module stands out for its interoperability with IoT devices, paving the way for a more interconnected and intelligent ecosystem. Its advanced features such as facial detection, motion tracking, and object recognition empower users across various domains, from consumer electronics to industrial solutions, making it an indispensable tool for modern digital infrastructures.
Overview: PCIe Gen6 is a high-speed, layered protocol interconnect interface supporting speeds up to 64GT/s, featuring multi-lanes and links. The Transport, Data Link, and Physical layers specified in the PCIe specification are implemented, along with PIPE interface logic connecting to PHY and AXI Bridging logic for application connectivity. Specifications:  Supports PCIe Gen 6 and Pipe 5.X Specifications  Core supports Flit and non-Flit Mode  Lane Configurations: X16, X8, X4, X2, X1  AXI MM and Streaming supported  Supports Gen1 to Gen6 modes  Data rate support of 2.5 GT/s, 5 GT/s, 8 GT/s, 16 GT/s, 32 GT/s, 64 GT/s  PAM support when operating at 64GT/s  Encoding/Decoding Support: 8b/10b, 128b/130b, 1b/1b  Supports SerDes and non-SerDes architecture  Optional DMA support as plugin module  Support for alternate negotiation protocol  Can operate as an endpoint or root complex  Lane polarity control through register  Lane de-skew supported  Support for L1 states and L0P  Support for SKP OS add/removal and SRIS mode  No equalization support through configuration  Deemphasis negotiation support at 5GT/s  Supports EI inferences in all modes  Supports PTM, OBFF, MSI, MSIX, Power management, and all message formats
The Aries fgOTN processor family is engineered according to the ITU-T G.709.20 fgOTN standard. This line of processors handles a variety of signals, including E1/T1, FE/GE, and STM1/STM4, effectively monitoring and managing alarms and performance metrics. Aries processors excel at fine-grain traffic aggregation, efficiently channeling fgODUflex traffic across OTN lines to support Ethernet, SDH, PDH client services. Their capacity to map signals to fgODUflex containers, which are then multiplexed into higher order OTN signals, demonstrates their versatility and efficiency. By allowing cascaded configurations with other Aries devices or Apodis processors, Aries products optimize traffic routes through OTN infrastructures, positioning them as essential components in optical networking and next-generation access scenarios.
Overview: The Multi-Protocol Accelerator IP is a versatile technology designed to support low latency and high bandwidth accelerators for efficient CPU-to-device and CPU-to-memory communication. It also enables switching for fan-out to connect more devices, memory pooling for increased memory utilization efficiency, and provides memory capacity with support for hot-plug, security enhancements, persistent memory support, and memory error reporting. Key Features:  CXL 3.0 Support: Compliant with CXL spec V3.X/V2.X  PCIe Compatibility: Supports PCIe spec 6.0/5.0  CPI Interface: Support for CPI Interface  AXI Interface: Configurable AXI master, AXI slave  Bus Support: PIPE/FLEX bus, Lane x1,x2,x4,x8,x16  Protocol Support: Gen3, Gen4, Gen5 & Gen6, Fallback Mode  Register Checks: Configuration and Memory Mapped registers  Dual Mode: Supports Dual Mode operation  Transfer Support: HBR/PBR & LOpt Transfers, Standard Cache and Mem Transfers  CXL Support: Can function as both CXL host and device  Data Transfer: Supports Standard IO, 68Byte Flit, and 256Byte Flit Transfers  FlexBus Features: FlexBus Link Features, ARB/MUX, ARB/MUX Bypass  Optimization: Latency Optimization, Credit Return Forcing, Empty Flits (Latency Optimized)  Power Management: Supports Power Management features  Enhancements: CXL IDE, RAS Features, Poison & Viral Handling, MLD/SLD  Testing: Compliance Testing and Error Scenarios support
Silicon Creations' Free Running Oscillators provide dependable timing solutions for a range of applications such as watchdog timers and core clock generators in low-power systems. These oscillators, crafted with compactness and efficiency in mind, support a gamut of processes from 65nm to the latest 3nm technologies. These oscillators excel in low power consumption, often requiring less than 30µW during operation. Their robust design ensures they deliver high precision over a temperature range from -40°C to 125°C with supply voltage variabilities factored in. The simplicity in design negates the need for external components, promoting easier integration and reduced overall system complexity. Precise tuning capabilities allow for accuracy levels up to ±1.5% after process trimming, ensuring outstanding performance in volatile environmental conditions. This level of reliability makes them ideal for integration into various consumer electronics, automotive controls, and other precision-demanding applications where space and power constraints are critical.
Silicon Creations delivers precision LC-PLLs designed for ultra-low jitter applications requiring high-end performance. These LC-tank PLLs are equipped with advanced digital architectures supporting wide frequency tuning capabilities, primarily suited for converter and PHY applications. They ensure exceptional jitter performance, maintaining values well below 300fs RMS. The LC-PLLs from Silicon Creations are characterized by their capacity to handle fractional-N operations, with active noise cancellation features allowing for clean signal synthesis free of unwanted spurs. This architecture leads to significant power efficiencies, with some IPs consuming less than 10mW. Their low footprint and high frequency integrative capabilities enable seamless deployments across various chip designs, creating a perfect balance between performance and size. Particular strength lies in these PLLs' ability to meet stringent PCIe6 reference clocking requirements. With programmable loop bandwidth and an impressive tuning range, they offer designers a powerful toolset for achieving precise signal control within cramped system on chip environments. These products highlight Silicon Creations’ commitment to providing industry-leading performance and reliability in semiconductor design.
Our Expanded Serial Peripheral Interface (JESD251) Slave controller offers high data throughput, low signal count, and limited backward compatibility with legacy Serial Peripheral Interface (SPI) devices. It is used to connect xSPI Master devices in computing, automotive, Internet of Things, embedded systems, and mobile system processors to non-volatile memories, graphics peripherals, networking peripherals, FPGAs, and sensor devices. Features • Compliant with JEDEC standard JESD251 expanded Serial Peripheral Interface (xSPI) for Non-Volatile Memory Devices, Version 1.0. • Supports Single Data Rate (SDR) and Double Data Rate (DDR). • Supports source synchronous clocking. • Supports data transfer rates up to: o 400MT/s (200MHz Clock) o 333MT/s (167MHz Clock) o 266MT/s (133MHz Clock) o 200MT/s (100MHz Clock) • Supports Deep Power Down (DPD) enter and exit commands. • Standard support for eight IO ports, with the possibility to increase IO ports based on system performance requirements. • Optional support for Data Strobe (DS) for timing reference. • Supports 1-bit wide SDR transfer. • Supports Profile 1.0 commands to manage nonvolatile memory devices. • Supports Profile 2.0 commands for reading or writing data for any type of slave device. • Compatible with non-volatile memory arrays such as NOR Flash, NAND Flash, FRAM, and nvSRAM. • Compatible with volatile memory arrays such as SRAM, PSRAM, and DRAM. • Supports register-mapped input/output functions. • Supports programmable function devices such as FPGAs. Application • Consumer Electronics. • Defence & Aerospace. • Virtual Reality. • Augmented Reality. • Medical. • Biometrics (Fingerprints, etc). • Automotive Devices. • Sensor Devices. Deliverables • Verilog Source code. • User Guide. • IP Integration Guide. • Run and Synthesis script. • Encrypted Verification Testbench Environment. • Basic Test-suite.
RaiderChip's GenAI v1 is a pioneering hardware-based generative AI accelerator, designed to perform local inference at the Edge. This technology integrates optimally with on-premises servers and embedded devices, offering substantial benefits in privacy, performance, and energy efficiency over traditional hybrid AI solutions. The design of the GenAI v1 NPU streamlines the process of executing large language models by embedding them directly onto the hardware, eliminating the need for external components like CPUs or internet connections. With its ability to support complex models such as the Llama 3.2 with 4-bit quantization on LPDDR4 memory, the GenAI v1 achieves unprecedented efficiency in AI token processing, coupled with energy savings and reduced latency. What sets GenAI v1 apart is its scalability and cost-effectiveness, significantly outperforming competitive solutions such as Intel Gaudi 2, Nvidia's cloud GPUs, and Google's cloud TPUs in terms of memory efficiency. This solution maximizes the number of tokens generated per unit of memory bandwidth, thus addressing one of the primary limitations in generative AI workflow. Furthermore, the adept memory usage of GenAI v1 reduces the dependency on costly memory types like HBM, opening the door to more affordable alternatives without diminishing processing capabilities. With a target-agnostic approach, RaiderChip ensures the GenAI v1 can be adapted to various FPGAs and ASICs, offering configuration flexibility that allows users to balance performance with hardware costs. Its compatibility with a wide range of transformers-based models, including proprietary modifications, ensures GenAI v1's robust placement across sectors requiring high-speed processing, like finance, medical diagnostics, and autonomous systems. RaiderChip's innovation with GenAI v1 focuses on supporting both vanilla and quantized AI models, ensuring high computation speeds necessary for real-time applications without compromising accuracy. This capability underpins their strategic vision of enabling versatile and sustainable AI solutions across industries. By prioritizing integration ease and operational independence, RaiderChip provides a tangible edge in applying generative AI effectively and widely.
The eSi-Connect suite introduces a fully integrated solution encompassing a wide variety of processor peripherals, each interfacing seamlessly through standard AMBA protocols like AXI, AHB, or APB, simplifying integration and development of SoC architectures. This suite features memory controllers for DDR, SPI Flash, and interfaces including USB, UART, and GPIO among others, bounded by real-time and control functionalities such as timers and watchdogs. Each peripheral component is highly configurable to adjust features like FIFO sizes for UART, I2C clock rates, SPI operating modes, providing modular flexibility to target specific application needs. Low-level driver software accompanies each peripheral for real-time deployments, enhancing the module's utility for prompt SoC integration and application fulfillment. This attribute ensures enhanced interoperability within diverse design environments fulfilling both immediate and long-term product objectives through architectural simplicity and reliable performance-level adaptability.
The AHB-Lite Multilayer Switch developed by Roa Logic is engineered to provide a high-performance, low-latency interconnect solution for systems using the AHB-Lite bus protocol. This IP is designed to support an unlimited number of bus masters and slaves, ensuring scalability and flexibility in complex system architectures. By enabling efficient data routing, the switch enhances throughput and overall system performance, making it indispensable in data-intensive applications. Capable of handling multiple data paths simultaneously, the multilayer switch ensures that there are no bottlenecks in data flow, facilitating real-time data processing and communication. Its design features are tailored to optimize latency and throughput, effectively addressing the challenges encountered in high-demand environments. Roa Logic provides a comprehensive suite of resources, including thorough documentation and testbench environments, to simplify the integration of this switch into larger system designs. This support ensures that developers can achieve optimal performance with ease, utilizing the switch's capabilities to enhance system interconnectivity and efficiency significantly. The AHB-Lite Multilayer Switch exemplifies the commitment of Roa Logic to provide innovative, responsive solutions that cater to the evolving needs of the semiconductor industry.
The Ring PLLs offered by Silicon Creations illustrate a versatile clocking solution, well-suited for numerous frequency generation tasks within integrated circuit designs. Known for their general-purpose and specialized applications, these PLLs are crafted to serve a massive array of industries. Their high configurability makes them applicable for diverse synthesis needs, acting as the backbone for multiple clocking strategies across different environments. Silicon Creations' Ring PLLs epitomize high integration with functions tailored for low jitter and precision clock generation, suitable for battery-operated devices and systems demanding high accuracy. Applications span from general clocking to precise Audio Codecs and SerDes configurations requiring dedicated performance metrics. The Ring PLL architecture achieves best-in-class long-term and period jitter performance with both integer and fractional modes available. Designed to support high volumes of frequencies with minimal footprint, these PLLs aid in efficient space allocation within system designs. Their use of silicon-proven architectures and modern validation methodologies assure customers of high reliability and quick integration into existing SoC designs, emphasizing low risk and high reward configurations.
The Vantablack S-VIS Space Coating is engineered for space applications, where it serves as an advanced stray light suppression and blackbody coating. Suitable for use on satellite instruments, this coating helps to minimize the light reflection that can occur in space environments, thereby ensuring higher accuracy in optical measurements and instrument calibration. Vantablack S-VIS offers exceptional spectral absorption from ultraviolet through to the terahertz range, crucial for a variety of optical systems. Its lightweight and highly absorbent properties allow for more compact baffle and calibration systems without compromising performance. The coating has demonstrated reliability in space missions, offering consistent absorption over extended periods. This coating is particularly critical for optical systems that operate under the challenging conditions of space, including variations in temperature and pressure, as well as the intense radiation environment. It has been applied successfully in low earth orbit operations, enhancing the operability of instruments by reducing system complexity and improving the accuracy of optical sensors.
The GH310 is specialized GPU IP tailored for 2D sprite graphics with an emphasis on high pixel processing capabilities. It achieves minimal gate count, ensuring it occupies less silicon area while delivering robust graphic outputs. Designed to handle large volumes of sprite graphics efficiently, the GH310 is perfect for applications requiring rapid rendering and minimal hardware overhead. This makes it favorable for systems where space and power savings are crucial yet high-quality graphics are needed. Its architecture allows for optimized performance tailored for specific graphical needs, translating into a resource-efficient solution for developers seeking to integrate intricate graphical features in their products without excessive resource consumption.
iWave Global introduces the ARINC 818 Switch, a pivotal component in the management and routing of video data within avionics systems. Designed for applications that require efficient video data distribution and management, the switch is optimized for performance in environments with stringent data handling requirements. The switch's architecture supports a high level of bandwidth, allowing for the smooth routing of multiple video streams in real-time. Its design includes advanced features that ensure low-latency, error-free data transfer, integral to maintaining the integrity and reliability of video data in critical applications. Featuring robust interoperability characteristics, the ARINC 818 Switch easily integrates into existing systems, facilitating modular expansion and adaptability to new technological standards. It is indispensable for any aerospace project that involves complex video data management, providing a stable platform for video data routing and switching.
The Chimera GPNPU from Quadric is designed as a general-purpose neural processing unit intended to meet a broad range of demands in machine learning inference applications. It is engineered to perform both matrix and vector operations along with scalar code within a single execution pipeline, which offers significant flexibility and efficiency across various computational tasks. This product achieves up to 864 Tera Operations per Second (TOPs), making it suitable for intensive applications including automotive safety systems. Notably, the GPNPU simplifies system-on-chip (SoC) hardware integration by consolidating hardware functions into one processor core. This unification reduces complexity in system design tasks, enhances memory usage profiling, and optimizes power consumption when compared to systems involving multiple heterogeneous cores such as NPUs and DSPs. Additionally, its single-core setup enables developers to efficiently compile and execute diverse workloads, improving performance tuning and reducing development time. The architecture of the Chimera GPNPU supports state-of-the-art models with its Forward Programming Interface that facilitates easy adaptation to changes, allowing support for new network models and neural network operators. It’s an ideal solution for products requiring a mix of traditional digital signal processing and AI inference like radar and lidar signal processing, showcasing a rare blend of programming simplicity and long-term flexibility. This capability future-proofs devices, expanding their lifespan significantly in a rapidly evolving tech landscape.
The KL520 was Kneron's first foray into AI SoCs, characterized by its small size and energy efficiency. This chip integrates a dual ARM Cortex M4 CPU architecture, which can function both as a host processor and as a supportive AI co-processor for diverse edge devices. Ideal for smart devices such as door locks and cameras, it is compatible with various 3D sensor technologies, offering a balance of compact design and high performance. As a result, this SoC has been adopted by multiple products in the smart home and security sectors.
The Mixed-Signal CODEC offered by Archband Labs integrates advanced analog and digital audio processing to deliver superior sound quality. Designed for a variety of applications such as portable audio devices, automotive systems, and entertainment systems, this CODEC provides efficiency and high performance. With cutting-edge technologies, it handles complex signal conversions with minimal power consumption. This CODEC supports numerous interface standards, making it a versatile component in numerous audio architectures. It's engineered to offer precise sound reproduction and maintains audio fidelity across all use cases. The integrated components within the CODEC streamline design processes and reduce the complexity of audio system implementations. Furthermore, the Mixed-Signal CODEC incorporates features that support high-resolution audio, ensuring compatibility with high-definition sound systems. It's an ideal choice for engineers looking for a reliable and comprehensive audio processing solution.
The KL630 chip stands out with its pioneering NPU architecture, making it the industry's first to support Int4 precision alongside transformer networks. This unique capability enables it to achieve exceptional computational efficiency and low energy consumption, suitable for a wide variety of applications. The chip incorporates an ARM Cortex A5 CPU, providing robust support for all major AI frameworks and delivering superior ISP capabilities for handling low light conditions and HDR applications, making it ideal for security, automotive, and smart city uses.
The PDM-to-PCM Converter from Archband Labs leads in transforming pulse density modulation signals into pulse code modulation signals. This converter is essential in applications where high fidelity of audio signal processing is vital, including digital audio systems and communication devices. Archband’s solution ensures accurate conversion, preserving the integrity and clarity of the original audio. This converter is crafted to seamlessly integrate with a wide array of systems, offering flexibility and ease-of-use in various configurations. Its robust design supports a wide range of input frequencies, making it adaptable to different signal environments. The PDM-to-PCM Converter also excels in minimizing latency and reducing overhead processing times. It’s engineered for environments where precision and sound quality are paramount, ensuring that audio signals remain crisp and undistorted during conversion processes.
The AHB-Lite Timer from Roa Logic is a precision timing module designed to comply with the RISC-V Privileged specification. This timer is engineered to manage time-sensitive operations within systems that utilize the AHB-Lite bus protocol, ensuring accurate timing for a variety of applications. By providing robust timer functionalities, the AHB-Lite Timer assists in overseeing operations where precise timing is crucial, such as coordinating tasks within embedded systems or managing periods in control processes. Its compliance with RISC-V standards ensures that it integrates seamlessly with systems based on this widely adopted open standard, enhancing compatibility and performance. Developers can take advantage of Roa Logic's comprehensive support materials, which include detailed documentation and pre-configured test environments, to facilitate the easy integration of the timer into existing designs. This support infrastructure is indicative of Roa Logic's commitment to simplifying the adoption and effective utilization of its sophisticated IP offerings within diverse system architectures.
Silicon Creations' Analog Glue solutions provide essential analog functionalities to complete custom SoC designs seamlessly. These functional blocks, which constitute buffer and bandgap reference circuits, are vital for seamless on-chip clock distribution and ensure low-jitter operations. Analog Glue includes crucial components such as power-on reset (POR) generators and bridging circuits to support various protocols and interfaces within SoCs. These supplementary macros are crafted to complement existing PLLs and facilities like SerDes, securing reliable signal transmission under varied operating circumstances. Serving as the unsung heroes of chip integration, these Analog Glue functions mitigate the inevitable risks of complex SoC designs, supporting efficient design flows and effective population of chip real estate. Thus, by emphasizing critical system coherency, they enhance overall component functionality, providing a stable infrastructure upon which additional system insights can be leveraged.
The HOTLink II Product Suite is another remarkable offering from Great River Technology. Built to complement their ARINC 818 suite, HOTLink II provides an integrated framework for crafting high-performance digital data links. This suite ensures seamless, secure, and reliable data transmission over fiber or copper cables across various platforms. Developed with a focus on flexibility and functionality, the HOTLink II capabilities enhance system integrators' ability to deploy effective communication solutions within aircraft and other demanding environments. The emphasis on robust, low-latency data transfer makes it an ideal choice for real-time applications where precision and reliability are paramount. Broad compatibility is a hallmark of HOTLink II, facilitating integration into diverse infrastructures. Backed by Great River Technology's expertise and support, customers are empowered to advance their system communication capabilities efficiently and cost-effectively.
Silicon Creations crafts highly reliable LVDS interfaces designed to meet diverse application needs, going from bi-directional I/Os to specialized uni-directional configurations. Spanning process compatibilities from 90nm CMOS to advanced 7nm FinFET, these interfaces are a cornerstone for high-speed data communication systems, thriving particularly in video data transmission and chip-to-chip communications. Supporting robust data rates over multiple channels, the LVDS Interfaces guarantee flexible programmability and protocol compatibility with standards such as FPD-Link and Camera-Link. They capitalize on proven PLL and CDR architectures for superior signal integrity and error-free data transfers. Operating efficiently in various technology nodes, they remain highly effective across collaborative chipset environments. The interfaces are fortified with adaptable features like dynamic phase alignment to stabilize data sequences and on-die termination options for superior signal integrity. Their proven record places them as a critical enabler in applications where consistent high-speed data transfer is paramount, demonstrating Silicon Creations’ prowess in delivering industry-leading communication solutions.
The Apodis family of Optical Transport Network processors adheres to ITU-T standards, offering a comprehensive suite for signal termination, processing, and multiplexing. Designed to handle both SONET/SDH and Ethernet client services, these processors map signals to Optical Transport Network (OTN), empowering versatile any-port, any-service configurations. Apodis processors are notable for their capacity to support up to 16 client ports and four 10G OTN line ports, delivering bandwidth scalability up to 40G, crucial for wireless backhaul and fronthaul deployments. With a robust, non-blocking OTN switching fabric, Apodis facilitates seamless client-to-line and line-to-line connections while optimally managing network bandwidth. This adaptability makes the Apodis processors an ideal choice for next-generation access networks and optical infrastructures.
Clock generation solutions from Analog Circuit Works are engineered to pair seamlessly with other IP products, enhancing the functionality and performance of integrated systems. Their offerings focus on providing consistent, reliable clock signals that are essential for synchronizing complex digital circuits, thus playing a pivotal role in maintaining efficient system operation. These solutions cater to varying clock frequencies, tailored to fit a diverse set of process technologies. Analog Circuit Works capitalizes on their ability to design optimized clock circuits that cater to both high-frequency and optimized low-frequency operations, ensuring that they meet specific design requirements while facilitating smoother integration into diverse application environments. The clock generation IP serves as a backbone for ensuring operational timing precision within devices, providing foundational support that enhances the overall synchronization and performance of intricate electronic systems. This reliability and adaptability make these solutions vital in complex electronics where time-sensitive operations are critical.
The Ultra-Low Latency 10G Ethernet MAC from Chevin Technology is tailored for environments where speed and minimal delay are critical. Designed with a focus on reducing latency, this IP core enables high-frequency traders and ultra-fast data acquisition systems to operate with unparalleled efficiency. By using advanced algorithms and streamlined architecture, it achieves extremely low latencies, contributing to faster processing and decision-making. This Ethernet MAC supports full 10 Gbps bandwidth and operates efficiently across a varied range of data-intensive applications. It remains highly customizable, allowing integration with a variety of protocols and applications, thus catering to specific project needs without compromising on speed or performance. As a result, this MAC is particularly suited to sectors where time is of the essence, such as financial services, automated trading systems, and real-time data streaming. Chevin Technology also provides extensive support and documentation to ensure that users can achieve the best possible results from this advanced IP.
xcore.ai is a powerful platform tailored for the intelligent IoT market, offering unmatched flexibility and performance. It boasts a unique multi-threaded micro-architecture that provides low-latency and deterministic performance, perfect for smart applications. Each xcore.ai contains 16 logical cores distributed across two multi-threaded processor tiles, each equipped with 512kB of SRAM and capable of both integer and floating-point operations. The integrated interprocessor communication allows high-speed data exchange, ensuring ultimate scalability across multiple xcore.ai SoCs within a unified development environment.
The NeuroVoice chip by Polyn Technology is engineered to improve voice processing capabilities for a variety of consumer electronic devices, particularly focusing on addressing challenges associated with traditional digital voice solutions. Built on the NASP platform, this AI chip is tailored to operate efficiently in noisy environments without relying on cloud-based processing, thus ensuring privacy and reducing latency. A key feature of NeuroVoice is its ultra-low power consumption, which allows continuous device operation even in power-sensitive applications like wearables and smart home devices. It includes abilities such as always-on voice activity detection, smart voice control, speaker recognition, and real-time voice extraction. This amalgamation of capabilities makes the NeuroVoice a versatile component in enhancing voice-controlled systems' efficacy. NeuroVoice stands out by seamlessly integrating into devices, offering users the advantage of precise voice recognition and activity detection with minimal energy demands. It further differentiates itself by delivering clear communication even amidst irregular background noises, setting a new benchmark for on-device audio processing with its advanced neural network-driven design.
The Ethernet Real-Time Publish-Subscribe (RTPS) IP Core presents a complete hardware-based solution for the Ethernet RTPS protocol, enhancing real-time data distribution across complex network settings. Designed to meet the demands of high-performance environments, this core ensures minimal latency in data transfers, maintaining the integrity and synchronization essential for time-sensitive operations. The RTPS core supports intricate network systems demanding reliability and speed, making it indispensable in communication infrastructures where real-time data dissemination is paramount. Its robust design ensures adaptability and seamless integration into existing Ethernet platforms, empowering mission-critical operations with reliable data flow capabilities. The RTPS solution is vital for defense and aerospace industries that rely on expedited and accurate data exchanges, supporting agile and responsive decision-making processes.
The pPLL03F-GF22FDX is tailored for performance computing applications, providing an all-digital Fractional-N PLL with a focus on low jitter and compact design. Operating at frequencies up to 4GHz and offering jitter capabilities below 10 picoseconds RMS, it is optimal for clocking solutions in systems requiring stringent timing accuracy, such as high-performance computing and signal processing applications. This PLL leverages Perceptia's advanced all-digital PLL technology, ensuring consistent performance across various semiconductor processes. It is well-suited for systems with complex clock domains, providing multiple outputs through programmable postscalers and an integrated power supply regulator for efficient power management. The pPLL03F can operate both in integer-N and fractional-N modes, extending flexibility in clock frequency configuration. Ideal for complex system-on-chip (SoC) designs, the pPLL03F-GF22FDX minimizes area usage with its compact die size of less than 0.01 square millimeters. Its low power requirements, under 5mW, make it a favorable choice for innovative digital designs demanding both reliability and energy efficiency. Available in a variety of process nodes, it seamlessly integrates into diverse design environments.
The GV380 is a compact and powerful GPU IP designed to handle complex vector graphics with ease. This OpenVG 1.1 compliant GPU leverages a fourth generation architecture that minimizes CPU load while maximizing pixel performance in vector processing. The IP is ideal for embedded systems needing enhanced 2D graphics performance. It can seamlessly integrate with digital cameras and similar devices to render high-quality graphics without burdening the central processing unit. This efficiency is crucial in environments where processing capacity and battery life are valued. By offering substantial gains in pixel processing through innovative architectural improvements, the GV380 enables richer graphics and smoother interactions in embedded applications, supporting enhanced user experiences.
Silicon Library Inc. provides a DisplayPort/eDP solution that forms a connection backbone in modern digital displays, supporting DP/eDP 1.4 standards. This interface IP is pivotal in ensuring pristine video and audio delivery specially adapted for use in monitors, laptops, and high-resolution screens. Crafted to handle significant data throughputs, this IP ensures seamless integration into high-end display systems. Its robust design allows for the smooth transfer of high-definition content, eliminating bottlenecks that are common in high-data environments. This efficiency is vital for next-generation devices that rely on Prompt rendering and delivery of complex visual data. Designed with versatility in mind, the DisplayPort/eDP caters to both embedded device needs and standalone display needs, offering exceptional performance and reliability. It's an essential component for manufacturers looking to implement top-grade visual technologies in devices aiming for a premium user experience.
The Nerve IIoT Platform is a comprehensive solution for machine builders, offering cloud-managed edge computing capabilities. This innovative platform delivers high levels of openness, security, flexibility, and real-time data handling, enabling businesses to embark on their digital transformation journeys. Nerve's architecture allows for seamless integration with a variety of hardware devices, from basic gateways to advanced IPCs, ensuring scalability and operational efficiency across different industrial settings. Nerve facilitates the collection, processing, and analysis of machine data in real-time, which is crucial for optimizing production and enhancing operational efficiency. By providing robust remote management functionalities, businesses can efficiently handle device operations and application deployments from any location. This capacity to manage data flows between the factory floor and the cloud transitions enterprises into a new era of digital management, thereby minimizing costs and maximizing productivity. The platform also supports multiple cloud environments, empowering businesses to select their preferred cloud service while maintaining operational continuity. With its secure, IEC 62443-4-1 certified infrastructure, Nerve ensures that both data and applications remain protected from cyber threats. Its integration of open technologies, such as Docker and virtual machines, further facilitates rapid implementation and prototyping, enabling businesses to adapt swiftly to ever-changing demands.
The AXI4 DMA Controller by Digital Blocks provides robust multi-channel direct memory access across various systems, capable of managing up to 16 independent data transfers. It supports scatter-gather data management and integrates flexibly with AXI4 interfaces for efficient data movement and processing, ideal for tasks ranging from simple to complex data throughput requirements.
The KL530 is built with an advanced heterogeneous AI chip architecture, designed to enhance computing efficiency while reducing power usage. Notably, it is recognized as the first in the market to support INT4 precision and transformers for commercial applications. The chip, featuring a low-power ARM Cortex M4 CPU, delivers impressive performance with 1 TOPS@INT 4 computing power, providing up to 70% higher processing efficiency compared to INT8 architectures. Its integrated smart ISP optimizes image quality, supporting AI models like CNN and RNN, suitable for IoT and AIoT ecosystems.
The Flexibilis Ethernet Switch (FES) is a versatile Ethernet Layer-2 switch IP designed to deliver high-speed, reliable packet forwarding across a network. With triple-speed ranging from 10 Mbps to 1 Gbps, FES supports full-duplex Ethernet interfaces, enhancing data transfer efficiency and network performance. Its design emphasizes seamless integration within programmable hardware environments, complying with IEEE1588v2 standards for time synchronization. FES is engineered for scalability, offering configurations that range from 3-port to 12-port setups, thereby providing flexibility in supporting various network sizes and applications. It includes support for a variety of interface types, such as MII, GMII, and others, enhancing its compatibility with diverse network setups. As part of its robust feature set, FES incorporates packet filtering and Virtual LAN (VLAN) tagging for optimized traffic management. This switch IP core is adept at handling the demands of high-availability networks, with advanced memory management features that prevent resource bottlenecks. By minimizing latency and maximizing throughput, FES is ideal for applications that require reliable communication such as industrial automation and telecommunication networks, reinforcing Flexibilis' reputation for delivering resilient and high-performing network solutions.
The C100 is designed to enhance IoT connectivity and performance with its highly integrated architecture. Built around a robust 32-bit RISC-V CPU running up to 1.5GHz, this chip offers powerful processing capabilities ideal for IoT applications. Its architecture includes embedded RAM and ROM memory, facilitating efficient data handling and computations. A prime feature of the C100 is its integration of Wi-Fi components and various transmission interfaces, enhancing its utility in diverse IoT environments. The inclusion of an ADC, LDO, and a temperature sensor supports myriad applications, ensuring devices can operate in a wide range of conditions and applications. The chip's low power consumption is a critical factor in this design, enabling longer operation duration in connected devices and reducing maintenance frequency due to less charging or battery replacement needs. This makes the C100 chip suitable for secure smart home systems, interactive toys, and healthcare devices.
The Hyperspectral Imaging System developed by Imec represents a significant advancement in the realm of imaging technology. This sophisticated system is capable of capturing and processing a wide spectrum of wavelengths simultaneously, making it ideal for detailed spectral analysis in both industrial and research applications. This imaging system is instrumental in providing accurate and high-resolution data that can be crucial in fields like agriculture, environmental monitoring, and medical diagnostics. Imec's Hyperspectral Imaging System is notable for its integration into small and efficient devices, enabling portable and flexible use in various scenarios. The system's design leverages cutting-edge nanoelectronics to ensure that it is both lightweight and highly functional, offering unparalleled performance on the go. Its ability to capture detailed spectral information expands its utility across multiple disciplines, making it a versatile tool for addressing complex analytical challenges. The unique technology behind this system is grounded in Imec's expertise in photonics and CMOS sensors, ensuring superior sensitivity and precision. This hyperspectral imaging technology is designed to provide real-time, reliable information with a high degree of accuracy, supporting applications that require detailed spectroscopic data, thus empowering industries to make more informed decisions.
iWave Global delivers the Serial FPDP (sFPDP) solution, a high-bandwidth, low-latency serial communication protocol widely deployed in high-performance computing systems. This technology is optimized for applications that require rapid data transport, such as radar and high-definition video processing, making it a vital tool in industrial and defense sectors. By supporting high throughput rates, the Serial FPDP ensures timely and reliable data transmission, crucial for systems where time sensitivity and data integrity are paramount. The solution is particularly designed to address real-time data operations, ensuring that data handling meets rigorous industry standards. With its robust design, the Serial FPDP accommodates various network topologies, allowing for the flexible deployment of communication systems. This flexibility and performance make it highly applicable in environments where system designers demand unobstructed high-speed data transfer capabilities.
The 2D FFT core is engineered to deliver fast processing for two-dimensional FFT computations, essential in image and video processing applications. By utilizing both internal and external memory effectively, this core is capable of handling large data sets typical in medical imaging or aerial surveillance systems. This core leverages Dillon Engineering’s ParaCore Architect utility to maximize flexibility and efficiency. It takes advantage of a two-engine design, where data can flow between stages without interruption, ensuring high throughput and minimal memory delays. Such a robust setup is vital for applications where swift processing of extensive data grids is crucial. The architecture is structured to provide consistent, high-quality transform computations that are essential in applications where accuracy and speed are non-negotiable. The 2D FFT core, with its advanced design parameters, supports the varied demands of modern imaging technology, providing a reliable tool for developers and engineers working within these sectors.
The DB9000AXI Display Controller is an advanced solution for LCD and OLED panels, supporting resolutions ranging from 320x240 up to 1920x1080 in its standard release, with capabilities expanding to 4K and 8K in advanced modes. This controller integrates with frame buffer memory via the AMBA AXI protocol fabric, offering programmable resolutions. Optional features include overlay windows, hardware cursor, and advanced color space conversion.
The GenAI v1-Q from RaiderChip brings forth a specialized focus on quantized AI operations, reducing memory requirements significantly while maintaining impressive precision and speed. This innovative accelerator is engineered to execute large language models in real-time, utilizing advanced quantization techniques such as Q4_K and Q5_K, thereby enhancing AI inference efficiency especially in memory-constrained environments. By offering a 276% boost in processing speed alongside a 75% reduction in memory footprint, GenAI v1-Q empowers developers to integrate advanced AI capabilities into smaller, less powerful devices without sacrificing operational quality. This makes it particularly advantageous for applications demanding swift response times and low latency, including real-time translation, autonomous navigation, and responsive customer interactions. The GenAI v1-Q diverges from conventional AI solutions by functioning independently, free from external network or cloud auxiliaries. Its design harmonizes superior computational performance with scalability, allowing seamless adaptation across variegated hardware platforms including FPGAs and ASIC implementations. This flexibility is crucial for tailoring performance parameters like model scale, inference velocity, and power consumption to meet exacting user specifications effectively. RaiderChip's GenAI v1-Q addresses crucial AI industry needs with its ability to manage multiple transformer-based models and confidential data securely on-premises. This opens doors for its application in sensitive areas such as defense, healthcare, and financial services, where confidentiality and rapid processing are paramount. With GenAI v1-Q, RaiderChip underscores its commitment to advancing AI solutions that are both environmentally sustainable and economically viable.
The THOR platform is a versatile tool for developing application-specific NFC sensor and data logging solutions. It incorporates silicon-proven IP blocks, creating a comprehensive ASIC platform suitable for rigorous monitoring and continuous data logging applications across various industries. THOR is designed for accelerated development timelines, leveraging low power and high-security features. Equipped with multi-protocol NFC capabilities and integrated temperature sensors, the THOR platform supports a wide range of external sensors, enhancing its adaptability to diverse monitoring needs. Its energy-efficient design allows operations via energy harvesting or battery power, ensuring sustainability in its applications. This platform finds particular utility in sectors demanding precise environmental monitoring and data management, such as logistics, pharmaceuticals, and industrial automation. The platform's capacity for AES/DES encrypted data logging ensures secure data handling, making it a reliable choice for sectors with stringent data protection needs.
The Dual-Drive™ Power Amplifier FCM1401 exemplifies advanced engineering in power amplification, designed specifically for extreme efficiency in wireless communication devices. Operating at a center frequency of 14 GHz, it boasts a sophisticated architecture that minimizes silicon area while enhancing performance metrics. One of the standout features of the FCM1401 is its impressive core drain efficiency, which reaches up to 62%, offering significant power savings and extended battery life for end users. Such efficiencies are particularly crucial in mobile devices, where power remains a critical resource. Moreover, this power amplifier features a dual-stage design to facilitate better signal strength and lower transmission losses. With an optimally configured supply voltage range, the FCM1401 performs without efficiency bottlenecking, crucial for systems with constrained power budgets. Its meticulous construction results in an efficiency at device output around 70%, allowing it to outperform competitors across various metrics. These enhancements not only make the FCM1401 ideal for mobile and satellite communications but also align perfectly with initiatives to lower telecommunication costs through energy-efficient technology. Supported by a drain efficiency that peaks even under full load conditions, Falcomm’s FCM1401 assures users of reliability under diverse operational scenarios. The assurance of minimal loss in complex QAM scenarios further underscores its potential for diverse communication applications. This exemplary power amplifier serves as a testament to Falcomm's commitment to innovation, combining unprecedented efficiency with practical applications in everyday technology.
The High-Speed Phase-Locked Loop (PLL) from SkyeChip is crafted for optimal frequency synthesis in ICs, supporting extensive range outputs from 300MHz to 3.2GHz. This flexibility is achieved through a richly configurable architecture that accommodates different division ratios. Built to support reference clock frequencies from 100MHz to 350MHz, it offers broad application versatility. Its VCO frequency range underscores its adaptability to various system needs, particularly in environments demanding high-speed and high-accuracy. Due to its low power consumption and stability, this PLL is ideal for systems requiring consistent and precise clock distribution. It is suited for a range of applications from consumer electronics to more intensive industrial systems requiring robust clock management solutions.
The Tentiva Video FMC is a versatile board crafted for sophisticated video processing tasks. Its modular setup, featuring two PHY slots, facilitates easy customization and expansion. These slots are equipped to support high-speed data communication, providing up to 20 Gbps, making it suitable for a range of digital video projects. The Tentiva board's compatibility with various PHY cards, including the DisplayPort 2.1 TX and RX cards, allows it to flexibly manage video transmission and reception tasks. These cards are specifically designed to work with DisplayPort-compatible devices, such as monitors and GPUs, ensuring seamless and reliable performance in handling DisplayPort video signals. Furthermore, the Tentiva is meticulously crafted to integrate with FPGA development boards that incorporate FMC headers. This capability offers extensive adaptability and expands its utilities in numerous development environments, thereby making it an essential tool for professionals in digital video processing.
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