All IPs > Graphic & Peripheral
Graphic & Peripheral Semiconductor IPs are critical components in the design and development of electronics that require efficient and robust control over multimedia and peripheral functions. This category of semiconductor IP encompasses a wide array of technologies used to manage and optimize graphics rendering, audio processing, data communication, and peripheral interfaces in electronic devices such as computers, smartphones, tablets, and other smart gadgets.
In this vivid category, you'll find a variety of subcategories tailored to specific functionalities. For instance, the Graphics Processing Unit (GPU) semiconductor IPs are pivotal for rendering images and video, essential in gaming, virtual reality, and professional content creation. Audio Controllers handle sound processing, ensuring crisp and seamless audio output, crucial for devices prioritizing high-quality sound delivery.
Other key components in the Graphic & Peripheral category include Peripheral Controllers, which facilitate the integration of various input/output devices, enhancing the device's interactivity and user experience. DMA Controllers are responsible for moving data efficiently between memory and peripherals, minimizing the CPU load. These IPs enhance overall system performance by ensuring that data flow is smooth and uninterrupted.
From Clock Generators that synchronize the entire system's operations to Interrupt Controllers managing priority tasks, each semiconductor IP in this category plays a unique role in ensuring that electronic devices operate at peak efficiency. By exploring these subcategories, companies and developers can find the precise semiconductors needed to support cutting-edge multimedia and peripheral technologies in their next product launch.
The Akida 2nd Generation processor further advances BrainChip's AI capabilities with enhanced programmability and efficiency for complex neural network operations. Building on the principles of its predecessor, this generation is optimized for 8-, 4-, and 1-bit weights and activations, offering more robust activation functions and support for advanced temporal and spatial neural networks. A standout feature of the Akida 2nd Generation is its enhanced teaching capability, which includes learning directly on the chip. This enables the system to perform one-shot and few-shot learning, significantly boosting its ability to adapt to new tasks without extensive reprogramming. Its architecture supports more sophisticated machine learning models such as Convolutional Neural Networks (CNNs) and Spatio-Temporal Event-Based Neural Networks, optimizing them for energy-efficient application at the edge. The processor's design reduces the necessity for host CPU involvement, thus minimizing communication overhead and conserving energy. This makes it particularly suitable for real-time data processing applications where quick and efficient data handling is crucial. With event-based hardware that accelerates processing, the Akida 2nd Generation is designed for scalability, providing flexible solutions across a wide range of AI-driven tasks.
The KL730 AI SoC is an advanced powerhouse, utilizing third-generation NPU architecture to deliver up to 8 TOPS of efficient computing. This architecture excels in both CNN and transformer applications, optimizing DDR bandwidth usage. Its robust video processing features include 4K 60FPS video output, with exceptional performance in noise reduction, dynamic range, and low-light scenarios. With versatile application support ranging from intelligent security to autonomous driving, the KL730 stands out by delivering exceptional processing capabilities.
Sunplus’s LVDS IP is designed for efficient data transmission in applications requiring low power consumption and high noise immunity. This Low Voltage Differential Signaling technology is particularly effective for transferring large amounts of data over long distances with minimal signal degradation. Ideal for use in display panels and digital communication systems, LVDS technology offers high-speed data rates while maintaining low electromagnetic interference (EMI). This allows for clearer and more reliable data communication, essential for high-resolution video and complex data streams. The architecture supports scalability and adaptability, making it suitable for various applications including video displays, automotive infotainment systems, and industrial communications. It is engineered to maintain signal integrity even under challenging environmental conditions, a testament to its robustness and reliability.
Overview: The UCIe IP supports multiple protocols (CXL/PCIe/Streaming) to connect chiplets, reducing overall development cycles for IPs and SOCs. With flexible application and PHY interfaces, The UCIe IP is ideal for SOCs and chiplets. Key Features:  Supports UCIe 1.0 Specification  Supports CXL 2.0 and CXL 3.0 Specifications  Supports PCIe Gen6 Specification  Supports PCIe Gen5 and older versions of PCIe specifications  Supports single and two-stack modules  Supports CXL 2.0 68Byte flit mode with Fallback mode for PCIe non-flit mode transfers  Supports CXL 3.0 256Byte flit mode  Supports PCIe Gen6 flit mode  Configurable up to 64-lane configuration for Advanced UCIe modules and 16 lanes for Standard UCIe modules  Supports sideband and Mainband signals  Supports Lane repair handling  Data to clock point training and eye width sweep support from transmitter and receiver ends  UCIe controller can work as Downstream or Upstream  Main Band Lane reversal supported  Dynamic sense of normal and redundant clock and data lines activation  UCIe enumeration through DVSEC  Error logging and reporting supported  Error injection supported through Register programming  RDI/FDI PM entry, Exit, Abort flows supported  Dynamic clock gang at adapter supported Configurable Options:  Maximum link width (x1, x2, x4, x8, x16)  MPS (128B to 4KB)  MRRS (128B to 4KB)  Transmit retry/Receive buffer size  Number of Virtual Channels  L1 PM substate support  Optional Capability Features can be Configured  Number of PF/VFDMA configurable Options  AXI MAX payload size Variations  Multiple CPI Interfaces (Configurable)  Cache/memory configurable  Type 0/1/2 device configurable
The AI Camera Module is an innovative solution designed to bring cutting-edge AI capabilities to camera systems. Known for its enhanced image quality and AI-based processing, this module integrates seamlessly with a wide array of systems to deliver superior performance in real-time scenarios. It is equipped to handle complex image processing tasks, making it invaluable for applications ranging from security to AI-driven analytics. By incorporating the latest AI advancements into its operation, this module facilitates heightened awareness and analysis capabilities across various sectors. Altek's AI Camera Module emphasizes high-resolution image capture, ensuring that every detail is accurately recorded and processed for precise analysis. This technology not only supports high-definition imaging but also optimizes power consumption, making it suitable for integration into IoT and edge computing environments. Such adaptations are crucial for systems requiring constant, real-time image processing while retaining high operational efficiency. The module's design also promotes adaptability, allowing for custom configurations that meet specific client requirements. Its capability to integrate AI functionalities directly into the camera hardware enhances its appeal in industries focused on automation, surveillance, and smart analytics. This product affirms Altek's role in pioneering technological advancements that align with current and future demands for intelligent, efficient, and scalable solutions.
Overview: The Expanded Serial Peripheral Interface (xSPI) Master/Slave controller offers high data throughput, low signal count, and limited backward compatibility with legacy SPI devices. It is designed to connect xSPI Master/Slave devices in computing, automotive, Internet of Things, embedded systems, and mobile processors to various peripherals such as non-volatile memories, graphics peripherals, networking devices, FPGAs, and sensor devices. Key Features:  Compliance with JEDEC standard JESD251 eXpanded SPI for Non-Volatile Memory Devices, Version 1.0  Support for Single master and multiple slaves per interface port  Single Data Rate (SDR) and Double Data Rate (DDR) support  Source synchronous clocking  Deep Power Down (DPD) enter and exit commands  Eight IO ports in standard, expandable based on system requirements  Optional Data Strobe (DS) for write masking  bit wide SDR transfer support  Profile 1.0 Commands for non-volatile memory device management  Profile 2.0 Commands for read or write data for various slave devices Applications:  Consumer Electronics  Defense & Aerospace  Virtual Reality  Augmented Reality  Medical  Biometrics  Automotive Devices  Sensor Devices
xcore.ai stands as a cutting-edge processor that brings sophisticated intelligence, connectivity, and computation capabilities to a broad range of smart products. Designed to deliver optimal performance for applications in consumer electronics, industrial control, and automotive markets, it efficiently handles complex processing tasks with low power consumption and rapid execution speeds. This processor facilitates seamless integration of AI capabilities, enhancing voice processing, audio interfacing, and real-time analytics functions. It supports various interfacing options to accommodate different peripheral and sensor connections, thus providing flexibility in design and deployment across multiple platforms. Moreover, the xcore.ai ensures robust performance in environments requiring precise control and high data throughput. Its compatibility with a wide array of software tools and libraries enables developers to swiftly create and iterate applications, reducing the time-to-market and optimizing the design workflows.
Our Expanded Serial Peripheral Interface (JESD251) Master controller features a low signal count and high data bandwidth, making it ideal for use in computing, automotive, Internet of Things, embedded systems, and mobile system processors. It connects multiple sources of Serial Peripheral Interface (xSPI) slave devices, including nonvolatile memories, graphics peripherals, networking peripherals, FPGAs, and sensor devices. Features • Compliant with JEDEC standard JESD251 expanded Serial Peripheral Interface (xSPI) for Non-Volatile Memory Devices, Version 1.0. • Supports a single master and multiple slaves per interface port. • Supports Single Data Rate and Double Data Rate. • Supports source synchronous clocking. • Supports data transfer rates up to: o 400MT/s (200MHz Clock) o 333MT/s (167MHz Clock) o 266MT/s (133MHz Clock) o 200MT/s (100MHz Clock) • Supports Deep Power Down (DPD) enter and exit commands. • Standard support for eight IO ports, with the possibility to increase IO ports based on system performance requirements. • Optional support for Data Strobe (DS) for writemasking. • Supports 1-bit wide SDR transfer. • Supports Profile 1.0 commands to manage nonvolatile memory devices. • Supports Profile 2.0 commands to read or writedata for any type of slave device. • Compatible with non-volatile memory arrays such as NOR Flash, NAND Flash, FRAM, and nvSRAM. • Compatible with volatile memory arrays such as SRAM, PSRAM, and DRAM. • Supports register-mapped input/output functions. • Supports programmable function devices such as FPGAs. Application • Consumer Electronics. • Defence & Aerospace. • Virtual Reality. • Augmented Reality. • Medical. • Biometrics (Fingerprints, etc). • Automotive Devices. • Sensor Devices. Deliverables • Verilog Source code. • User Guide. • IP Integration Guide. • Run and Synthesis script. • Encrypted Verification Testbench Environment. • Basic Test-suite.
The Aries fgOTN processor family is engineered according to the ITU-T G.709.20 fgOTN standard. This line of processors handles a variety of signals, including E1/T1, FE/GE, and STM1/STM4, effectively monitoring and managing alarms and performance metrics. Aries processors excel at fine-grain traffic aggregation, efficiently channeling fgODUflex traffic across OTN lines to support Ethernet, SDH, PDH client services. Their capacity to map signals to fgODUflex containers, which are then multiplexed into higher order OTN signals, demonstrates their versatility and efficiency. By allowing cascaded configurations with other Aries devices or Apodis processors, Aries products optimize traffic routes through OTN infrastructures, positioning them as essential components in optical networking and next-generation access scenarios.
Silicon Creations delivers precision LC-PLLs designed for ultra-low jitter applications requiring high-end performance. These LC-tank PLLs are equipped with advanced digital architectures supporting wide frequency tuning capabilities, primarily suited for converter and PHY applications. They ensure exceptional jitter performance, maintaining values well below 300fs RMS. The LC-PLLs from Silicon Creations are characterized by their capacity to handle fractional-N operations, with active noise cancellation features allowing for clean signal synthesis free of unwanted spurs. This architecture leads to significant power efficiencies, with some IPs consuming less than 10mW. Their low footprint and high frequency integrative capabilities enable seamless deployments across various chip designs, creating a perfect balance between performance and size. Particular strength lies in these PLLs' ability to meet stringent PCIe6 reference clocking requirements. With programmable loop bandwidth and an impressive tuning range, they offer designers a powerful toolset for achieving precise signal control within cramped system on chip environments. These products highlight Silicon Creations’ commitment to providing industry-leading performance and reliability in semiconductor design.
Chimera GPNPU provides a groundbreaking architecture, melding the efficiency of neural processing units with the flexibility and programmability of processors. It supports a full range of AI and machine learning workloads autonomously, eliminating the need for supplementary CPUs or GPUs. The processor is future-ready, equipped to handle new and emerging AI models with ease, thanks to its C++ programmability. What makes Chimera stand out is its ability to manage a diverse array of workloads within a singular processor framework that combines matrix, vector, and scalar operations. This harmonization ensures maximum performance for applications across various market sectors, such as automotive, mobile devices, and network edge systems. These capabilities are designed to streamline the AI development process and facilitate high-performance inference tasks, crucial for modern gadget ecosystems. The architecture is fully synthesizable, allowing it to be implemented in any process technology, from current to advanced nodes, adjusting to desired performance targets. The adoption of a hybrid Von Neuman and 2D SIMD matrix design supports a broad suite of DSP operations, providing a comprehensive toolkit for complex graph and AI-related processing.
RaiderChip's GenAI v1 is a pioneering hardware-based generative AI accelerator, designed to perform local inference at the Edge. This technology integrates optimally with on-premises servers and embedded devices, offering substantial benefits in privacy, performance, and energy efficiency over traditional hybrid AI solutions. The design of the GenAI v1 NPU streamlines the process of executing large language models by embedding them directly onto the hardware, eliminating the need for external components like CPUs or internet connections. With its ability to support complex models such as the Llama 3.2 with 4-bit quantization on LPDDR4 memory, the GenAI v1 achieves unprecedented efficiency in AI token processing, coupled with energy savings and reduced latency. What sets GenAI v1 apart is its scalability and cost-effectiveness, significantly outperforming competitive solutions such as Intel Gaudi 2, Nvidia's cloud GPUs, and Google's cloud TPUs in terms of memory efficiency. This solution maximizes the number of tokens generated per unit of memory bandwidth, thus addressing one of the primary limitations in generative AI workflow. Furthermore, the adept memory usage of GenAI v1 reduces the dependency on costly memory types like HBM, opening the door to more affordable alternatives without diminishing processing capabilities. With a target-agnostic approach, RaiderChip ensures the GenAI v1 can be adapted to various FPGAs and ASICs, offering configuration flexibility that allows users to balance performance with hardware costs. Its compatibility with a wide range of transformers-based models, including proprietary modifications, ensures GenAI v1's robust placement across sectors requiring high-speed processing, like finance, medical diagnostics, and autonomous systems. RaiderChip's innovation with GenAI v1 focuses on supporting both vanilla and quantized AI models, ensuring high computation speeds necessary for real-time applications without compromising accuracy. This capability underpins their strategic vision of enabling versatile and sustainable AI solutions across industries. By prioritizing integration ease and operational independence, RaiderChip provides a tangible edge in applying generative AI effectively and widely.
Silicon Creations' Free Running Oscillators provide dependable timing solutions for a range of applications such as watchdog timers and core clock generators in low-power systems. These oscillators, crafted with compactness and efficiency in mind, support a gamut of processes from 65nm to the latest 3nm technologies. These oscillators excel in low power consumption, often requiring less than 30µW during operation. Their robust design ensures they deliver high precision over a temperature range from -40°C to 125°C with supply voltage variabilities factored in. The simplicity in design negates the need for external components, promoting easier integration and reduced overall system complexity. Precise tuning capabilities allow for accuracy levels up to ±1.5% after process trimming, ensuring outstanding performance in volatile environmental conditions. This level of reliability makes them ideal for integration into various consumer electronics, automotive controls, and other precision-demanding applications where space and power constraints are critical.
Overview: PCIe Gen6 is a high-speed, layered protocol interconnect interface supporting speeds up to 64GT/s, featuring multi-lanes and links. The Transport, Data Link, and Physical layers specified in the PCIe specification are implemented, along with PIPE interface logic connecting to PHY and AXI Bridging logic for application connectivity. Specifications:  Supports PCIe Gen 6 and Pipe 5.X Specifications  Core supports Flit and non-Flit Mode  Lane Configurations: X16, X8, X4, X2, X1  AXI MM and Streaming supported  Supports Gen1 to Gen6 modes  Data rate support of 2.5 GT/s, 5 GT/s, 8 GT/s, 16 GT/s, 32 GT/s, 64 GT/s  PAM support when operating at 64GT/s  Encoding/Decoding Support: 8b/10b, 128b/130b, 1b/1b  Supports SerDes and non-SerDes architecture  Optional DMA support as plugin module  Support for alternate negotiation protocol  Can operate as an endpoint or root complex  Lane polarity control through register  Lane de-skew supported  Support for L1 states and L0P  Support for SKP OS add/removal and SRIS mode  No equalization support through configuration  Deemphasis negotiation support at 5GT/s  Supports EI inferences in all modes  Supports PTM, OBFF, MSI, MSIX, Power management, and all message formats
The Akida IP platform is a revolutionary neural processor inspired by the workings of the human brain to achieve unparalleled cognitive capabilities and energy efficiency. This self-contained neural processor utilizes a scalable architecture that can be configured from 1 to 128 nodes, each capable of supporting 128 MAC operations. It allows for the execution of complex neural network operations with minimal power and latency, making it ideal for edge AI applications in vision, audio, and sensor fusion. The Akida IP supports multiple data formats including 4-, 2-, and 1-bit weights and activations, enabling the seamless execution of various neural networks across multiple layers. Its convolutional and fully-connected neural processors can perform multi-layered executions independently of a host CPU, enhancing flexibility in diverse applications. Additionally, its event-based hardware acceleration significantly reduces computation and communication loads, preserving host CPU resources and optimizing overall system efficiency. Silicon-proven, the Akida platform provides a cost-effective and secure solution due to its on-chip learning capabilities, supporting one-shot and few-shot learning methods. By maintaining sensitive data on-chip, the system offers improved security and privacy. Its extensive configurability ensures adaptability for post-silicon applications, making Akida an intelligent and scalable choice for developers. It is especially suited for implementations that require real-time processing and sophisticated AI functionalities at the edge.
iWave Global introduces the ARINC 818 Switch, a pivotal component in the management and routing of video data within avionics systems. Designed for applications that require efficient video data distribution and management, the switch is optimized for performance in environments with stringent data handling requirements. The switch's architecture supports a high level of bandwidth, allowing for the smooth routing of multiple video streams in real-time. Its design includes advanced features that ensure low-latency, error-free data transfer, integral to maintaining the integrity and reliability of video data in critical applications. Featuring robust interoperability characteristics, the ARINC 818 Switch easily integrates into existing systems, facilitating modular expansion and adaptability to new technological standards. It is indispensable for any aerospace project that involves complex video data management, providing a stable platform for video data routing and switching.
The ARINC 818 Product Suite is a comprehensive solution set designed to support the entire lifecycle of ARINC 818 enabled equipment. This suite offers tools and resources essential for developing, qualifying, testing, and simulating ARINC 818 products. It is recognized for its robust design and ability to address the complexities of high-performance avionics systems. Within the product suite, users can access the ARINC 818 Development Suite and Flyable Products, providing a framework for both development and in-field application. The suite is indispensable for organizations aiming to integrate ARINC 818 into their systems, ensuring precise data handling and compatibility. Great River Technology's experience in crafting over 100 mission-critical systems is embedded into the suite, offering unmatched expertise and dependability. By leveraging this suite, companies can ensure the reliable operation and seamless integration of ARINC 818 technologies.
EXOSTIV is an advanced FPGA capture solution designed to monitor and visualize internal FPGA signals operating at full speed. Particularly focused on providing efficient debugging and validation, EXOSTIV is invaluable for engineers dealing with complex FPGA designs that surpass the capabilities of traditional simulation methods. Its primary advantage lies in enabling full-speed analysis in real-world environments, minimizing production-level FPGA bugs and reducing total engineering costs. With its probe connectivity featuring QSFP28 and various compatible adapters, EXOSTIV ensures seamless integration with existing FPGA chips. It supports up to 4 transceivers at significant bandwidths, allowing comprehensive signal capture. The system's capacity to handle up to 65 Gbps ensures that a vast amount of data can be analyzed and stored, enabling engineers to uncover intricate design issues that would otherwise go unnoticed. EXOSTIV leverages powerful software environments to enhance usability and functionality. It includes tools like the Exostiv Core Inserter, which aids in the generation and modification of IP instances across multiple levels--from RTL to netlist insertion. These capabilities provide users with extensive control over their debug and validation processes, making the EXOSTIV a versatile addition to their FPGA development toolkit.
The KL520 AI SoC introduces edge AI with efficiency in size and power, setting a standard in the market for such technologies. Featuring a dual ARM Cortex M4 CPU, it serves as a versatile AI co-processor, supporting an array of smart devices. It’s designed for compatibility with various sensor technologies, enabling powerful 3D sensing capabilities.
Overview: The Multi-Protocol Accelerator IP is a versatile technology designed to support low latency and high bandwidth accelerators for efficient CPU-to-device and CPU-to-memory communication. It also enables switching for fan-out to connect more devices, memory pooling for increased memory utilization efficiency, and provides memory capacity with support for hot-plug, security enhancements, persistent memory support, and memory error reporting. Key Features:  CXL 3.0 Support: Compliant with CXL spec V3.X/V2.X  PCIe Compatibility: Supports PCIe spec 6.0/5.0  CPI Interface: Support for CPI Interface  AXI Interface: Configurable AXI master, AXI slave  Bus Support: PIPE/FLEX bus, Lane x1,x2,x4,x8,x16  Protocol Support: Gen3, Gen4, Gen5 & Gen6, Fallback Mode  Register Checks: Configuration and Memory Mapped registers  Dual Mode: Supports Dual Mode operation  Transfer Support: HBR/PBR & LOpt Transfers, Standard Cache and Mem Transfers  CXL Support: Can function as both CXL host and device  Data Transfer: Supports Standard IO, 68Byte Flit, and 256Byte Flit Transfers  FlexBus Features: FlexBus Link Features, ARB/MUX, ARB/MUX Bypass  Optimization: Latency Optimization, Credit Return Forcing, Empty Flits (Latency Optimized)  Power Management: Supports Power Management features  Enhancements: CXL IDE, RAS Features, Poison & Viral Handling, MLD/SLD  Testing: Compliance Testing and Error Scenarios support
Our Expanded Serial Peripheral Interface (JESD251) Slave controller offers high data throughput, low signal count, and limited backward compatibility with legacy Serial Peripheral Interface (SPI) devices. It is used to connect xSPI Master devices in computing, automotive, Internet of Things, embedded systems, and mobile system processors to non-volatile memories, graphics peripherals, networking peripherals, FPGAs, and sensor devices. Features • Compliant with JEDEC standard JESD251 expanded Serial Peripheral Interface (xSPI) for Non-Volatile Memory Devices, Version 1.0. • Supports Single Data Rate (SDR) and Double Data Rate (DDR). • Supports source synchronous clocking. • Supports data transfer rates up to: o 400MT/s (200MHz Clock) o 333MT/s (167MHz Clock) o 266MT/s (133MHz Clock) o 200MT/s (100MHz Clock) • Supports Deep Power Down (DPD) enter and exit commands. • Standard support for eight IO ports, with the possibility to increase IO ports based on system performance requirements. • Optional support for Data Strobe (DS) for timing reference. • Supports 1-bit wide SDR transfer. • Supports Profile 1.0 commands to manage nonvolatile memory devices. • Supports Profile 2.0 commands for reading or writing data for any type of slave device. • Compatible with non-volatile memory arrays such as NOR Flash, NAND Flash, FRAM, and nvSRAM. • Compatible with volatile memory arrays such as SRAM, PSRAM, and DRAM. • Supports register-mapped input/output functions. • Supports programmable function devices such as FPGAs. Application • Consumer Electronics. • Defence & Aerospace. • Virtual Reality. • Augmented Reality. • Medical. • Biometrics (Fingerprints, etc). • Automotive Devices. • Sensor Devices. Deliverables • Verilog Source code. • User Guide. • IP Integration Guide. • Run and Synthesis script. • Encrypted Verification Testbench Environment. • Basic Test-suite.
The AHB-Lite Multilayer Switch is a sophisticated interconnect solution designed to support multiple bus masters and slaves within an AMBA AHB-Lite system. It features high performance and low latency, facilitating efficient communication between various system components by providing a flexible interconnection fabric. This architecture can manage a significant number of simultaneous data transfers, optimizing the throughput in complex SoC environments. This switch fabric empowers designers to construct scalable systems with numerous processors and peripherals without compromising on speed or efficiency. Its configurability allows for tailored setups in terms of bus masters and slaves, supporting high-priority traffic schemes for enhanced system operations. By providing a robust and versatile solution, the AHB-Lite Multilayer Switch plays a crucial role in managing data flow, ensuring seamless operation across diverse embedded applications.
With cutting-edge NPU architecture, the KL630 AI SoC pushes the boundaries of performance efficiency and low energy consumption. It stands as a pioneering solution supporting Int4 precision and transformer neural networks, offering noteworthy performance for diverse applications. Anchored by an ARM Cortex A5 CPU, it boasts compute efficiency and energy savings, making it ideal for various edge devices.
eSi-Connect offers an extensive suite of AMBA-compliant peripheral IPs designed to streamline SoC integration. This suite encompasses versatile memory controllers, standard off-chip interface support, and essential control functions. Its configurability and compatibility with low-level software drivers make it suitable for real-time deployment in complex system architectures, promoting reliable connectivity across various applications.
The Ring PLLs offered by Silicon Creations illustrate a versatile clocking solution, well-suited for numerous frequency generation tasks within integrated circuit designs. Known for their general-purpose and specialized applications, these PLLs are crafted to serve a massive array of industries. Their high configurability makes them applicable for diverse synthesis needs, acting as the backbone for multiple clocking strategies across different environments. Silicon Creations' Ring PLLs epitomize high integration with functions tailored for low jitter and precision clock generation, suitable for battery-operated devices and systems demanding high accuracy. Applications span from general clocking to precise Audio Codecs and SerDes configurations requiring dedicated performance metrics. The Ring PLL architecture achieves best-in-class long-term and period jitter performance with both integer and fractional modes available. Designed to support high volumes of frequencies with minimal footprint, these PLLs aid in efficient space allocation within system designs. Their use of silicon-proven architectures and modern validation methodologies assure customers of high reliability and quick integration into existing SoC designs, emphasizing low risk and high reward configurations.
The AHB-Lite Timer is a robust timer module compliant with the RISC-V Privileged Specification 1.9.1, designed to provide precise timing and control within a system. This module is an integral part of complex SoC designs where accurate timing functions are essential. Its design offers flexibility and precision, making it ideal for a range of applications that demand reliable timekeeping and event management. The timer supports various counting modes and functions, allowing users to define cycles and generate interrupts based on time-based events. Its versatility and adaptability make it an indispensable component in managing scheduling and timing tasks within embedded systems. By integrating the AHB-Lite Timer, designers can enhance system efficiency and performance, ensuring responsive and accurate operational outcomes.
The PDM-to-PCM Converter from Archband Labs leads in transforming pulse density modulation signals into pulse code modulation signals. This converter is essential in applications where high fidelity of audio signal processing is vital, including digital audio systems and communication devices. Archband’s solution ensures accurate conversion, preserving the integrity and clarity of the original audio. This converter is crafted to seamlessly integrate with a wide array of systems, offering flexibility and ease-of-use in various configurations. Its robust design supports a wide range of input frequencies, making it adaptable to different signal environments. The PDM-to-PCM Converter also excels in minimizing latency and reducing overhead processing times. It’s engineered for environments where precision and sound quality are paramount, ensuring that audio signals remain crisp and undistorted during conversion processes.
The GH310 stands out as a high-performance GPU IP unit tailored specifically for 2D sprite graphics. This IP core is designed to couple high pixel processing capabilities with a minimal gate count, ensuring efficient performance for graphics-intensive tasks in embedded systems. Its design prioritizes power saving and performance balance, enabling it to handle demanding graphics with energy efficiency. The GH310 supports a broad range of applications, enhancing the user experience by offering smooth and vibrant sprite graphics, essential for various embedded system interfaces and displays. TAKUMI's GH310 IP embodies innovation in creating efficient and compact graphics solutions for embedded platforms. By maintaining efficient processing and low power consumption, the GH310 furthers TAKUMI's commitment to developing advanced technology solutions that meet the evolving needs of the electronics industry.
Silicon Creations crafts highly reliable LVDS interfaces designed to meet diverse application needs, going from bi-directional I/Os to specialized uni-directional configurations. Spanning process compatibilities from 90nm CMOS to advanced 7nm FinFET, these interfaces are a cornerstone for high-speed data communication systems, thriving particularly in video data transmission and chip-to-chip communications. Supporting robust data rates over multiple channels, the LVDS Interfaces guarantee flexible programmability and protocol compatibility with standards such as FPD-Link and Camera-Link. They capitalize on proven PLL and CDR architectures for superior signal integrity and error-free data transfers. Operating efficiently in various technology nodes, they remain highly effective across collaborative chipset environments. The interfaces are fortified with adaptable features like dynamic phase alignment to stabilize data sequences and on-die termination options for superior signal integrity. Their proven record places them as a critical enabler in applications where consistent high-speed data transfer is paramount, demonstrating Silicon Creations’ prowess in delivering industry-leading communication solutions.
The Apodis family of Optical Transport Network processors adheres to ITU-T standards, offering a comprehensive suite for signal termination, processing, and multiplexing. Designed to handle both SONET/SDH and Ethernet client services, these processors map signals to Optical Transport Network (OTN), empowering versatile any-port, any-service configurations. Apodis processors are notable for their capacity to support up to 16 client ports and four 10G OTN line ports, delivering bandwidth scalability up to 40G, crucial for wireless backhaul and fronthaul deployments. With a robust, non-blocking OTN switching fabric, Apodis facilitates seamless client-to-line and line-to-line connections while optimally managing network bandwidth. This adaptability makes the Apodis processors an ideal choice for next-generation access networks and optical infrastructures.
The HOTLink II Product Suite is engineered to deliver advanced capabilities in high-speed data and video link technologies. It serves as an essential toolset for developing and implementing HOTLink II protocols effectively, catering to the specific needs of modern avionics systems requiring reliable and high-throughput data transfer. This suite includes various components that enable the seamless transmission and conversion of data, supporting both development and operational phases. Its design incorporates technologies that enhance data integrity and efficiency, making it integral to systems where performance and reliability are critical. Great River Technology ensures that each component of the HOTLink II suite is crafted with precision, providing comprehensive support and simplifying integration processes. The suite redounds to the extensive expertise of Great River Technology in the sector, reinforcing their standing as providers of pioneering solutions.
Silicon Creations' Analog Glue solutions provide essential analog functionalities to complete custom SoC designs seamlessly. These functional blocks, which constitute buffer and bandgap reference circuits, are vital for seamless on-chip clock distribution and ensure low-jitter operations. Analog Glue includes crucial components such as power-on reset (POR) generators and bridging circuits to support various protocols and interfaces within SoCs. These supplementary macros are crafted to complement existing PLLs and facilities like SerDes, securing reliable signal transmission under varied operating circumstances. Serving as the unsung heroes of chip integration, these Analog Glue functions mitigate the inevitable risks of complex SoC designs, supporting efficient design flows and effective population of chip real estate. Thus, by emphasizing critical system coherency, they enhance overall component functionality, providing a stable infrastructure upon which additional system insights can be leveraged.
The ARINC 818-3 IP Core from iWave Global represents an advancement in avionics video interface technology, designed for high-speed and high-fidelity video data transmission. This IP core addresses the needs of modern aerospace systems that require robust video communication links both for military and commercial use. It supports a wide array of enhancements over previous generations, including increased bandwidth and improved signal integrity. This ensures that the ARINC 818-3 IP Core can handle the demands of next-generation avionic systems seamlessly, supporting advanced video processing and display systems. The core's design prioritizes modularity and scalability, allowing for easy integration and expansion to meet evolving system requirements. It is positioned as an essential tool for aviation applications demanding high reliability and accuracy in video data handling and display solutions, making it indispensable for new and retrofitted aerospace projects.
iWave Global delivers the Serial FPDP (sFPDP) solution, a high-bandwidth, low-latency serial communication protocol widely deployed in high-performance computing systems. This technology is optimized for applications that require rapid data transport, such as radar and high-definition video processing, making it a vital tool in industrial and defense sectors. By supporting high throughput rates, the Serial FPDP ensures timely and reliable data transmission, crucial for systems where time sensitivity and data integrity are paramount. The solution is particularly designed to address real-time data operations, ensuring that data handling meets rigorous industry standards. With its robust design, the Serial FPDP accommodates various network topologies, allowing for the flexible deployment of communication systems. This flexibility and performance make it highly applicable in environments where system designers demand unobstructed high-speed data transfer capabilities.
The Mixed-Signal CODEC offered by Archband Labs integrates advanced analog and digital audio processing to deliver superior sound quality. Designed for a variety of applications such as portable audio devices, automotive systems, and entertainment systems, this CODEC provides efficiency and high performance. With cutting-edge technologies, it handles complex signal conversions with minimal power consumption. This CODEC supports numerous interface standards, making it a versatile component in numerous audio architectures. It's engineered to offer precise sound reproduction and maintains audio fidelity across all use cases. The integrated components within the CODEC streamline design processes and reduce the complexity of audio system implementations. Furthermore, the Mixed-Signal CODEC incorporates features that support high-resolution audio, ensuring compatibility with high-definition sound systems. It's an ideal choice for engineers looking for a reliable and comprehensive audio processing solution.
Designed for performance computing, the pPLL03F-GF22FDX is an advanced all-digital fractional-N PLL developed for low-jitter and compact applications. It operates efficiently at clock frequencies reaching up to 4GHz, specifically crafted to meet the demands of performance computing blocks and ADCs/DACs that have moderate SNR prerequisites. A crucial aspect of its design is its compatibility with multi-PLL systems, enabling implementations in complex SoCs with numerous clock domains. Tailored for GlobalFoundries 22FDX, this IP ensures robust and reliable performance across varied PVT conditions.
Dillon Engineering's 2D FFT core delivers robust performance for transforming two-dimensional data sets into the frequency domain with high precision and efficiency. By leveraging both internal and external memory between dual FFT engines, this core optimizes the data processing pipeline, ensuring fast and reliable results even as data complexity increases. Ideal for applications that handle image processing and data matrix transformations, the 2D FFT core navigates data bandwidth constraints with ease, maintaining throughput even for larger data sets. This core's design maximizes data accuracy and minimizes processing delays, crucial for applications requiring precise image recognition and analysis. Thanks to the adaptable nature provided by Dillon's ParaCore Architect, this IP core is easily customized for various FPGA and ASIC environments. Its flexibility and robust processing capabilities make the 2D FFT core a key component for cutting-edge applications in fields where data translation and processing are critical.
ISELED is an innovative technology that revolutionizes automotive interior lighting by integrating all necessary hardware functions for fully software-defined lighting. It features smart RGB LEDs which are pre-calibrated by manufacturers, ensuring consistent color temperature and exceptional lighting quality. This technology simplifies the integration process by allowing users to send simple digital commands to control the color output of the LEDs without needing additional complex setups for color mixing and temperature compensation. ISELED is equipped to handle synchronous lighting displays and dynamic effects across vehicle interiors. The connectivity aspect of ISELED is enhanced by its ILaS protocol, allowing direct cable connections between lighting systems and enabling efficient power conversion. This makes it suitable for applications requiring resilience in communication, despite potential power failures on the board. With capabilities for bridging data over Ethernet, ISELED supports centralized control and synchronization from a vehicle's ECU.
The KL530 is Kneron's state-of-the-art AI chip with a unique NPU architecture, leading the market in INT4 precision and transformers. Designed for higher efficiency, it features lower power consumption while maintaining robust performance. The chip supports various AI models and configurations, making it adaptable across AIoT and other technology landscapes.
The GenAI v1-Q from RaiderChip brings forth a specialized focus on quantized AI operations, reducing memory requirements significantly while maintaining impressive precision and speed. This innovative accelerator is engineered to execute large language models in real-time, utilizing advanced quantization techniques such as Q4_K and Q5_K, thereby enhancing AI inference efficiency especially in memory-constrained environments. By offering a 276% boost in processing speed alongside a 75% reduction in memory footprint, GenAI v1-Q empowers developers to integrate advanced AI capabilities into smaller, less powerful devices without sacrificing operational quality. This makes it particularly advantageous for applications demanding swift response times and low latency, including real-time translation, autonomous navigation, and responsive customer interactions. The GenAI v1-Q diverges from conventional AI solutions by functioning independently, free from external network or cloud auxiliaries. Its design harmonizes superior computational performance with scalability, allowing seamless adaptation across variegated hardware platforms including FPGAs and ASIC implementations. This flexibility is crucial for tailoring performance parameters like model scale, inference velocity, and power consumption to meet exacting user specifications effectively. RaiderChip's GenAI v1-Q addresses crucial AI industry needs with its ability to manage multiple transformer-based models and confidential data securely on-premises. This opens doors for its application in sensitive areas such as defense, healthcare, and financial services, where confidentiality and rapid processing are paramount. With GenAI v1-Q, RaiderChip underscores its commitment to advancing AI solutions that are both environmentally sustainable and economically viable.
The Ultra-Low Latency 10G Ethernet MAC IP core by Chevin Technology exemplifies cutting-edge design for high-speed network communications, catered specifically to deliver the lowest possible latency. It is meticulously constructed to meet the demands of applications that require minimal delay in data exchange, thus maximising data throughput. The IP core is finely tuned for deployment in FPGAs, optimizing the balance between performance and resource utilization. Benefiting from a streamlined logic architecture, this IP core enhances the efficiency of hardware accelerations and simplifies the incorporation of Ethernet connectivity into customer systems. Its fundamental construction is rooted in Chevin’s extensive experience with Ethernet technologies and it has been thoroughly tested to ensure reliable operation across a diverse range of settings. This Ethernet MAC utilises all-logic architecture which removes need for additional CPU or software intervention, providing immense power savings and reduced system complexity. Features like programmable interframe gap control and flexible licensing allow for the tailored installation in both traditional and contemporary systems. The combination of robust performance capabilities alongside expert support creates a compelling choice for integrators focused on high-speed, low-latency Ethernet solutions.
The Chipchain C100 is a pioneering solution in IoT applications, providing a highly integrated single-chip design that focuses on low power consumption without compromising performance. Its design incorporates a powerful 32-bit RISC-V CPU which can reach speeds up to 1.5GHz. This processing power ensures efficient and capable computing for diverse IoT applications. This chip stands out with its comprehensive integrated features including embedded RAM and ROM, making it efficient in both processing and computing tasks. Additionally, the C100 comes with integrated Wi-Fi and multiple interfaces for transmission, broadening its application potential significantly. Other notable features of the C100 include an ADC, LDO, and a temperature sensor, enabling it to handle a wide array of IoT tasks more seamlessly. With considerations for security and stability, the Chipchain C100 facilitates easier and faster development in IoT applications, proving itself as a versatile component in smart devices like security systems, home automation products, and wearable technology.
Clock Generation IP from Analog Circuit Works facilitates the creation of precise timing and control signals needed in complex electronic systems. These solutions are vital in synchronizing various parts of a system, ensuring they operate coherently and efficiently. The ability to generate high-frequency clocks with minimal jitter and low power consumption distinguishes these offerings. They cater to a range of applications from consumer electronics to industrial machinery, where reliable clock distribution is paramount. With flexibility to integrate with different process technologies, they provide an essential component for developing advanced multi-core processing systems and other synchronized systems. This IP is engineered to deliver consistent performance with respect to both phase noise and power efficiency.
KPIT's digital connected solutions revolutionize the automotive cockpit and in-cabin experience, enhancing personalization, productivity, and safety for drivers. These solutions are driven by technologies such as high-resolution displays, augmented reality head-up displays, and AI-powered virtual assistants, all integrated to create a seamless and dynamic digital environment within the vehicle. The cloud and over-the-air (OTA) updates further enrich the consumer experience by providing regular enhancements and new features. The innovative market leadership KPIT demonstrates is evident in their rapid development and integration capabilities, which meet the growing demands of OEMs for swift market entry. KPIT addresses critical challenges in cost constraints and system integration, ensuring that advanced features coexist with the necessary affordability and cohesion between hardware and software components. Through these digital solutions, KPIT stands as a preferred partner for automakers pursuing cutting-edge cockpit and connectivity advancements. By continuously innovating and expanding their offering, KPIT enhances the value proposition of modern vehicles, ensuring that automakers remain competitive in the fast-evolving automotive landscape.
The Flexibilis Ethernet Switch (FES) is an advanced Layer 2 switch IP core designed to enable gigabit forwarding capabilities across multiple Ethernet ports. Compatible with IEEE 802.1D MAC bridges, FES features triple-speed Ethernet interfaces for efficient handling and prioritization of network traffic. Its integration with IEEE 1588 Precision Time Protocol ensures accurate timekeeping across the network, which is crucial for applications requiring precise timing. The FES supports various configurations and interfaces, making it adaptable to specific application requirements while maintaining robust network performance.
The AXI4 DMA Controller from Digital Blocks revolutionizes data management in System-on-Chip architectures through high-performance Direct Memory Access capabilities. Supporting a span of 1 to 16 channels, it handles data transfers between memory and peripherals with agility, ideal for both small and large datasets. Designed for high throughput, it includes a multi-channel architecture that can expand from 32 to up to 256 channels, demonstrating exceptional scalability for future data demands. Each channel within the DMA Controller operates independently with dedicated Read and Write Controllers, ensuring minimal overhead during transfers. It facilitates complex data flow configurations including scatter-gather linked-list data controls and comprehensive support for different burst modes within the AXI3 and AXI4 protocols. Its design incorporates advanced features that users can selectively enable to optimize silicon resource usage and cost efficiency. Additionally, it accommodates complex AXI4-Stream to memory-mapped interface transfers, making it versatile for a variety of applications, from high-speed data environments to embedded systems requiring optimized memory access and control.
The TW330 is part of TAKUMI’s robust line of graphics solutions, showcasing a refined architecture specifically for optimizing embedded system graphics. This product extends TAKUMI's reputation for producing effective hardware solutions that balance performance with low power consumption and minimal CPU load. Especially suitable for digital display devices, the TW330 offers a pronounced efficiency in graphics rendering, setting the stage for enhanced visuals and user interactivity. It aligns with application needs that require impressive performance without compromise on power. By elevating graphics capabilities, the TW330 continues to serve the needs of sophisticated graphic systems. It remains a testament to TAKUMI's innovation in providing top-of-the-line graphics IP solutions to meet the high expectations of today's digital technology demands.
This Ethernet RTPS Core provides a complete IP solution for the Ethernet RTPS protocol, essential in mission-critical networks. It supports real-time communication and data synchronization across devices, critical for systems requiring precise timing and reliable data exchange.
The ADQ35 is a high-throughput digitizer designed for critical signal processing applications. Known for its 12-bit accuracy and high sampling rates, it stands out in delivering up to 10 GSPS, supporting single or dual-channel data streams. This ensures data integrity and speed for applications that demand precision and reliability, such as telecommunications and high-speed imaging. Equipped with enhanced processing capabilities, the ADQ35 ensures superior handling of complex datasets, making it suitable for scientific research and advanced electronics projects. Its robust design caters to the needs of modern digital systems, allowing for a seamless integration into existing infrastructure to facilitate expansive projects. This device also features streaming capabilities that provide a continuous flow of high-quality data, excelling in applications that require constant monitoring and data analysis. The ADQ35 digitizer is an excellent choice for industries that rely on swift and accurate data interpretation, enhancing overall system performance and technical output.
Silicon Library Inc.'s DisplayPort/eDP is an advanced interface IP crafted for delivering high-definition audio-visual data. It conforms to the specifications of DP/eDP 1.4, positioning it as a critical component for devices like laptops, monitors, and digital signage, where seamless and high-quality display output is required. This product supports high-resolution displays with considerable bandwidth, enabling the transmission of ultra-high-definition content efficiently and effectively. Its design takes into account the need for reduced power consumption, aligning with the trend towards more energy-efficient electronics without compromising on performance. The DisplayPort/eDP IP ensures excellent signal transmission quality, meeting the stringent demands of modern digital displays. It also features compatibility with various control protocols, providing flexibility in integration across different devices. As multimedia consumption continues to rise, this IP offers a strategic advantage in developing cutting-edge display solutions.
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