All IPs > Graphic & Peripheral
Graphic & Peripheral Semiconductor IPs are critical components in the design and development of electronics that require efficient and robust control over multimedia and peripheral functions. This category of semiconductor IP encompasses a wide array of technologies used to manage and optimize graphics rendering, audio processing, data communication, and peripheral interfaces in electronic devices such as computers, smartphones, tablets, and other smart gadgets.
In this vivid category, you'll find a variety of subcategories tailored to specific functionalities. For instance, the Graphics Processing Unit (GPU) semiconductor IPs are pivotal for rendering images and video, essential in gaming, virtual reality, and professional content creation. Audio Controllers handle sound processing, ensuring crisp and seamless audio output, crucial for devices prioritizing high-quality sound delivery.
Other key components in the Graphic & Peripheral category include Peripheral Controllers, which facilitate the integration of various input/output devices, enhancing the device's interactivity and user experience. DMA Controllers are responsible for moving data efficiently between memory and peripherals, minimizing the CPU load. These IPs enhance overall system performance by ensuring that data flow is smooth and uninterrupted.
From Clock Generators that synchronize the entire system's operations to Interrupt Controllers managing priority tasks, each semiconductor IP in this category plays a unique role in ensuring that electronic devices operate at peak efficiency. By exploring these subcategories, companies and developers can find the precise semiconductors needed to support cutting-edge multimedia and peripheral technologies in their next product launch.
The KL730 is a third-generation AI chip that integrates advanced reconfigurable NPU architecture, delivering up to 8 TOPS of computing power. This cutting-edge technology enhances computational efficiency across a range of applications, including CNN and transformer networks, while minimizing DDR bandwidth requirements. The KL730 also boasts enhanced video processing capabilities, supporting 4K 60FPS outputs. With expertise spanning over a decade in ISP technology, the KL730 stands out with its noise reduction, wide dynamic range, fisheye correction, and low-light imaging performance. It caters to markets like intelligent security, autonomous vehicles, video conferencing, and industrial camera systems, among others.
The Akida 2nd Generation represents a leap forward in the realm of AI processing, enhancing upon its predecessor with greater flexibility and improved efficiency. This advanced neural processor core is tailored for modern applications demanding real-time response and ultra-low power consumption, making it ideal for compact and battery-operated devices. Akida 2nd Generation supports various programming configurations, including 8-, 4-, and 1-bit weights and activations, thus providing developers with the versatility to optimize performance versus power consumption to meet specific application needs. Its architecture is fully digital and silicon-proven, ensuring reliable deployment across diverse hardware setups. With features such as programmable activation functions and support for sophisticated neural network models, Akida 2nd Generation enables a broad spectrum of AI tasks. From object detection in cameras to sophisticated audio sensing, this iteration of the Akida processor is built to handle the most demanding edge applications while sustaining BrainChip's hallmark efficiency in processing power per watt.
Overview: The UCIe IP supports multiple protocols (CXL/PCIe/Streaming) to connect chiplets, reducing overall development cycles for IPs and SOCs. With flexible application and PHY interfaces, The UCIe IP is ideal for SOCs and chiplets. Key Features:  Supports UCIe 1.0 Specification  Supports CXL 2.0 and CXL 3.0 Specifications  Supports PCIe Gen6 Specification  Supports PCIe Gen5 and older versions of PCIe specifications  Supports single and two-stack modules  Supports CXL 2.0 68Byte flit mode with Fallback mode for PCIe non-flit mode transfers  Supports CXL 3.0 256Byte flit mode  Supports PCIe Gen6 flit mode  Configurable up to 64-lane configuration for Advanced UCIe modules and 16 lanes for Standard UCIe modules  Supports sideband and Mainband signals  Supports Lane repair handling  Data to clock point training and eye width sweep support from transmitter and receiver ends  UCIe controller can work as Downstream or Upstream  Main Band Lane reversal supported  Dynamic sense of normal and redundant clock and data lines activation  UCIe enumeration through DVSEC  Error logging and reporting supported  Error injection supported through Register programming  RDI/FDI PM entry, Exit, Abort flows supported  Dynamic clock gang at adapter supported Configurable Options:  Maximum link width (x1, x2, x4, x8, x16)  MPS (128B to 4KB)  MRRS (128B to 4KB)  Transmit retry/Receive buffer size  Number of Virtual Channels  L1 PM substate support  Optional Capability Features can be Configured  Number of PF/VFDMA configurable Options  AXI MAX payload size Variations  Multiple CPI Interfaces (Configurable)  Cache/memory configurable  Type 0/1/2 device configurable
The Akida IP is an advanced processor core designed to mimic the efficient processing characteristics of the human brain. Inspired by neuromorphic engineering principles, it delivers real-time AI performance while maintaining a low power profile. The architecture of the Akida IP is sophisticated, allowing seamless integration into existing systems without the need for continuous external computation. Equipped with capabilities for processing vision, audio, and sensor data, the Akida IP stands out by being able to handle complex AI tasks directly on the device. This is done by utilizing a flexible mesh of nodes that efficiently distribute cognitive computing tasks, enabling a scalable approach to machine learning applications. Each node supports hundreds of MAC operations and can be configured to adapt to various computational requirements, making it a versatile choice for AI-centric endeavors. Moreover, the Akida IP is particularly beneficial for edge applications where low latency, high efficiency, and security are paramount. With capabilities for event-based processing and on-chip learning, it enhances response times and reduces data transfer needs, thereby bolstering device autonomy. This solidifies its position as a leading solution for embedding AI into devices across multiple industries.
iWave Global introduces the ARINC 818 Switch, a pivotal component in the management and routing of video data within avionics systems. Designed for applications that require efficient video data distribution and management, the switch is optimized for performance in environments with stringent data handling requirements. The switch's architecture supports a high level of bandwidth, allowing for the smooth routing of multiple video streams in real-time. Its design includes advanced features that ensure low-latency, error-free data transfer, integral to maintaining the integrity and reliability of video data in critical applications. Featuring robust interoperability characteristics, the ARINC 818 Switch easily integrates into existing systems, facilitating modular expansion and adaptability to new technological standards. It is indispensable for any aerospace project that involves complex video data management, providing a stable platform for video data routing and switching.
The AI Camera Module from Altek is a versatile, high-performance component designed to meet the increasing demand for smart vision solutions. This module features a rich integration of imaging lens design and combines both hardware and software capacities to create a seamless operational experience. Its design is reinforced by Altek's deep collaboration with leading global brands, ensuring a top-tier product capable of handling diverse market requirements. Equipped to cater to AI and IoT interplays, the module delivers outstanding capabilities that align with the expectations for high-resolution imaging, making it suitable for edge computing applications. The AI Camera Module ensures that end-user diversity is meaningfully addressed, offering customization in device functionality which supports advanced processing requirements such as 2K and 4K video quality. This module showcases Altek's prowess in providing comprehensive, all-in-one camera solutions which leverage sophisticated imaging and rapid processing to handle challenging conditions and demands. The AI Camera's technical blueprint supports complex AI algorithms, enhancing not just image quality but also the device's interactive capacity through facial recognition and image tracking technology.
The Aries fgOTN processor family is engineered according to the ITU-T G.709.20 fgOTN standard. This line of processors handles a variety of signals, including E1/T1, FE/GE, and STM1/STM4, effectively monitoring and managing alarms and performance metrics. Aries processors excel at fine-grain traffic aggregation, efficiently channeling fgODUflex traffic across OTN lines to support Ethernet, SDH, PDH client services. Their capacity to map signals to fgODUflex containers, which are then multiplexed into higher order OTN signals, demonstrates their versatility and efficiency. By allowing cascaded configurations with other Aries devices or Apodis processors, Aries products optimize traffic routes through OTN infrastructures, positioning them as essential components in optical networking and next-generation access scenarios.
Silicon Creations delivers precision LC-PLLs designed for ultra-low jitter applications requiring high-end performance. These LC-tank PLLs are equipped with advanced digital architectures supporting wide frequency tuning capabilities, primarily suited for converter and PHY applications. They ensure exceptional jitter performance, maintaining values well below 300fs RMS. The LC-PLLs from Silicon Creations are characterized by their capacity to handle fractional-N operations, with active noise cancellation features allowing for clean signal synthesis free of unwanted spurs. This architecture leads to significant power efficiencies, with some IPs consuming less than 10mW. Their low footprint and high frequency integrative capabilities enable seamless deployments across various chip designs, creating a perfect balance between performance and size. Particular strength lies in these PLLs' ability to meet stringent PCIe6 reference clocking requirements. With programmable loop bandwidth and an impressive tuning range, they offer designers a powerful toolset for achieving precise signal control within cramped system on chip environments. These products highlight Silicon Creations’ commitment to providing industry-leading performance and reliability in semiconductor design.
Chimera GPNPU is engineered to revolutionize AI/ML computational capabilities on single-core architectures. It efficiently handles matrix, vector, and scalar code, unifying AI inference and traditional C++ processing under one roof. By alleviating the need for partitioning AI workloads between different processors, it streamlines software development and drastically speeds up AI model adaptation and integration. Ideal for SoC designs, the Chimera GPNPU champions an architecture that is both versatile and powerful, handling complex parallel workloads with a single unified binary. This configuration not only boosts software developer productivity but also ensures an enduring flexibility capable of accommodating novel AI model architectures on the horizon. The architectural fabric of the Chimera GPNPU seamlessly blends the high matrix performance of NPUs with C++ programmability found in traditional processors. This core is delivered in a synthesizable RTL form, with scalability options ranging from a single-core to multi-cluster designs to meet various performance benchmarks. As a testament to its adaptability, the Chimera GPNPU can run any AI/ML graph from numerous high-demand application areas such as automotive, mobile, and home digital appliances. Developers seeking optimization in inference performance will find the Chimera GPNPU a pivotal tool in maintaining cutting-edge product offerings. With its focus on simplifying hardware design, optimizing power consumption, and enhancing programmer ease, this processor ensures a sustainable and efficient path for future AI/ML developments.
xcore.ai is XMOS Semiconductor's innovative programmable chip designed for advanced AI, DSP, and I/O applications. It enables developers to create highly efficient systems without the complexity typical of multi-chip solutions, offering capabilities that integrate AI inference, DSP tasks, and I/O control seamlessly. The chip architecture boasts parallel processing and ultra-low latency, making it ideal for demanding tasks in robotics, automotive systems, and smart consumer devices. It provides the toolset to deploy complex algorithms efficiently while maintaining robust real-time performance. With xcore.ai, system designers can leverage a flexible platform that supports the rapid prototyping and development of intelligent applications. Its performance allows for seamless execution of tasks such as voice recognition and processing, industrial automation, and sensor data integration. The adaptable nature of xcore.ai makes it a versatile solution for managing various inputs and outputs simultaneously, while maintaining high levels of precision and reliability. In automotive and industrial applications, xcore.ai supports real-time control and monitoring tasks, contributing to smarter, safer systems. For consumer electronics, it enhances user experience by enabling responsive voice interfaces and high-definition audio processing. The chip's architecture reduces the need for exterior components, thus simplifying design and reducing overall costs, paving the way for innovative solutions where technology meets efficiency and scalability.
Our Expanded Serial Peripheral Interface (JESD251) Master controller features a low signal count and high data bandwidth, making it ideal for use in computing, automotive, Internet of Things, embedded systems, and mobile system processors. It connects multiple sources of Serial Peripheral Interface (xSPI) slave devices, including nonvolatile memories, graphics peripherals, networking peripherals, FPGAs, and sensor devices. Features • Compliant with JEDEC standard JESD251 expanded Serial Peripheral Interface (xSPI) for Non-Volatile Memory Devices, Version 1.0. • Supports a single master and multiple slaves per interface port. • Supports Single Data Rate and Double Data Rate. • Supports source synchronous clocking. • Supports data transfer rates up to: o 400MT/s (200MHz Clock) o 333MT/s (167MHz Clock) o 266MT/s (133MHz Clock) o 200MT/s (100MHz Clock) • Supports Deep Power Down (DPD) enter and exit commands. • Standard support for eight IO ports, with the possibility to increase IO ports based on system performance requirements. • Optional support for Data Strobe (DS) for writemasking. • Supports 1-bit wide SDR transfer. • Supports Profile 1.0 commands to manage nonvolatile memory devices. • Supports Profile 2.0 commands to read or writedata for any type of slave device. • Compatible with non-volatile memory arrays such as NOR Flash, NAND Flash, FRAM, and nvSRAM. • Compatible with volatile memory arrays such as SRAM, PSRAM, and DRAM. • Supports register-mapped input/output functions. • Supports programmable function devices such as FPGAs. Application • Consumer Electronics. • Defence & Aerospace. • Virtual Reality. • Augmented Reality. • Medical. • Biometrics (Fingerprints, etc). • Automotive Devices. • Sensor Devices. Deliverables • Verilog Source code. • User Guide. • IP Integration Guide. • Run and Synthesis script. • Encrypted Verification Testbench Environment. • Basic Test-suite.
RaiderChip's GenAI v1 is a pioneering hardware-based generative AI accelerator, designed to perform local inference at the Edge. This technology integrates optimally with on-premises servers and embedded devices, offering substantial benefits in privacy, performance, and energy efficiency over traditional hybrid AI solutions. The design of the GenAI v1 NPU streamlines the process of executing large language models by embedding them directly onto the hardware, eliminating the need for external components like CPUs or internet connections. With its ability to support complex models such as the Llama 3.2 with 4-bit quantization on LPDDR4 memory, the GenAI v1 achieves unprecedented efficiency in AI token processing, coupled with energy savings and reduced latency. What sets GenAI v1 apart is its scalability and cost-effectiveness, significantly outperforming competitive solutions such as Intel Gaudi 2, Nvidia's cloud GPUs, and Google's cloud TPUs in terms of memory efficiency. This solution maximizes the number of tokens generated per unit of memory bandwidth, thus addressing one of the primary limitations in generative AI workflow. Furthermore, the adept memory usage of GenAI v1 reduces the dependency on costly memory types like HBM, opening the door to more affordable alternatives without diminishing processing capabilities. With a target-agnostic approach, RaiderChip ensures the GenAI v1 can be adapted to various FPGAs and ASICs, offering configuration flexibility that allows users to balance performance with hardware costs. Its compatibility with a wide range of transformers-based models, including proprietary modifications, ensures GenAI v1's robust placement across sectors requiring high-speed processing, like finance, medical diagnostics, and autonomous systems. RaiderChip's innovation with GenAI v1 focuses on supporting both vanilla and quantized AI models, ensuring high computation speeds necessary for real-time applications without compromising accuracy. This capability underpins their strategic vision of enabling versatile and sustainable AI solutions across industries. By prioritizing integration ease and operational independence, RaiderChip provides a tangible edge in applying generative AI effectively and widely.
The AHB-Lite APB4 Bridge serves as a crucial interconnect that facilitates communication between the AMBA 3 AHB-Lite and AMBA APB bus protocols. As a parameterized soft IP, it offers flexibility and adaptability in managing system interconnections, bridging the gap between high-speed and low-speed peripherals with efficiency. The bridge's architecture is designed to maintain data integrity while transferring information across different protocol tiers. This bridge supports the implementation of a seamless transition for data exchanges, ensuring data packets are transmitted with minimal latency. It is ideal for systems that require stable connectivity across multiple peripheral interfaces, delivering a cohesive platform for system designers to enhance operational uniformity. By enabling efficient bus conversion, it supports broader system architectures, contributing to the overall efficiency of embedded designs. With its open-architecture design, the AHB-Lite APB4 Bridge caters to a wide range of applications, providing necessary adaptability to meet the unique demands of each project. Its robust design ensures that it can accommodate the complex architectures of modern embedded systems, enhancing both performance and reliability.
The GenAI v1-Q from RaiderChip brings forth a specialized focus on quantized AI operations, reducing memory requirements significantly while maintaining impressive precision and speed. This innovative accelerator is engineered to execute large language models in real-time, utilizing advanced quantization techniques such as Q4_K and Q5_K, thereby enhancing AI inference efficiency especially in memory-constrained environments. By offering a 276% boost in processing speed alongside a 75% reduction in memory footprint, GenAI v1-Q empowers developers to integrate advanced AI capabilities into smaller, less powerful devices without sacrificing operational quality. This makes it particularly advantageous for applications demanding swift response times and low latency, including real-time translation, autonomous navigation, and responsive customer interactions. The GenAI v1-Q diverges from conventional AI solutions by functioning independently, free from external network or cloud auxiliaries. Its design harmonizes superior computational performance with scalability, allowing seamless adaptation across variegated hardware platforms including FPGAs and ASIC implementations. This flexibility is crucial for tailoring performance parameters like model scale, inference velocity, and power consumption to meet exacting user specifications effectively. RaiderChip's GenAI v1-Q addresses crucial AI industry needs with its ability to manage multiple transformer-based models and confidential data securely on-premises. This opens doors for its application in sensitive areas such as defense, healthcare, and financial services, where confidentiality and rapid processing are paramount. With GenAI v1-Q, RaiderChip underscores its commitment to advancing AI solutions that are both environmentally sustainable and economically viable.
iWave Global delivers the Serial FPDP (sFPDP) solution, a high-bandwidth, low-latency serial communication protocol widely deployed in high-performance computing systems. This technology is optimized for applications that require rapid data transport, such as radar and high-definition video processing, making it a vital tool in industrial and defense sectors. By supporting high throughput rates, the Serial FPDP ensures timely and reliable data transmission, crucial for systems where time sensitivity and data integrity are paramount. The solution is particularly designed to address real-time data operations, ensuring that data handling meets rigorous industry standards. With its robust design, the Serial FPDP accommodates various network topologies, allowing for the flexible deployment of communication systems. This flexibility and performance make it highly applicable in environments where system designers demand unobstructed high-speed data transfer capabilities.
Overview: The Expanded Serial Peripheral Interface (xSPI) Master/Slave controller offers high data throughput, low signal count, and limited backward compatibility with legacy SPI devices. It is designed to connect xSPI Master/Slave devices in computing, automotive, Internet of Things, embedded systems, and mobile processors to various peripherals such as non-volatile memories, graphics peripherals, networking devices, FPGAs, and sensor devices. Key Features:  Compliance with JEDEC standard JESD251 eXpanded SPI for Non-Volatile Memory Devices, Version 1.0  Support for Single master and multiple slaves per interface port  Single Data Rate (SDR) and Double Data Rate (DDR) support  Source synchronous clocking  Deep Power Down (DPD) enter and exit commands  Eight IO ports in standard, expandable based on system requirements  Optional Data Strobe (DS) for write masking  bit wide SDR transfer support  Profile 1.0 Commands for non-volatile memory device management  Profile 2.0 Commands for read or write data for various slave devices Applications:  Consumer Electronics  Defense & Aerospace  Virtual Reality  Augmented Reality  Medical  Biometrics  Automotive Devices  Sensor Devices
Overview: PCIe Gen6 is a high-speed, layered protocol interconnect interface supporting speeds up to 64GT/s, featuring multi-lanes and links. The Transport, Data Link, and Physical layers specified in the PCIe specification are implemented, along with PIPE interface logic connecting to PHY and AXI Bridging logic for application connectivity. Specifications:  Supports PCIe Gen 6 and Pipe 5.X Specifications  Core supports Flit and non-Flit Mode  Lane Configurations: X16, X8, X4, X2, X1  AXI MM and Streaming supported  Supports Gen1 to Gen6 modes  Data rate support of 2.5 GT/s, 5 GT/s, 8 GT/s, 16 GT/s, 32 GT/s, 64 GT/s  PAM support when operating at 64GT/s  Encoding/Decoding Support: 8b/10b, 128b/130b, 1b/1b  Supports SerDes and non-SerDes architecture  Optional DMA support as plugin module  Support for alternate negotiation protocol  Can operate as an endpoint or root complex  Lane polarity control through register  Lane de-skew supported  Support for L1 states and L0P  Support for SKP OS add/removal and SRIS mode  No equalization support through configuration  Deemphasis negotiation support at 5GT/s  Supports EI inferences in all modes  Supports PTM, OBFF, MSI, MSIX, Power management, and all message formats
The Ring PLLs offered by Silicon Creations illustrate a versatile clocking solution, well-suited for numerous frequency generation tasks within integrated circuit designs. Known for their general-purpose and specialized applications, these PLLs are crafted to serve a massive array of industries. Their high configurability makes them applicable for diverse synthesis needs, acting as the backbone for multiple clocking strategies across different environments. Silicon Creations' Ring PLLs epitomize high integration with functions tailored for low jitter and precision clock generation, suitable for battery-operated devices and systems demanding high accuracy. Applications span from general clocking to precise Audio Codecs and SerDes configurations requiring dedicated performance metrics. The Ring PLL architecture achieves best-in-class long-term and period jitter performance with both integer and fractional modes available. Designed to support high volumes of frequencies with minimal footprint, these PLLs aid in efficient space allocation within system designs. Their use of silicon-proven architectures and modern validation methodologies assure customers of high reliability and quick integration into existing SoC designs, emphasizing low risk and high reward configurations.
The KL520 marks Kneron's foray into the edge AI landscape, offering an impressive combination of size, power efficiency, and performance. Armed with dual ARM Cortex M4 processors, this chip can operate independently or as a co-processor to enable AI functionalities such as smart locks and security monitoring. The KL520 is adept at 3D sensor integration, making it an excellent choice for applications in smart home ecosystems. Its compact design allows devices powered by it to operate on minimal power, such as running on AA batteries for extended periods, showcasing its exceptional power management capabilities.
The ARINC 818 Streaming IP Core is tailored to convert pixel bus data into an ARINC 818 formatted Fibre Channel stream and vice versa. It offers real-time streaming capabilities, which are essential for aerospace systems requiring precise format conversion. This dual-functionality enhances its utility in scenarios where adaptable data interchange is necessary for effective visual data communication. With its intricate design, this core is highly efficient in supporting video transmission protocols, providing robustness for streaming data between digital formats. Ensuring seamless data integration helps mitigate potential data loss or delays, critical in flight operations and real-time video processing. Thus, it stands as a valuable component in avionics communication networks where reliable data streams are paramount.
The KL530 represents a significant advancement in AI chip technology with a new NPU architecture optimized for both INT4 precision and transformer networks. This SOC is engineered to provide high processing efficiency and low power consumption, making it suitable for AIoT applications and other innovative scenarios. It features an ARM Cortex M4 CPU designed for low-power operation and offers a robust computational power of up to 1 TOPS. The chip's ISP enhances image quality, while its codec ensures efficient multimedia compression. Notably, the chip's cold start time is under 500 ms with an average power draw of less than 500 mW, establishing it as a leader in energy efficiency.
The KL630 is a pioneering AI chipset featuring Kneron's latest NPU architecture, which is the first to support Int4 precision and transformer networks. This cutting-edge design ensures exceptional compute efficiency with minimal energy consumption, making it ideal for a wide array of applications. With an ARM Cortex A5 CPU at its core, the KL630 excels in computation while maintaining low energy expenditure. This SOC is designed to handle both high and low light conditions optimally and is perfectly suited for use in diverse edge AI devices, from security systems to expansive city and automotive networks.
Great River Technology offers the ARINC 818 Product Suite, a comprehensive collection of tools and products designed to cover the full spectrum of ARINC 818 applications. This suite is pivotal for engineers and designers who are focused on the aviation sector, providing solutions necessary for the creation, testing, and deployment of high-speed digital interfaces in avionics. The suite supports design and implementation phases by offering robust support tools tailored for ARINC 818 development, including detailed implementers' guides and simulation resources. What's unique about this suite is its ability to facilitate process integrations for ARINC 818 standards across various platforms, making it adaptable for differing needs in aviation systems. The integration tools provided ensure that systems can efficiently manage data and video transmissions, providing clarity, speed, and reliability, all essential factors in mission-critical environments. Great River Technology’s ARINC 818 Product Suite is engineered to ensure seamless interoperability, offering support from initial project development through to practical operation, thus enabling avionic systems to function optimally in both standard and specialized conditions.
The PDM-to-PCM Converter from Archband Labs leads in transforming pulse density modulation signals into pulse code modulation signals. This converter is essential in applications where high fidelity of audio signal processing is vital, including digital audio systems and communication devices. Archband’s solution ensures accurate conversion, preserving the integrity and clarity of the original audio. This converter is crafted to seamlessly integrate with a wide array of systems, offering flexibility and ease-of-use in various configurations. Its robust design supports a wide range of input frequencies, making it adaptable to different signal environments. The PDM-to-PCM Converter also excels in minimizing latency and reducing overhead processing times. It’s engineered for environments where precision and sound quality are paramount, ensuring that audio signals remain crisp and undistorted during conversion processes.
aiSim 5 stands as a cutting-edge simulation tool specifically crafted for the automotive sector, with a strong focus on validating ADAS and autonomous driving solutions. It distinguishes itself with an AI-powered digital twin creation capability, offering a meticulously optimized sensor simulation environment that guarantees reproducibility and determinism. The adaptable architecture of aiSim allows seamless integration with existing industry toolchains, significantly minimizing the need for costly real-world testing.\n\nOne of the key features of aiSim is its capability to simulate various challenging weather conditions, enhancing testing accuracy across diverse environments. This includes scenarios like snowstorms, heavy fog, and rain, with sensors simulated based on physics, offering changes in conditions in real-time. Its certification with ISO 26262 ASIL-D attests to its automotive-grade quality and reliability, providing a new standard for testing high-fidelity sensor data in varied operational design domains.\n\nThe flexibility of aiSim is further highlighted through its comprehensive SDKs and APIs, which facilitate smooth integration into various systems under test. Additionally, users can leverage its extensive 3D asset library to establish detailed, realistic testing environments. AI-based rendering technologies underpin aiSim's data simulation, achieving both high efficiency and accuracy, thereby enabling rapid and effective validation of advanced driver assistance and autonomous driving systems.
Digital Blocks' AXI4 DMA Controller is a robust solution designed for transferring data efficiently between systems over the AXI4 interface. Supporting up to 16 independent channels, it excels in high data throughput both for small and large data sets. Its capabilities are extended with advanced DMA features, allowing custom configurations to minimize silicon usage and licensing costs. Precise control over DMA operations is facilitated through its customizable settings, supporting a flexible range of interface buses and addressing modes.
KPIT Technologies' Integrated Diagnostics and Aftersales Transformation (iDART) is an advanced solution focused on improving vehicle diagnostics and enhancing aftersales service operations. This innovative platform brings together various diagnostic tools, data analytics, and service management applications to provide comprehensive support throughout the vehicle’s lifecycle. iDART is designed to streamline diagnostics processes, facilitate accurate fault detection, and enhance customer service by enabling predictive maintenance and quicker resolution of vehicle issues. By integrating onboard diagnostics with cloud-based platforms, KPIT offers real-time insights and proactive service measures that reduce downtime and improve vehicle reliability. KPIT's iDART platform helps automotive companies enhance their aftersales services with efficient, digitally driven solutions, optimizing operational costs and improving customer satisfaction. These services align with modern expectations of connectivity, providing the automotive sector with the tools needed to deliver sophisticated, customer-centric aftersales and diagnostic services.
The KL720 AI SoC is designed for optimal performance-to-power ratios, achieving 0.9 TOPS per watt. This makes it one of the most efficient chips available for edge AI applications. The SOC is crafted to meet high processing demands, suitable for high-end devices including smart TVs, AI glasses, and advanced cameras. With an ARM Cortex M4 CPU, it enables superior 4K imaging, full HD video processing, and advanced 3D sensing capabilities. The KL720 also supports natural language processing (NLP), making it ideal for emerging AI interfaces such as AI assistants and gaming gesture controls.
eSi-Connect offers an extensive suite of AMBA-compliant peripheral IPs designed to streamline SoC integration. This suite encompasses versatile memory controllers, standard off-chip interface support, and essential control functions. Its configurability and compatibility with low-level software drivers make it suitable for real-time deployment in complex system architectures, promoting reliable connectivity across various applications.
RAIV represents Siliconarts' General Purpose-GPU (GPGPU) offering, engineered to accelerate data processing across diverse industries. This versatile GPU IP is essential in sectors engaged in high-performance computing tasks, such as autonomous driving, IoT, and sophisticated data centers. With RAIV, Siliconarts taps into the potential of the fourth industrial revolution, enabling rapid computation and seamless data management. The RAIV architecture is poised to deliver unmatched efficiency in high-demand scenarios, supporting massive parallel processing and intricate calculations. It provides an adaptable framework that caters to the needs of modern computing, ensuring balanced workloads and optimized performance. Whether used for VR/AR applications or supporting the back-end infrastructure of data-intensive operations, RAIV is designed to meet and exceed industry expectations. RAIV’s flexible design can be tailored to enhance a broad spectrum of applications, promising accelerated innovation in sectors dependent on AI and machine learning. This GPGPU IP not only underscores Siliconarts' commitment to technological advancement but also highlights its capability to craft solutions that drive forward computational boundaries.
The aLFA-C is a programmable interfacing ASIC designed specifically for space-borne infrared ROICs and other image sensors. It significantly reduces the need for traditional front-end electronics by integrating essential functions onto a single chip. A standout feature includes its capability to operate with a single unregulated supply, aided by on-chip LDOs and regulators. aLFA-C offers extensive programmability, including a fully programmable sequencer for ROIC interfacing, and supports various digital output configurations such as CMOS, LVDS, or CML. It includes SPI interfaces for seamless image sensor integration and features analog acquisition over multiple channels, with high precision 16-bit ADCs, allowing parallel or interleave configuration for flexible data handling speeds. This ASIC is equipped with several measurement capabilities for resistance, voltage, and current, and provides programmable voltage and current sources. With resilience against TID, SEU, and SEL, it's highly reliable in harsh space environments. It's operational over a wide temperature range from 35K to 330K, suitable for varied applications in extreme conditions.
Our Expanded Serial Peripheral Interface (JESD251) Slave controller offers high data throughput, low signal count, and limited backward compatibility with legacy Serial Peripheral Interface (SPI) devices. It is used to connect xSPI Master devices in computing, automotive, Internet of Things, embedded systems, and mobile system processors to non-volatile memories, graphics peripherals, networking peripherals, FPGAs, and sensor devices. Features • Compliant with JEDEC standard JESD251 expanded Serial Peripheral Interface (xSPI) for Non-Volatile Memory Devices, Version 1.0. • Supports Single Data Rate (SDR) and Double Data Rate (DDR). • Supports source synchronous clocking. • Supports data transfer rates up to: o 400MT/s (200MHz Clock) o 333MT/s (167MHz Clock) o 266MT/s (133MHz Clock) o 200MT/s (100MHz Clock) • Supports Deep Power Down (DPD) enter and exit commands. • Standard support for eight IO ports, with the possibility to increase IO ports based on system performance requirements. • Optional support for Data Strobe (DS) for timing reference. • Supports 1-bit wide SDR transfer. • Supports Profile 1.0 commands to manage nonvolatile memory devices. • Supports Profile 2.0 commands for reading or writing data for any type of slave device. • Compatible with non-volatile memory arrays such as NOR Flash, NAND Flash, FRAM, and nvSRAM. • Compatible with volatile memory arrays such as SRAM, PSRAM, and DRAM. • Supports register-mapped input/output functions. • Supports programmable function devices such as FPGAs. Application • Consumer Electronics. • Defence & Aerospace. • Virtual Reality. • Augmented Reality. • Medical. • Biometrics (Fingerprints, etc). • Automotive Devices. • Sensor Devices. Deliverables • Verilog Source code. • User Guide. • IP Integration Guide. • Run and Synthesis script. • Encrypted Verification Testbench Environment. • Basic Test-suite.
The Apodis family of Optical Transport Network processors adheres to ITU-T standards, offering a comprehensive suite for signal termination, processing, and multiplexing. Designed to handle both SONET/SDH and Ethernet client services, these processors map signals to Optical Transport Network (OTN), empowering versatile any-port, any-service configurations. Apodis processors are notable for their capacity to support up to 16 client ports and four 10G OTN line ports, delivering bandwidth scalability up to 40G, crucial for wireless backhaul and fronthaul deployments. With a robust, non-blocking OTN switching fabric, Apodis facilitates seamless client-to-line and line-to-line connections while optimally managing network bandwidth. This adaptability makes the Apodis processors an ideal choice for next-generation access networks and optical infrastructures.
Silicon Creations' Free Running Oscillators provide dependable timing solutions for a range of applications such as watchdog timers and core clock generators in low-power systems. These oscillators, crafted with compactness and efficiency in mind, support a gamut of processes from 65nm to the latest 3nm technologies. These oscillators excel in low power consumption, often requiring less than 30µW during operation. Their robust design ensures they deliver high precision over a temperature range from -40°C to 125°C with supply voltage variabilities factored in. The simplicity in design negates the need for external components, promoting easier integration and reduced overall system complexity. Precise tuning capabilities allow for accuracy levels up to ±1.5% after process trimming, ensuring outstanding performance in volatile environmental conditions. This level of reliability makes them ideal for integration into various consumer electronics, automotive controls, and other precision-demanding applications where space and power constraints are critical.
The ARINC 818-3 IP Core from iWave Global represents an advancement in avionics video interface technology, designed for high-speed and high-fidelity video data transmission. This IP core addresses the needs of modern aerospace systems that require robust video communication links both for military and commercial use. It supports a wide array of enhancements over previous generations, including increased bandwidth and improved signal integrity. This ensures that the ARINC 818-3 IP Core can handle the demands of next-generation avionic systems seamlessly, supporting advanced video processing and display systems. The core's design prioritizes modularity and scalability, allowing for easy integration and expansion to meet evolving system requirements. It is positioned as an essential tool for aviation applications demanding high reliability and accuracy in video data handling and display solutions, making it indispensable for new and retrofitted aerospace projects.
The C100 IoT chip by Chipchain is engineered to meet the diverse needs of modern IoT applications. It integrates a powerful 32-bit RISC-V CPU capable of reaching speeds up to 1.5GHz, with built-in RAM and ROM to facilitate efficient data processing and computational capabilities. This sophisticated single-chip solution is known for its low power consumption, making it ideal for a variety of IoT devices. This chip supports seamless connectivity through embedded Wi-Fi and multiple transmission interfaces, allowing it to serve broad application areas with minimal configuration complexity. Additionally, it boasts integrated ADCs, LDOs, and temperature sensors, offering a comprehensive toolkit for developers looking to innovate across fields like security, healthcare, and smart home technology. Notably, the C100 simplifies the development process with its high level of integration and performance. It stands as a testament to Chipchain's commitment to providing reliable, high-performance solutions for the rapidly evolving IoT landscape. The chip's design focuses on ensuring stability and security, which are critical in IoT installations.
Silicon Creations crafts highly reliable LVDS interfaces designed to meet diverse application needs, going from bi-directional I/Os to specialized uni-directional configurations. Spanning process compatibilities from 90nm CMOS to advanced 7nm FinFET, these interfaces are a cornerstone for high-speed data communication systems, thriving particularly in video data transmission and chip-to-chip communications. Supporting robust data rates over multiple channels, the LVDS Interfaces guarantee flexible programmability and protocol compatibility with standards such as FPD-Link and Camera-Link. They capitalize on proven PLL and CDR architectures for superior signal integrity and error-free data transfers. Operating efficiently in various technology nodes, they remain highly effective across collaborative chipset environments. The interfaces are fortified with adaptable features like dynamic phase alignment to stabilize data sequences and on-die termination options for superior signal integrity. Their proven record places them as a critical enabler in applications where consistent high-speed data transfer is paramount, demonstrating Silicon Creations’ prowess in delivering industry-leading communication solutions.
The Ultra-Low Latency 10G Ethernet MAC from Chevin Technology is designed for FPGA applications that prioritize speed and efficiency. This IP core achieves exceptional data transfer rates with minimized latency, making it ideal for projects where time-sensitive communication is critical. Its design focuses on reducing the complexity and power consumption typical of high-speed Ethernet solutions. A key advantage of this ultra-low latency MAC is its ability to operate without the need for additional CPUs or software, thanks to its all-logic architecture. This not only simplifies integration but also reduces the overall footprint of the design, allowing more space for other functionalities within the FPGA. Targeting industries such as defense and data storage, this Ethernet MAC ensures high reliability and performance. It allows for seamless implementation into various FPGA platforms, demonstrating Chevin Technology's commitment to versatile and adaptable design solutions that meet specific industry needs.
Silicon Creations offers a diverse suite of PLLs designed for a wide range of clocking solutions in modern SoCs. The Robust PLLs cover an extensive range of applications with their multi-functional capability, adaptable for various frequency synthesis needs. With ultra-wide input and output capabilities, and best-in-class jitter performances, these PLLs are ideal for complex SoC environments. Their construction ensures modest area consumption and application-appropriate power levels, making them a versatile choice for numerous clocking applications. The Robust PLLs integrate advanced designs like Low-Area Integer PLLs that minimize component usage while maximizing performance metrics, crucial for achieving high figures of merit concerning period jitter. High operational frequencies and superior jitter characteristics further position these PLLs as highly competitive solutions in applications requiring precision and reliability. By incorporating innovative architectures, they support precision data conversion and adaptable clock synthesis for systems requiring both integer and fractional-N modes without the significant die area demands found in traditional designs.
The AHB-Lite Timer module designed by Roa Logic is compliant with the RISC-V Privileged 1.9.1 specification, offering a versatile timing solution for embedded applications. As an integral peripheral, it provides precise timing functionalities, enabling applications to perform scheduled operations accurately. Its parameterized design allows developers to adjust the timer's features to match the needs of their system effectively. This timer module supports a broad scope of timing tasks, ranging from simple delay setups to complex timing sequences, making it ideal for various embedded system requirements. The flexibility in its design ensures straightforward implementation, reducing complexity and enhancing the overall performance of the target application. With RISC-V compliance at its core, the AHB-Lite Timer ensures synchronization and precision in signal delivery, crucial for systems tasked with critical timing operations. Its adaptable architecture and dependable functionality make it an exemplary choice for projects where timing accuracy is required.
Overview: The Multi-Protocol Accelerator IP is a versatile technology designed to support low latency and high bandwidth accelerators for efficient CPU-to-device and CPU-to-memory communication. It also enables switching for fan-out to connect more devices, memory pooling for increased memory utilization efficiency, and provides memory capacity with support for hot-plug, security enhancements, persistent memory support, and memory error reporting. Key Features:  CXL 3.0 Support: Compliant with CXL spec V3.X/V2.X  PCIe Compatibility: Supports PCIe spec 6.0/5.0  CPI Interface: Support for CPI Interface  AXI Interface: Configurable AXI master, AXI slave  Bus Support: PIPE/FLEX bus, Lane x1,x2,x4,x8,x16  Protocol Support: Gen3, Gen4, Gen5 & Gen6, Fallback Mode  Register Checks: Configuration and Memory Mapped registers  Dual Mode: Supports Dual Mode operation  Transfer Support: HBR/PBR & LOpt Transfers, Standard Cache and Mem Transfers  CXL Support: Can function as both CXL host and device  Data Transfer: Supports Standard IO, 68Byte Flit, and 256Byte Flit Transfers  FlexBus Features: FlexBus Link Features, ARB/MUX, ARB/MUX Bypass  Optimization: Latency Optimization, Credit Return Forcing, Empty Flits (Latency Optimized)  Power Management: Supports Power Management features  Enhancements: CXL IDE, RAS Features, Poison & Viral Handling, MLD/SLD  Testing: Compliance Testing and Error Scenarios support
The AHB-Lite Multilayer Switch by Roa Logic is a sophisticated interconnect fabric that provides high performance with low latency capabilities. Designed for extensive connectivity, it supports an unlimited number of bus masters and slaves, making it ideal for large-scale system architectures. This switch ensures data is efficiently propagated through various paths, optimizing resource allocation and throughput in complex systems. With a focus on performance, the multilayer switch is crafted to manage data traffic within high-demand environments seamlessly. Its support for multiple layers allows it to efficiently handle concurrent data transactions, facilitating effective communication between different system components. The adaptive structure and controlled latency pathways enable it to fit a multitude of applications, including those requiring rapid data transfer and processing. The AHB-Lite Multilayer Switch is engineered to integrate seamlessly into modern system architectures, enhancing throughput without compromising on signal integrity. Its robust design and flexible configuration options make it indispensable within systems necessitating dynamic connectivity solutions.
The RayCore MC is a revolutionary real-time path and ray-tracing GPU designed to enhance rendering with minimal power consumption. This GPU IP is tailored for real-time applications, offering a rich graphical experience without compromising on speed or efficiency. By utilizing advanced ray-tracing capabilities, RayCore MC provides stunning visual effects and lifelike animations, setting a high standard for quality in digital graphics. Engineered for scalability and performance, RayCore MC stands out in the crowded field of GPU technologies by delivering seamless, low-latency graphics. It is particularly suited for applications in gaming, virtual reality, and the burgeoning metaverse, where realistic rendering is paramount. The architecture supports efficient data management, ensuring that even the most complex visual tasks are handled with ease. RayCore MC's architecture supports a wide array of applications beyond entertainment, making it a vital tool in areas such as autonomous vehicles and data-driven industries. Its blend of power efficiency and graphical prowess ensures that developers can rely on RayCore MC for cutting-edge, resource-light graphic solutions.
The GH310 offers high-performance 2D sprite graphics capabilities with an emphasis on pixel throughput and minimal gate count. This makes it an excellent choice for applications that require rapid sprite rendering and high pixel density, such as user interfaces and gaming devices. Its optimized architecture supports efficient sprite operations, making it a versatile choice for embedded systems.
The 10G Ethernet MAC and PCS from Chevin Technology offers a high-performance solution for FPGA-based applications requiring efficient data transfer. Designed to maximize link utilization, this IP core provides sustained high throughput with minimal latency, utilizing a compact architecture that saves space and power. The core is suitable for environments that demand reliable Ethernet connectivity, ensuring optimal performance in FPGA designs. This IP core is particularly beneficial for energy-conscious applications as it operates with lower power consumption compared to solutions requiring additional CPU or software components. The design is optimized for both Intel and AMD FPGAs, providing a versatile solution that is easy to integrate into existing projects. By providing robust data transfer capabilities, the 10G Ethernet MAC and PCS core supports cutting-edge applications in fields such as industrial imaging, data storage, and scientific research. Its design ensures that users can implement multiple cores within a single FPGA, offering flexibility and scalability for a range of Ethernet needs.
A2e's H.264 FPGA Encoder and CODEC Micro Footprint Cores provide a customizable solution targeting FPGAs. Known for its small size and rapid execution, the core supports 1080p60 H.264 Baseline with a singular core, making it one of the industry's swiftest and most efficient FPGA offerings. The core is compliant with ITAR, offering options to adjust pixel depths and resolutions according to specific needs. Its high-performance capability includes offering a latency of just 1ms at 1080p30, which is crucial for applications demanding rapid processing speeds. This licensable core is ideal for developers needing robust video compression capabilities in a compact form factor. The H.264 cores can be finely tuned to meet unique project specifications, enabling developers to implement varied pixel resolutions and depths, further enhancing the core's versatility for different application requirements. With a licensable evaluation option available, prospective users can explore the core’s functionalities before opting for full integration. This flexibility makes it suitable for projects demanding customizable compression solutions without the burden of full-scale initial commitment. Furthermore, A2e provides comprehensive integration and custom design services, allowing these cores to be seamlessly absorbed into existing systems or developed into new solutions. This support ensures minimized risk and accelerated project timelines, allowing developers to focus on innovation and efficiency in their video-centric applications.
The Spiking Neural Processor T1 is an ultra-low power processor developed specifically for enhancing sensor capabilities at the edge. By leveraging advanced Spiking Neural Networks (SNNs), the T1 efficiently deciphers patterns in sensor data with minimal latency and power usage. This processor is especially beneficial in real-time applications, such as audio recognition, where it can discern speech from audio inputs with sub-millisecond latency and within a strict power budget, typically under 1mW. Its mixed-signal neuromorphic architecture ensures that pattern recognition functions can be continually executed without draining resources. In terms of processing capabilities, the T1 resembles a dedicated engine for sensor tasks, offering functionalities like signal conditioning, filtering, and classification independent of the main application processor. This means tasks traditionally handled by general-purpose processors can now be offloaded to the T1, conserving energy and enhancing performance in always-on scenarios. Such functionality is crucial for pervasive sensing tasks across a range of industries. With an architecture that balances power and performance impeccably, the T1 is prepared for diverse applications spanning from audio interfaces to the rapid deployment of radar-based touch-free interactions. Moreover, it supports presence detection systems, activity recognition in wearables, and on-device ECG processing, showcasing its versatility across various technological landscapes.
The Ethernet Real-Time Publish-Subscribe (RTPS) IP Core is crafted to provide a comprehensive hardware implementation of the Ethernet RTPS protocol. This core is indispensable in real-time communication networks that require the seamless integration of data streams with minimal latency. It ensures low-latency operation and efficient data exchange, which are crucial for mission-critical applications. Designing systems capable of maintaining integrity and synchronous data dissemination is the primary goal of this IP core. It is optimally structured to ensure swift data processing, making it a key component in systems where real-time data publishing and subscription minimize response delays. The RTPS IP Core stands out as a strategic solution for real-time networking in communication-intensive industries.
ELFIS2 is a sophisticated visible light imaging ASIC designed to deliver superior performance under the extreme conditions typical in space. Known for its radiation hard design, it withstands both total ionizing dose (TID) and single event effects (SEU/SEL), ensuring dependable operation even when exposed to high radiation levels in outer space. This image sensor features HDR (High Dynamic Range) capabilities, which allow it to capture clear, contrast-rich images in environments with varying light intensities, without motion artifacts thanks to its Motion Artifact Free (MAF) technology. Additionally, its global shutter ensures that every pixel is exposed simultaneously, preventing distortion in high-speed imaging applications. Utilizing back-side illumination (BSI), the ELFIS2 achieves superior sensitivity and quantum efficiency, making it an ideal choice for challenging lighting conditions. This combination of advanced features makes the ELFIS2 particularly well-suited for scientific and space-based imaging applications requiring exacting standards.
The DisplayPort 1.4 core provides a comprehensive solution for DisplayPort requirements, implementing both source and sink capabilities. It supports link rates ranging from 1.62 Gbps to 8.1 Gbps, fitting standard DisplayPort and eDP scenarios efficiently. Users can take advantage of its support for multiple lanes, specifically 1, 2, and 4 lanes configurations, enabling versatile video interface options such as Native and AXI stream interfaces. This facilitates a strong multimedia performance, catering to both Single Stream Transport (SST) and Multi Stream Transport (MST) modes. The video processing toolkit accompanying this IP aims at aiding users in diverse video operations. These tools include a timing generator, a versatile test pattern generator, and crucial video clock recovery mechanisms. To simplify the integration into various systems, the IP is supported across a broad range of FPGA devices, including AMD and Intel lines, providing users with choice and flexibility for their specific application needs. Notably, it supports diverse video formats and color spaces, such as RGB, YCbCr 4:4:4, 4:2:2, and 4:2:0 at pixel depths of 8 and 10 bits. Secondary data packets handling audio and metadata enhance its multimedia capabilities. Furthermore, Parretto offers the source code on GitHub for ease of custom development, ensuring developers have the tools they need to adapt the IP to their unique systems.
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