All IPs > Wireless Communication
The Wireless Communication category at Silicon Hub encompasses a diverse array of semiconductor IPs designed to facilitate seamless wireless connectivity in today's rapidly evolving technological landscape. As the demand for higher data rates and uninterrupted connectivity grows, these IPs play a vital role in enabling devices to communicate efficiently across various protocols and standards. This category includes highly specialized IPs that support the implementation and enhancement of wireless communication technologies in a variety of applications ranging from consumer electronics to industrial systems.
Within this category, semiconductor IPs cover a wide spectrum of wireless standards and protocols. This includes evolving mobile communication standards like 3GPP-5G and LTE, which are essential for cellular networks' operation and are pivotal in the deployment of the latest 5G networks. For localized wireless communication, standards such as 802.11 (commonly referred to as Wi-Fi), Bluetooth, NFC, and Wireless USB are covered, facilitating device interconnectivity and data exchange in numerous consumer electronics, IoT devices, and more. Industrial and professional applications may utilize IPs related to standards like WiMAX (802.16), CPRI, OBSAI, which are crucial for network infrastructure and robust communication systems.
In addition to these, the Wireless Communication category includes IPs for satellite navigation systems like GPS, ensuring accurate geolocation services essential for navigation devices in both personal and commercial use. Standards like UWB (Ultra-Wideband) offer high-speed data transmission over short ranges, beneficial for applications demanding rapid short-range communication. Furthermore, for high-definition broadcasting, IPs supporting Digital Video Broadcast standards offer necessary capabilities to meet market demands for clear and reliable video content transmission.
This extensive category of semiconductor IPs under Wireless Communication not only provides the architectural needs for state-of-the-art communication devices but also accommodates future technological advancements. By integrating these IPs, semiconductor product designers and engineers can efficiently develop solutions tailored for enhanced connectivity, ensuring their products remain at the forefront of technological innovation and meet the ever-growing expectations of modern consumers for instant and reliable wireless communication. Whether you are developing next-gen smartphones, IoT solutions, or advanced networking systems, these IPs are critical components in achieving superior performance and connectivity.
BrainChip's Akida Neural Processor IP is a groundbreaking development in neuromorphic processing, designed to mimic the human brain in interpreting sensory inputs. By implementing an event-based architecture, it processes only the critical data at the point of acquisition, achieving unparalleled performance with significantly reduced power consumption. This architecture enables on-chip learning, reducing dependency on cloud processing, thus enhancing privacy and security.\n\nThe Akida Neural Processor IP supports incremental learning and high-speed inference across a vast range of applications, making it highly versatile. It is structured to handle data sparsity effectively, which cuts down on operations substantially, leading to considerable improvements in efficiency and responsiveness. The processor's scalability and compact design allow for wide deployment, from minimal-node setups for ultra-low power operations to more extensive configurations for handling complex tasks.\n\nImportantly, the Akida processor uses a fully customizable AI neural processor that leverages event-based processing and an on-chip mesh network for seamless communication. The technology also features support for hybrid quantized weights and provides robust tools for integration, including fully synthesizable RTL IP packages, hardware-based event processing, and on-chip learning capabilities.
The Akida 2nd Generation is an evolution of BrainChip's innovative neural processor technology. It builds upon its predecessor's strengths by delivering even greater efficiency and a broader range of applications. The processor maintains an event-based architecture that optimizes performance and power consumption, providing rapid response times suitable for edge AI applications that prioritize speed and privacy.\n\nThis next-generation processor enhances accuracy with support for 8-bit quantization, which allows for finer grained processing capabilities and more robust AI model implementations. Furthermore, it offers extensive scalability, supporting configurations from a few nodes for low-power needs to many nodes for handling more complex cognitive tasks. As with the previous version, its architecture is inherently cloud-independent, enabling inference and learning directly on the device.\n\nAkida 2nd Generation continues to push the boundaries of AI processing at the edge by offering enhanced processing capabilities, making it ideal for applications demanding high accuracy and efficiency, such as automotive safety systems, consumer electronics, and industrial monitoring.
The Low Density Parity Check (LDPC) codes are powerful, capacity approaching channel codes and have exceptional error correction capabilities. The high degree of parallelism that they offer enables efficient, high throughput hardware architectures. The ntLDPC_WiFi6 IP Core is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes and is fully compliant with IEEE 802.11 n/ac/ax standard. The Quasi-Cyclic LDPC codes are based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that they offer high throughput at low implementation complexity. The ntLDPC_WiFi6 decoder IP Core may optionally implement one of two approximations of the log-domain LDPC iterative decoding algorithm (Belief propagation) known as either Layered Normalized Offset Min-Sum Algorithm or Layered Lambda-min Algorithm. Selecting between the two algorithms presents a decoding performance .vs. system resources utilization trade-off. The core is highly reconfigurable and fully compliant to the IEEE 802.11 n/ac/ax Wi-Fi4, Wi-Fi5 and Wi-Fi 6 standards. The ntLDPC_WiFi6 encoder IP implements a 81-bit parallel systematic LDPC encoder. An off-line profiling Matlab script processes the original matrices and produces a set of constants that are associated with the matrix and hardcoded in the RTL encoder.
The **Ceva-Waves Bluetooth platform** includes field-proven hardware IP for baseband controller, modem, and 2.4 GHz RF transceiver functions, and allows use of many third-party radio IPs as well. The platform includes optimized baseband controller hardware and software, and above the Host Controller Interface (HCI) a host-agnostic software protocol stack supporting all major Bluetooth profiles. The built-in 802.15.4 add-on suite shares the same Bluetooth radio, and includes IEEE 802.15.4 MAC & modem hardware IP and software, and is compatible with Zigbee, Thread and Matter host protocol stacks. The Ceva-Waves Bluetooth platform is also available as part of the **Ceva-Waves Links family** of multi-protocol turnkey platforms, including with optimized Wi-Fi & Bluetooth co-existence interface and packet traffic arbiter. The Ceva-Waves Bluetooth platforms also comprises a state-of-the-art radio in TSMC 12nm FFC+ supporting all the latest Bluetooth 6.0 dual mode features, along with next gen Bluetooth High Data Throughput and IEEE 802.15.4. Its innovative architecture provides best in class performance in term of power consumption, die size, sensitivity and output power. [**Learn more about Ceva's Bluetooth solution>**](https://www.ceva-ip.com/product/ceva-waves-bluetooth/?utm_source=silicon_hub&utm_medium=ip_listing&utm_campaign=ceva_waves_bluetooth_page)
**Ceva-Waves UWB platform** cuts the development time and risk for implementing a wide range of UWB functionality in SoCs. It provides optimized MAC and PHY hardware IP and supporting software for secure and accurate ranging, and Doppler Radar presence detection applications. It can be implemented in an SoC independently or in conjunction with the Ceva-Waves Bluetooth platform, as well as part of the Ceva-Waves Links family of multiprotocol platforms. The Ceva-Waves UWB platform includes hardware IP for an optimized UWB MAC and PHY meeting 802.15.4 HRP, FiRa 3.0, and the Car Connectivity Consortium Digital Key 3.0 (CCC DK3.0) requirements. The platform includes advanced Wi-Fi interference suppression. A comprehensive suite of CPU-agnostic software stacks that support FiRa 3.0 MAC, CCC DK3.0 MAC, and radar for implementing applications such as automotive digital keys and in-cabin child-presence detection (CPD), general power-saving presence detection in laptops, TVs and smart buildings, asset tracking tags, real-time location services (RTLS), and tap-free payment. [**Learn more about our UWB soluion>**](https://www.ceva-ip.com/product/ceva-waves-uwb/?utm_source=silicon_hub&utm_medium=ip_listing&utm_campaign=ceva_waves_uwb_page)
The Polar ID Biometric Security System by Metalenz revolutionizes smartphone biometric security with its advanced imaging capabilities that capture the full polarization state of light. This system detects unique facial polarization signatures, enabling high-precision face authentication that even sophisticated 3D masks cannot deceive. Unlike traditional systems requiring multiple optical modules, Polar ID achieves secure recognition with a single image, ideal for secure digital payments and more. Operating efficiently across various lighting conditions, from bright daylight to complete darkness, Polar ID ensures robust security without compromising user convenience. By leveraging meta-optic technology, it offers a compact, cost-effective alternative to structured light solutions, suitable for widespread deployment across millions of mobile devices.
**Ceva-XC21** is the most efficient vector DSP core available today for communications applications. The Ceva-XC21 DSP is designed for low-power, cost- and size-optimized cellular IoT modems, NTN VSAT terminals, eMBB and uRLLC applications. Ceva-XC21 offers scalable architecture and dual thread design with support for AI, addressing growing demand for smarter, yet more cost and power efficient cellular devices. Targeted for 5G and 5G-Advanced workloads, the Ceva-XC21 has multiple products configurations enabling system designers to optimize the size and cost to their specific application needs. The Ceva-XC21, based on the advanced Ceva-XC20 architecture, features a product line of 3 vector DSP cores. Each of the cores offers a unique performance & area configuration with a SW compatibility between them. The different cores span across single thread or dual thread configurations, and 32 or 64 16bits x 16bits MACs. The Ceva-XC212, the highest performing variant of the Ceva-XC21 delivers up to 1.8x times the performance of Ceva’s previous-generation Ceva-XC4500 architecture, while reducing the core area. Ceva-XC210, the smallest configuration of the Ceva-XC21, enables system designers to reduce the core die size in 48% compared with the previous generation. Ceva-XC211 offers the same performance envelope compared with the previous generation at 63% of the area. [**Learn more about Ceva-XC21>**](https://www.ceva-ip.com/product/ceva-xc21/?utm_source=silicon_hub&utm_medium=ip_listing&utm_campaign=ceva_xc21_page)
The HOTLink II Product Suite is another remarkable offering from Great River Technology. Built to complement their ARINC 818 suite, HOTLink II provides an integrated framework for crafting high-performance digital data links. This suite ensures seamless, secure, and reliable data transmission over fiber or copper cables across various platforms. Developed with a focus on flexibility and functionality, the HOTLink II capabilities enhance system integrators' ability to deploy effective communication solutions within aircraft and other demanding environments. The emphasis on robust, low-latency data transfer makes it an ideal choice for real-time applications where precision and reliability are paramount. Broad compatibility is a hallmark of HOTLink II, facilitating integration into diverse infrastructures. Backed by Great River Technology's expertise and support, customers are empowered to advance their system communication capabilities efficiently and cost-effectively.
EW6181 is an IP solution crafted for applications demanding extensive integration levels, offering flexibility by being licensable in various forms such as RTL, gate-level netlist, or GDS. Its design methodology focuses on delivering the lowest possible power consumption within the smallest footprint. The EW6181 effectively extends battery life for tags and modules due to its efficient component count and optimized Bill of Materials (BoM). Additionally, it is backed by robust firmware ensuring highly accurate and reliable location tracking while offering support and upgrades. The IP is particularly suitable for challenging application environments where precision and power efficiency are paramount, making it adaptable across different technology nodes given the availability of its RF frontend.
The ORC3990 SoC is a state-of-the-art solution designed for satellite IoT applications within Totum's DMSS™ network. This low-power sensor-to-satellite system integrates an RF transceiver, ARM CPUs, memories, and PA to offer seamless IoT connectivity via LEO satellite networks. It boasts an optimized link budget for effective indoor signal coverage, eliminating the need for additional GNSS components. This compact SoC supports industrial temperature ranges and is engineered for a 10+ year battery life using advanced power management.
The ntLDPC_5GNR Base Graph Encoder IP Core is defined in 3GPP TS 38.212 standard document and it is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes. The specification defines two sets of LDPC Base Graphs and their respective derived Parity Check Matrices. Each Base Graph can be combined with 8 sets of lifting sizes (Zc) in a total of 51 different lifting sizes. This way by using the 2 Base Graphs, the 5G NR specification defines up to 102 possible distinct LDPC modes of operation to select from, for optimum decoding performance, depending on target application code block size and code rate (using the additional rate matching module features). For Base Graph 1 we have LDPC(N=66xZc,K=22xZc) sized code blocks, while for Base Graph 2 we have LDPC(N=50xZc,K=[6,8,9,10]xZc) sized code blocks. The ntLDPCE_5GNR Encoder IP implements a multi-parallel systematic LDPC encoder. Parallelism depends on the selected lifting sizes subsets chosen for implementation. Shortened blocks are supported with granularity at lifting size Zc-bit boundaries. Customizable modes generation is also supported beyond the scope of the 5G-NR specification with features such as: “flat parity bits puncturing instead of Rate Matching Bit Selection”, “maintaining the first 2xZc payload bits instead of eliminating it before transmission”, etc. The ntLDPCD_5GNR decoder IP implements a maximum lifting size of Zc_MAX-bit parallel systematic LDPC layered decoder. Each layer corresponds to Zc_MAX expanded rows of the original LDPC matrix. Each layer element corresponds to the active ZcxZc shifted identity sub-matrices within the layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit, in order to update the layers LLR estimates and extrinsic information iteratively until the required number of decoding iterations has been run. The decoder IP also features a powerful optional early termination (ET) criterion, to maintain practically equivalent error correction performance, while significantly increasing its throughput rate and/or reducing hardware cost. Additionally it reports how many decoding iterations have been performed when ET is activated, for system performance observation and calibration purposes. Finally a simple, yet robust, flow control handshaking mechanism is included in both IPs, which is used to communicate the IPs availability to adjacent system components. This logic is easily portable into any communication protocol, like AXI4 stream IF.
The NeuroVoice chip by Polyn Technology is engineered to improve voice processing capabilities for a variety of consumer electronic devices, particularly focusing on addressing challenges associated with traditional digital voice solutions. Built on the NASP platform, this AI chip is tailored to operate efficiently in noisy environments without relying on cloud-based processing, thus ensuring privacy and reducing latency. A key feature of NeuroVoice is its ultra-low power consumption, which allows continuous device operation even in power-sensitive applications like wearables and smart home devices. It includes abilities such as always-on voice activity detection, smart voice control, speaker recognition, and real-time voice extraction. This amalgamation of capabilities makes the NeuroVoice a versatile component in enhancing voice-controlled systems' efficacy. NeuroVoice stands out by seamlessly integrating into devices, offering users the advantage of precise voice recognition and activity detection with minimal energy demands. It further differentiates itself by delivering clear communication even amidst irregular background noises, setting a new benchmark for on-device audio processing with its advanced neural network-driven design.
The Nerve IIoT Platform is a comprehensive solution for machine builders, offering cloud-managed edge computing capabilities. This innovative platform delivers high levels of openness, security, flexibility, and real-time data handling, enabling businesses to embark on their digital transformation journeys. Nerve's architecture allows for seamless integration with a variety of hardware devices, from basic gateways to advanced IPCs, ensuring scalability and operational efficiency across different industrial settings. Nerve facilitates the collection, processing, and analysis of machine data in real-time, which is crucial for optimizing production and enhancing operational efficiency. By providing robust remote management functionalities, businesses can efficiently handle device operations and application deployments from any location. This capacity to manage data flows between the factory floor and the cloud transitions enterprises into a new era of digital management, thereby minimizing costs and maximizing productivity. The platform also supports multiple cloud environments, empowering businesses to select their preferred cloud service while maintaining operational continuity. With its secure, IEC 62443-4-1 certified infrastructure, Nerve ensures that both data and applications remain protected from cyber threats. Its integration of open technologies, such as Docker and virtual machines, further facilitates rapid implementation and prototyping, enabling businesses to adapt swiftly to ever-changing demands.
Convolutional FEC codes are very popular because of their powerful error correction capability and are especially suited for correcting random errors. The most effective decoding method for these codes is the soft decision Viterbi algorithm. ntVIT core is a high performance, fully configurable convolutional FEC core, comprised of a 1/N convolutional encoder, a variable code rate puncturer/depuncturer and a soft input Viterbi decoder. Depending on the application, the core can be configured for specific code parameters requirements. The highly configurable architecture makes it ideal for a wide range of applications. The convolutional encoder maps 1 input bit to N encoded bits, to generate a rate 1/N encoded bitstream. A puncturer can be optionally used to derive higher code rates from the 1/N mother code rate. On the encoder side, the puncturer deletes certain number of bits in the encoded data stream according to a user defined puncturing pattern which indicates the deleting bit positions. On the decoder side, the depuncturer inserts a-priori-known data at the positions and flags to the Viterbi decoder these bits positions as erasures. The Viterbi decoder uses a maximum-likelihood detection recursive process to cor-rect errors in the data stream. The Viterbi input data stream can be composed of hard or soft bits. Soft decision achieves a 2 to 3dB in-crease in coding gain over hard-decision decoding. Data can be received continuously or with gaps.
The TW330 Image Warping IP utilizes advanced GPU processing technology to offer high-performance image distortion correction. It features extensive capabilities including coordinate transformation, any-shape image transformations, and supports resolutions up to 16K x 16K for both RGB and YUV formats. Ideal for digitally correcting images distorted by wide-angle or fish-eye lenses on various devices, this technology is key in fields such as automotive display systems, VR/AR devices, and high-definition projectors. It makes real-time, on-the-fly image correction feasible, elevating the quality of visual outputs for demanding applications. Through its flexible and efficient design, TW330 enables seamless integration into systems requiring dynamic and precise image modification capabilities, paving the way for developing more interactive and immersive visual experiences.
The Dual-Drive™ Power Amplifier FCM1401 exemplifies advanced engineering in power amplification, designed specifically for extreme efficiency in wireless communication devices. Operating at a center frequency of 14 GHz, it boasts a sophisticated architecture that minimizes silicon area while enhancing performance metrics. One of the standout features of the FCM1401 is its impressive core drain efficiency, which reaches up to 62%, offering significant power savings and extended battery life for end users. Such efficiencies are particularly crucial in mobile devices, where power remains a critical resource. Moreover, this power amplifier features a dual-stage design to facilitate better signal strength and lower transmission losses. With an optimally configured supply voltage range, the FCM1401 performs without efficiency bottlenecking, crucial for systems with constrained power budgets. Its meticulous construction results in an efficiency at device output around 70%, allowing it to outperform competitors across various metrics. These enhancements not only make the FCM1401 ideal for mobile and satellite communications but also align perfectly with initiatives to lower telecommunication costs through energy-efficient technology. Supported by a drain efficiency that peaks even under full load conditions, Falcomm’s FCM1401 assures users of reliability under diverse operational scenarios. The assurance of minimal loss in complex QAM scenarios further underscores its potential for diverse communication applications. This exemplary power amplifier serves as a testament to Falcomm's commitment to innovation, combining unprecedented efficiency with practical applications in everyday technology.
The Hyperspectral Imaging System developed by Imec represents a significant advancement in the realm of imaging technology. This sophisticated system is capable of capturing and processing a wide spectrum of wavelengths simultaneously, making it ideal for detailed spectral analysis in both industrial and research applications. This imaging system is instrumental in providing accurate and high-resolution data that can be crucial in fields like agriculture, environmental monitoring, and medical diagnostics. Imec's Hyperspectral Imaging System is notable for its integration into small and efficient devices, enabling portable and flexible use in various scenarios. The system's design leverages cutting-edge nanoelectronics to ensure that it is both lightweight and highly functional, offering unparalleled performance on the go. Its ability to capture detailed spectral information expands its utility across multiple disciplines, making it a versatile tool for addressing complex analytical challenges. The unique technology behind this system is grounded in Imec's expertise in photonics and CMOS sensors, ensuring superior sensitivity and precision. This hyperspectral imaging technology is designed to provide real-time, reliable information with a high degree of accuracy, supporting applications that require detailed spectroscopic data, thus empowering industries to make more informed decisions.
Palma Ceia SemiDesign's 802.11ah HaLow Transceiver is developed to meet the critical requirements for next-generation IoT and mobile devices. This component caters to applications where extended battery life and long-range capabilities are imperative. Conforming to the IEEE 802.11ah standard, it effectively supports a range of modulation bandwidths while offering low-noise operation and superior receiver sensitivity. One of its significant advantages is its low current consumption, which greatly extends battery life, a crucial factor for IoT devices. The transceiver's robust design incorporates a balanced, low-noise receiver capable of processing a wide range of signal levels, ensuring reliability even in challenging environments. The inclusion of features like integrated DC offset correction and I/Q calibration further underscores its practical application for stable and precise signal processing. Easy interface compatibility and a host of modulation options position the 802.11ah HaLow Transceiver as an ideal choice for a multitude of IoT deployments, from asset management to building automation. Its adaptability to both standalone and SoC integration enhances its usability across various sectors, attesting to its comprehensive design and performance.
AccelerComm's LDPC solution stands out for its innovative design that marries block-parallel and row-parallel architectures to deliver peak performance and efficiency. Primarily designed for 5G NR use cases, this product supports both data and control channels, proving its versatility across different communication requirements. With a focus on maximizing throughput and minimizing latency, the LDPC decoder is optimized for various hardware formats, including ASIC, FPGA, and software implementations. It supports a wide range of configurations, allowing it to adapt to specific performance requirements across applications. This LDPC solution has been rigorously validated against IEEE standards and offers enhanced error correction capabilities within a compact design. By reducing resource demands while improving overall communication reliability, it exemplifies AccelerComm's commitment to leading-edge technological solutions.
CANmodule-III is a feature-rich CAN controller designed to optimize communications in embedded systems. It supports the concept of mailboxes, offering 16 receive buffers and 8 transmit buffers, each with its own filter for precise control. The module is compliant with the ISO 11898-1 standard for CAN 2.0A/B, making it suitable for automotive and industrial applications where robust and reliable communication is critical. With an AMBA 3 APB interface, it integrates smoothly into ARM-based SoCs, while its synchronous design allows for efficient operation without waiting periods. This module's architecture includes a programmable priority arbitration mechanism, ensuring that messages with a higher priority are transmitted first, an essential feature in systems where timing is crucial. Its design is scalable, allowing for adaptation to specific system requirements, making it versatile for use in various embedded systems. The module also supports features like single-shot transmission and offers debugging support through listen-only and loopback modes. In addition to its core functionality, the CANmodule-III boasts a robust interrupt management system, capable of handling multiple error sources. This includes a locally controlled interrupt and an optional external AHB interface for broader system compatibility. All these features are designed to ensure seamless integration into larger systems, providing a comprehensive CAN controller solution that is adaptable and efficient.
CANmodule-IIIx is an advanced CAN controller core that supports a vast array of communication needs in embedded systems. This module enhances message management with 32 receive and 32 transmit buffers, each equipped with its own filter. Designed to comply with ISO 11898-1, it facilitates comprehensive CAN 2.0A/B communications, ensuring compatibility and performance across multiple applications, including automotive and robotics industries. The module includes an AMBA 3 APB interface for straightforward integration within ARM-based SoCs and is structured using technology-independent HDL, which allows it to be easily adapted to both ASIC and FPGA platforms. Its design offers robust message handling, with programmable priority arbitration that secures the timely transmission of critical messages, a crucial feature in environments demanding immediate response. Providing extensive support for higher layer protocols, the CANmodule-IIIx covers essential elements like automatic RTR response handling and generates interrupts for various message and error conditions. Debugging is also simplified through its listen-only, internal, and external loopback modes. This multibuffering system offers enhanced message management suitable for complex and critical operations.
AccelerComm's High PHY Accelerators provide a suite of IP cores designed to boost signal processing capabilities for 5G New Radio applications. Integrating patented high-performance algorithms, this library of accelerators ensures peak throughput and efficiency, facilitating robust signal processing across ASIC, FPGA, and SoC platforms. These accelerators are characterized by their ability to significantly reduce latency and improve spectral efficiency, making them indispensable in high-demand environments. By supporting a wide array of features, including high-throughput modulation/demodulation and sophisticated error correction techniques, the accelerators empower systems to handle intricate data transmission with precision. Moreover, these accelerators seamlessly integrate with existing hardware platforms, offering a versatile solution for enhancing signal processing in diverse network scenarios. Their robust design and functionality reflect AccelerComm's commitment to driving innovation in communication technologies.
Polar encoding and decoding for 5G NR leverages AccelerComm's expertise in creating sophisticated IP that reduces resource and memory demands while delivering superior BLER performance. This solution, selected for 5G NR control channels, utilizes PC- and CRC-aided SCL polar decoding techniques to achieve high error correction accuracy. The polar IP is fully compliant with 3GPP NR standards, encompassing the entire encoding and decoding chain required for seamless integration. It offers high levels of parallel processing and scalability, making it suitable for diverse applications, from simple to complex data transmission systems. With its configurable design, the Polar IP allows adjustments in decoder list size to best fit specific BLER and PPA requirements. This flexibility, combined with its efficient integration capabilities, underscores its role as a critical enabler of efficient, high-performance wireless communication solutions.
The ASPER sensor operates at a 79GHz frequency, making it a sophisticated module for automotive applications like parking assistance. This short-range radar sensor boasts a coverage of 180 degrees with a superior detection range that extends beyond other conventional technology, such as ultrasonic systems. Its application in vehicle systems allows for enhanced features, including rear and front collision warning, blind spot detection, and more. ASPER is designed to detect low-lying objects and maintain accurate function in adverse weather conditions like fog or rain, making it a versatile component for comprehensive vehicle safety and awareness systems.
The GNSS VHDL Library is a cornerstone offering from GNSS Sensor Ltd, engineered to provide a potent solution for those integrating Global Navigation Satellite System functionalities. This library is lauded for its configurability, allowing developers to harness the power of satellite navigation on-chip efficiently. It facilitates the incorporation of GPS, GLONASS, and Galileo systems into digital designs with minimum fuss. Designed to be largely independent from specific CPU platforms, the GNSS VHDL Library stands out for its flexibility. It employs a single configuration file to adapt to different hardware environments, ensuring broad compatibility and ease of implementation. Whether for research or commercial application, this library allows for rapid prototyping of reliable GNSS systems, providing essential building blocks for precise navigation capabilities. Integrating fast search engines and offering configurable signal processing capabilities, the library supports scalability across platforms, making it a crucial component for industries requiring high-precision navigation technology. Its architecture supports both 32-bit SPARC-V8 and 64-bit RISC-V system-on-chips, highlighting its adaptability and cutting-edge design.
The eSi-Comms suite is a versatile toolset designed for enabling sophisticated communication functionalities in integrated circuits. Known for its high degree of parameterization, this communication IP adapts to various industry standards, effectively facilitating connectivity across a range of applications. Built to support modern wireless and wireline standards like Wi-Fi, Li-Fi, LTE, and DVB, eSi-Comms demonstrates a balance between adaptability and high performance, suiting dynamic communication environments. It facilitates robust network communications, ensuring seamless data exchange and reliable connectivity in demanding scenarios. EnSilica's focus on optimized resource usage allows eSi-Comms to deliver top-tier communication capabilities with minimized power consumption, a crucial feature in portable and battery-operated devices. Furthermore, its integration ability ensures that it aligns with diverse system architectures, enhancing interoperability across different technology ecosystems.
**Ceva-Waves Links** is a growing family of multi-standard wireless platforms. By optimizing connectivity support for various combinations of **Wi-Fi, Bluetooth, 802.15.4, and ultra-wideband (UWB)**, the Ceva-Waves Links family provides preconfigured, optimized solutions for SoCs requiring multiple connectivity standards. All Ceva-Waves Links configurations are based on field-proven Ceva-Waves hardware IP and software stacks. Unique Ceva coexistence algorithms ensure efficient and interference-free operation of multiple connections while sharing one radio. The **Ceva-Waves Links family** offers combinations of Ceva-Waves Wi-Fi, Ceva-Waves Bluetooth, 802.15.4 (supporting protocols such as Thread, Matter and Zigbee), and Ceva-Waves UWB hardware IP, integrated with Ceva or third-party radios and CPU- and OS-agnostic software stacks. New platforms will be introduced to address market trends or customers’ demands. [**Learn more about Ceva-Waves Links family solution>**](https://www.ceva-ip.com/product/ceva-waves-links/?utm_source=silicon_hub&utm_medium=ip_listing&utm_campaign=ceva_waves_links_page)
The ARINC 818 Direct Memory Access (DMA) component provides a thorough hardware IP solution tailored for the transmission and reception of the ARINC 818 protocol. Engineered for use in embedded systems applications, it optimizes formatting, timing, and buffer management, crucial for maintaining seamless operations. This core takes significant responsibilities off the main processor, boosting efficiency across embedded environments by handling demanding protocol requirements robustly. Its architecture is optimized to enhance embedded application performance, promoting smooth and efficient interactions between diverse system components. Critical for protocol offloading, this solution delivers substantial improvements in processing times and data management within advanced communication infrastructures. The ARINC 818 DMA is essential for systems faced with complex data engagements, ensuring resource maximization without compromise on performance or reliability.
Functioning as a comprehensive cross-correlator, the XCM_64X64 facilitates efficient and precise signal processing required in synthetic radar receivers and advanced spectrometers. Designed on IBM's 45nm SOI CMOS technology, it supports ultra-low power operation at about 1.5W for the entire array, with a sampling performance of 1GSps across a bandwidth of 10MHz to 500MHz. The ASIC is engineered to manage high-throughput data channels, a vital component for high-energy physics and space observation instruments.
The transceiver is designed to be used together with an RF tuner, and ADC/DAC converters. The system has internal state machine to control the operation, and can be externally configured via the SPI interface. This design is a Mobile WiMAX baseband transceiver core for both Base station and Mobile station, supplied as a portable and synthesizable Verilog-2001 IP. The system was designed to be used in conjunction with a standard RF tuner. The operation of the transceiver is automated by a master finite state machine.
Ubi.cloud is a breakthrough geolocation solution designed to offload GPS and Wi-Fi computing tasks to the cloud effectively. This innovation results in significantly smaller, more efficient geolocation devices, ideal for IoT tracking applications. By reducing the size and energy consumption of the hardware, Ubi.cloud provides organizations with the ability to deploy diverse tracking solutions across their operations. It supports global GPS positioning for outdoor use and Wi-Fi for indoor urban tracking, making it versatile for various needs. Designed to minimize the inherent power and size issues of traditional GNSS modules, Ubi.cloud leverages advanced embedded technologies like UbiGNSS and UbiWIFI. These allow for remarkable on-time performance improvements compared to traditional setups, drastically cutting down receiver chipset consumption and boosting battery life. With Ubi.cloud, businesses can integrate cutting-edge geolocation capabilities into their devices using a pay-as-you-go model or life-time licenses, ensuring flexibility in application. This makes it ideal for asset tracking of unpowered devices, fitting into existing systems seamlessly or being part of new innovative designs.
The XCM_64X64_A is a powerful array designed for cross-correlation operations, integrating 128 ADCs each capable of 1GSps. Targeted at high-precision synthetic radar and radiometer systems, this ASIC delivers ultra-low power consumption around 0.5W, ensuring efficient performance over a wide bandwidth range from 10MHz to 500MHz. Built on IBM's 45nm SOI CMOS technology, it forms a critical component in systems requiring rapid data sampling and intricate signal processing, all executed with high accuracy, making it ideal for airborne and space-based applications.
The PCS2100 is Palma Ceia SemiDesign's innovative solution specifically engineered for IoT communication within Wi-Fi HaLow networks. This single modem chip is designed for client-side applications, essential for creating a robust IoT ecosystem as envisioned under the IEEE 802.11ah specification. The PCS2100 is integral in enhancing network span owing to its operational capability in sub-gigahertz frequencies, extending communication range up to a kilometer. Characterized by low power consumption and efficient data handling, the PCS2100 stands out in environments demanding scalable throughput and long-lasting operational life. Its architectural design supports advanced features like Target Wake Time (TWT) and Resource Allocation Windowing (RAW), allowing fine-tuned control of device activity to significantly conserve energy in demanding IoT applications. The PCS2100's support for narrow-band transmission, coupled with sophisticated modulation schemes, gives it a performance edge in sensor-intensive environments. This makes it ideal for applications that require continuous connectivity and efficient data streaming, such as surveillance systems or industrial monitoring. Its comprehensive interface options further enhance its integration and deployment flexibility in various IoT settings.
The UHS-II solution for high-definition content is meticulously designed for rapid data transfer, catering predominantly to high-performance storage applications. This solution efficiently supports various high-definition content formats, ensuring seamless transmission and integration with sophisticated imaging devices. Its extensive compatibility with diverse storage systems and high-speed interfaces enables it to meet the rigorous demands of modern digital video and photographic environments.
The 802.15.4 Transceiver Core is essential for low-rate wireless personal area networks (LR-WPANs), supporting applications like Zigbee and other IoT communication standards. This core offers an excellent balance of low power consumption and reliable data transfer, crucial for devices that require sustained battery operation. Tailored for use in smart homes and industrial environments, this transceiver core provides robust security features and scalability to support a comprehensive range of connected devices. It simplifies the integration process by providing a complete RF solution that reduces total component count and cost. The transceiver is built on RF CMOS technology, enabling it to be stably implemented in varied settings without performance degradation. Its design ensures compatibility with a broad range of sensors and devices, reinforcing its position as a versatile and reliable choice for any networking need in IoT and automation applications.
ArrayNav is a groundbreaking GNSS solution utilizing patented adaptive antenna technology, crafted to provide automotive Advanced Driver-Assistance Systems (ADAS) with unprecedented precision and capacity. By employing multiple antennas, ArrayNav substantially enhances sensitivity and coverage through increased antenna gain, mitigates multipath fading with antenna diversity, and offers superior interference and jamming rejection capabilities. This advancement leads to greater accuracy in open environments and markedly better functionality within urban settings, often challenging due to signal interference. It is designed to serve both standalone and cloud-dependent use cases, thereby granting broad application flexibility.
Arteris's Ncore Cache Coherent Interconnect IP addresses the complex challenges of multi-core ASIC development, offering a scalable, highly configurable solution for coherent network-on-chip designs. This IP supports multiple protocols, including Arm and RISC-V, and is engineered to comply with ISO 26262 for safety-critical applications. Ncore enables seamless communication and cache coherence across varied processor cores, enhancing performance while meeting stringent functional safety standards. Its capability to automate Fault Modes Effects and Diagnostic Analysis (FMEDA) further simplifies safety compliance, proving its value in advanced SoCs where reliability and high throughput are critical.
The 802.11 LDPC core by Wasiela is engineered for high throughput applications in wireless communication systems. It excels in providing frame-to-frame on-the-fly configuration, allowing developers to balance throughput and error correction performance according to specific needs. This LDPC solution is compliant with relevant throughput and performance specifications, ensuring reliable bit-error-rate and packet-error-rate outcomes that meet industry standards. The core's adaptability in decoding iterations is key to maintaining high efficiency without compromising on quality.
The mmWave PLL is a robust phase-locked loop designed specifically for millimeter-wave frequencies. This advanced PLL offers low phase noise and supports high-frequency bands crucial for various wireless communication and radar applications. Its compact design and broad frequency coverage make it a versatile component for next-generation wireless and communication hardware, including IoT devices and high-speed data links.
Dyumnin Semiconductors' RISCV SoC is a robust solution built around a 64-bit quad-core server-class RISC-V CPU, designed to meet advanced computing demands. This chip is modular, allowing for the inclusion of various subsystems tailored to specific applications. It integrates a sophisticated AI/ML subsystem that features an AI accelerator tightly coupled with a TensorFlow unit, streamlining AI operations and enhancing their efficiency. The SoC supports a multimedia subsystem equipped with IP for HDMI, Display Port, and MIPI, as well as camera and graphic accelerators for comprehensive multimedia processing capabilities. Additionally, the memory subsystem includes interfaces for DDR, MMC, ONFI, NorFlash, and SD/SDIO, ensuring compatibility with a wide range of memory technologies available in the market. This versatility makes it a suitable choice for devices requiring robust data storage and retrieval capabilities. To address automotive and communication needs, the chip's automotive subsystem provides connectivity through CAN, CAN-FD, and SafeSPI IPs, while the communication subsystem supports popular protocols like PCIe, Ethernet, USB, SPI, I2C, and UART. The configurable nature of this SoC allows for the adaptation of its capabilities to meet specific end-user requirements, making it a highly flexible tool for diverse applications.
Trion FPGAs by Efinix are engineered for the fast-paced edge and IoT markets. Built on a 40 nm process, these FPGAs offer a wide range of logic density from 4K to 120K logic elements. They bring power-performance-area advantages for general-purpose custom logic applications, including mobile and IoT markets, while also enhancing computing capabilities in emerging technologies such as deep learning and edge computing. The Trion family is known for its small packages, which enable its deployment in highly integrated systems. Features such as the DDR DRAM Controller and MIPI CSI-2 Controller are hardened into the architecture, ensuring smooth data management and transfer in applications that demand real-time processing. This makes Trion FPGAs an excellent choice for various industrial, medical, and consumer applications where space and power efficiency are critical. With a focus on longevity, Efinix supports Trion FPGAs with a stable product lifecycle, aligning with market requirements for dependable, production-ready solutions. These FPGAs are versatile enough to serve applications in edge computing, video processing, industrial automation, and more, offering a complete system solution with their embedded interfaces and soft processor systems.
Wireless IP developed by Analog Circuit Works provides essential capabilities for portable, medical, and sensor application domains. These IP blocks are critical in enabling wireless power and data transmission, thereby supporting the autonomy and versatility of modern devices that rely heavily on wireless technologies. The solutions offered are designed with a focus on maximizing frequency capabilities while ensuring efficiency across various environmental scenarios. This adaptability ensures that these IPs meet the rigorous demands of applications where wireless communication and power provisioning are at the forefront of user expectations. Analog Circuit Works' wireless solutions are fine-tuned to provide enhanced robustness and reliability, facilitating seamless integration within devices that require stable and sustained wireless operations. As a result, they are perfectly suited for innovations in IoT and other rapidly evolving technology landscapes requiring high-quality wireless interface and communication solutions.
The RWM6050 Baseband Modem is a cutting-edge component designed for high-efficiency wireless communications, ideally suited for dense data transmission environments. This modem acts as a fundamental building block within Blu Wireless's product portfolio, enabling seamless integration into various network architectures. Focusing on addressing the needs of complex wireless systems, the RWM6050 optimizes data flow and enhances connectivity capabilities within mmWave deployments. Technical proficiency is at the core of RWM6050's design, targeting high-speed data processing and signal integrity. It supports multiple communication standards, ensuring compatibility and flexibility in diverse operational settings. The modem's architecture is crafted to manage substantial data payloads effectively, fostering reliable, high-bandwidth communication across different sectors, including telecommunications and IoT applications. The RWM6050 is engineered to simplify the setup of communication networks and improve performance in crowded signal environments. Its robust design not only accommodates the challenges posed by demanding applications but also anticipates future advancements within wireless communication technologies. The modem provides a scalable yet efficient solution that meets the industry's evolving requirements.
Digital PreDistortion (DPD) technology is pivotal for enhancing the efficiency of RF power amplifiers. Systems4Silicon's DPD offering, known as FlexDPD, is a comprehensive adaptive linearization subsystem. This solution is vendor-independent, allowing for seamless compilation whether targeting ASICs, FPGAs, or SoC platforms. It is engineered to boost radio transmission efficiency dramatically.\n\nFlexDPD is adaptable to evolving market needs, supporting multi-standard, multi-carrier wireless systems like 5G and O-RAN networks. Its field-proven scalability ensures it can manage transmission bandwidths exceeding 1 GHz, making it apt for various applications with high data throughput demands. The technology has been crafted to align with the growing complexity and performance expectations of modern wireless networks.\n\nThe solution enhances the power efficiency by effectively linearizing amplifiers, thus mitigating distortions and optimizing output. It ensures systems run at optimal power levels, crucial for energy savings and overall operational efficiency within high-frequency communication environments. Systems4Silicon provides extensive support services, ensuring smooth implementation and ongoing optimization for FlexDPD users.
ntLDPC_SDAOCT IP implements a 5G-NR Base Graph 1 systematic Encoder/Decoder based on Quasi-Cyclic LDPC Codes (QC-LDPC), with lifting size Zc=384 and Information Block Size 8448 bits. The implementation is based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that it offers high throughput at low implementation complexity. The ntLDPCE_SDAOCT Encoder IP implements a systematic LDPC Zc=384 encoder. Input and Output may be selected to be 32-bit or 128-bits per clock cycle prior to synthesis, while internal operations are 384-bits parallel per clock cycle. Depending on code rate, the respective amount of parity bits are generated and the first 2xZc=768 payload bits are discarded. There are 5 code rate modes of operation available (8448,8448)-bypass, (9984,8448)-0.8462, (11136,8448)-0.7586, (12672,8448)-0.6667 and (16896,8448)-0.5. The ntLDPCD_SDAOCT Base Graph Decoder IP may optionally implement one of two approximations of the log-domain LDPC iterative decoding algorithm (Belief propagation) known as either Layered Min-Sum Algorithm (MS) or Layered Lambda-min Algorithm (LMIN). Variations of Layered MS available are Offset Min-Sum (OMS), Normalized Min-Sum (NMS), and Normalized Offset Min-Sum (NOMS). Selecting between these algorithms presents a decoding performance vs. system resources utilization trade-off. The ntLDPCD_SDAOCT decoder IP implements a Zc=384 parallel systematic LDPC layered decoder. Each layer corresponds to Zc=384 expanded rows of the original LDPC matrix. Each layer element corresponds to the active ZcxZc shifted identity submatrices within the layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit, in order to update the layers LLR estimates and extrinsic information iteratively until the required number of decoding iterations has been run. The decoder IP also features a powerful optional early termination (ET) criterion, to maintain practically equivalent error correction performance, while significantly increasing its throughput rate and/or reducing hardware cost. Additionally it reports how many decoding iterations have been performed when ET is activated, for system performance observation and calibration purposes. Finally a simple, yet robust, flow control handshaking mechanism is included in both IPs, which is used to communicate the IPs availability to adjacent system components. This logic is easily portable into any communication protocol, like AXI4 stream IF.
The Dynamic PhotoDetector for Smartphone Applications is ActLight's state-of-the-art solution for enhancing mobile light sensing technology. This component integrates cutting-edge Dynamic PhotoDetector capabilities, utilizing a unique mode of operation that offers unprecedented levels of sensitivity and performance in detecting light changes. Aimed at applications like proximity and ambient light sensing, the DPD ensures that smartphones can dynamically adjust functions such as screen brightness and feature activation based on environmental lighting, thereby offering users a richer, more adaptive experience. It is particularly efficient in optimizing power consumption due to its ability to operate at lower voltages than traditional sensors, which not only preserves battery life but also supports sustainable device usage. The sensor's design allows for seamless incorporation into existing smartphone architectures without necessitating major redesigns, enabling manufacturers to easily enhance their devices with high-precision light sensing capabilities. Its ability to capture highly accurate 3D data further paves the way for innovative applications in augmented and virtual realities, making the DPD a versatile tool for future-looking smartphone features.
ParkerVision's Direct-to-Data (D2D) Technology marks a transformative development in RF communication, significantly enhancing the performance of modern smartphones and wireless devices. This innovative technology replaces the century-old super-heterodyne downconverter with a new RF downconverter that operates efficiently within CMOS architectures. D2D allows RF receivers to connect more seamlessly across global bands while processing high data rates essential for today's media and communication needs. D2D RF receivers built on ParkerVision technology minimize power usage while delivering fast data speeds, substantially contributing to the functionality and efficiency of modern smartphones. These receivers are capable of handling a wide spectrum of data rates from streaming video to large data transfers, thanks to their high-performance design capable of managing a range of signal strengths from various distances with cellular towers. This patented technology plays a crucial role in the smartphone revolution, with its incorporation leading to smarter, faster devices. These developments are enabled by a precise downconversion mechanism that transforms high-frequency RF signals into data-efficient formats. The D2D technology reduces the traditional noise and signal loss, making it a cornerstone in the advancement of mobile and IoT device communication strategies.
The PACE Photonic Arithmetic Computing Engine from Lightelligence represents a paradigm shift in computing technologies. By utilizing photonic processes, this product significantly boosts computing speeds while maintaining energy efficiency. PACE is designed to leverage the inherent capabilities of photonics to perform high-speed arithmetic calculations, which are essential for complex data processing tasks. It's an ideal solution for industries demanding rapid and intensive computational power without the typical energy overhead.<br> <br> This advanced engine is central to the development of next-generation computing environments, where performance metrics exceed traditional expectations. By converting light signals into computing potential, PACE ensures that intensive processes such as AI computations, data analyses, and real-time processing are handled more efficiently. This product is tailored for enterprises seeking to minimize latency and enhance throughput across various applications.<br> <br> PACE not only meets the requirements of current computational demands but also sets the stage for future innovations in the field. It's a promising tool for developers and researchers aiming to explore the unexplored realms of digital capabilities, fostering an era of optical computing that's faster and more efficient than ever before. This makes PACE an indispensable component in both current and upcoming technological advancements.
In channel coding redundancy is inserted in the transmitted information bit-stream. This redundant information is used in the decoder to eliminate the channel noise. The error correction capability of a FEC system strongly depends on the amount of redundancy as well as on the coding algorithm itself. TPCs perform well in the moderate to high SNRs because the effect of error floor is less. As TPCs have more advantage when a high rate code is used, they are suitable for commercial applications in wireless and satellite communications. The ntTPC Turbo Product Codec IP core is consisted of the Turbo Product Encoder (ntTPCe) and the Turbo Product Decoder (ntTPCd) blocks. The product code C is derived from two/three constituent codes, namely C1, C2 and optionally C3. The information data is encoded in two/three dimensions. Every row of C is a code of C2 and every column of C is a code of C1. When the third coding dimension is enabled, then there are C3 C1*C2 data planes. The ntTPC core supports both e-Hamming and Single Parity Codes as the constituent codes. The core also supports shortening of rows or columns of the product table, as well as turbo shortening. Shortening is a way of providing more powerful codes by removing information bits from the code. The ntTPCe core receives the information bits row by row from left to right and transmits the encoded bits in the same order. It consists of a row, column and 3D encoder. The ntTPCd decoder receives soft information from the channel in the 2’s complement number system and the input samples are received row by row from left to right. The implemented decoding algorithm computes the extrinsic information for every dimension C1, C2, C3 by iteratively decoding words that are near the soft-input word. An advanced scalable and parametric design approach produces custom design versions tailored to end customer applications design tradeoffs.
The PCD03D Turbo Decoder is adept at handling multiple state decoding for standards such as DVB-RCS and IEEE 802.16 WiMAX. Its core design features an 8-state duobinary decoding structure, facilitating precise and quick signal deconstruction. Additionally, the optional inclusion of a 64-state Viterbi decoder enhances versatility and performance in various environments. This decoder is tailored for applications where agility and high data throughput are critical, making it an invaluable asset in wireless communication infrastructures. The decoder’s architecture supports expansive VHDL core integration, providing durable solutions across FPGA platforms.
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