All IPs > Wireless Communication
The Wireless Communication category at Silicon Hub encompasses a diverse array of semiconductor IPs designed to facilitate seamless wireless connectivity in today's rapidly evolving technological landscape. As the demand for higher data rates and uninterrupted connectivity grows, these IPs play a vital role in enabling devices to communicate efficiently across various protocols and standards. This category includes highly specialized IPs that support the implementation and enhancement of wireless communication technologies in a variety of applications ranging from consumer electronics to industrial systems.
Within this category, semiconductor IPs cover a wide spectrum of wireless standards and protocols. This includes evolving mobile communication standards like 3GPP-5G and LTE, which are essential for cellular networks' operation and are pivotal in the deployment of the latest 5G networks. For localized wireless communication, standards such as 802.11 (commonly referred to as Wi-Fi), Bluetooth, NFC, and Wireless USB are covered, facilitating device interconnectivity and data exchange in numerous consumer electronics, IoT devices, and more. Industrial and professional applications may utilize IPs related to standards like WiMAX (802.16), CPRI, OBSAI, which are crucial for network infrastructure and robust communication systems.
In addition to these, the Wireless Communication category includes IPs for satellite navigation systems like GPS, ensuring accurate geolocation services essential for navigation devices in both personal and commercial use. Standards like UWB (Ultra-Wideband) offer high-speed data transmission over short ranges, beneficial for applications demanding rapid short-range communication. Furthermore, for high-definition broadcasting, IPs supporting Digital Video Broadcast standards offer necessary capabilities to meet market demands for clear and reliable video content transmission.
This extensive category of semiconductor IPs under Wireless Communication not only provides the architectural needs for state-of-the-art communication devices but also accommodates future technological advancements. By integrating these IPs, semiconductor product designers and engineers can efficiently develop solutions tailored for enhanced connectivity, ensuring their products remain at the forefront of technological innovation and meet the ever-growing expectations of modern consumers for instant and reliable wireless communication. Whether you are developing next-gen smartphones, IoT solutions, or advanced networking systems, these IPs are critical components in achieving superior performance and connectivity.
The Akida 2nd Generation represents a leap forward in the realm of AI processing, enhancing upon its predecessor with greater flexibility and improved efficiency. This advanced neural processor core is tailored for modern applications demanding real-time response and ultra-low power consumption, making it ideal for compact and battery-operated devices. Akida 2nd Generation supports various programming configurations, including 8-, 4-, and 1-bit weights and activations, thus providing developers with the versatility to optimize performance versus power consumption to meet specific application needs. Its architecture is fully digital and silicon-proven, ensuring reliable deployment across diverse hardware setups. With features such as programmable activation functions and support for sophisticated neural network models, Akida 2nd Generation enables a broad spectrum of AI tasks. From object detection in cameras to sophisticated audio sensing, this iteration of the Akida processor is built to handle the most demanding edge applications while sustaining BrainChip's hallmark efficiency in processing power per watt.
**Ceva-Waves Links** is a growing family of multi-standard wireless platforms. By optimizing connectivity support for various combinations of **Wi-Fi, Bluetooth, 802.15.4, and ultra-wideband (UWB)**, the Ceva-Waves Links family provides preconfigured, optimized solutions for SoCs requiring multiple connectivity standards. All Ceva-Waves Links configurations are based on field-proven Ceva-Waves hardware IP and software stacks. Unique Ceva coexistence algorithms ensure efficient and interference-free operation of multiple connections while sharing one radio. The **Ceva-Waves Links family** offers combinations of Ceva-Waves Wi-Fi, Ceva-Waves Bluetooth, 802.15.4 (supporting protocols such as Thread, Matter and Zigbee), and Ceva-Waves UWB hardware IP, integrated with Ceva or third-party radios and CPU- and OS-agnostic software stacks. New platforms will be introduced to address market trends or customers’ demands. [**Learn more about Ceva-Waves Links family solution>**](https://www.ceva-ip.com/product/ceva-waves-links/?utm_source=silicon_hub&utm_medium=ip_listing&utm_campaign=ceva_waves_links_page)
The **Ceva-Waves Bluetooth platform** includes field-proven hardware IP for baseband controller, modem, and 2.4 GHz RF transceiver functions, and allows use of many third-party radio IPs as well. The platform includes optimized baseband controller hardware and software, and above the Host Controller Interface (HCI) a host-agnostic software protocol stack supporting all major Bluetooth profiles. The built-in 802.15.4 add-on suite shares the same Bluetooth radio, and includes IEEE 802.15.4 MAC & modem hardware IP and software, and is compatible with Zigbee, Thread and Matter host protocol stacks. The Ceva-Waves Bluetooth platform is also available as part of the **Ceva-Waves Links family** of multi-protocol turnkey platforms, including with optimized Wi-Fi & Bluetooth co-existence interface and packet traffic arbiter. The Ceva-Waves Bluetooth platforms also comprises a state-of-the-art radio in TSMC 12nm FFC+ supporting all the latest Bluetooth 6.0 dual mode features, along with next gen Bluetooth High Data Throughput and IEEE 802.15.4. Its innovative architecture provides best in class performance in term of power consumption, die size, sensitivity and output power. [**Learn more about Ceva's Bluetooth solution>**](https://www.ceva-ip.com/product/ceva-waves-bluetooth/?utm_source=silicon_hub&utm_medium=ip_listing&utm_campaign=ceva_waves_bluetooth_page)
**Ceva-XC21** is the most efficient vector DSP core available today for communications applications. The Ceva-XC21 DSP is designed for low-power, cost- and size-optimized cellular IoT modems, NTN VSAT terminals, eMBB and uRLLC applications. Ceva-XC21 offers scalable architecture and dual thread design with support for AI, addressing growing demand for smarter, yet more cost and power efficient cellular devices. Targeted for 5G and 5G-Advanced workloads, the Ceva-XC21 has multiple products configurations enabling system designers to optimize the size and cost to their specific application needs. The Ceva-XC21, based on the advanced Ceva-XC20 architecture, features a product line of 3 vector DSP cores. Each of the cores offers a unique performance & area configuration with a SW compatibility between them. The different cores span across single thread or dual thread configurations, and 32 or 64 16bits x 16bits MACs. The Ceva-XC212, the highest performing variant of the Ceva-XC21 delivers up to 1.8x times the performance of Ceva’s previous-generation Ceva-XC4500 architecture, while reducing the core area. Ceva-XC210, the smallest configuration of the Ceva-XC21, enables system designers to reduce the core die size in 48% compared with the previous generation. Ceva-XC211 offers the same performance envelope compared with the previous generation at 63% of the area. [**Learn more about Ceva-XC21>**](https://www.ceva-ip.com/product/ceva-xc21/?utm_source=silicon_hub&utm_medium=ip_listing&utm_campaign=ceva_xc21_page)
**Ceva-Waves UWB platform** cuts the development time and risk for implementing a wide range of UWB functionality in SoCs. It provides optimized MAC and PHY hardware IP and supporting software for secure and accurate ranging, and Doppler Radar presence detection applications. It can be implemented in an SoC independently or in conjunction with the Ceva-Waves Bluetooth platform, as well as part of the Ceva-Waves Links family of multiprotocol platforms. The Ceva-Waves UWB platform includes hardware IP for an optimized UWB MAC and PHY meeting 802.15.4 HRP, FiRa 3.0, and the Car Connectivity Consortium Digital Key 3.0 (CCC DK3.0) requirements. The platform includes advanced Wi-Fi interference suppression. A comprehensive suite of CPU-agnostic software stacks that support FiRa 3.0 MAC, CCC DK3.0 MAC, and radar for implementing applications such as automotive digital keys and in-cabin child-presence detection (CPD), general power-saving presence detection in laptops, TVs and smart buildings, asset tracking tags, real-time location services (RTLS), and tap-free payment. [**Learn more about our UWB soluion>**](https://www.ceva-ip.com/product/ceva-waves-uwb/?utm_source=silicon_hub&utm_medium=ip_listing&utm_campaign=ceva_waves_uwb_page)
The Low Density Parity Check (LDPC) codes are powerful, capacity approaching channel codes and have exceptional error correction capabilities. The high degree of parallelism that they offer enables efficient, high throughput hardware architectures. The ntLDPC_WiFi6 IP Core is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes and is fully compliant with IEEE 802.11 n/ac/ax standard. The Quasi-Cyclic LDPC codes are based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that they offer high throughput at low implementation complexity. The ntLDPC_WiFi6 decoder IP Core may optionally implement one of two approximations of the log-domain LDPC iterative decoding algorithm (Belief propagation) known as either Layered Normalized Offset Min-Sum Algorithm or Layered Lambda-min Algorithm. Selecting between the two algorithms presents a decoding performance .vs. system resources utilization trade-off. The core is highly reconfigurable and fully compliant to the IEEE 802.11 n/ac/ax Wi-Fi4, Wi-Fi5 and Wi-Fi 6 standards. The ntLDPC_WiFi6 encoder IP implements a 81-bit parallel systematic LDPC encoder. An off-line profiling Matlab script processes the original matrices and produces a set of constants that are associated with the matrix and hardcoded in the RTL encoder.
**Ceva-PentaG2** is a complete IP platform for implementing a wide range of user-equipment and IoT cellular modems. The platform includes a variety of DSPs, modem hardware modules, software libraries, and simulation tools. Capabilities of the Ceva-PentaG2 include New Radio (NR) physical layer design ranging across all 3GPP profiles from RedCap IoT and mMTC, through eMBB up to ultra-reliable low-latency communications (URLLC). The platform has two base configurations. Ceva-PentaG2 Max emphasizes performance and scalability for enhanced mobile broadband (eMBB) and future proofing design for next generation 5G-Advanced releases. Ceva-PentaG2 Lite emphasizes extreme energy and area efficiency for lower-throughput applications such as LTE Cat 1, RedCap, and optimized cellular IoT applications. The PentaG2 platform comprises a set of Ceva DSP cores, optimized fixed-function hardware accelerators, and proven, optimized software modules. By using this platform, designers can implement optimized, hardware-accelerated processing chains for all main modem functions. In the selection process, designers can tune their design for any point across a huge space of area, power consumption, latency, throughput, and channel counts. Solutions can fit applications ranging from powerful eMBB for mobile and Fixed Wireless Access (FWA) devices to connected vehicles, cellular IoT modules, and even smart watches. System-C models in Ceva’s Virtual Platform Simulator (VPS) aid architectural exploration and system tuning, while an FPGA-based emulation kit speeds SoC integration. [**Learn more about Ceva-PentaG2 solution>**](https://www.ceva-ip.com/product/ceva-pentag2/?utm_source=silicon_hub&utm_medium=ip_listing&utm_campaign=ceva_pentag2_page)
**Ceva-Waves Dragonfly platform** is a turnkey platform with optimized, low-power hardware IP and protocol software for implementing narrow-band IoT (NB-IoT) cellular modem SoCs. Extensions provide support for GNSS such as GPS and BeiDou and for sensor-fusion applications. The Ceva-Waves Dragonfly platform comprises hardware IP with an enhanced Ceva-BX1 processor, specific hardware accelerators, and SoC infrastructure IP. Software includes NB-IoT protocol stack for L1 through L3 functions including encryption and software PHY, a task-optimized RTOS, and optional GNSS receiver and control software, all executing on the Ceva-BX1. Pre-certified for 3GPP Release 15 CAT NB2, the solution is tuned for small footprint and extremely low power, yet has headroom for additional software-defined functions, such as sensor fusion. [**Learn more about Ceva-Waves Dragonfly>**](https://www.ceva-ip.com/product/ceva-waves-dragonfly/?utm_source=silicon_hub&utm_medium=ip_listing&utm_campaign=ceva_waves_dragonfly_page)
Chimera GPNPU is engineered to revolutionize AI/ML computational capabilities on single-core architectures. It efficiently handles matrix, vector, and scalar code, unifying AI inference and traditional C++ processing under one roof. By alleviating the need for partitioning AI workloads between different processors, it streamlines software development and drastically speeds up AI model adaptation and integration. Ideal for SoC designs, the Chimera GPNPU champions an architecture that is both versatile and powerful, handling complex parallel workloads with a single unified binary. This configuration not only boosts software developer productivity but also ensures an enduring flexibility capable of accommodating novel AI model architectures on the horizon. The architectural fabric of the Chimera GPNPU seamlessly blends the high matrix performance of NPUs with C++ programmability found in traditional processors. This core is delivered in a synthesizable RTL form, with scalability options ranging from a single-core to multi-cluster designs to meet various performance benchmarks. As a testament to its adaptability, the Chimera GPNPU can run any AI/ML graph from numerous high-demand application areas such as automotive, mobile, and home digital appliances. Developers seeking optimization in inference performance will find the Chimera GPNPU a pivotal tool in maintaining cutting-edge product offerings. With its focus on simplifying hardware design, optimizing power consumption, and enhancing programmer ease, this processor ensures a sustainable and efficient path for future AI/ML developments.
Great River Technology offers the ARINC 818 Product Suite, a comprehensive collection of tools and products designed to cover the full spectrum of ARINC 818 applications. This suite is pivotal for engineers and designers who are focused on the aviation sector, providing solutions necessary for the creation, testing, and deployment of high-speed digital interfaces in avionics. The suite supports design and implementation phases by offering robust support tools tailored for ARINC 818 development, including detailed implementers' guides and simulation resources. What's unique about this suite is its ability to facilitate process integrations for ARINC 818 standards across various platforms, making it adaptable for differing needs in aviation systems. The integration tools provided ensure that systems can efficiently manage data and video transmissions, providing clarity, speed, and reliability, all essential factors in mission-critical environments. Great River Technology’s ARINC 818 Product Suite is engineered to ensure seamless interoperability, offering support from initial project development through to practical operation, thus enabling avionic systems to function optimally in both standard and specialized conditions.
ntLDPC_SDAOCT IP implements a 5G-NR Base Graph 1 systematic Encoder/Decoder based on Quasi-Cyclic LDPC Codes (QC-LDPC), with lifting size Zc=384 and Information Block Size 8448 bits. The implementation is based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that it offers high throughput at low implementation complexity. The ntLDPCE_SDAOCT Encoder IP implements a systematic LDPC Zc=384 encoder. Input and Output may be selected to be 32-bit or 128-bits per clock cycle prior to synthesis, while internal operations are 384-bits parallel per clock cycle. Depending on code rate, the respective amount of parity bits are generated and the first 2xZc=768 payload bits are discarded. There are 5 code rate modes of operation available (8448,8448)-bypass, (9984,8448)-0.8462, (11136,8448)-0.7586, (12672,8448)-0.6667 and (16896,8448)-0.5. The ntLDPCD_SDAOCT Base Graph Decoder IP may optionally implement one of two approximations of the log-domain LDPC iterative decoding algorithm (Belief propagation) known as either Layered Min-Sum Algorithm (MS) or Layered Lambda-min Algorithm (LMIN). Variations of Layered MS available are Offset Min-Sum (OMS), Normalized Min-Sum (NMS), and Normalized Offset Min-Sum (NOMS). Selecting between these algorithms presents a decoding performance vs. system resources utilization trade-off. The ntLDPCD_SDAOCT decoder IP implements a Zc=384 parallel systematic LDPC layered decoder. Each layer corresponds to Zc=384 expanded rows of the original LDPC matrix. Each layer element corresponds to the active ZcxZc shifted identity submatrices within the layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit, in order to update the layers LLR estimates and extrinsic information iteratively until the required number of decoding iterations has been run. The decoder IP also features a powerful optional early termination (ET) criterion, to maintain practically equivalent error correction performance, while significantly increasing its throughput rate and/or reducing hardware cost. Additionally it reports how many decoding iterations have been performed when ET is activated, for system performance observation and calibration purposes. Finally a simple, yet robust, flow control handshaking mechanism is included in both IPs, which is used to communicate the IPs availability to adjacent system components. This logic is easily portable into any communication protocol, like AXI4 stream IF.
**Ceva-Waves Wi-Fi platforms portfolio** provide a comprehensive selection of hardware IP and CPU-agnostic host software for energy-efficient SoC implementation of any of a wide range of Wi-Fi subsystems, from Wi-Fi 4 to Wi-Fi 7, for both client devices and access points. The portfolio includes a suite of pre-optimized solutions for various generations and configurations for specific Wi-Fi uses, power consumption levels, and price points, ranging from low-bandwidth IoT connectivity to high-bandwidth hubs. Embedded into one of the Ceva-Waves Links multi-protocol wireless platforms, the Ceva-Waves Wi-Fi IPs can efficiently co-exist with the Ceva-Waves Bluetooth IPs and/or Ceva-Waves UWB IP. The Ceva-Waves Wi-Fi platforms comprise hardware modem PHY IP that supports DSSS, CCK, OFDM and OFDMA modulations; optimized MAC IP that offloads MAC functions from the CPU; and a comprehensive selection of MAC protocol software stacks. The IP and software elements are further organized into three main solution profiles. * Wi-Fi IoT is for energy-efficient low-bandwidth connectivity for IoT devices, supporting 2.4GHz single band or dual/triple bands on 2.4/5/6 GHz for IEEE 802.11n, ax, or be (Wi-Fi 4, 6 or 7). * Wi-Fi High-Performance supports up to 160 MHz bands at 2.4, 5, or 6 GHz in either single-antenna or 2×2 MIMO mode for IEEE 802.11ax or be (Wi-Fi 6 or 7), and is intended for consumer media-streaming applications. * Wi-Fi Access Point supports 160 MHz bands and 2×2 MIMO for IEEE 802.11ax or be (Wi-Fi 6/6E/7), for applications such as media access points, gateways, and small-cell offload that must support up to hundreds of clients. The Ceva-Waves Wi-Fi platforms include a coexistence interface that permits highly efficient operation with the Ceva-Waves Bluetooth platforms. [**Learn more about Ceva-Waves Wi-Fi solution>**](https://www.ceva-ip.com/product/ceva-waves-wi-fi/?utm_source=silicon_hub&utm_medium=ip_listing&utm_campaign=ceva_waves_wifi_page)
aiSim 5 stands as a cutting-edge simulation tool specifically crafted for the automotive sector, with a strong focus on validating ADAS and autonomous driving solutions. It distinguishes itself with an AI-powered digital twin creation capability, offering a meticulously optimized sensor simulation environment that guarantees reproducibility and determinism. The adaptable architecture of aiSim allows seamless integration with existing industry toolchains, significantly minimizing the need for costly real-world testing.\n\nOne of the key features of aiSim is its capability to simulate various challenging weather conditions, enhancing testing accuracy across diverse environments. This includes scenarios like snowstorms, heavy fog, and rain, with sensors simulated based on physics, offering changes in conditions in real-time. Its certification with ISO 26262 ASIL-D attests to its automotive-grade quality and reliability, providing a new standard for testing high-fidelity sensor data in varied operational design domains.\n\nThe flexibility of aiSim is further highlighted through its comprehensive SDKs and APIs, which facilitate smooth integration into various systems under test. Additionally, users can leverage its extensive 3D asset library to establish detailed, realistic testing environments. AI-based rendering technologies underpin aiSim's data simulation, achieving both high efficiency and accuracy, thereby enabling rapid and effective validation of advanced driver assistance and autonomous driving systems.
The Ncore Cache Coherent Interconnect is designed to tackle the complexities inherent in multicore SoC environments. By maintaining coherence across heterogeneous cores, it enables efficient data sharing and optimizes cache use. This in turn enhances the throughput of the system, ensuring reliable performance with reduced latency. The architecture supports a wide range of cores, making it a versatile option for many applications in high-performance computing. With Ncore, designers can address the challenges of maintaining data consistency across different processor cores without incurring significant power or performance penalties. The interconnect's capability to handle multicore scenarios means it is perfectly suited for advanced computing solutions where data integrity and speed are paramount. Additionally, its configuration options allow customization to meet specific project needs, maintaining flexibility in design applications. Its efficiency in multi-threading environments, coupled with robust data handling, marks it as a crucial component in designing state-of-the-art SoCs. By supporting high data throughput, Ncore keeps pace with the demands of modern processing needs, ensuring seamless integration and operation across a variety of sectors.
Systems4Silicon's DPD solution enhances power efficiency in RF power amplifiers by using advanced predistortion techniques. This technology is part of a comprehensive subsystem known as FlexDPD, which is adaptive and scalable, independent of any particular hardware platform. It supports multiple radio standards, including 5G and O-RAN, and is ready for deployment on either ASICs or FPGA platforms. Engineered for field performance, it offers a perfect balance of reliability and adaptability across numerous applications, meeting broad technical requirements.
The EW6181 GPS and GNSS solution from EtherWhere is tailored for applications requiring high integration levels, offering licenses in RTL, gate-level netlist, or GDS formats. This highly adaptable IP can be ported across various technology nodes, provided an RF frontend is available. Designed to be one of the smallest and most power-efficient cores, it optimizes battery life significantly in devices such as tags and modules, making it ideal for challenging environments. The IP's strengths lie in its digital processing capabilities, utilizing cutting-edge DSP algorithms for precision and reliability in location tracking. With a digital footprint approximately 0.05mm² on a 5nm node, the EW6181 boasts a remarkably compact size, aiding in minimal component use and a streamlined Bill of Materials (BoM). Its stable firmware ensures accurate and reliable position fixations. In terms of implementation, this IP offers a combination of compact design and extreme power efficiency, providing substantial advantages in battery-operated environments. The EW6181 delivers critical support and upgrades, facilitating seamless high-reliability tracking for an array of applications demanding precise navigation.
Convolutional FEC codes are very popular because of their powerful error correction capability and are especially suited for correcting random errors. The most effective decoding method for these codes is the soft decision Viterbi algorithm. ntVIT core is a high performance, fully configurable convolutional FEC core, comprised of a 1/N convolutional encoder, a variable code rate puncturer/depuncturer and a soft input Viterbi decoder. Depending on the application, the core can be configured for specific code parameters requirements. The highly configurable architecture makes it ideal for a wide range of applications. The convolutional encoder maps 1 input bit to N encoded bits, to generate a rate 1/N encoded bitstream. A puncturer can be optionally used to derive higher code rates from the 1/N mother code rate. On the encoder side, the puncturer deletes certain number of bits in the encoded data stream according to a user defined puncturing pattern which indicates the deleting bit positions. On the decoder side, the depuncturer inserts a-priori-known data at the positions and flags to the Viterbi decoder these bits positions as erasures. The Viterbi decoder uses a maximum-likelihood detection recursive process to cor-rect errors in the data stream. The Viterbi input data stream can be composed of hard or soft bits. Soft decision achieves a 2 to 3dB in-crease in coding gain over hard-decision decoding. Data can be received continuously or with gaps.
The ntLDPC_5GNR Base Graph Encoder IP Core is defined in 3GPP TS 38.212 standard document and it is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes. The specification defines two sets of LDPC Base Graphs and their respective derived Parity Check Matrices. Each Base Graph can be combined with 8 sets of lifting sizes (Zc) in a total of 51 different lifting sizes. This way by using the 2 Base Graphs, the 5G NR specification defines up to 102 possible distinct LDPC modes of operation to select from, for optimum decoding performance, depending on target application code block size and code rate (using the additional rate matching module features). For Base Graph 1 we have LDPC(N=66xZc,K=22xZc) sized code blocks, while for Base Graph 2 we have LDPC(N=50xZc,K=[6,8,9,10]xZc) sized code blocks. The ntLDPCE_5GNR Encoder IP implements a multi-parallel systematic LDPC encoder. Parallelism depends on the selected lifting sizes subsets chosen for implementation. Shortened blocks are supported with granularity at lifting size Zc-bit boundaries. Customizable modes generation is also supported beyond the scope of the 5G-NR specification with features such as: “flat parity bits puncturing instead of Rate Matching Bit Selection”, “maintaining the first 2xZc payload bits instead of eliminating it before transmission”, etc. The ntLDPCD_5GNR decoder IP implements a maximum lifting size of Zc_MAX-bit parallel systematic LDPC layered decoder. Each layer corresponds to Zc_MAX expanded rows of the original LDPC matrix. Each layer element corresponds to the active ZcxZc shifted identity sub-matrices within the layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit, in order to update the layers LLR estimates and extrinsic information iteratively until the required number of decoding iterations has been run. The decoder IP also features a powerful optional early termination (ET) criterion, to maintain practically equivalent error correction performance, while significantly increasing its throughput rate and/or reducing hardware cost. Additionally it reports how many decoding iterations have been performed when ET is activated, for system performance observation and calibration purposes. Finally a simple, yet robust, flow control handshaking mechanism is included in both IPs, which is used to communicate the IPs availability to adjacent system components. This logic is easily portable into any communication protocol, like AXI4 stream IF.
LightningBlu is a cutting-edge solution provided by Blu Wireless, designed specifically to serve the high-speed rail industry. This technology offers consistent, on-the-move multi-gigabit connectivity between trackside and train, which ensures a reliable provision of on-board services. These services include seamless internet access, enhanced entertainment options, and real-time information, creating a superior passenger experience while traveling. Utilizing mmWave technology, LightningBlu is capable of offering carrier-grade performance, supporting Mobility applications with remarkable consistency even at speeds exceeding 300 km/h. Such capabilities promise to revolutionize the connectivity standards within the high-speed rail networks. By integrating this advanced system, railway operators can ensure uninterrupted communication channels, thus optimizing their operations and boosting passenger satisfaction. The solution primarily operates within the mmWave spectrum of 57-71 GHz, making it a future-proof choice that aligns with the expanding global demand for high-quality, high-speed railway communications. With LightningBlu, Blu Wireless is spearheading the movement towards carbon-free, robust connectivity solutions, setting a new standard in the transportation sector.
The CANmodule-III is a sophisticated full CAN controller designed to handle communication on the CAN bus with outstanding efficiency. Built upon Bosch's fundamental CAN architecture, this module is fully CAN 2.0B compliant, facilitating seamless communication transactions across the network. It is optimized for system-on-chip integrations, providing customizable options to cater to specific application requirements. The module stands out with its inherited functions which ensure uninterrupted main core operations, even when additional functionalities are layered around it. Having been deployed in various applications from aerospace to industrial control, the CANmodule-III's proven reliability makes it a preferred choice for developers seeking robust communication solutions in FPGA and ASIC technologies.
The Digital Radio (GDR) from GIRD Systems is an advanced software-defined radio (SDR) platform that offers extensive flexibility and adaptability. It is characterized by its multi-channel capabilities and high-speed signal processing resources, allowing it to meet a diverse range of system requirements. Built on a core single board module, this radio can be configured for both embedded and standalone operations, supporting a wide frequency range. The GDR can operate with either one or two independent transceivers, with options for full or half duplex configurations. It supports single channel setups as well as multiple-input multiple-output (MIMO) configurations, providing significant adaptability in communication scenarios. This flexibility makes it an ideal choice for systems that require rapid reconfiguration or scalability. Known for its robust construction, the GDR is designed to address challenging signal processing needs in congested environments, making it suitable for a variety of applications. Whether used in defense, communications, or electronic warfare, the GDR's ability to seamlessly switch configurations ensures it meets the evolving demands of modern communications technology.
The AST 500 and AST GNSS-RF represent cutting-edge semiconductor solutions in the realm of GNSS technology. These chips are meticulously designed to enhance the performance of Global Navigation Satellite Systems, allowing them to function with heightened accuracy and reliability. With advanced RF front-end technologies, these ICs efficiently handle GNSS signals across multiple satellite systems, ensuring robust connectivity and precise location tracking. Leveraging state-of-the-art process technology, AST 500 and AST GNSS-RF chips are fabricated in leading semiconductor foundries, providing superior signal integrity and low noise performance. These ICs are engineered to perform optimally under various environmental conditions, making them suitable for both commercial and defence applications. Their compatibility with systems such as GPS, GLONASS, and Galileo ensures versatility and global applicability. By integrating these chips, devices can achieve improved positioning accuracy and faster time-to-first-fix, making them an ideal choice for navigation-centric products across multiple industries, including automotive and aerospace.
AccelerComm’s High PHY Accelerators serve as the cornerstone of their full physical layer offerings. These accelerators, available as ASIC and FPGA-ready IP cores, integrate with customer solutions using standard interfaces, bolstered by bit-accurate models for simulation and verification, expediting system-level integration with minimum risk. Incorporating space-hardened platforms from industry leaders, these accelerators leverage patented algorithms to maximize throughput and minimize both power consumption and hardware demands. This ensures they are perfectly suited for deploying in high-performance, space-specific applications where environmental factors impose unique restrictions. Designed to be adaptable across multiple platforms, these accelerators capitalize on years of technological advancement to provide efficient solutions, thereby elevating the capabilities of modern communication systems to meet and exceed the sophisticated demands of the 5G and 6G landscape.
D2D® Technology, developed by ParkerVision, is a revolutionary approach to RF conversion that transforms how wireless communication operates. This technology eliminates traditional intermediary stages, directly converting RF signals to digital data. The result is a more streamlined and efficient communication process that reduces complexity and power consumption. By bypassing conventional analog-to-digital conversion steps, D2D® achieves higher data accuracy and reliability. Its direct conversion approach not only enhances data processing speeds but also minimizes energy usage, making it an ideal solution for modern wireless devices that demand both performance and efficiency. ParkerVision's D2D® technology continues to influence a broad spectrum of wireless applications. From improving the connectivity in smartphones and wearable devices to optimizing signal processing in telecommunication networks, D2D® is a cornerstone of ParkerVision's technological offerings, illustrating their commitment to advancing communication technology through innovative RF solutions.
The Polar ID is an innovative biometric security system that elevates facial recognition technology through its use of sophisticated meta-optics. By capturing and analyzing the unique polarization signature of a face, Polar ID delivers a new standard in security. This system can detect spoofing attempts that incorporate 3D masks or other similar deceptive tactics, ensuring high security through accurate human authentication. Polar ID minimizes the complexity typically associated with face recognition systems by integrating essential optical functions into a single optic. Its compact design results in cost savings and reduces the space required for optical modules in devices like smartphones. Operating in near-infrared light, Polar ID can consistently deliver secure face unlock capabilities even under challenging lighting conditions, dramatically outperforming traditional systems that may fail in bright or dark environments. The platform does not rely on time-of-flight sensors or structured light projectors, which are costly and complex. Instead, Polar ID leverages the simplicity and efficiency of its single-shot identification process to deliver immediate authentication results. This makes it a potent tool for securing mobile transactions and providing safer user experiences in consumer technology.
The RISCV SoC - Quad Core Server Class is engineered for high-performance applications requiring robust processing capabilities. Designed around the RISC-V architecture, this SoC integrates four cores to offer substantial computing power. It's ideal for server-class operations, providing both performance efficiency and scalability. The RISCV architecture allows for open-source compatibility and flexible customization, making it an excellent choice for users who demand both power and adaptability. This SoC is engineered to handle demanding workloads efficiently, making it suitable for various server applications.
The 802.11n/ac/ax LDPC decoder is developed for high throughput WLAN applications. It features layered decoding, soft decision decoding, and is compliant with IEEE 802.11n/ac/ax standards. The decoder supports all LDPC code rates of ½, ⅔, ¾, and ⅚, as well as all LDPC codeword sizes of 648, 1296, and 1944 bits. This IP provides a high throughput design and allows for frame-to-frame on-the-fly configuration, offering configurable LDPC decoding iterations for a trade-off between throughput and error correction performance.
The L5-Direct GNSS Receiver by oneNav is a revolutionary solution built to leverage the advanced capabilities of L5-band satellite signals. Distinguishing itself by operating solely on the L5 frequency, this product delivers exceptional positioning accuracy and resilience, free from the interference commonly associated with legacy L1 signals. This advanced GNSS receiver is engineered to cater to a variety of professional applications that demand robust performance under challenging conditions, such as dense urban areas.\n\nLeveraging oneNav's proprietary Application Specific Array Processor (ASAP), the system provides best-in-class GPS signal acquisition and processing without compromising sensitivity or fix time. The use of an innovative single RF chain allows for optimal antenna placement, reducing the overall form factor and enabling integration into devices that require stringent size and cost constraints. This makes it an ideal choice for wearable and IoT device applications where space and energy consumptions are pivotal considerations.\n\nAdditionally, the L5-Direct GNSS Receiver incorporates machine learning algorithms to effectively mitigate multipath errors, offering unrivaled accuracy by distinguishing direct from reflected signals. The system is specifically designed to be energy efficient, offering extended operational life critical for applications such as smart wearables and asset tracking devices. Its resilience against GPS jamming and interference ensures it remains a reliable choice for mission-critical operations.
The TW330 distortion correction IP is tailored for use in applications requiring dynamic image transformations, such as VR headsets and automotive HUDs. Utilizing GPU-powered technologies, it offers real-time coordinate transformations, distortion corrections, and other modifications up to a resolution of 16K x 16K in both RGB and YUV formats. This IP is crucial for enhancing visual accuracy and display adaptability across varied markets.
ntRSD core implements a time-domain Reed-Solomon decoding algorithm. The core is parameterized in terms of bits per symbol, maximum codeword length and maximum number of parity symbols. It also supports varying on the fly shortened codes. Therefore any desirable code-rate can be easily achieved rendering the decoder ideal for fully adaptive FEC applications. ntRSD core supports erasure decoding thus doubling its error correction capability. The core also supports continuous or burst decoding. The implementation is very low latency, high speed with a simple interface for easy integration in SoC applications.
The ORC3990 is a groundbreaking LEO Satellite Endpoint SoC engineered for use in the Totum DMSS Network, offering exceptional sensor-to-satellite connectivity. This SoC operates within the ISM band and features advanced RF transceiver technology, power amplifiers, ARM CPUs, and embedded memory. It boasts a superior link budget that facilitates indoor signal coverage. Designed with advanced power management capabilities, the ORC3990 supports over a decade of battery life, significantly reducing maintenance requirements. Its industrial temperature range of -40 to +85 degrees Celsius ensures stable performance in various environmental conditions. The compact design of the ORC3990 fits seamlessly into any orientation, further enhancing its ease of use. The SoC's innovative architecture eliminates the need for additional GNSS chips, achieving precise location fixes within 20 meters. This capability, combined with its global LEO satellite coverage, makes the ORC3990 a highly attractive solution for asset tracking and other IoT applications where traditional terrestrial networks fall short.
AccelerComm's LDPC Channel Coding solutions are crafted to meet the exacting requirements of 5G standards, offering unprecedented performance and efficiency. Complete with encoder and decoder capabilities, this solution enhances hardware and power efficiency, meeting all 3GPP specified throughput and error correction targets crucial for the physical layer. Ideal for integration within FPGA or ASIC applications, the IP is engineered to handle typical NTN channel conditions effectively, showcasing a 0.8dB improvement in decoder performance, which notably reduces latency and HARQ retries. This efficiency is achieved through innovative algorithms developed from AccelerComm's research, ensuring minimal error floors. This flexible package underscores the ease of integration, providing adaptable parameters to match diverse application needs, thus offering a practical solution for industries aiming to optimize their 5G infrastructures.
The IP Platform for Low-Power IoT is engineered to accelerate product development with highly integrated, customizable solutions specifically tailored for IoT applications. It consists of pre-validated IP platforms that serve as comprehensive building blocks for IoT devices, featuring ARM and RISC-V processor compatibility. Built for ultra-low power consumption, these platforms support smart and secure application needs, offering a scalable approach for different market requirements. Whether it's for beacons, active RFID, or connected audio devices, these platforms are ideal for various IoT applications demanding rapid development and integration. The solutions provided within this platform are not only power-efficient but also ready for AI implementation, enabling smart, AI-ready IoT systems. With FPGA evaluation mechanisms and comprehensive integration support, the IP Platform for Low-Power IoT ensures a seamless transition from concept to market-ready product.
The 802.11ah HaLow Transceiver by Palma Ceia SemiDesign is crafted to meet the rigorous demands of modern IoT applications, which require efficient power usage and extended connection ranges. Conforming to the Wi-Fi HaLow standard, this transceiver is pivotal for developing low-power, long-range wireless networks. The device is equipped to handle various bandwidths and supports a wide frequency range, ensuring connectivity over great distances without compromising on power efficiency. Integrated features enable low-noise operations and real-time signal processing enhancements, which are crucial for maintaining high-quality links in variable environments. This transceiver is especially suited for battery-operated IoT devices, providing flexibility in design with its interfaces and calibration mechanisms. Its versatile nature makes it an asset for applications such as smart meters, security systems, and other automated infrastructure components, facilitating robust and secure communication across various IoT settings.
The Hyperspectral Imaging System developed by Imec is designed to capture images across numerous wavelengths, enabling detailed analysis of spectral information beyond conventional imaging. This hyperspectral imaging technology is pivotal in extracting valuable insights in fields such as precision agriculture, environmental monitoring, and industrial inspection. With its versatile applications, it offers enhanced capabilities in material identification, chemical analysis, and quality control processes. This system incorporates state-of-the-art sensors that capture data with high spectral and spatial resolution, providing a comprehensive spectral fingerprint of the imaged scene. It excels in distinguishing subtle differences in material properties by analyzing the light reflected from different surfaces across various spectral bands. By using this advanced imaging system, users can perform complex analyses such as vegetation monitoring, pollution detection, and mineral mapping with unprecedented precision. It allows for non-destructive testing, which is crucial for industries like food safety, pharmaceutical production, and environmental science.
This technology represents a significant innovation in the field of wireless energy transfer, allowing for the efficient transmission of power without physical connections or radiation. By leveraging magnetic resonance, this non-radiative energy transfer system can power devices over distances with high efficiency. It's designed to be safe and environmentally friendly, avoiding the pitfalls of electromagnetic radiation while maintaining a high level of power transfer efficiency. The technology finds its applications in various sectors, including consumer electronics, automotive, and industrial applications where it provides a seamless and reliable solution to power transfer needs. The system's capability to transfer power efficiently without contact makes it ideal for scenarios where traditional power connections might be impractical or inconvenient, enabling new levels of convenience and flexibility for users. Designed to integrate smoothly with existing infrastructure, this energy transfer system can significantly reduce reliance on traditional charging methods, paving the way for more innovative and sustainable energy solutions. Furthermore, the system's architecture is geared towards scalability and adaptability, making it suitable for a wide range of devices and use cases.
The RFicient chip is a cutting-edge technology designed to optimize power usage in IoT applications. This ultra-low-power receiver is ideal for environments requiring long-term battery operation, such as remote sensors in industrial IoT setups. With its efficient energy harvesting capabilities, the RFicient chip is pivotal in advancing sustainable technology solutions, reducing power consumption within the Internet of Things (IoT) framework.
The FCM1401 is a highly efficient 14GHz CMOS power amplifier tailored for applications within the Ku-band spectrum, typically ranging from 12.4GHz to 16GHz. It excels in performance by delivering significant RF output power also characterized by a gain of 22dB. This amplifier is engineered with a power added efficiency (PAE) of 47%, making it an optimal choice for long-range communication systems where energy conservation is paramount. Additionally, it operates with a supply voltage of 1.8V, which aligns with its design for lower power consumption. This product is available in a QFN package, providing a compact solution for modern RF system designs.
The Forward Error Correction (FEC) sub-system is one of the essential basing blocks in any communication systems, so a powerful FEC code is needed. The New Radio (NR) FEC for the control channel is designed based on Polar codes, allowing close to the Shannon limit/Capacity operation. It features Polar code successive cancellation decoding, as needed for the 3GPP physical layer standard, with Parity Check bits that simplify the pruning of the search tree. The encoding of the NR Polar code is performed in GF(2), structured using static reliabilities from the ETSI standard. This IP Core supports a maximum code block length of 1024 bits and a minimum of 32 bits. It can be easily integrated with interleavers and Rate matching circuitry to support all rates required by 5G NR. Additional features include successive cancellation decoding with list decoding, soft decision decoding, high peak rates, low latency, and compliance with the 3GPP TS 38.212 V15.1.1 standard. The IP Core is suitable for applications such as 3GPP-LTE Rel. 15 control channels, 5G NR air interfaces, machine-to-machine communication, and high traffic IoT.
LTE Lite is a streamlined PHY solution tailored for user equipment compliant with CAT 0/1 standards. The system offers versatile channel bandwidth selections, accommodating a wide range from 1.4 MHz to 20 MHz. Key functionalities include modulation support up to 64QAM, and time tracking measurement capabilities. The LTE Lite PHY integrates seamlessly with external RF tuners via an analog to digital converter, offering frequency correction for offsets up to 500 KHz and timing corrections for mismatches as large as 50ppm. Documented as Verilog-2001 IP, it enhances adaptability for LTE systems integration.
KPIT Technologies' Digital Connected Solutions are at the cutting edge of automotive digital transformation, playing a crucial role in integrating cloud computing, IoT, and big data analytics with vehicle ecosystems. These solutions enable automakers to optimize vehicle performance, enhance user experience, and improve operational efficiencies through data-driven insights and connectivity. The comprehensive range of services offered under digital connected solutions includes cloud-based data management, real-time analytics, IoT integrations, and digital twin deployments. These technologies are engineered to empower automakers with actionable insights that aid in predictive maintenance, remote diagnostics, and the development of personalized driver experiences. By delivering scalable and secure digital solutions, KPIT supports automakers in crafting innovative strategies for vehicle lifecycle management and customer engagement. The company's robust digital platforms ensure enhanced vehicle connectivity and provide the backbone for future technological advancements in automotive digitization, fostering a new era of smart, efficient vehicles.
The Electric and Conventional Powertrain Solutions offered by KPIT Technologies harness cutting-edge advancements to address the diverse needs of modern automotive power systems. KPIT's powertrain solutions are pivotal for enhancing the efficiency and performance of internal combustion engines as well as electric and hybrid vehicles. Through the integration of advanced control systems, intelligent energy management, and innovative propulsion technologies, KPIT delivers comprehensive solutions that align with global emissions and energy conservation regulations. These powertrain solutions encompass everything from component-level optimizations to full system integration, ensuring that vehicles meet the desired performance metrics while achieving sustainability goals. KPIT employs sophisticated simulation tools and methodologies to fine-tune powertrain architectures, contributing to the development of clean and efficient transportation technologies. KPIT's commitment to innovation in this domain enables automakers to transition smoothly towards more sustainable power options. By offering tailored powertrain solutions, KPIT not only supports existing automotive platforms but also paves the way for future-ready technologies that meet evolving consumer expectations and regulatory requirements.
ArrayNav harnesses adaptive antenna technology to enhance GNSS functionality, optimizing performance in environments with complex multichannel challenges. By leveraging various antennas, ArrayNav achieves enhanced sensitivity and coverage, significantly mitigating issues such as multipath fading. This results in greater positional accuracy even in dense urban environments known for signal interference. This adaptive approach presents an invaluable asset for automotive Advanced Driver Assistance Systems (ADAS), where high precision and rapid response times are critical. The improved antenna diversity offered by ArrayNav not only augments signal strength but also robustly rejects interference and jamming attempts, assuring consistent operation and accuracy. In terms of power efficiency, ArrayNav stands out by combining exceptional accuracy with reduced power needs, offering a flexible solution adaptable for both standalone and cloud-computing modes. This dual capability ensures that system designers have the optimal framework for developing customized solutions catering to specific application requirements. Overall, ArrayNav’s cutting-edge technology fosters improved GNSS operations by delivering enhanced sensitivity and accuracy, thereby meeting the stringent demands of modern automotive and navigation systems.
The NaviSoC is an advanced GNSS receiver integrated with an application processor on a single silicon die. It offers robust solutions with exceptional jamming and spoofing resistance, crafted for the mass market. This system-on-chip is known for its high levels of precision, security, and low power usage while maintaining a compact form factor. The NaviSoC system is designed to be highly flexible, allowing for extensive customization to meet diverse user needs. Its diverse application spectrum makes the NaviSoC suitable for location-based services (LBS), Internet of Things (IoT) applications, and detailed lane-level navigation systems. It is equally efficient in handling asset tracking operations and is instrumental in time synchronization tasks. Moreover, the NaviSoC finds significant utility in emerging sectors like UAV and autonomous drones, providing smart platforms for agriculture and comprehensive surveying and mapping activities. What sets the NaviSoC apart is its ability to deliver high reliability and security in demanding environments, ensuring optimal performance regardless of application. Its small size paired with low power requirements makes it an ideal choice for portable and mobile devices, providing a robust platform for developers seeking versatile and powerful GNSS functionalities.
ntRSE core implements the Reed Solomon encoding algorithm and is parameterized in terms of bits per symbol, maximum codeword length and maximum number of parity symbols. It also supports varying on the fly shortened codes. Therefore any desirable code-rate can be easily achieved rendering the decoder ideal for fully adaptive FEC applications. ntRSE core supports continuous or burst decoding. The implementation is very low latency, high speed with a simple interface for easy integration in SoC applications.
AES, or Advanced Encryption Standard, is a cryptographic algorithm that stands as a cornerstone in secure data encryption. Helion's AES standard modes provide a range of configurations tailored to ensure data integrity and confidentiality across various applications. These modes are optimally designed for ASICs and FPGAs, promising high performance with low power consumption. The implementation of AES by Helion is distinguished by its flexibility and security, catering to industries that require stringent data protection. The IP core supports multiple AES modes, including ECB, CBC, CFB, OFB, and CTR, each with specific operational characteristics that address different security needs. The efficient design ensures reduced resource usage, which is particularly beneficial for cost-sensitive and resource-constrained environments. Helion's AES cores are compatible with global encryption standards and can be integrated seamlessly into existing frameworks. This adaptability makes them an ideal choice for applications such as secure communications, data storage encryption, and internet security protocols.
ShortLink offers a powerful and comprehensive RF Transceiver IP for 433, 868, and 915 MHz frequency bands, which is compliant with the IEEE 802.15.4-2015 standard. With features like data rates ranging from 1.2 k to 500 kbps, it provides a robust solution for diverse low-power wireless network applications. The transceiver handles both transmission and reception at various bands, making it suitable for worldwide deployment. The integration is simplified with built-in voltage regulators, bandgap references, and bias generation. The flexible design of this RF transceiver supports different modulation techniques, including GFSK, BPSK, and O-QPSK, catering to a wide range of communication needs. The configurable architecture ensures compatibility with custom protocols beyond standard applications, providing adaptability for unique project requirements. Built for reliability, the IP showcases RX sensitivity down to -106 dBm and TX power ranging from -20 to +8 dBm, ensuring long-distance communication capabilities and excellent power efficiency. The inherent compliance with standard wireless communication protocols eliminates the need for external radio chips, streamlining the integration process into various SoC designs.
The WiMAX Software Stack by Lekha Wireless serves as a cornerstone for delivering Broadband Wireless Access (BWA) solutions, characterized by high data throughput and long-range coverage. This stack is instrumental for operators aiming to enhance broadband services in both urban and rural settings, offering an effective alternative to traditional wired networks with its robust wireless capabilities. Optimized for scalability, the WiMAX Stack addresses the broad spectrum of broadband needs, ranging from fixed deployments to mobile applications, and supports seamless integration into existing network ecosystems. Its comprehensive feature set ensures operators can deliver consistent high-speed internet access while maintaining service quality and reliability. By facilitating cost-effective deployments, the stack empowers service providers to expand their market reach and enhance their service portfolio without extensive infrastructure investments.
In smartphone applications, ActLight’s Dynamic PhotoDetector (DPD) offers a step-change in photodetection technology, enhancing features such as proximity sensing and ambient light detection. This high sensitivity sensor, with its ability to detect subtle changes in light, supports functions like automatic screen brightness adjustments and energy-efficient proximity sensing. Designed for low voltage operation, the DPD effectively reduces power consumption, making it suitable for high-performance phones without increasing thermal load. The technology also facilitates innovative applications like 3D imaging and eye-tracking, adding richness to user experiences in gaming and augmented reality.
The transceiver is designed to be used together with an RF tuner, and ADC/DAC converters. The system has internal state machine to control the operation, and can be externally configured via the SPI interface. This design is a Mobile WiMAX baseband transceiver core for both Base station and Mobile station, supplied as a portable and synthesizable Verilog-2001 IP. The system was designed to be used in conjunction with a standard RF tuner. The operation of the transceiver is automated by a master finite state machine.
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