All IPs > Wireless Communication
The Wireless Communication category at Silicon Hub encompasses a diverse array of semiconductor IPs designed to facilitate seamless wireless connectivity in today's rapidly evolving technological landscape. As the demand for higher data rates and uninterrupted connectivity grows, these IPs play a vital role in enabling devices to communicate efficiently across various protocols and standards. This category includes highly specialized IPs that support the implementation and enhancement of wireless communication technologies in a variety of applications ranging from consumer electronics to industrial systems.
Within this category, semiconductor IPs cover a wide spectrum of wireless standards and protocols. This includes evolving mobile communication standards like 3GPP-5G and LTE, which are essential for cellular networks' operation and are pivotal in the deployment of the latest 5G networks. For localized wireless communication, standards such as 802.11 (commonly referred to as Wi-Fi), Bluetooth, NFC, and Wireless USB are covered, facilitating device interconnectivity and data exchange in numerous consumer electronics, IoT devices, and more. Industrial and professional applications may utilize IPs related to standards like WiMAX (802.16), CPRI, OBSAI, which are crucial for network infrastructure and robust communication systems.
In addition to these, the Wireless Communication category includes IPs for satellite navigation systems like GPS, ensuring accurate geolocation services essential for navigation devices in both personal and commercial use. Standards like UWB (Ultra-Wideband) offer high-speed data transmission over short ranges, beneficial for applications demanding rapid short-range communication. Furthermore, for high-definition broadcasting, IPs supporting Digital Video Broadcast standards offer necessary capabilities to meet market demands for clear and reliable video content transmission.
This extensive category of semiconductor IPs under Wireless Communication not only provides the architectural needs for state-of-the-art communication devices but also accommodates future technological advancements. By integrating these IPs, semiconductor product designers and engineers can efficiently develop solutions tailored for enhanced connectivity, ensuring their products remain at the forefront of technological innovation and meet the ever-growing expectations of modern consumers for instant and reliable wireless communication. Whether you are developing next-gen smartphones, IoT solutions, or advanced networking systems, these IPs are critical components in achieving superior performance and connectivity.
Akida Neural Processor IP is a groundbreaking component offering a self-contained AI processing solution capable of locally executing AI/ML workloads without reliance on external systems. This IP's configurability allows it to be tailored to various applications, emphasizing space-efficient and power-conscious designs. Supporting both convolutional and fully-connected layers, along with multiple quantization formats, it addresses the data movement challenge inherent in AI, significantly curtailing power usage while maintaining high throughput rates. Akida is designed for deployment scalability, supporting as little as two nodes up to extensive networks where complex models can thrive.
The second generation of BrainChip's Akida platform expands upon its predecessor with enhanced features for even greater performance, efficiency, and accuracy in AI applications. This platform leverages advanced 8-bit quantization and advanced neural network support, including temporal event-based neural nets and vision transformers. These advancements allow for significant reductions in model size and computational requirements, making the Akida 2nd Generation a formidable component for edge AI solutions. The platform effectively supports complex neural models necessary for a wide range of applications, from advanced vision tasks to real-time data processing, all while minimizing cloud interaction to protect data privacy.
The Low Density Parity Check (LDPC) codes are powerful, capacity approaching channel codes and have exceptional error correction capabilities. The high degree of parallelism that they offer enables efficient, high throughput hardware architectures. The ntLDPC_WiFi6 IP Core is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes and is fully compliant with IEEE 802.11 n/ac/ax standard. The Quasi-Cyclic LDPC codes are based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that they offer high throughput at low implementation complexity. The ntLDPC_WiFi6 decoder IP Core may optionally implement one of two approximations of the log-domain LDPC iterative decoding algorithm (Belief propagation) known as either Layered Normalized Offset Min-Sum Algorithm or Layered Lambda-min Algorithm. Selecting between the two algorithms presents a decoding performance .vs. system resources utilization trade-off. The core is highly reconfigurable and fully compliant to the IEEE 802.11 n/ac/ax Wi-Fi4, Wi-Fi5 and Wi-Fi 6 standards. The ntLDPC_WiFi6 encoder IP implements a 81-bit parallel systematic LDPC encoder. An off-line profiling Matlab script processes the original matrices and produces a set of constants that are associated with the matrix and hardcoded in the RTL encoder.
The ADQ35 digitizer is designed for high-throughput applications, featuring a dual-channel configuration capable of achieving a sampling rate up to 10 GSPS. This 12-bit digitizer is tailored for applications that require simultaneous data streams and efficient high-speed data transfer, making it ideal for use in advanced signal analysis.
Focused on the advancement of autonomous mobility, KPIT's ADAS and Autonomous Driving solutions aim to address the multifaceted challenges that come with higher levels of vehicle autonomy. Safety remains the top priority, necessitating comprehensive testing and robust security protocols to ensure consumer trust. Current development practices often miss crucial corner cases by concentrating largely on standard conditions. KPIT tackles these issues through a holistic, multi-layered approach. Their solutions integrate state-of-the-art AI-driven decision-making systems that extend beyond basic perception, enhancing system reliability and intelligence. They've established robust simulation environments to ensure feature development covers all conceivable driving scenarios, contributing to the broader adoption of Level 3 and up autonomous systems. The company also offers extensive validation frameworks combining various testing methodologies to continually refine and prove their systems. This ensures each autonomous feature is thoroughly vetted before deployment, firmly positioning KPIT as a trusted partner for automakers aiming to bring safe, reliable, and highly autonomous vehicles to market.
The ORC3990 SoC is a state-of-the-art solution designed for satellite IoT applications within Totum's DMSS™ network. This low-power sensor-to-satellite system integrates an RF transceiver, ARM CPUs, memories, and PA to offer seamless IoT connectivity via LEO satellite networks. It boasts an optimized link budget for effective indoor signal coverage, eliminating the need for additional GNSS components. This compact SoC supports industrial temperature ranges and is engineered for a 10+ year battery life using advanced power management.
The HOTLink II Product Suite is another remarkable offering from Great River Technology. Built to complement their ARINC 818 suite, HOTLink II provides an integrated framework for crafting high-performance digital data links. This suite ensures seamless, secure, and reliable data transmission over fiber or copper cables across various platforms. Developed with a focus on flexibility and functionality, the HOTLink II capabilities enhance system integrators' ability to deploy effective communication solutions within aircraft and other demanding environments. The emphasis on robust, low-latency data transfer makes it an ideal choice for real-time applications where precision and reliability are paramount. Broad compatibility is a hallmark of HOTLink II, facilitating integration into diverse infrastructures. Backed by Great River Technology's expertise and support, customers are empowered to advance their system communication capabilities efficiently and cost-effectively.
Polar ID offers an advanced solution for secure facial recognition in smartphones. This system harnesses the revolutionary capabilities of meta-optics to capture a unique polarization signature from human faces, adding a distinct layer of security against sophisticated spoofing methods like 3D masks. With its compact design, Polar ID replaces the need for bulky optical modules and costly time-of-flight sensors, making it a cost-effective alternative for facial authentication. The Polar ID system operates efficiently under diverse lighting conditions, ensuring reliable performance both in bright sunlight and in total darkness. This adaptability is complemented by the system’s high-resolution capability, surpassing that of traditional facial recognition technologies, allowing it to function seamlessly even when users are wearing face coverings, such as glasses or masks. By incorporating this high level of precision and security, Polar ID provides an unprecedented user experience in biometric solutions. As an integrated solution, Polar ID leverages state-of-the-art polarization imaging, combined with near-infrared technology operating at 940nm, which provides robust and secure face unlock functionality for an increasing range of mobile devices. This innovation delivers enhanced digital security and convenience, significantly reducing complexity and integration costs for manufacturers, while setting a new standard for biometric authentication in smartphones and beyond.
The EW6181 is a cutting-edge multi-GNSS silicon solution offering the lowest power consumption and high sensitivity for exemplary accuracy across a myriad of navigation applications. This GNSS chip is adept at processing signals from numerous satellite systems including GPS L1, Glonass, BeiDou, Galileo, and several augmentation systems like SBAS. The integrated chip comprises an RF frontend, a digital baseband processor, and an ARM microcontroller dedicated to operating the firmware, allowing for flexible integration across devices needing efficient power usage. Designed with a built-in DC-DC converter and LDOs, the EW6181 silicon streamlines its bill of materials, making it perfect for battery-powered devices, providing extended operational life without compromising on performance. By incorporating patent-protected algorithms, the EW6181 achieves a remarkably compact footprint while delivering superior performance characteristics. Especially suited for dynamic applications such as action cameras and wearables, its antenna diversity capabilities ensure exceptional connectivity and positioning fidelity. Moreover, by enabling cloud functionality, the EW6181 pushes boundaries in power efficiency and accuracy, catering to connected environments where greater precision is paramount.
The NaviSoC by ChipCraft is a highly integrated GNSS system-on-chip (SoC) designed to bring navigation technologies to a single die. Combining a GNSS receiver with an application processor, the NaviSoC delivers unmatched precision in a dependable, scalable, and cost-effective package. Designed for minimal energy consumption, it caters to cutting-edge applications in location-based services (LBS), the Internet of Things (IoT), and autonomous systems like UAVs and drones. This innovative product facilitates a wide range of customizations, adaptable to varied market needs. Whether the application involves precise lane-level navigation or asset tracking and management, the NaviSoC meets and exceeds market expectations by offering enhanced security and reliability, essential for synchronization and smart agricultural processes. Its compact design, which maintains high efficiency and flexibility, ensures that clients can tailor their systems to exact specifications without compromise. NaviSoC stands as a testament to ChipCraft's pioneering approach to GNSS technologies.
AccelerComm presents the Polar encoding and decoding suite for the 3GPP NR, featuring a comprehensive chain that enables quick integration and minimizes additional developmental efforts. This advanced IP utilizes PC and CRC-aided SCL decoding methods to deliver uncompromising error correction performance, adeptly handling the intricacies of 5G applications.\n\nThe Polar IP supports an extensive range of block sizes, tightly integrating each component to optimize performance while reducing latency and resource use. Its flexibility is further highlighted by its highly configurable parameters, which allow users to tailor its implementation to specific performance demands and power efficiency expectations.\n\nBy offering support for prevalent FPGA platforms like AMD and Intel, alongside ASIC optimizations, this Polar solution is a versatile option for developers seeking robust and integral solutions for burgeoning 5G networks. With ease of integration and superior performance metrics, it remains a leading solution in comprehensive 5G data processing.
The TW330 Image Warping IP utilizes advanced GPU processing technology to offer high-performance image distortion correction. It features extensive capabilities including coordinate transformation, any-shape image transformations, and supports resolutions up to 16K x 16K for both RGB and YUV formats. Ideal for digitally correcting images distorted by wide-angle or fish-eye lenses on various devices, this technology is key in fields such as automotive display systems, VR/AR devices, and high-definition projectors. It makes real-time, on-the-fly image correction feasible, elevating the quality of visual outputs for demanding applications. Through its flexible and efficient design, TW330 enables seamless integration into systems requiring dynamic and precise image modification capabilities, paving the way for developing more interactive and immersive visual experiences.
The CANmodule-IIIx by Inicore is an enhanced CAN controller with a design that caters to sophisticated system-on-chip requirements. It features 32 receive and 32 transmit mailboxes, offering substantial flexibility and control over CAN network traffic. This module is ideal for applications necessitating high throughput and advanced message handling. Its compliance with full CAN2.0B standards ensures wide applicability across various sectors, making it an integral part of communication systems in automotive and industrial fields. The CANmodule-IIIx delivers an excellent balance of performance and functionality.
The eSi-Comms IP suite provides a highly adaptable OFDM-based MODEM and DFE portfolio, crucial for facilitating communications-oriented ASIC designs. This IP offers adept handling of many air interface standards in use today, making it ideal for 4G, 5G, Wi-Fi, and other wireless applications. The suite includes advanced DSP algorithms for ensuring robust links under various conditions, using a core design that is highly configurable to the specific needs of high-performance communication systems. Notably, it supports synchronization, equalization, and channel decoding, boasting features like BPSK to 1024-QAM demodulation and multi-antenna processing.
Convolutional FEC codes are very popular because of their powerful error correction capability and are especially suited for correcting random errors. The most effective decoding method for these codes is the soft decision Viterbi algorithm. ntVIT core is a high performance, fully configurable convolutional FEC core, comprised of a 1/N convolutional encoder, a variable code rate puncturer/depuncturer and a soft input Viterbi decoder. Depending on the application, the core can be configured for specific code parameters requirements. The highly configurable architecture makes it ideal for a wide range of applications. The convolutional encoder maps 1 input bit to N encoded bits, to generate a rate 1/N encoded bitstream. A puncturer can be optionally used to derive higher code rates from the 1/N mother code rate. On the encoder side, the puncturer deletes certain number of bits in the encoded data stream according to a user defined puncturing pattern which indicates the deleting bit positions. On the decoder side, the depuncturer inserts a-priori-known data at the positions and flags to the Viterbi decoder these bits positions as erasures. The Viterbi decoder uses a maximum-likelihood detection recursive process to cor-rect errors in the data stream. The Viterbi input data stream can be composed of hard or soft bits. Soft decision achieves a 2 to 3dB in-crease in coding gain over hard-decision decoding. Data can be received continuously or with gaps.
ASPER is an advanced 79 GHz mmWave radar offering expansive 180-degree field coverage, designed to excel in park assist solutions. This radar module replaces traditional ultrasonic systems with improved accuracy, capable of extended detection ranges from 5 cm to 100 meters. Its adaptability across various vehicle classes makes it ideal for applications in automotive, transportation, and industrial environments, delivering unparalleled performance even in adverse conditions.
The GNSS VHDL Library by GNSS Sensor Ltd is an advanced collection of VHDL modules crafted for GNSS integration. This library offers a customizable GNSS engine along with Fast Search Engine capabilities for systems like GPS, Glonass, and Galileo. The utility of these modules extends to supporting independent RF channels and includes features like Viterbi decoders and self-test modules, thereby ensuring comprehensive functionality. The library is architected to provide high flexibility and independence from specific CPU platforms, driven by a single configuration file that allows for seamless adaptation across different environments. It supports integration with various external bus interfaces through its innovative bridge modules, ensuring streamlined operations and interactions with other system components. With its extensive configurability, the library can accommodate a wide range of configurations, including the number of supported systems, channels, and frequency bands. This allows developers to adapt the architecture to specific project needs efficiently. Additionally, the library's RF front-end capabilities significantly reduce system development costs and complexities by offering a ready-to-use navigation solution suitable for FPGA development boards and beyond.
Inicore’s CANmodule-III is a mailbox-based CAN controller offering robust performance for system-on-chip solutions. Designed with advanced features to manage communication effectively, this controller supports a comprehensive range of CAN applications. With its scalability and ease of integration, it remains a preferred choice for industries requiring reliable CAN solutions. The CANmodule-III’s design simplicity ensures that it is a dependable component in complex electronic systems, meeting various compliance standards and providing an exceptional communication protocol foundation.
The ARINC 818 Direct Memory Access (DMA) IP Core is specifically designed to optimize data transaction processes within ARINC 818 protocols, particularly emphasizing receipt and transmission efficiency. This core is an essential component for embedded applications where offloading of formatting, timing, and buffer management is crucial for operational success. Ideal for avionics applications, the core simplifies integration by efficiently managing data transfer operations between system nodes through coordinated DMA mechanisms. It provides a streamlined hardware solution, reducing the overhead typically associated with direct memory operations and improving the overall system performance. Built with scalability in mind, the ARINC 818 DMA IP Core supports various data rates and configurations, enhancing its adaptability to different system architectures. By minimizing CPU intervention in data handling, it increases processing efficiency, further ensuring high-speed data handling with minimal delay or disruption.
Palma Ceia's 802.11ah HaLow Transceiver meets the industry's demands for efficient, long-range connectivity tailored for IoT applications. Compliant with the IEEE 802.11ah standard, commonly recognized as Wi-Fi HaLow, it ensures robust communication over expansive areas ideal for modern IoT installations. Designed to support low-power operations and extended battery life, this transceiver is optimal for devices where prolonged autonomy is crucial. It operates efficiently across 1 MHz to 4 MHz channels, providing broad spectral coverage and guarantees superior receiver sensitivity and low noise, augmented by direct conversion technology. The HaLow Transceiver integrates advanced RF design techniques, featuring a highly linear Rx path, low latency, and scalability which eases integration with SoCs or standalone implementations. Supporting various interfaces and equipped with a battery monitor and onboard temperature sensor, it envisions diverse applications, from asset tracking to smart factories.
The Hyperspectral Imaging System is designed to provide comprehensive imaging capabilities that capture data across a wide spectrum of wavelengths. This system goes beyond traditional imaging techniques by combining multiple spectral images, each representing a different wavelength range. By doing this, it enables the identification and analysis of various materials and substances based on their spectral signatures. Ideal for applications in agriculture, healthcare, and industry, it allows for the precise characterisation of elements and compounds, contributing to advancements in fields such as remote sensing and environmental monitoring.
Functioning as a comprehensive cross-correlator, the XCM_64X64 facilitates efficient and precise signal processing required in synthetic radar receivers and advanced spectrometers. Designed on IBM's 45nm SOI CMOS technology, it supports ultra-low power operation at about 1.5W for the entire array, with a sampling performance of 1GSps across a bandwidth of 10MHz to 500MHz. The ASIC is engineered to manage high-throughput data channels, a vital component for high-energy physics and space observation instruments.
802.11 LDPC from Wasiela represents a significant advancement in error correction technologies for wireless communication. Engineered to support high-throughput connections, this module allows dynamic adjustment with on-the-fly configuration between frames. The design achieves a well-balanced performance by fine-tuning the number of LDPC decoding iterations, offering a scalable trade-off between throughput and error correction strength. This module is tailored to meet the stringent specifications necessary for high performance in modern wireless networks. It excels at delivering reliable bit-error-rate and packet-error-rate metrics that align with current industry benchmarks. Wasiela’s 802.11 LDPC product underlines their innovation in pushing the boundaries of what forward error correction technologies can achieve, ensuring communications are both robust and efficient.
The LDPC solution by AccelerComm is meticulously optimized for the 5G NR standard, ensuring superior efficiency and performance. This encoder and decoder IP triumphantly addresses the pivotal needs of the 5G network by combining maximal hardware efficiency with enhanced power efficiency. It is adeptly designed to fulfill the rigorous throughput and error correction targets outlined by 3GPP standards.\n\nIntended for integration into both FPGA and ASIC environments, the LDPC IP is highly configurable, providing numerous settings to cater to a broad array of applications. Its capability to support maximum data rates while minimizing latency makes it an indispensable element in advanced communication infrastructures.\n\nWith enhanced BLER performance and an innovative design that outstrips generic LDPC solutions, this implementation significantly reduces latency and resource utilization. Offering low power consumption and half the energy per bit compared to competitors, it provides a balanced approach to meeting both diverse operational demands and stringent power budgets.
The ADQ35-WB RF digitizer is crafted for high-performance data acquisition with versatility at its core. It offers users a dual-channel capability with an impressive sample rate of up to 10 GSPS, and it extends its performance with a usable analog bandwidth reaching 9 GHz. This makes it a formidable option for professionals demanding precision and accuracy in RF signal digitization.
CoreVCO is a versatile Voltage-Controlled Oscillator designed for precision in frequency modulation. Its capability to produce a wide range of frequencies with excellent phase noise characteristics makes it a preferred choice for high-frequency telecommunications and broadcast applications. The design of CoreVCO emphasizes stability and responsiveness, ensuring rapid adaptation to changes in control voltage. This attribute is crucial for maintaining signal integrity across varying operational conditions, making CoreVCO reliable in both laboratory and field environments. With what CoreVCO offers, electronic systems achieve high efficiency and adaptability, aligning with modern digital communication standards. The oscillator is architected to seamlessly integrate into existing systems, providing scalable solutions for developers seeking robust frequency control modules.
The FCM1401 is part of Falcomm's line of advanced Dual-Drive™ power amplifiers designed to enhance efficiency in wireless applications. Engineered for operation at a center frequency of 14 GHz, this two-stage power amplifier maximizes energy use while maintaining exceptional performance standards. Its innovative design includes CMOS SOI platform integration, boasting world-class efficiencies unmatched by conventional solutions in the market. The technology also comes with alternative options across other silicon platforms like GaAs, GaN, and SiGe, providing versatile application potential. This power amplifier achieves remarkable efficiency levels; a two-stage power-added efficiency (PAE) of 56% and a drain efficiency nearing 70%. The design also incorporates a 0.5x reduction in silicon area without degrading overall capabilities. The FCM1401 supports a broad range of applications from telecommunications to space communications, helping to lower operational costs while enhancing signal strength. Moreover, the amplifier’s robust design allows it to operate across a supply voltage between 1.6V to 2.0V without any loss in efficiency, ensuring stable performance under diverse conditions. With such specifications, the FCM1401 proves an ideal candidate for integrative use in advanced wireless communication infrastructures, offering substantial battery life improvements and energy savings to connected devices.
AccelerComm's High PHY Accelerators offer an impressive portfolio of IP accelerators tailored for 5G NR, enhancing O-RAN deployments with advanced signal processing capabilities. These accelerators emphasize maximum throughput and minimal power and latency, leveraging scalable technology for ASIC, FPGA, and SoC applications.\n\nCentral to these accelerators are patented high-performance signal processing algorithms, which enhance throughput significantly, making them crucial in scenarios demanding rapid data processing and low latency. The offering is ideal for improving the speed and efficiency of high-demand networks, reinforced by extensive research led by industry experts from Southampton University.\n\nMoreover, the accelerators encompass a wide variety of signal processing techniques such as LDPC and advanced equalization, to optimize the entire data transmission process. The result is a remarkable boost in spectral efficiency and overall network performance, making these accelerators indispensable for cutting-edge wireless technologies and their future-forward deployments.
The ntLDPC_5GNR Base Graph Encoder IP Core is defined in 3GPP TS 38.212 standard document and it is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes. The specification defines two sets of LDPC Base Graphs and their respective derived Parity Check Matrices. Each Base Graph can be combined with 8 sets of lifting sizes (Zc) in a total of 51 different lifting sizes. This way by using the 2 Base Graphs, the 5G NR specification defines up to 102 possible distinct LDPC modes of operation to select from, for optimum decoding performance, depending on target application code block size and code rate (using the additional rate matching module features). For Base Graph 1 we have LDPC(N=66xZc,K=22xZc) sized code blocks, while for Base Graph 2 we have LDPC(N=50xZc,K=[6,8,9,10]xZc) sized code blocks. The ntLDPCE_5GNR Encoder IP implements a multi-parallel systematic LDPC encoder. Parallelism depends on the selected lifting sizes subsets chosen for implementation. Shortened blocks are supported with granularity at lifting size Zc-bit boundaries. Customizable modes generation is also supported beyond the scope of the 5G-NR specification with features such as: “flat parity bits puncturing instead of Rate Matching Bit Selection”, “maintaining the first 2xZc payload bits instead of eliminating it before transmission”, etc. The ntLDPCD_5GNR decoder IP implements a maximum lifting size of Zc_MAX-bit parallel systematic LDPC layered decoder. Each layer corresponds to Zc_MAX expanded rows of the original LDPC matrix. Each layer element corresponds to the active ZcxZc shifted identity sub-matrices within the layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit, in order to update the layers LLR estimates and extrinsic information iteratively until the required number of decoding iterations has been run. The decoder IP also features a powerful optional early termination (ET) criterion, to maintain practically equivalent error correction performance, while significantly increasing its throughput rate and/or reducing hardware cost. Additionally it reports how many decoding iterations have been performed when ET is activated, for system performance observation and calibration purposes. Finally a simple, yet robust, flow control handshaking mechanism is included in both IPs, which is used to communicate the IPs availability to adjacent system components. This logic is easily portable into any communication protocol, like AXI4 stream IF.
ActLight has tailored its Dynamic PhotoDetector (DPD) technology for smartphone applications to meet the growing demand for high-performance sensors. This sensor promises to elevate the smartphone experience with cutting-edge proximity and ambient light sensing capabilities. Utilizing a 3D Time-of-Flight (ToF) approach, it enables precise detection and response to varying lighting conditions, significantly enhancing the functionality of smart devices. The DPD technology operates on a low-voltage platform, which reduces both power consumption and thermal output, making it an ideal solution for managing battery-intensive tasks. Its ability to detect even the smallest light changes allows for finely tuned screen adaptations, improving the user interface and device efficiency. By providing advanced light sensitivity and low-energy operation, ActLight's DPD enhances mobile devices' overall utility and performance. This allows for sharper imaging, more immersive applications, and more precise environmental sensing, crafting a superior and user-friendly smartphone experience. Its integration into smartphones paves the way for more efficient and innovative mobile technologies.
The mmWave PLL is crafted for high-frequency applications, delivering superior phase lock across a range of millimeter-wave frequencies. It is tailored to meet the stringent demands of modern communication systems, enabling enhanced data transmission speeds and connectivity. Combining advanced signal stability with low phase noise, the mmWave PLL offers precise frequency management, crucial for next-generation wireless networks. It leverages cutting-edge technology to minimize power consumption, while maintaining high performance, a balancing act essential for today's technology. This PLL supports a broad spectrum of frequencies, making it versatile for varied applications in telecommunications and radar systems. Its design ensures that it remains robust under high-frequency operations, offering reliable performance for critical infrastructure and technology deployments.
NeuroVoice is a powerful ultra-low-power neuromorphic front-end chip engineered for voice processing in environments plagued by irregular noises and privacy concerns. This chip, built on the NASP framework, improves real-time voice recognition, reducing reliance on cloud processing and providing heightened privacy. It is ideal for applications in hearables, smart home devices, and other AI-driven voice control systems, capable of efficiently processing human voice amidst noise. The NeuroVoice chip addresses key challenges faced by existing digital solutions, such as excessive power consumption and low latency in real-time scenarios. Its brain-inspired architecture processes voice commands independently of the cloud, which minimizes Internet dependency and enhances privacy. Furthermore, the chip's ability to manage voice detection and extraction makes it suitable for diverse environments ranging from urban noise to quiet domestic settings. Advanced features of the NeuroVoice chip include its ultra-fast inference capability, processing all data locally and ensuring user privacy without compromising performance. By supporting applications like smart earbuds and IoT devices, NeuroVoice optimizes energy efficiency while maintaining superior voice processing quality. This innovative technology not only empowers users with clearer communication abilities but also encourages adoption across multiple consumer electronics.
PCS2100 is a modem chip specifically crafted for Wi-Fi HaLow IoT applications, part of Palma Ceia's lineup designed according to IEEE 802.11ah standard. This chip empowers IoT devices by ensuring effective long-range communication over low power networks, essential for smart networks scaling up extensive regions. It functions over sub-gigahertz bands, distinguishing itself by enabling communication extending up to 1 kilometer. This expansive reach, combined with the high-density network support, makes the PCS2100 exceptionally suitable for smart city infrastructures and industrial IoT networks. The chip's architecture allows it to operate over 755 to 928 MHz bands with great efficiency, abiding to different regional regulations. Enhanced by protocols that minimize power use, such as Target Wake Time, this chip ensures long battery life in IoT deployments, pivotal for resource-heavy setups like smart manufacturing. The PCS2100 includes robust security protocols, supporting WPA3 Personal and others, to ensure secure data transmission across device connections.
The XCM_64X64_A is a powerful array designed for cross-correlation operations, integrating 128 ADCs each capable of 1GSps. Targeted at high-precision synthetic radar and radiometer systems, this ASIC delivers ultra-low power consumption around 0.5W, ensuring efficient performance over a wide bandwidth range from 10MHz to 500MHz. Built on IBM's 45nm SOI CMOS technology, it forms a critical component in systems requiring rapid data sampling and intricate signal processing, all executed with high accuracy, making it ideal for airborne and space-based applications.
The ADQ7DC stands out with its high-resolution 14-bit digitization capability, providing users with a single or dual-channel configuration for enhanced flexibility. Its formidable 10 GSPS sampling speed offers compelling performance for applications requiring high fidelity data conversion, allowing for intricate RF signal capture and analysis.
The PCD03D Turbo Decoder is adept at handling multiple state decoding for standards such as DVB-RCS and IEEE 802.16 WiMAX. Its core design features an 8-state duobinary decoding structure, facilitating precise and quick signal deconstruction. Additionally, the optional inclusion of a 64-state Viterbi decoder enhances versatility and performance in various environments. This decoder is tailored for applications where agility and high data throughput are critical, making it an invaluable asset in wireless communication infrastructures. The decoder’s architecture supports expansive VHDL core integration, providing durable solutions across FPGA platforms.
ArrayNav represents a significant leap forward in navigation technology through the implementation of multiple antennas which greatly enhances GNSS performance. With its capability to recognize and eliminate multipath signals or those intended for jamming or spoofing, ArrayNav ensures a high degree of accuracy and reliability in diverse environments. Utilizing four antennas along with specialized firmware, ArrayNav can place null signals in the direction of unwanted interference, thus preserving the integrity of GNSS operations. This setup not only delivers a commendable 6-18dB gain in sensitivity but also ensures sub-meter accuracy and faster acquisition times when acquiring satellite data. ArrayNav is ideal for urban canyons and complex terrains where signal integrity is often compromised by reflections and multipath. As a patented solution from EtherWhere, it efficiently remedies poor GNSS performance issues associated with interference, making it an invaluable asset in high-reliability navigation systems. Moreover, the system provides substantial improvements in sensitivity, allowing for robust navigation not just in clear open skies but also in challenging urban landscapes. Through this additive capability, ArrayNav promotes enhanced vehicular ADAS applications, boosting overall system performance and achieving higher safety standards.
The ntLDPC_DVBS2X IP Core is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes. These LDPC codes are based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that they offer high throughput at low implementation complexity. The ntLDPC_DVBS2X decoder IP Core may optionally implement one of two approximations of the log-domain LDPC iterative decoding algorithm (Belief propagation) known as either Layered Offset Min-Sum Algorithm or Layered Lambda-min Algorithm. Selecting between the two algorithms presents a decoding performance .vs. system resources utilization trade-off. The core is highly reconfigurable and fully compliant to the DVB-S2 and DVB-S2X standards. Two highly complex off-line preprocessing series of procedures are performed to optimize the DVB LDPC parity check matrices to enable efficient RTL implementation. The ntLDPC_DVBS2X encoder IP implements a 360-bit parallel systematic LDPC IRA encoder. An off-line profiling Matlab script processes the original IRA matrices and produces a set of constants that are associated with the matrix and hardcoded in the RTL encoder. Actual encoding is performed as a three part recursive computation process, where row sums, checksums of all produced rows column-wise and finally transposed parity bit sums are calculated. The ntLDPC_DVBS2X decoder IP implements a 360-bit parallel systematic LDPC layered decoder. Two separate off-line profiling Matlab series of scripts are used to (a) process the original IRA matrices and produce the layered matrices equivalents (b) resolve any possible conflicts produced by the layered transformation. The decoder IP permutes each block’s parity LLRs to become compatible with the layered decoding scheme and stores channel LLRs to processes them in layered format. Each layer corresponds to 360 expanded rows of the original LDPC matrix. Each layer element corresponds to the active 360x360 shifted identity submatrices, within a layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit.
The UHS-II solution is crafted to enhance data transfer rates within low-voltage environments. It particularly supports high-definition content transmission, which is critical for modern mobile devices requiring seamless streaming and heavy data loads. Utilizing a modular design approach, it ensures a robust and efficient layout that facilitates optimal performance and reliability.
The RWM6050 Baseband Modem from Blu Wireless is integral to their high bandwidth, high capacity mmWave solutions. Designed for cost-effectiveness and power efficiency, this modem forms a central component of multi-gigabit radio interfaces. It provides robust connectivity for access and backhaul markets through its notable flexibility and high performance. Partnering with mmWave RF chipsets, the RWM6050 delivers flexible channelisation modes and modulation coding capabilities, enabling it to handle extensive bandwidth requirements and achieve multi-gigabit data rates. This is supported by dual modems that include a mixed-signal front-end, enhancing its adaptability across a vast range of communications environments. Key technical features include integrated network synchronization and a programmable real-time scheduler. These features, combined with advanced beam forming support and digital front-end processing, make the RWM6050 a versatile tool in optimizing connectivity solutions. The modem's specifications ensure high efficiency in various network topologies, highlighting its role as a crucial asset in contemporary telecommunications settings.
Ubi.cloud is an innovative solution by Ubiscale that transforms the landscape of IoT device geolocation. It effectively transfers the power-intensive processes of GPS and Wi-Fi to the cloud, thereby significantly reducing the size, power usage, and cost of tracking devices. Ubi.cloud's focus is on providing ubiquitous geolocation by combining GPS for outdoor navigation with Wi-Fi for precise indoor and urban tracking. The architecture of Ubi.cloud integrates embedded technologies like UbiGNSS and UbiWIFI, and aims for substantial power savings and efficient operation. UbiGNSS minimizes power usage during location computation, boasting impressive power savings compared to traditional GPS cold-start processes. Meanwhile, UbiWiFi offers rapid location determination, outperforming standard Wi-Fi sniffing techniques. Ubi.cloud supports low-power wide-area networks like Sigfox, LoRa, and NB-IoT, ensuring versatile application across various IoT infrastructures. The solution provides not just location but accuracy metrics, while the device's power can be completely turned off between location updates to conserve energy. This combination of efficiency, adaptability, and cost-effectiveness makes Ubi.cloud an ideal solution for developers aiming to enhance IoT device capabilities with minimal resource consumption.
The FCM3801-BD power amplifier completes Falcomm’s Dual-Drive™ series with remarkable functionality for high-frequency applications. Designed for a center frequency of 38 GHz, it offers expanded performance capabilities that address the needs of the modern telecommunications landscape. Its integration with CMOS SOI and other advanced platforms like GaAs or GaN underscores its utility in diverse application scenarios. Excelling in energy efficiency, the FCM3801-BD achieves a power-added efficiency (PAE) up to 56%, which reduces energy usage without compromising performance. This makes it an excellent choice for systems aiming to cut energy costs while delivering high data throughput. As with the other products in this series, the FCM3801-BD supports a balanced power range and maintains efficiency across a supply voltage span of 1.6V to 2.0V. This amplifier is perfectly tailored for expansive high-bandwidth roles, making it suitable for telecommunications and cutting-edge wireless technology explorations. Its design ensures developers can maximize output while maintaining an environmentally friendly footprint, thus aiding in global efforts to reduce carbon emissions alongside boosting technological efficiency.
Efinix's Trion FPGAs provide an ideal solution for edge computing and IoT applications, where power efficiency, speed, and integration capabilities are critical. The Trion family, built on a 40 nm process node, offers a range of devices with logic elements between 4K to 120K, catering to both simple and complex application needs. Their comprehensive interface support, including MIPI, DDR, and LVDS, enhances their suitability for high-bandwidth applications in communication, consumer, and industrial sectors.\n\nTrion FPGAs are designed for high integration in space-constrained environments. The small package sizes, such as the WLCSP, make it feasible to integrate these FPGAs directly onto small-scale devices. The incorporation of hardened MIPI and DDR controllers further streamlines the ability to handle video and data-heavy tasks, which is increasingly relevant in today's data-centric tech landscape.\n\nWith robust I/O features, these FPGAs provide versatile connection options for a range of peripherals, fulfilling the demands of industries that rely on high-speed and reliable data transfer. The support for a variety of standards combined with their easy-to-use development environment fosters a more straightforward transition from design to deployment. Efinix ensures these products are capable of handling future advancements by committing to a longer product lifecycle, promising designers a secure investment.
The Digital PreDistortion (DPD) Solution by Systems4Silicon is a cutting-edge technology developed to maximize the power efficiency of RF power amplifiers. Known as FlexDPD, this solution is vendor-independent, allowing it to be compiled across various FPGA or ASIC platforms. It's designed to be scalable, optimizing resources according to bandwidth, performance, and multiple antennae requirements. One of the key benefits of FlexDPD is its substantial efficiency improvements, reaching over 50% when used with modern GaN devices in Doherty configurations, surpassing distortion improvements of 45 dB. FlexDPD is versatile, operating with communication standards including multi-carrier, multi-standard, and various generations from 2G to 5G. It supports both time division and frequency division duplexing, and can accommodate wide Tx bandwidths, limited only by equipment capabilities. The technology is also agnostic to amplifier topology and transistor technology, providing broad applicability across different setups, whether class A/B or Doherty, and different transistor types like LDMOS, GaAs, or GaN. This technology integrates seamlessly with Crest Factor Reduction (CFR) and envelope tracking techniques, ensuring a low footprint on resources while maximizing efficiency. With complementary integration and performance analysis tools, Systems4Silicon provides comprehensive support and documentation, ensuring that clients can maximize the benefits of their DPD solution.
The DVB-S2-LDPC-BCH module by Wasiela integrates cutting-edge forward error correction capabilities with high efficiency. This product leverages the power of Low-Density Parity-Check codes concatenated with Bose-Chaudhuri-Hocquenghem (BCH) codes, ensuring reliable operation near the theoretical limits of data transmission. Designed for satellite communications, the DVB-S2-LDPC-BCH decoder supports an irregular parity check matrix and employs layered decoding techniques. The inclusion of the minimum sum algorithm enhances precision and performance through soft decision decoding. It is fully compliant with ETSI standards, making it a secure choice for satellite broadcast applications. The module offers a variety of throughput and error correction configurations, facilitated by a comprehensive delivery package, including synthesizable Verilog, test benches, and extensive documentation. This intellectual property core proves itself indispensable for modern digital video broadcasting needs, offering both power and adaptability.
Wasiela’s LTE Lite solution is designed to bring flexibility and performance to LTE communications through an optimized PHY layer that caters to User Equipment (UE) standards. The system's compliance to CAT 0/1 PHY ensures breadth in application while accommodating various channel bandwidths ranging from 1.4 MHz to 20 MHz. Employing advanced modulation techniques such as QPSK, 16QAM, and 64QAM, this module can dynamically track time and manage frequency corrections. Its operation is managed by a master finite state machine, making it readily adaptable to integrate with various RF tuners while ensuring synchrony and precision in signal processing. The LTE Lite IP is built from synthesizable Verilog, providing portability across platforms with comprehensive support, including system modeling, test benches, and documentation. Designed for integration into modern telecommunications, the LTE Lite delivers efficient and reliable LTE performance tailored to diverse deployment needs.
The Nerve IIoT Platform by TTTech Industrial is engineered to bridge the gap between real-time data and IT functionalities in industrial environments. This platform allows machine builders and operators to effectively manage edge computing needs with a cloud-managed approach, ensuring safe and flexible deployment of applications and data handling. At its core, Nerve is designed to deliver real-time data processing capabilities that enhance operational efficiency. This platform is distinguished by its integration with off-the-shelf hardware, providing scalability from gateways to industrial PCs. Its architecture supports virtual machines and network protocols such as CODESYS and Docker, thereby enabling a diverse range of functionalities. Nerve’s modular system allows users to license features as needed, optimizing both edge and cloud operations. Additionally, Nerve delivers substantial business benefits by increasing machine performance and generating new digital revenue streams. It supports remote management and updates, reducing service costs and downtime, while improving cybersecurity through standards compliant measures. Enterprises can use Nerve to connect multiple machines globally, facilitating seamless integration into existing infrastructures and expanding digital capabilities. Overall, Nerve positions itself as a formidable IIoT solution that combines technical sophistication with practical business applications, merging the physical and digital worlds for smarter industry operations.
ntLDPC_SDAOCT IP implements a 5G-NR Base Graph 1 systematic Encoder/Decoder based on Quasi-Cyclic LDPC Codes (QC-LDPC), with lifting size Zc=384 and Information Block Size 8448 bits. The implementation is based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that it offers high throughput at low implementation complexity. The ntLDPCE_SDAOCT Encoder IP implements a systematic LDPC Zc=384 encoder. Input and Output may be selected to be 32-bit or 128-bits per clock cycle prior to synthesis, while internal operations are 384-bits parallel per clock cycle. Depending on code rate, the respective amount of parity bits are generated and the first 2xZc=768 payload bits are discarded. There are 5 code rate modes of operation available (8448,8448)-bypass, (9984,8448)-0.8462, (11136,8448)-0.7586, (12672,8448)-0.6667 and (16896,8448)-0.5. The ntLDPCD_SDAOCT Base Graph Decoder IP may optionally implement one of two approximations of the log-domain LDPC iterative decoding algorithm (Belief propagation) known as either Layered Min-Sum Algorithm (MS) or Layered Lambda-min Algorithm (LMIN). Variations of Layered MS available are Offset Min-Sum (OMS), Normalized Min-Sum (NMS), and Normalized Offset Min-Sum (NOMS). Selecting between these algorithms presents a decoding performance vs. system resources utilization trade-off. The ntLDPCD_SDAOCT decoder IP implements a Zc=384 parallel systematic LDPC layered decoder. Each layer corresponds to Zc=384 expanded rows of the original LDPC matrix. Each layer element corresponds to the active ZcxZc shifted identity submatrices within the layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit, in order to update the layers LLR estimates and extrinsic information iteratively until the required number of decoding iterations has been run. The decoder IP also features a powerful optional early termination (ET) criterion, to maintain practically equivalent error correction performance, while significantly increasing its throughput rate and/or reducing hardware cost. Additionally it reports how many decoding iterations have been performed when ET is activated, for system performance observation and calibration purposes. Finally a simple, yet robust, flow control handshaking mechanism is included in both IPs, which is used to communicate the IPs availability to adjacent system components. This logic is easily portable into any communication protocol, like AXI4 stream IF.
In channel coding redundancy is inserted in the transmitted information bit-stream. This redundant information is used in the decoder to eliminate the channel noise. The error correction capability of a FEC system strongly depends on the amount of redundancy as well as on the coding algorithm itself. TPCs perform well in the moderate to high SNRs because the effect of error floor is less. As TPCs have more advantage when a high rate code is used, they are suitable for commercial applications in wireless and satellite communications. The ntTPC Turbo Product Codec IP core is consisted of the Turbo Product Encoder (ntTPCe) and the Turbo Product Decoder (ntTPCd) blocks. The product code C is derived from two/three constituent codes, namely C1, C2 and optionally C3. The information data is encoded in two/three dimensions. Every row of C is a code of C2 and every column of C is a code of C1. When the third coding dimension is enabled, then there are C3 C1*C2 data planes. The ntTPC core supports both e-Hamming and Single Parity Codes as the constituent codes. The core also supports shortening of rows or columns of the product table, as well as turbo shortening. Shortening is a way of providing more powerful codes by removing information bits from the code. The ntTPCe core receives the information bits row by row from left to right and transmits the encoded bits in the same order. It consists of a row, column and 3D encoder. The ntTPCd decoder receives soft information from the channel in the 2’s complement number system and the input samples are received row by row from left to right. The implemented decoding algorithm computes the extrinsic information for every dimension C1, C2, C3 by iteratively decoding words that are near the soft-input word. An advanced scalable and parametric design approach produces custom design versions tailored to end customer applications design tradeoffs.
Wireless IP developed by Analog Circuit Works provides essential capabilities for portable, medical, and sensor application domains. These IP blocks are critical in enabling wireless power and data transmission, thereby supporting the autonomy and versatility of modern devices that rely heavily on wireless technologies. The solutions offered are designed with a focus on maximizing frequency capabilities while ensuring efficiency across various environmental scenarios. This adaptability ensures that these IPs meet the rigorous demands of applications where wireless communication and power provisioning are at the forefront of user expectations. Analog Circuit Works' wireless solutions are fine-tuned to provide enhanced robustness and reliability, facilitating seamless integration within devices that require stable and sustained wireless operations. As a result, they are perfectly suited for innovations in IoT and other rapidly evolving technology landscapes requiring high-quality wireless interface and communication solutions.
Join the world's most advanced semiconductor IP marketplace!
It's free, and you'll get all the tools you need to discover IP, meet vendors and manage your IP workflow!