All IPs > Wireless Communication
The Wireless Communication category at Silicon Hub encompasses a diverse array of semiconductor IPs designed to facilitate seamless wireless connectivity in today's rapidly evolving technological landscape. As the demand for higher data rates and uninterrupted connectivity grows, these IPs play a vital role in enabling devices to communicate efficiently across various protocols and standards. This category includes highly specialized IPs that support the implementation and enhancement of wireless communication technologies in a variety of applications ranging from consumer electronics to industrial systems.
Within this category, semiconductor IPs cover a wide spectrum of wireless standards and protocols. This includes evolving mobile communication standards like 3GPP-5G and LTE, which are essential for cellular networks' operation and are pivotal in the deployment of the latest 5G networks. For localized wireless communication, standards such as 802.11 (commonly referred to as Wi-Fi), Bluetooth, NFC, and Wireless USB are covered, facilitating device interconnectivity and data exchange in numerous consumer electronics, IoT devices, and more. Industrial and professional applications may utilize IPs related to standards like WiMAX (802.16), CPRI, OBSAI, which are crucial for network infrastructure and robust communication systems.
In addition to these, the Wireless Communication category includes IPs for satellite navigation systems like GPS, ensuring accurate geolocation services essential for navigation devices in both personal and commercial use. Standards like UWB (Ultra-Wideband) offer high-speed data transmission over short ranges, beneficial for applications demanding rapid short-range communication. Furthermore, for high-definition broadcasting, IPs supporting Digital Video Broadcast standards offer necessary capabilities to meet market demands for clear and reliable video content transmission.
This extensive category of semiconductor IPs under Wireless Communication not only provides the architectural needs for state-of-the-art communication devices but also accommodates future technological advancements. By integrating these IPs, semiconductor product designers and engineers can efficiently develop solutions tailored for enhanced connectivity, ensuring their products remain at the forefront of technological innovation and meet the ever-growing expectations of modern consumers for instant and reliable wireless communication. Whether you are developing next-gen smartphones, IoT solutions, or advanced networking systems, these IPs are critical components in achieving superior performance and connectivity.
Akida Neural Processor IP by BrainChip serves as a pivotal technology asset for enhancing edge AI capabilities. This IP core is specifically designed to process neural network tasks with a focus on extreme efficiency and power management, making it an ideal choice for battery-powered and small-footprint devices. By utilizing neuromorphic principles, the Akida Neural Processor ensures that only the most relevant computations are prioritized, which translates to substantial energy savings while maintaining high processing speeds. This IP's compatibility with diverse data types and its ability to form multi-layer neural networks make it versatile for a wide range of industries including automotive, consumer electronics, and healthcare. Furthermore, its capability for on-device learning, without network dependency, contributes to improved device autonomy and security, making the Akida Neural Processor an integral component for next-gen intelligent systems. Companies adopting this IP can expect enhanced AI functionality with reduced development overheads, enabling quicker time-to-market for innovative AI solutions.
The Akida 2nd Generation continues BrainChip's legacy of low-power, high-efficiency AI processing at the edge. This iteration of the Akida platform introduces expanded support for various data precisions, including 8-, 4-, and 1-bit weights and activations, which enhance computational flexibility and efficiency. Its architecture is significantly optimized for both spatial and temporal data processing, serving applications that demand high precision and rapid response times such as robotics, advanced driver-assistance systems (ADAS), and consumer electronics. The Akida 2nd Generation's event-based processing model greatly reduces unnecessary operations, focusing on real-time event detection and response, which is vital for applications requiring immediate feedback. Furthermore, its sophisticated on-chip learning capabilities allow adaptation to new tasks with minimal data, fostering more robust AI models that can be personalized to specific use cases without extensive retraining. As industries continue to migrate towards AI-powered solutions, the Akida 2nd Generation provides a compelling proposition with its improved performance metrics and lower power consumption profile.
**Ceva-XC21** is the most efficient vector DSP core available today for communications applications. The Ceva-XC21 DSP is designed for low-power, cost- and size-optimized cellular IoT modems, NTN VSAT terminals, eMBB and uRLLC applications. Ceva-XC21 offers scalable architecture and dual thread design with support for AI, addressing growing demand for smarter, yet more cost and power efficient cellular devices. Targeted for 5G and 5G-Advanced workloads, the Ceva-XC21 has multiple products configurations enabling system designers to optimize the size and cost to their specific application needs. The Ceva-XC21, based on the advanced Ceva-XC20 architecture, features a product line of 3 vector DSP cores. Each of the cores offers a unique performance & area configuration with a SW compatibility between them. The different cores span across single thread or dual thread configurations, and 32 or 64 16bits x 16bits MACs. The Ceva-XC212, the highest performing variant of the Ceva-XC21 delivers up to 1.8x times the performance of Ceva’s previous-generation Ceva-XC4500 architecture, while reducing the core area. Ceva-XC210, the smallest configuration of the Ceva-XC21, enables system designers to reduce the core die size in 48% compared with the previous generation. Ceva-XC211 offers the same performance envelope compared with the previous generation at 63% of the area. [**Learn more about Ceva-XC21>**](https://www.ceva-ip.com/product/ceva-xc21/?utm_source=silicon_hub&utm_medium=ip_listing&utm_campaign=ceva_xc21_page)
The **Ceva-Waves Bluetooth platform** includes field-proven hardware IP for baseband controller, modem, and 2.4 GHz RF transceiver functions, and allows use of many third-party radio IPs as well. The platform includes optimized baseband controller hardware and software, and above the Host Controller Interface (HCI) a host-agnostic software protocol stack supporting all major Bluetooth profiles. The built-in 802.15.4 add-on suite shares the same Bluetooth radio, and includes IEEE 802.15.4 MAC & modem hardware IP and software, and is compatible with Zigbee, Thread and Matter host protocol stacks. The Ceva-Waves Bluetooth platform is also available as part of the **Ceva-Waves Links family** of multi-protocol turnkey platforms, including with optimized Wi-Fi & Bluetooth co-existence interface and packet traffic arbiter. The Ceva-Waves Bluetooth platforms also comprises a state-of-the-art radio in TSMC 12nm FFC+ supporting all the latest Bluetooth 6.0 dual mode features, along with next gen Bluetooth High Data Throughput and IEEE 802.15.4. Its innovative architecture provides best in class performance in term of power consumption, die size, sensitivity and output power. [**Learn more about Ceva's Bluetooth solution>**](https://www.ceva-ip.com/product/ceva-waves-bluetooth/?utm_source=silicon_hub&utm_medium=ip_listing&utm_campaign=ceva_waves_bluetooth_page)
The Low Density Parity Check (LDPC) codes are powerful, capacity approaching channel codes and have exceptional error correction capabilities. The high degree of parallelism that they offer enables efficient, high throughput hardware architectures. The ntLDPC_WiFi6 IP Core is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes and is fully compliant with IEEE 802.11 n/ac/ax standard. The Quasi-Cyclic LDPC codes are based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that they offer high throughput at low implementation complexity. The ntLDPC_WiFi6 decoder IP Core may optionally implement one of two approximations of the log-domain LDPC iterative decoding algorithm (Belief propagation) known as either Layered Normalized Offset Min-Sum Algorithm or Layered Lambda-min Algorithm. Selecting between the two algorithms presents a decoding performance .vs. system resources utilization trade-off. The core is highly reconfigurable and fully compliant to the IEEE 802.11 n/ac/ax Wi-Fi4, Wi-Fi5 and Wi-Fi 6 standards. The ntLDPC_WiFi6 encoder IP implements a 81-bit parallel systematic LDPC encoder. An off-line profiling Matlab script processes the original matrices and produces a set of constants that are associated with the matrix and hardcoded in the RTL encoder.
**Ceva-Waves Links** is a growing family of multi-standard wireless platforms. By optimizing connectivity support for various combinations of **Wi-Fi, Bluetooth, 802.15.4, and ultra-wideband (UWB)**, the Ceva-Waves Links family provides preconfigured, optimized solutions for SoCs requiring multiple connectivity standards. All Ceva-Waves Links configurations are based on field-proven Ceva-Waves hardware IP and software stacks. Unique Ceva coexistence algorithms ensure efficient and interference-free operation of multiple connections while sharing one radio. The **Ceva-Waves Links family** offers combinations of Ceva-Waves Wi-Fi, Ceva-Waves Bluetooth, 802.15.4 (supporting protocols such as Thread, Matter and Zigbee), and Ceva-Waves UWB hardware IP, integrated with Ceva or third-party radios and CPU- and OS-agnostic software stacks. New platforms will be introduced to address market trends or customers’ demands. [**Learn more about Ceva-Waves Links family solution>**](https://www.ceva-ip.com/product/ceva-waves-links/?utm_source=silicon_hub&utm_medium=ip_listing&utm_campaign=ceva_waves_links_page)
**Ceva-Waves UWB platform** cuts the development time and risk for implementing a wide range of UWB functionality in SoCs. It provides optimized MAC and PHY hardware IP and supporting software for secure and accurate ranging, and Doppler Radar presence detection applications. It can be implemented in an SoC independently or in conjunction with the Ceva-Waves Bluetooth platform, as well as part of the Ceva-Waves Links family of multiprotocol platforms. The Ceva-Waves UWB platform includes hardware IP for an optimized UWB MAC and PHY meeting 802.15.4 HRP, FiRa 3.0, and the Car Connectivity Consortium Digital Key 3.0 (CCC DK3.0) requirements. The platform includes advanced Wi-Fi interference suppression. A comprehensive suite of CPU-agnostic software stacks that support FiRa 3.0 MAC, CCC DK3.0 MAC, and radar for implementing applications such as automotive digital keys and in-cabin child-presence detection (CPD), general power-saving presence detection in laptops, TVs and smart buildings, asset tracking tags, real-time location services (RTLS), and tap-free payment. [**Learn more about our UWB soluion>**](https://www.ceva-ip.com/product/ceva-waves-uwb/?utm_source=silicon_hub&utm_medium=ip_listing&utm_campaign=ceva_waves_uwb_page)
The Jotunn8 AI Accelerator represents a pioneering approach in AI inference chip technology, designed to cater to the demanding needs of contemporary data centers. Its architecture is optimized for high-speed deployment of AI models, combining rapid data processing capabilities with cost-effectiveness and energy efficiency. By integrating features such as ultra-low latency and substantial throughput capacity, it supports real-time applications like chatbots and fraud detection that require immediate data processing and agile responses. The chip's impressive performance per watt metric ensures a lower operational cost, making it a viable option for scalable AI operations that demand both efficiency and sustainability. By reducing power consumption, Jotunn8 not only minimizes expenditure but also contributes to a reduced carbon footprint, aligning with the global move towards greener technology solutions. These attributes make Jotunn8 highly suitable for applications where energy considerations and environmental impact are paramount. Additionally, Jotunn8 offers flexibility in memory performance, allowing for the integration of complexity in AI models without compromising on speed or efficiency. The design emphasizes robustness in handling large-scale AI services, catering to the new challenges posed by expanding data needs and varied application environments. Jotunn8 is not simply about enhancing inference speed; it proposes a new baseline for scalable AI operations, making it a foundational element for future-proof AI infrastructure.
The ARINC 818 Product Suite is a comprehensive collection of tools and resources designed to support the full development lifecycle for ARINC 818 enabled equipment. This suite assists in the implementation and testing of ARINC 818 protocols, which are crucial for systems that require high-performance video and data transmission, such as in avionics and defense applications. The product suite is built to facilitate not only the development and qualification but also the simulation of ARINC 818 products, ensuring effective integration into mission-critical environments. The suite’s tools include development software and Implementer's guides, enabling seamless access to ARINC 818 capabilities.
**Ceva-PentaG2** is a complete IP platform for implementing a wide range of user-equipment and IoT cellular modems. The platform includes a variety of DSPs, modem hardware modules, software libraries, and simulation tools. Capabilities of the Ceva-PentaG2 include New Radio (NR) physical layer design ranging across all 3GPP profiles from RedCap IoT and mMTC, through eMBB up to ultra-reliable low-latency communications (URLLC). The platform has two base configurations. Ceva-PentaG2 Max emphasizes performance and scalability for enhanced mobile broadband (eMBB) and future proofing design for next generation 5G-Advanced releases. Ceva-PentaG2 Lite emphasizes extreme energy and area efficiency for lower-throughput applications such as LTE Cat 1, RedCap, and optimized cellular IoT applications. The PentaG2 platform comprises a set of Ceva DSP cores, optimized fixed-function hardware accelerators, and proven, optimized software modules. By using this platform, designers can implement optimized, hardware-accelerated processing chains for all main modem functions. In the selection process, designers can tune their design for any point across a huge space of area, power consumption, latency, throughput, and channel counts. Solutions can fit applications ranging from powerful eMBB for mobile and Fixed Wireless Access (FWA) devices to connected vehicles, cellular IoT modules, and even smart watches. System-C models in Ceva’s Virtual Platform Simulator (VPS) aid architectural exploration and system tuning, while an FPGA-based emulation kit speeds SoC integration. [**Learn more about Ceva-PentaG2 solution>**](https://www.ceva-ip.com/product/ceva-pentag2/?utm_source=silicon_hub&utm_medium=ip_listing&utm_campaign=ceva_pentag2_page)
EW6181 is an IP solution crafted for applications demanding extensive integration levels, offering flexibility by being licensable in various forms such as RTL, gate-level netlist, or GDS. Its design methodology focuses on delivering the lowest possible power consumption within the smallest footprint. The EW6181 effectively extends battery life for tags and modules due to its efficient component count and optimized Bill of Materials (BoM). Additionally, it is backed by robust firmware ensuring highly accurate and reliable location tracking while offering support and upgrades. The IP is particularly suitable for challenging application environments where precision and power efficiency are paramount, making it adaptable across different technology nodes given the availability of its RF frontend.
**Ceva-Waves Dragonfly platform** is a turnkey platform with optimized, low-power hardware IP and protocol software for implementing narrow-band IoT (NB-IoT) cellular modem SoCs. Extensions provide support for GNSS such as GPS and BeiDou and for sensor-fusion applications. The Ceva-Waves Dragonfly platform comprises hardware IP with an enhanced Ceva-BX1 processor, specific hardware accelerators, and SoC infrastructure IP. Software includes NB-IoT protocol stack for L1 through L3 functions including encryption and software PHY, a task-optimized RTOS, and optional GNSS receiver and control software, all executing on the Ceva-BX1. Pre-certified for 3GPP Release 15 CAT NB2, the solution is tuned for small footprint and extremely low power, yet has headroom for additional software-defined functions, such as sensor fusion. [**Learn more about Ceva-Waves Dragonfly>**](https://www.ceva-ip.com/product/ceva-waves-dragonfly/?utm_source=silicon_hub&utm_medium=ip_listing&utm_campaign=ceva_waves_dragonfly_page)
The HOTLink II Product Suite constitutes a range of resources specifically tailored for systems utilizing HOTLink II™ technology. This suite is engineered to manage high-speed video and data communication in environments where reliability and precision are paramount. It is ideal for applications in aerospace where maintaining high data integrity is critical. The suite provides robust solutions for both the development and operational stages, enhancing system performance. With its extensive support for different phases of product lifecycle management, the HOTLink II suite ensures that products meet the high standards required for mission-critical military and industrial applications.
The ntLDPC_5GNR Base Graph Encoder IP Core is defined in 3GPP TS 38.212 standard document and it is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes. The specification defines two sets of LDPC Base Graphs and their respective derived Parity Check Matrices. Each Base Graph can be combined with 8 sets of lifting sizes (Zc) in a total of 51 different lifting sizes. This way by using the 2 Base Graphs, the 5G NR specification defines up to 102 possible distinct LDPC modes of operation to select from, for optimum decoding performance, depending on target application code block size and code rate (using the additional rate matching module features). For Base Graph 1 we have LDPC(N=66xZc,K=22xZc) sized code blocks, while for Base Graph 2 we have LDPC(N=50xZc,K=[6,8,9,10]xZc) sized code blocks. The ntLDPCE_5GNR Encoder IP implements a multi-parallel systematic LDPC encoder. Parallelism depends on the selected lifting sizes subsets chosen for implementation. Shortened blocks are supported with granularity at lifting size Zc-bit boundaries. Customizable modes generation is also supported beyond the scope of the 5G-NR specification with features such as: “flat parity bits puncturing instead of Rate Matching Bit Selection”, “maintaining the first 2xZc payload bits instead of eliminating it before transmission”, etc. The ntLDPCD_5GNR decoder IP implements a maximum lifting size of Zc_MAX-bit parallel systematic LDPC layered decoder. Each layer corresponds to Zc_MAX expanded rows of the original LDPC matrix. Each layer element corresponds to the active ZcxZc shifted identity sub-matrices within the layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit, in order to update the layers LLR estimates and extrinsic information iteratively until the required number of decoding iterations has been run. The decoder IP also features a powerful optional early termination (ET) criterion, to maintain practically equivalent error correction performance, while significantly increasing its throughput rate and/or reducing hardware cost. Additionally it reports how many decoding iterations have been performed when ET is activated, for system performance observation and calibration purposes. Finally a simple, yet robust, flow control handshaking mechanism is included in both IPs, which is used to communicate the IPs availability to adjacent system components. This logic is easily portable into any communication protocol, like AXI4 stream IF.
The CANmodule-III is an advanced CAN controller designed to efficiently manage communication over the Controller Area Network. It features a mailbox architecture with a robust 32 receive and 32 transmit mailboxes, offering full compliance with the CAN2.0B standard. This core is optimized for a variety of high-demanding applications across aerospace, automotive, and industrial sectors. In terms of integration, the CANmodule-III is crafted for seamless incorporation into systems-on-chip, adapting easily to both FPGA and ASIC designs. The architecture, originally based on Bosch’s fundamental CAN design, allows for customizable message filtering, providing flexibility in handling different communication scenarios. The integration of application-specific functions as add-ons means that the core itself remains unaffected, ensuring consistent performance. This CAN controller is also known for its efficient transaction management on the bus, making it a preferred choice for environments where reliability and precision are critical. The CANmodule-III’s system support functions and streamlined processing capabilities see it effectively used in various industry-specific applications where optimized communication is paramount.
The Polar ID system by Metalenz revolutionizes biometric security through its unique use of meta-optic technology. It captures the polarization signature of a human face, delivering a new level of security that can detect sophisticated 3D masks. Unlike traditional structured light technologies, which rely on complex dot-pattern projectors, Polar ID simplifies the module through a single, low-profile polarization camera that operates in near-infrared, ensuring functionality across varied lighting conditions and environments. Polar ID offers ultra-secure facial authentication capable of operating in both daylight and darkness, accommodating obstacles such as sunglasses and masks. This capability makes it particularly effective for smartphones and other consumer electronics, providing a more reliable and secure alternative to existing fingerprint and visual recognition technologies. By integrating smoothly into the most challenging smartphone designs, Polar ID minimizes the typical hardware footprint, making advanced biometric security accessible at a lower cost. This one-of-a-kind technology not only enhances digital security but also provides seamless user experiences by negating the need for multiple optical components. Its high resolution and accuracy ensure that performance is not compromised, safeguarding user authentication in real-time, even in adverse conditions. By advancing face unlock solutions, Polar ID stands as a future-ready answer to the rising demand for unobtrusive digital security in mainstream devices.
Convolutional FEC codes are very popular because of their powerful error correction capability and are especially suited for correcting random errors. The most effective decoding method for these codes is the soft decision Viterbi algorithm. ntVIT core is a high performance, fully configurable convolutional FEC core, comprised of a 1/N convolutional encoder, a variable code rate puncturer/depuncturer and a soft input Viterbi decoder. Depending on the application, the core can be configured for specific code parameters requirements. The highly configurable architecture makes it ideal for a wide range of applications. The convolutional encoder maps 1 input bit to N encoded bits, to generate a rate 1/N encoded bitstream. A puncturer can be optionally used to derive higher code rates from the 1/N mother code rate. On the encoder side, the puncturer deletes certain number of bits in the encoded data stream according to a user defined puncturing pattern which indicates the deleting bit positions. On the decoder side, the depuncturer inserts a-priori-known data at the positions and flags to the Viterbi decoder these bits positions as erasures. The Viterbi decoder uses a maximum-likelihood detection recursive process to cor-rect errors in the data stream. The Viterbi input data stream can be composed of hard or soft bits. Soft decision achieves a 2 to 3dB in-crease in coding gain over hard-decision decoding. Data can be received continuously or with gaps.
**Ceva-Waves Wi-Fi platforms portfolio** provide a comprehensive selection of hardware IP and CPU-agnostic host software for energy-efficient SoC implementation of any of a wide range of Wi-Fi subsystems, from Wi-Fi 4 to Wi-Fi 7, for both client devices and access points. The portfolio includes a suite of pre-optimized solutions for various generations and configurations for specific Wi-Fi uses, power consumption levels, and price points, ranging from low-bandwidth IoT connectivity to high-bandwidth hubs. Embedded into one of the Ceva-Waves Links multi-protocol wireless platforms, the Ceva-Waves Wi-Fi IPs can efficiently co-exist with the Ceva-Waves Bluetooth IPs and/or Ceva-Waves UWB IP. The Ceva-Waves Wi-Fi platforms comprise hardware modem PHY IP that supports DSSS, CCK, OFDM and OFDMA modulations; optimized MAC IP that offloads MAC functions from the CPU; and a comprehensive selection of MAC protocol software stacks. The IP and software elements are further organized into three main solution profiles. * Wi-Fi IoT is for energy-efficient low-bandwidth connectivity for IoT devices, supporting 2.4GHz single band or dual/triple bands on 2.4/5/6 GHz for IEEE 802.11n, ax, or be (Wi-Fi 4, 6 or 7). * Wi-Fi High-Performance supports up to 160 MHz bands at 2.4, 5, or 6 GHz in either single-antenna or 2×2 MIMO mode for IEEE 802.11ax or be (Wi-Fi 6 or 7), and is intended for consumer media-streaming applications. * Wi-Fi Access Point supports 160 MHz bands and 2×2 MIMO for IEEE 802.11ax or be (Wi-Fi 6/6E/7), for applications such as media access points, gateways, and small-cell offload that must support up to hundreds of clients. The Ceva-Waves Wi-Fi platforms include a coexistence interface that permits highly efficient operation with the Ceva-Waves Bluetooth platforms. [**Learn more about Ceva-Waves Wi-Fi solution>**](https://www.ceva-ip.com/product/ceva-waves-wi-fi/?utm_source=silicon_hub&utm_medium=ip_listing&utm_campaign=ceva_waves_wifi_page)
The Digital Radio (GDR) from GIRD Systems is an advanced software-defined radio (SDR) platform that offers extensive flexibility and adaptability. It is characterized by its multi-channel capabilities and high-speed signal processing resources, allowing it to meet a diverse range of system requirements. Built on a core single board module, this radio can be configured for both embedded and standalone operations, supporting a wide frequency range. The GDR can operate with either one or two independent transceivers, with options for full or half duplex configurations. It supports single channel setups as well as multiple-input multiple-output (MIMO) configurations, providing significant adaptability in communication scenarios. This flexibility makes it an ideal choice for systems that require rapid reconfiguration or scalability. Known for its robust construction, the GDR is designed to address challenging signal processing needs in congested environments, making it suitable for a variety of applications. Whether used in defense, communications, or electronic warfare, the GDR's ability to seamlessly switch configurations ensures it meets the evolving demands of modern communications technology.
ntLDPC_SDAOCT IP implements a 5G-NR Base Graph 1 systematic Encoder/Decoder based on Quasi-Cyclic LDPC Codes (QC-LDPC), with lifting size Zc=384 and Information Block Size 8448 bits. The implementation is based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that it offers high throughput at low implementation complexity. The ntLDPCE_SDAOCT Encoder IP implements a systematic LDPC Zc=384 encoder. Input and Output may be selected to be 32-bit or 128-bits per clock cycle prior to synthesis, while internal operations are 384-bits parallel per clock cycle. Depending on code rate, the respective amount of parity bits are generated and the first 2xZc=768 payload bits are discarded. There are 5 code rate modes of operation available (8448,8448)-bypass, (9984,8448)-0.8462, (11136,8448)-0.7586, (12672,8448)-0.6667 and (16896,8448)-0.5. The ntLDPCD_SDAOCT Base Graph Decoder IP may optionally implement one of two approximations of the log-domain LDPC iterative decoding algorithm (Belief propagation) known as either Layered Min-Sum Algorithm (MS) or Layered Lambda-min Algorithm (LMIN). Variations of Layered MS available are Offset Min-Sum (OMS), Normalized Min-Sum (NMS), and Normalized Offset Min-Sum (NOMS). Selecting between these algorithms presents a decoding performance vs. system resources utilization trade-off. The ntLDPCD_SDAOCT decoder IP implements a Zc=384 parallel systematic LDPC layered decoder. Each layer corresponds to Zc=384 expanded rows of the original LDPC matrix. Each layer element corresponds to the active ZcxZc shifted identity submatrices within the layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit, in order to update the layers LLR estimates and extrinsic information iteratively until the required number of decoding iterations has been run. The decoder IP also features a powerful optional early termination (ET) criterion, to maintain practically equivalent error correction performance, while significantly increasing its throughput rate and/or reducing hardware cost. Additionally it reports how many decoding iterations have been performed when ET is activated, for system performance observation and calibration purposes. Finally a simple, yet robust, flow control handshaking mechanism is included in both IPs, which is used to communicate the IPs availability to adjacent system components. This logic is easily portable into any communication protocol, like AXI4 stream IF.
The ORC3990 is a groundbreaking LEO Satellite Endpoint SoC engineered for use in the Totum DMSS Network, offering exceptional sensor-to-satellite connectivity. This SoC operates within the ISM band and features advanced RF transceiver technology, power amplifiers, ARM CPUs, and embedded memory. It boasts a superior link budget that facilitates indoor signal coverage. Designed with advanced power management capabilities, the ORC3990 supports over a decade of battery life, significantly reducing maintenance requirements. Its industrial temperature range of -40 to +85 degrees Celsius ensures stable performance in various environmental conditions. The compact design of the ORC3990 fits seamlessly into any orientation, further enhancing its ease of use. The SoC's innovative architecture eliminates the need for additional GNSS chips, achieving precise location fixes within 20 meters. This capability, combined with its global LEO satellite coverage, makes the ORC3990 a highly attractive solution for asset tracking and other IoT applications where traditional terrestrial networks fall short.
The Digital PreDistortion (DPD) Solution from Systems4Silicon is a comprehensive adaptive technology aimed at improving the efficiency of RF power amplifiers. It is designed to maximize amplifier performance by allowing operation in the non-linear region while significantly reducing distortion. The solution is highly scalable, allowing for resource optimization across bandwidth, performance, and multiple antenna configurations. It is technology-agnostic, supporting various transistor technologies such as LDMOS and GaN, and can be adapted to different amplifier topologies including Doherty configurations. Benefits of the DPD technology include achieving over 50% efficiency improvements when utilized alongside the latest GaN devices, with amplifier distortion improvements of over 45 dB. This IP also supports multi-carrier and multi-standard transmissions, covering a broad array of standards such as 3G, 4G, 5G, DVB, and many more. It is compliant with the O-RAN standard for 7-2x deployments, making it a versatile solution for modern wireless communication systems. Systems4Silicon's DPD solution includes comprehensive integration and performance analysis tools, backed by expert support from experienced radio systems engineers. Designed for both FPGA/SoC and ASIC platforms, it provides a low resource footprint while ensuring maximum efficiency across diverse applications.
GNSS Sensor Ltd offers the GNSS VHDL Library, a powerful suite designed to support the integration of GNSS capabilities into FPGA and ASIC products. The library encompasses a range of components, including configurable GNSS engines, Viterbi decoders, RF front-end control modules, and a self-test module, providing a comprehensive toolkit for developers. This library is engineered to be highly flexible and adaptable, supporting a wide range of satellite systems such as GPS, GLONASS, and Galileo, across various configurations. Its architecture aims to ensure independence from specific CPU platforms, allowing for easy adoption across different systems. The GNSS VHDL Library is instrumental in developing cost-effective and simplified system-on-chip solutions, with capabilities to support extensive configurations and frequency bandwidths. It facilitates rapid prototyping and efficient verification processes, crucial for deploying reliable GNSS-enabled devices.
The 802.11ah HaLow Transceiver is engineered to fulfill the demands of modern IoT applications, where low power consumption and extended range are critical. It aligns with the IEEE 802.11ah standard, commonly termed as Wi-Fi HaLow™, and offers exceptional flexibility for new generations of IoT and mobile devices.\n\nBoasting features like low noise direct conversion and integrated calibration for I/Q pathways, this transceiver supports multiple modulation bandwidths, including 1 MHz, 2 MHz, and up to 4 MHz. With its capabilities spanning significant frequency ranges, the design ensures stable connectivity with minimum latency and enhanced receiver sensitivity.\n\nOne of its strengths lies in extensibility, providing superb integration potential either as a part of a broader system-on-chip (SoC) or as a standalone communication module. Designed with minimal power draw, it also allows using external power amplifiers to enhance transmission power, aligning with diverse application needs such as asset tracking, building security, and broader sensor networks.
The Hyperspectral Imaging System developed by Imec is a revolutionary tool for capturing and analyzing light across a wide range of wavelengths. This system is particularly valuable for applications requiring detailed spectral analysis, such as agricultural inspection, environmental monitoring, and medical diagnostics. By capturing hundreds of narrow spectral bands, the system provides a comprehensive spectral profile of the subject, enabling precise identification of materials and substances. What sets Imec's Hyperspectral Imaging System apart is its ability to integrate seamlessly into existing devices, allowing for versatile use across various industries. The compact and efficient design ensures that it can be deployed in field conditions, offering real-time analysis capabilities that are crucial for immediate decision-making processes. The Hyperspectral Imaging System is designed with cutting-edge CMOS technology, ensuring high sensitivity and accuracy. This integration with CMOS technology not only enhances the performance but also ensures that the system is cost-effective and accessible to a broader range of applications and markets. As hyperspectral imaging continues to evolve, Imec's system stands as a leader in the field, providing unmatched resolution and reliability.
D2D® Technology, developed by ParkerVision, is a revolutionary approach to RF conversion that transforms how wireless communication operates. This technology eliminates traditional intermediary stages, directly converting RF signals to digital data. The result is a more streamlined and efficient communication process that reduces complexity and power consumption. By bypassing conventional analog-to-digital conversion steps, D2D® achieves higher data accuracy and reliability. Its direct conversion approach not only enhances data processing speeds but also minimizes energy usage, making it an ideal solution for modern wireless devices that demand both performance and efficiency. ParkerVision's D2D® technology continues to influence a broad spectrum of wireless applications. From improving the connectivity in smartphones and wearable devices to optimizing signal processing in telecommunication networks, D2D® is a cornerstone of ParkerVision's technological offerings, illustrating their commitment to advancing communication technology through innovative RF solutions.
The mmWave PLL offers precise high-frequency synthesis capabilities, ideal for mmWave communication applications. Designed to support the demanding requirements of modern telecommunications, this phase-locked loop circuit excels in providing stable and low phase noise performance at extremely high frequencies. This product is tailored for next-generation wireless systems, including 5G networks and beyond, where high data rates and low latency are critical. Its robust architecture allows it to deliver exceptional performance in bandwidth-intensive environments, making it a critical component in advanced RF front-end solutions. mmWave PLL's ability to maintain frequency stability while handling various interference and environmental variables highlights its importance in the seamless operation of high-speed communication infrastructures.
aiSim 5 represents a pivotal advancement in the simulation of automated driving systems, facilitating realistic and efficient validation of ADAS and autonomous driving components. Designed to exceed conventional expectations, aiSim 5 combines high-fidelity sensor and environment simulation with an AI-based digital twin concept to deliver unparalleled simulation accuracy and realism. It is the first simulator to be certified at ISO 26262 ASIL-D level, offering users the utmost industry trust.\n\nThe simulated environments are rooted in physics-based sensor data and cover a wide spectrum of operational design domains, including urban areas and highways. This ensures the simulation tests AD systems under diverse and challenging conditions, such as adverse weather events. aiSim 5's modular architecture supports easy integration with existing systems, leveraging open APIs to ensure seamless incorporation into various testing and continuous integration pipelines.\n\nNotably, aiSim 5 incorporates aiFab's domain randomization to create extensive synthetic data, mirroring real-world variances. This feature assists in identifying edge cases, allowing developers to test system responsiveness in rare but critical scenarios. By turning the spotlight on multi-sensor simulation and synthetic data generation, aiSim 5 acts as a powerful tool to accelerate the development lifecycle of ADAS and AD technologies, fostering innovation and development efficiency.\n\nThrough its intuitive graphical interface, aiSim 5 democratizes access to high-performance simulations, supporting operating systems like Microsoft Windows and Linux Ubuntu. This flexibility, coupled with the tool’s compatibility with numerous standards such as OpenSCENARIO and FMI, makes aiSim an essential component for automotive simulation projects striving for precision and agility.
The High PHY Accelerators from AccelerComm are a collection of signal processing cores designed for ASIC, FPGA, and SoC applications, primarily focused on boosting 5G NR communications. These accelerators incorporate proprietary algorithms that allow users to attain the highest levels of throughput, efficiency, and power savings. These accelerator cores are engineered to facilitate seamless integration into existing systems, significantly improving spectral efficiency through advanced processing techniques. The use of patented algorithms allows for overcoming system noise and interference, delivering superior performance for complex wireless communication networks. Moreover, these accelerators excel at minimizing latency and resource consumption, providing an optimal balance between high performance and low power requirements. Recognized for their flexibility, these accelerators support scalable architectures, customizable for various deployment scenarios. This versatility ensures operators and developers can adapt solutions to fit small, cost-sensitive applications or larger enterprise demands, enhancing the ability to handle high data volumes with integrity and reliability.
The Ncore Cache Coherent Interconnect from Arteris is engineered to overcome challenges associated with multicore SoC designs. It delivers high-bandwidth, low-latency interconnect fabric enhancing communication efficiency across various SoC components and multiple dies. Designed to ensure reliable performance and scalability, this coherent NoC addresses complex tasks by implementing heterogeneous coherency, and it is scalable from small embedded systems to extensive multi-die designs. Ncore promotes effective cache management, providing full coherency for processors and I/O coherency for accelerators. It supports various coherency protocols including CHI-E and ACE, and comes with ISO 26262 certification, meeting stringent safety standards in automotive environments. The inherent AMBA support allows seamless integration with existing and new SoC infrastructures, enhancing data handling efficiency. By offering automated generation of diagnostic analysis and fault modes, Ncore aids developers in creating secure systems ready for advanced automotive and AI applications, thereby accelerating their time-to-market. Its configurability and extensive protocol support position it as a trusted choice for industries requiring flexible and robust system integration solutions.
The TW330 distortion correction IP is tailored for use in applications requiring dynamic image transformations, such as VR headsets and automotive HUDs. Utilizing GPU-powered technologies, it offers real-time coordinate transformations, distortion corrections, and other modifications up to a resolution of 16K x 16K in both RGB and YUV formats. This IP is crucial for enhancing visual accuracy and display adaptability across varied markets.
The FCM1401 is a 14GHz CMOS Power Amplifier tailored for Ku-band applications, operating over a frequency range of 12.4 to 16 GHz. This amplifier exhibits a gain of 22 dB and a saturated output power (Psat) of 19.24 dBm, ensuring optimal performance with a power-added efficiency (PAE) of 47%. The architecture enables reduction in battery consumption and heat output, making it ideal for satellite and telecom applications. Its small silicon footprint facilitates integration in space-constrained environments.
AccelerComm offers an innovative LDPC solution specifically for 5G NR systems, pushing the boundaries of performance with its advanced block-parallel and row-parallel architectures. This sophisticated solution enhances data channel performance by utilizing a combination of scalability, high throughput, and low latency to maintain optimal communication systems. The LDPC solution effectively addresses standard 5G data channels, achieving substantive gains in resource utilization efficiency. By improving the already stringent latency specifications to support numerology 4, the solution ensures comprehensive code and transport block processing capabilities. It also upholds IEEE standards, providing a compliant pathway for high reliability and operational efficiency. Designed for integration across multiple platforms, including ASIC, FPGA, and software form factors, LDPC’s flexibility allows for deployment in a range of network conditions. Its open standard software interfaces make it easily adaptable, presenting a robust and versatile framework for companies to enhance their 5G network communication protocols with minimal effort.
Packetcraft's Bluetooth LE Audio Solutions offer a full suite of host, controller, and LC3 components optimized for seamless transition to Bluetooth LE Audio. The platform supports Auracast broadcast audio and True Wireless Stereo (TWS), making it adaptable to prevalent chipsets and providing flexibility to product companies. The modular design facilitates simplified integration, ensuring companies can leverage advanced audio capabilities in a variety of applications. As Bluetooth audio technology evolves, Packetcraft remains at the leading edge, offering industry-leading solutions that cater to modern audio requirements.
Dyumnin's RISCV SoC is a versatile platform centered around a 64-bit quad-core server-class RISCV CPU, offering extensive subsystems, including AI/ML, automotive, multimedia, memory, cryptographic, and communication systems. This test chip can be reviewed in an FPGA format, ensuring adaptability and extensive testing possibilities. The AI/ML subsystem is particularly noteworthy due to its custom CPU configuration paired with a tensor flow unit, accelerating AI operations significantly. This adaptability lends itself to innovations in artificial intelligence, setting it apart in the competitive landscape of processors. Additionally, the automotive subsystem caters robustly to the needs of the automotive sector with CAN, CAN-FD, and SafeSPI IPs, all designed to enhance systems connectivity within vehicles. Moreover, the multimedia subsystem boasts a complete range of IPs to support HDMI, Display Port, MIPI, and more, facilitating rich audio and visual experiences across devices.
The AST 500 and AST GNSS-RF are multifaceted SOC and RF solutions designed for GNSS applications. They support a wide array of constellations such as GPS, GLONASS, NavIC, and others, in multiple frequency bands, enhancing navigation performance. These ICs integrate features like secure boots and data encryption, facilitating robust security measures crucial for sensitive data. The AST GNSS-RF is equipped with capabilities for L1, L2, L5, and S band reception, catering to high-fidelity signal requirements across various applications. The support for dual-band reception ensures that ionosphere errors are minimized, offering exceptional positioning accuracy.
Polar coding, a relatively recent addition to the 5G NR suite of technologies, is embraced by AccelerComm through their unique design that facilitates higher degrees of parallel processing. This advancement ensures operational efficiency and minimizes resource usage, thereby improving system robustness and throughput in 5G NR control channels. By employing a patented architecture, Polar coding exhibits flexibility and scalability, key to supporting high-performance 5G requirements. The reduced burden on hardware resources enables it to deliver superior BLER performance, crucial for meeting the stringent demands of modern telecommunications standards. Delivering across a spectrum of platforms, whether hardware-based like ASIC and FPGA or software-driven, Polar coding maintains a high degree of integration ease. This allows rapid deployment and alignment with existing infrastructure, ensuring seamless communication and data integrity in a wide array of network scenarios.
ntRSD core implements a time-domain Reed-Solomon decoding algorithm. The core is parameterized in terms of bits per symbol, maximum codeword length and maximum number of parity symbols. It also supports varying on the fly shortened codes. Therefore any desirable code-rate can be easily achieved rendering the decoder ideal for fully adaptive FEC applications. ntRSD core supports erasure decoding thus doubling its error correction capability. The core also supports continuous or burst decoding. The implementation is very low latency, high speed with a simple interface for easy integration in SoC applications.
The pPLL08 Family is a state-of-the-art lineup of all-digital RF frequency synthesizer PLLs engineered for high-frequency applications including 5G and WiFi. These PLLs are designed to deliver ultra-low jitter performance, achieving less than 300 femtoseconds RMS, while supporting frequencies up to 8GHz. Their exceptionally compact area of less than 0.05 square millimeters and low power consumption of under 15 milliwatts make them suitable for demanding RF environments. Built using Perceptia's second-generation digital PLL technology, the pPLL08 Family excels in maintaining consistent output regardless of PVT conditions, offering robust performance in RF applications as a local oscillator or clocking solution for high-performance ADCs and DACs. Its digital architecture minimizes interference from shared die circuits, ensuring superior signal-to-noise ratio performance. The PLLs in this family are available across numerous process technologies, including leading foundries like UMC and TSMC, ensuring flexibility and broad applicability. Perceptia also provides extensive integration support and adaptability for customization, tailoring solutions to meet specific hardware requirements and optimizing integration into various system architectures.
A trailblazer in high-speed rail connectivity, LightningBlu offers a groundbreaking, track-to-train multi-gigabit mmWave solution. This technology is renowned for its seamless integration with train networks, providing stable and fast connections crucial for high-speed transport. LightningBlu operates efficiently over a rail-friendly frequency range from 57-71 GHz and delivers an impressive data throughput of up to 3.5 Gbps. The system comprises both trackside and train-top nodes, each featuring innovative two-sector radios to ensure continuous, dynamic connection between the train and the trackside infrastructure. The design includes components qualified for rugged rail environments, promising extended service life and low maintenance needs. The solution significantly boosts operational efficiency for rail networks, being deployed in key infrastructures like South Western Railways and Caltrain in Silicon Valley. Versatile and resilient, LightningBlu adapts to varied complexities found in high-speed transport contexts. It communicates data faster than 5G while maintaining lower power consumption than traditional mobile networks, ensuring a superior commuter experience through its reliability and speed.
aiData serves as a comprehensive automated data pipeline tailored specifically for the development of ADAS and autonomous driving technologies. This solution optimizes various stages of MLOps, from data capturing to curation, significantly reducing the traditional manual workload required for assembling high-quality datasets. By leveraging cutting-edge technologies for data collection and annotation, aiData enhances the reliability and speed of deploying AD models, fostering a more efficient flow of data between developers and data scientists.\n\nOne of the standout features of aiData is its versioning system that ensures transparency and traceability throughout the data lifecycle. This system aids in curating datasets tailored for specific use cases via metadata enrichment and SQL querying, supporting seamless data management whether on-premise or cloud. Additionally, the aiData Recorder is engineered to produce high-quality datasets by enabling precise sensor calibration and synchronization, crucial for advanced driving applications.\n\nMoreover, the Auto Annotator component of aiData automates the traditionally labor-intensive process of data annotation, utilizing AI algorithms to produce annotations that meet high accuracy standards. This capability, combined with the aiData Metrics tool, allows for comprehensive validation of datasets, ensuring that they correctly reflect real-world conditions. Collectively, aiData empowers automotive developers to refine neural network algorithms and enhance detection software, accelerating the journey from MLOps to production.
The L5-Direct GNSS Receiver from oneNav, Inc. is a revolutionary product designed to engage directly with L5-band signals, a step away from the reliance on older L1 signals. This GNSS receiver captures signals directly in the L5-band, providing a superior solution that addresses the growing issue of GPS signal jamming, creating significant value for users including defense agencies and OEMs. It boasts unique features such as multi-constellation support, which allows users to access over 70 satellite signals from major constellations like GPS, Galileo, QZSS, and BeiDou. The L5-Direct technology integrates a single RF chain, simplifying design and improving efficiency, making it ideal for applications where space and cost are critical. The technology employs machine learning algorithms to mitigate multipath errors, an innovative approach that elevates accuracy by differentiating between direct and reflected signals in challenging terrains. This level of precision and independence from legacy signals captures the essence of what oneNav stands for. Additionally, the receiver's power efficiency is unmatched, thanks to the Application Specific Array Processor (ASAP), which manages processing speed to conserve energy. Its design is particularly advantageous for wearables, IoT devices, and systems requiring constant location tracking, ensuring a minimal power footprint while delivering consistent, accurate data. The L5-Direct GNSS Receiver is also built to withstand disruptions, with significant resilience to jamming and improved consistency in GPS-challenged environments.
CLOP Technologies' 60GHz Wireless Solution offers businesses an impressive alternative to traditional networking systems. Leveraging the IEEE 802.11ad WiFi standard and Wireless Gigabit Alliance MAC/PHY specifications, this solution achieves a peak data rate of up to 4.6Gbps. This makes it particularly suited for applications that require significant bandwidth, such as real-time, uncompressed HD video streaming and high-speed data transfers — operations that are notably quicker compared to current WiFi systems. The solution is engineered to support 802.11ad IP networking, providing a platform for IP-based applications like peer-to-peer data transfer and serving as a router or access point. Its architecture includes a USB 3.0 host interface and mechanisms for RF impairment compensation, ensuring both ease of access for host compatibility and robust performance even under high data rate operations. Operating on a frequency band ranging from 57GHz to 66GHz, the wireless solution utilizes modulation modes such as BPSK, QPSK, and 16QAM. It incorporates forward error correction (FEC) with LDPC codes, providing various coding rates for enhanced data integrity. Furthermore, the system boasts AES-128 hardware security, with quality of service maintained through IEEE 802.11e standards.
The ADQ35 is a high-performance digitizer that features dual-channel capabilities, providing a 12-bit resolution at an impressive 10 GSPS sampling rate. It is designed to meet demanding requirements for data acquisition, capable of streaming data at a throughput of 14 Gbyte/s. Equipped with up to a 3 GHz input bandwidth, it ensures precise signal capture and processing, making it ideal for a range of complex applications. This digitizer is optimized for scenarios requiring rapid data transfer and high fidelity in digital signal processing. Additionally, the ADQ35's architecture supports both single and dual-channel operations, adding versatility and adaptability in various operational setups. Its robust design supports pulse detection optimization, enhancing its effective resolution to an equivalent of 16-bit ENOB, thus delivering better signal integrity and improved measurement accuracy. Predominantly used in high-fidelity applications, it represents the pinnacle of Teledyne SP Devices’ dedication to precision engineering. The ADQ35 is also portable, providing an efficient solution for dynamic field operations while maintaining uncompromised data acquisition performance. This adaptability makes it a preferred choice for environments that require quick deployment and reliable results. Its integration within a system is facilitated by user-friendly software, enhancing usability while maintaining top-tier performance metrics.
The RWM6050 is a power-efficient baseband modem designed for high-capacity mmWave communication, ideal for market segments that require cost-effective and high-performance solutions. Developed in partnership with Renesas, this modem pairs seamlessly with mmWave RF chipsets to provide a highly configurable radio interface suitable for access and backhaul applications. Equipped with flexible channelisation and modulation coding capabilities, the RWM6050 can scale bandwidth to support multi-gigabit data transfers, boasting dual modem features and a mixed-signal front-end. This flexible architecture supports versatile deployment scenarios, enabling robust and high-speed connectivity over moderate distances. The RWM6050’s beamforming capabilities, enhanced by a phased array antenna, and advanced digital front-end processing, make it ideal for sophisticated data links. The modem integrates network synchronization and provides programmable real-time scheduling, affirming its role as a pivotal element in delivering reliable mmWave communication.
The transceiver is designed to be used together with an RF tuner, and ADC/DAC converters. The system has internal state machine to control the operation, and can be externally configured via the SPI interface. This design is a Mobile WiMAX baseband transceiver core for both Base station and Mobile station, supplied as a portable and synthesizable Verilog-2001 IP. The system was designed to be used in conjunction with a standard RF tuner. The operation of the transceiver is automated by a master finite state machine.
The MVUM1000 represents MEMS Vision's leading-edge innovation in ultrasound technology for medical imaging. This compact 256-element linear ultrasound array is designed using state-of-the-art capacitive micromachined ultrasound transducers (CMUTs), allowing for exceptional integration with interface electronics. Known for its energy efficiency and high sensitivity, the MVUM1000 delivers precise acoustic pressure detection, crucial for advanced imaging techniques. Supporting multiple imaging modes such as time-of-flight and Doppler, it is highly suited for applications ranging from point-of-care to cart-based ultrasound systems. The MVUM1000 array, with its 4.5 MHz center frequency and up to 256 elements, strikes a balance between fine resolution and powerful imaging capabilities, critical for medical diagnostics. The array's flexible design includes features like integrated front-end electronics and adjustable voltage inputs, enhancing its versatility in various contexts. Such capabilities not only improve imaging clarity but also support quick deployment in medical devices, further solidifying MEMS Vision's role in medical sensor innovation.
Under its eSi-Comms brand, EnSilica delivers a suite of highly parameterized communications IP solutions that play a crucial role in supporting modern communication standards such as 4G, 5G, Wi-Fi, and DVB. These IP blocks are designed to streamline the development of ASIC designs by providing a robust platform for OFDM-based modem solutions. The IP suite features advanced DSP algorithms for synchronization, equalization, demodulation, and channel decoding, ensuring robust communication links. It's optimized for integration into systems requiring flexibility and high performance.
Moonstone Laser Sources by Lightelligence provide cutting-edge photonic solutions aimed at facilitating advanced optical computing applications. These laser sources are tailored for high precision and efficiency, essential for tasks demanding robust photonic performance. The unique attributes of Moonstone make it suitable for integration into diverse technological frameworks where precision and reliability are paramount. As the backbone of optical computing, laser sources like Moonstone ensure that photonic applications achieve desired speed and accuracy, fostering greater innovation in photonics-driven technologies. With their focus on precision and application flexibility, Moonstone Laser Sources empower industries to explore new frontiers in photonics, supporting the evolution of next-generation computing technologies.
AccelerComm's Software-Defined High PHY is a malleable solution, catered to the ARM processor framework, capable of fulfilling the diverse requirements of modern telecommunications infrastructures. This technology is renowned for its optimization capabilities, functioning either with or without hardware acceleration, contingent on the exigencies of the target application with regards to power and capacity. The implementation of Software-Defined High PHY signifies a leap in configuring PHY layers, facilitating adaptation to varying performance and efficiency mandates of different hardware platforms. The technology supports seamless transitions across platforms, making it applicable for a spectrum of use cases, harmonizing with both flexible software protocols and established hardware standards. By uniting traditional hardware PHY layers with modern software innovations, this solution propels network performance while reducing latency, enhancing data throughput, and minimizing overall system power consumption. This adaptability is vital for enterprises aiming to meet the dynamic demands for quality and reliability in wireless communication network setups.
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