All IPs > Wireless Communication
The Wireless Communication category at Silicon Hub encompasses a diverse array of semiconductor IPs designed to facilitate seamless wireless connectivity in today's rapidly evolving technological landscape. As the demand for higher data rates and uninterrupted connectivity grows, these IPs play a vital role in enabling devices to communicate efficiently across various protocols and standards. This category includes highly specialized IPs that support the implementation and enhancement of wireless communication technologies in a variety of applications ranging from consumer electronics to industrial systems.
Within this category, semiconductor IPs cover a wide spectrum of wireless standards and protocols. This includes evolving mobile communication standards like 3GPP-5G and LTE, which are essential for cellular networks' operation and are pivotal in the deployment of the latest 5G networks. For localized wireless communication, standards such as 802.11 (commonly referred to as Wi-Fi), Bluetooth, NFC, and Wireless USB are covered, facilitating device interconnectivity and data exchange in numerous consumer electronics, IoT devices, and more. Industrial and professional applications may utilize IPs related to standards like WiMAX (802.16), CPRI, OBSAI, which are crucial for network infrastructure and robust communication systems.
In addition to these, the Wireless Communication category includes IPs for satellite navigation systems like GPS, ensuring accurate geolocation services essential for navigation devices in both personal and commercial use. Standards like UWB (Ultra-Wideband) offer high-speed data transmission over short ranges, beneficial for applications demanding rapid short-range communication. Furthermore, for high-definition broadcasting, IPs supporting Digital Video Broadcast standards offer necessary capabilities to meet market demands for clear and reliable video content transmission.
This extensive category of semiconductor IPs under Wireless Communication not only provides the architectural needs for state-of-the-art communication devices but also accommodates future technological advancements. By integrating these IPs, semiconductor product designers and engineers can efficiently develop solutions tailored for enhanced connectivity, ensuring their products remain at the forefront of technological innovation and meet the ever-growing expectations of modern consumers for instant and reliable wireless communication. Whether you are developing next-gen smartphones, IoT solutions, or advanced networking systems, these IPs are critical components in achieving superior performance and connectivity.
Akida's Neural Processor IP represents a leap in AI architecture design, tailored to provide exceptional energy efficiency and processing speed for an array of edge computing tasks. At its core, the processor mimics the synaptic activity of the human brain, efficiently executing tasks that demand high-speed computation and minimal power usage. This processor is equipped with configurable neural nodes capable of supporting innovative AI frameworks such as convolutional and fully-connected neural network processes. Each node accommodates a range of MAC operations, enhancing scalability from basic to complex deployment requirements. This scalability enables the development of lightweight AI solutions suited for consumer electronics as well as robust systems for industrial use. Onboard features like event-based processing and low-latency data communication significantly decrease the strain on host processors, enabling faster and more autonomous system responses. Akida's versatile functionality and ability to learn on the fly make it a cornerstone for next-generation technology solutions that aim to blend cognitive computing with practical, real-world applications.
The second-generation Akida platform builds upon the foundation of its predecessor with enhanced computational capabilities and increased flexibility for a broader range of AI and machine learning applications. This version supports 8-bit weights and activations in addition to the flexible 4- and 1-bit operations, making it a versatile solution for high-performance AI tasks. Akida 2 introduces support for programmable activation functions and skip connections, further enhancing the efficiency of neural network operations. These capabilities are particularly advantageous for implementing sophisticated machine learning models that require complex, interconnected processing layers. The platform also features support for Spatio-Temporal and Temporal Event-Based Neural Networks, advancing its application in real-time, on-device AI scenarios. Built as a silicon-proven, fully digital neuromorphic solution, Akida 2 is designed to integrate seamlessly with various microcontrollers and application processors. Its highly configurable architecture offers post-silicon flexibility, making it an ideal choice for developers looking to tailor AI processing to specific application needs. Whether for low-latency video processing, real-time sensor data analysis, or interactive voice recognition, Akida 2 provides a robust platform for next-generation AI developments.
**Ceva-Waves Links** is a growing family of multi-standard wireless platforms. By optimizing connectivity support for various combinations of **Wi-Fi, Bluetooth, 802.15.4, and ultra-wideband (UWB)**, the Ceva-Waves Links family provides preconfigured, optimized solutions for SoCs requiring multiple connectivity standards. All Ceva-Waves Links configurations are based on field-proven Ceva-Waves hardware IP and software stacks. Unique Ceva coexistence algorithms ensure efficient and interference-free operation of multiple connections while sharing one radio. The **Ceva-Waves Links family** offers combinations of Ceva-Waves Wi-Fi, Ceva-Waves Bluetooth, 802.15.4 (supporting protocols such as Thread, Matter and Zigbee), and Ceva-Waves UWB hardware IP, integrated with Ceva or third-party radios and CPU- and OS-agnostic software stacks. New platforms will be introduced to address market trends or customers’ demands. [**Learn more about Ceva-Waves Links family solution>**](https://www.ceva-ip.com/product/ceva-waves-links/?utm_source=silicon_hub&utm_medium=ip_listing&utm_campaign=ceva_waves_links_page)
**Ceva-XC21** is the most efficient vector DSP core available today for communications applications. The Ceva-XC21 DSP is designed for low-power, cost- and size-optimized cellular IoT modems, NTN VSAT terminals, eMBB and uRLLC applications. Ceva-XC21 offers scalable architecture and dual thread design with support for AI, addressing growing demand for smarter, yet more cost and power efficient cellular devices. Targeted for 5G and 5G-Advanced workloads, the Ceva-XC21 has multiple products configurations enabling system designers to optimize the size and cost to their specific application needs. The Ceva-XC21, based on the advanced Ceva-XC20 architecture, features a product line of 3 vector DSP cores. Each of the cores offers a unique performance & area configuration with a SW compatibility between them. The different cores span across single thread or dual thread configurations, and 32 or 64 16bits x 16bits MACs. The Ceva-XC212, the highest performing variant of the Ceva-XC21 delivers up to 1.8x times the performance of Ceva’s previous-generation Ceva-XC4500 architecture, while reducing the core area. Ceva-XC210, the smallest configuration of the Ceva-XC21, enables system designers to reduce the core die size in 48% compared with the previous generation. Ceva-XC211 offers the same performance envelope compared with the previous generation at 63% of the area. [**Learn more about Ceva-XC21>**](https://www.ceva-ip.com/product/ceva-xc21/?utm_source=silicon_hub&utm_medium=ip_listing&utm_campaign=ceva_xc21_page)
The **Ceva-Waves Bluetooth platform** includes field-proven hardware IP for baseband controller, modem, and 2.4 GHz RF transceiver functions, and allows use of many third-party radio IPs as well. The platform includes optimized baseband controller hardware and software, and above the Host Controller Interface (HCI) a host-agnostic software protocol stack supporting all major Bluetooth profiles. The built-in 802.15.4 add-on suite shares the same Bluetooth radio, and includes IEEE 802.15.4 MAC & modem hardware IP and software, and is compatible with Zigbee, Thread and Matter host protocol stacks. The Ceva-Waves Bluetooth platform is also available as part of the **Ceva-Waves Links family** of multi-protocol turnkey platforms, including with optimized Wi-Fi & Bluetooth co-existence interface and packet traffic arbiter. The Ceva-Waves Bluetooth platforms also comprises a state-of-the-art radio in TSMC 12nm FFC+ supporting all the latest Bluetooth 6.0 dual mode features, along with next gen Bluetooth High Data Throughput and IEEE 802.15.4. Its innovative architecture provides best in class performance in term of power consumption, die size, sensitivity and output power. [**Learn more about Ceva's Bluetooth solution>**](https://www.ceva-ip.com/product/ceva-waves-bluetooth/?utm_source=silicon_hub&utm_medium=ip_listing&utm_campaign=ceva_waves_bluetooth_page)
**Ceva-Waves UWB platform** cuts the development time and risk for implementing a wide range of UWB functionality in SoCs. It provides optimized MAC and PHY hardware IP and supporting software for secure and accurate ranging, and Doppler Radar presence detection applications. It can be implemented in an SoC independently or in conjunction with the Ceva-Waves Bluetooth platform, as well as part of the Ceva-Waves Links family of multiprotocol platforms. The Ceva-Waves UWB platform includes hardware IP for an optimized UWB MAC and PHY meeting 802.15.4 HRP, FiRa 3.0, and the Car Connectivity Consortium Digital Key 3.0 (CCC DK3.0) requirements. The platform includes advanced Wi-Fi interference suppression. A comprehensive suite of CPU-agnostic software stacks that support FiRa 3.0 MAC, CCC DK3.0 MAC, and radar for implementing applications such as automotive digital keys and in-cabin child-presence detection (CPD), general power-saving presence detection in laptops, TVs and smart buildings, asset tracking tags, real-time location services (RTLS), and tap-free payment. [**Learn more about our UWB soluion>**](https://www.ceva-ip.com/product/ceva-waves-uwb/?utm_source=silicon_hub&utm_medium=ip_listing&utm_campaign=ceva_waves_uwb_page)
The Low Density Parity Check (LDPC) codes are powerful, capacity approaching channel codes and have exceptional error correction capabilities. The high degree of parallelism that they offer enables efficient, high throughput hardware architectures. The ntLDPC_WiFi6 IP Core is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes and is fully compliant with IEEE 802.11 n/ac/ax standard. The Quasi-Cyclic LDPC codes are based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that they offer high throughput at low implementation complexity. The ntLDPC_WiFi6 decoder IP Core may optionally implement one of two approximations of the log-domain LDPC iterative decoding algorithm (Belief propagation) known as either Layered Normalized Offset Min-Sum Algorithm or Layered Lambda-min Algorithm. Selecting between the two algorithms presents a decoding performance .vs. system resources utilization trade-off. The core is highly reconfigurable and fully compliant to the IEEE 802.11 n/ac/ax Wi-Fi4, Wi-Fi5 and Wi-Fi 6 standards. The ntLDPC_WiFi6 encoder IP implements a 81-bit parallel systematic LDPC encoder. An off-line profiling Matlab script processes the original matrices and produces a set of constants that are associated with the matrix and hardcoded in the RTL encoder.
Quadric's Chimera GPNPU is an adaptable processor core designed to respond efficiently to the demand for AI-driven computations across multiple application domains. Offering up to 864 TOPS, this licensable core seamlessly integrates into system-on-chip designs needing robust inference performance. By maintaining compatibility with all forms of AI models, including cutting-edge large language models and vision transformers, it ensures long-term viability and adaptability to emerging AI methodologies. Unlike conventional architectures, the Chimera GPNPU excels by permitting complete workload management within a singular execution environment, which is vital in avoiding the cumbersome and resource-intensive partitioning of tasks seen in heterogeneous processor setups. By facilitating a unified execution of matrix, vector, and control code, the Chimera platform elevates software development ease, and substantially improves code maintainability and debugging processes. In addition to high adaptability, the Chimera GPNPU capitalizes on Quadric's proprietary Compiler infrastructure, which allows developers to transition rapidly from model conception to execution. It transforms AI workflows by optimizing memory utilization and minimizing power expenditure through smart data storage strategies. As AI models grow increasingly complex, the Chimera GPNPU stands out for its foresight and capability to unify AI and DSP tasks under one adaptable and programmable platform.
**Ceva-PentaG2** is a complete IP platform for implementing a wide range of user-equipment and IoT cellular modems. The platform includes a variety of DSPs, modem hardware modules, software libraries, and simulation tools. Capabilities of the Ceva-PentaG2 include New Radio (NR) physical layer design ranging across all 3GPP profiles from RedCap IoT and mMTC, through eMBB up to ultra-reliable low-latency communications (URLLC). The platform has two base configurations. Ceva-PentaG2 Max emphasizes performance and scalability for enhanced mobile broadband (eMBB) and future proofing design for next generation 5G-Advanced releases. Ceva-PentaG2 Lite emphasizes extreme energy and area efficiency for lower-throughput applications such as LTE Cat 1, RedCap, and optimized cellular IoT applications. The PentaG2 platform comprises a set of Ceva DSP cores, optimized fixed-function hardware accelerators, and proven, optimized software modules. By using this platform, designers can implement optimized, hardware-accelerated processing chains for all main modem functions. In the selection process, designers can tune their design for any point across a huge space of area, power consumption, latency, throughput, and channel counts. Solutions can fit applications ranging from powerful eMBB for mobile and Fixed Wireless Access (FWA) devices to connected vehicles, cellular IoT modules, and even smart watches. System-C models in Ceva’s Virtual Platform Simulator (VPS) aid architectural exploration and system tuning, while an FPGA-based emulation kit speeds SoC integration. [**Learn more about Ceva-PentaG2 solution>**](https://www.ceva-ip.com/product/ceva-pentag2/?utm_source=silicon_hub&utm_medium=ip_listing&utm_campaign=ceva_pentag2_page)
**Ceva-Waves Dragonfly platform** is a turnkey platform with optimized, low-power hardware IP and protocol software for implementing narrow-band IoT (NB-IoT) cellular modem SoCs. Extensions provide support for GNSS such as GPS and BeiDou and for sensor-fusion applications. The Ceva-Waves Dragonfly platform comprises hardware IP with an enhanced Ceva-BX1 processor, specific hardware accelerators, and SoC infrastructure IP. Software includes NB-IoT protocol stack for L1 through L3 functions including encryption and software PHY, a task-optimized RTOS, and optional GNSS receiver and control software, all executing on the Ceva-BX1. Pre-certified for 3GPP Release 15 CAT NB2, the solution is tuned for small footprint and extremely low power, yet has headroom for additional software-defined functions, such as sensor fusion. [**Learn more about Ceva-Waves Dragonfly>**](https://www.ceva-ip.com/product/ceva-waves-dragonfly/?utm_source=silicon_hub&utm_medium=ip_listing&utm_campaign=ceva_waves_dragonfly_page)
The ARINC 818 Product Suite is a comprehensive solution designed for professionals working with advanced avionics systems. It provides a robust framework for implementing, testing, and simulating ARINC 818 systems. The product suite includes a variety of tools and resources tailored for the lifecycle of ARINC 818 systems, ensuring that clients can develop mission-critical systems with confidence. With a primary focus on performance and scalability, the ARINC 818 Product Suite is developed to cater to complex requirements and to seamlessly integrate within existing technology stacks. Users benefit from its extensive compatibility and the ability to manage high-speed data effectively, making it a vital asset for those working in aviation and defense sectors.
The EW6181 GPS and GNSS Silicon is an advanced semiconductor solution specifically engineered for high-efficiency, low-power applications. This digital GNSS silicon offers a compact design with a footprint of approximately 0.05mm2, particularly when applied in 5nm semiconductor technology. Designed for seamless integration, the EW6181 combines innovative DSP algorithms and multi-node licensing flexibility, enhancing the overall device performance in terms of power conservation and reliability. Featuring a robust architecture, the EW6181 integrates meticulously calibrated components all aimed at reducing the bill of materials (BoM) while ensuring extended battery life for devices such as tracking tags and modules. This strategic component minimization directly translates to more efficient power usage, addressing the needs of power-sensitive applications across various sectors. Capable of supporting high-reliability location tracking, the EW6181 comes supplemented with stable firmware, ensuring dependable performance and future upgrade paths. Its adaptable IP core can be licensed in RTL, gate-level netlist, or GDS forms, adaptable to a wide range of technology nodes, assuming the availability of the RF frontend capabilities.
Convolutional FEC codes are very popular because of their powerful error correction capability and are especially suited for correcting random errors. The most effective decoding method for these codes is the soft decision Viterbi algorithm. ntVIT core is a high performance, fully configurable convolutional FEC core, comprised of a 1/N convolutional encoder, a variable code rate puncturer/depuncturer and a soft input Viterbi decoder. Depending on the application, the core can be configured for specific code parameters requirements. The highly configurable architecture makes it ideal for a wide range of applications. The convolutional encoder maps 1 input bit to N encoded bits, to generate a rate 1/N encoded bitstream. A puncturer can be optionally used to derive higher code rates from the 1/N mother code rate. On the encoder side, the puncturer deletes certain number of bits in the encoded data stream according to a user defined puncturing pattern which indicates the deleting bit positions. On the decoder side, the depuncturer inserts a-priori-known data at the positions and flags to the Viterbi decoder these bits positions as erasures. The Viterbi decoder uses a maximum-likelihood detection recursive process to cor-rect errors in the data stream. The Viterbi input data stream can be composed of hard or soft bits. Soft decision achieves a 2 to 3dB in-crease in coding gain over hard-decision decoding. Data can be received continuously or with gaps.
ntLDPC_SDAOCT IP implements a 5G-NR Base Graph 1 systematic Encoder/Decoder based on Quasi-Cyclic LDPC Codes (QC-LDPC), with lifting size Zc=384 and Information Block Size 8448 bits. The implementation is based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that it offers high throughput at low implementation complexity. The ntLDPCE_SDAOCT Encoder IP implements a systematic LDPC Zc=384 encoder. Input and Output may be selected to be 32-bit or 128-bits per clock cycle prior to synthesis, while internal operations are 384-bits parallel per clock cycle. Depending on code rate, the respective amount of parity bits are generated and the first 2xZc=768 payload bits are discarded. There are 5 code rate modes of operation available (8448,8448)-bypass, (9984,8448)-0.8462, (11136,8448)-0.7586, (12672,8448)-0.6667 and (16896,8448)-0.5. The ntLDPCD_SDAOCT Base Graph Decoder IP may optionally implement one of two approximations of the log-domain LDPC iterative decoding algorithm (Belief propagation) known as either Layered Min-Sum Algorithm (MS) or Layered Lambda-min Algorithm (LMIN). Variations of Layered MS available are Offset Min-Sum (OMS), Normalized Min-Sum (NMS), and Normalized Offset Min-Sum (NOMS). Selecting between these algorithms presents a decoding performance vs. system resources utilization trade-off. The ntLDPCD_SDAOCT decoder IP implements a Zc=384 parallel systematic LDPC layered decoder. Each layer corresponds to Zc=384 expanded rows of the original LDPC matrix. Each layer element corresponds to the active ZcxZc shifted identity submatrices within the layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit, in order to update the layers LLR estimates and extrinsic information iteratively until the required number of decoding iterations has been run. The decoder IP also features a powerful optional early termination (ET) criterion, to maintain practically equivalent error correction performance, while significantly increasing its throughput rate and/or reducing hardware cost. Additionally it reports how many decoding iterations have been performed when ET is activated, for system performance observation and calibration purposes. Finally a simple, yet robust, flow control handshaking mechanism is included in both IPs, which is used to communicate the IPs availability to adjacent system components. This logic is easily portable into any communication protocol, like AXI4 stream IF.
aiSim 5 is at the forefront of automotive simulation, providing a comprehensive environment for the validation and verification of ADAS and AD systems. This innovative simulator integrates AI and physics-based digital twin technology, creating an adaptable and realistic testing ground that accommodates diverse and challenging environmental scenarios. It leverages advanced sensor simulation capabilities to reproduce high fidelity data critical for testing and development. The simulator's architecture is designed for modularity, allowing seamless integration with existing systems through C++ and Python APIs. This facilitates a wide range of testing scenarios while ensuring compliance with ISO 26262 ASIL-D standards, which is a critical requirement for automotive industry trust. aiSim 5 offers developers significant improvements in testing efficiency, allowing for runtime performance adjustments with deterministic outcomes. Some key features of aiSim 5 include the ability to simulate varied weather conditions with real-time adaptable environments, a substantial library of 3D assets, and built-in domain randomization features through aiFab for synthetic data generation. Additionally, its innovative rendering engine, aiSim AIR, enhances simulation realism while optimizing computational resources. This tool serves as an ideal solution for companies looking to push the boundaries of ADAS and AD testing and deployment.
**Ceva-Waves Wi-Fi platforms portfolio** provide a comprehensive selection of hardware IP and CPU-agnostic host software for energy-efficient SoC implementation of any of a wide range of Wi-Fi subsystems, from Wi-Fi 4 to Wi-Fi 7, for both client devices and access points. The portfolio includes a suite of pre-optimized solutions for various generations and configurations for specific Wi-Fi uses, power consumption levels, and price points, ranging from low-bandwidth IoT connectivity to high-bandwidth hubs. Embedded into one of the Ceva-Waves Links multi-protocol wireless platforms, the Ceva-Waves Wi-Fi IPs can efficiently co-exist with the Ceva-Waves Bluetooth IPs and/or Ceva-Waves UWB IP. The Ceva-Waves Wi-Fi platforms comprise hardware modem PHY IP that supports DSSS, CCK, OFDM and OFDMA modulations; optimized MAC IP that offloads MAC functions from the CPU; and a comprehensive selection of MAC protocol software stacks. The IP and software elements are further organized into three main solution profiles. * Wi-Fi IoT is for energy-efficient low-bandwidth connectivity for IoT devices, supporting 2.4GHz single band or dual/triple bands on 2.4/5/6 GHz for IEEE 802.11n, ax, or be (Wi-Fi 4, 6 or 7). * Wi-Fi High-Performance supports up to 160 MHz bands at 2.4, 5, or 6 GHz in either single-antenna or 2×2 MIMO mode for IEEE 802.11ax or be (Wi-Fi 6 or 7), and is intended for consumer media-streaming applications. * Wi-Fi Access Point supports 160 MHz bands and 2×2 MIMO for IEEE 802.11ax or be (Wi-Fi 6/6E/7), for applications such as media access points, gateways, and small-cell offload that must support up to hundreds of clients. The Ceva-Waves Wi-Fi platforms include a coexistence interface that permits highly efficient operation with the Ceva-Waves Bluetooth platforms. [**Learn more about Ceva-Waves Wi-Fi solution>**](https://www.ceva-ip.com/product/ceva-waves-wi-fi/?utm_source=silicon_hub&utm_medium=ip_listing&utm_campaign=ceva_waves_wifi_page)
Digital Predistortion (DPD) is a sophisticated technology crafted to optimize the power efficiency of RF power amplifiers. The flagship product, FlexDPD, presents a complete, adaptable sub-system that can be customized to any ASIC or FPGA/SoC platform. Thanks to its scalability, it is compatible with various device vendors. Designed for high performance, this DPD solution significantly boosts RF efficiencies by counteracting signal distortion, ensuring clear and effective transmission. The core of the DPD solution lies in its adaptability to a broad range of systems including 5G, multi-carrier platforms, and O-RAN frameworks. It's built to handle transmission bandwidths exceeding 1 GHz, making it a versatile and future-proof technology. This capability not only enhances system robustness but also offers a seamless integration pathway for next-generation communication standards. Additionally, Systems4Silicon’s DPD solution is field-tested, ensuring reliability in real-world applications. The solution is particularly beneficial for projects that demand high signal integrity and efficiency, providing a tangible advantage in competitive markets. Its compatibility with both ASIC and FPGA implementations offers flexibility and choice to partners, significantly reducing development time and cost.
The HOTLink II Product Suite is designed to facilitate high-speed connectivity and data transfer in demanding environments. This suite of products offers robust solutions for those needing reliable and fast data links, catering to industries where performance and precision are crucial. As part of Great River Technology's offerings, HOTLink II stands out by providing comprehensive support throughout product lifecycles and ensuring compatibility with various systems. With HOTLink II, users can expect exceptional levels of performance and reliability thanks to its advanced design, which is geared towards meeting the rigorous demands of aerospace and defense applications. Whether implementing new systems or upgrading existing infrastructures, the HOTLink II Product Suite provides the versatility and capability needed to meet diverse clients' needs. The suite is particularly beneficial for engineers requiring high-performance link solutions that integrate seamlessly within larger systems, enhancing operational effectiveness and efficiency. It includes all the necessary tools to ensure a smooth deployment process while minimizing potential downtime associated with new technology integration.
The Digital Radio (GDR) from GIRD Systems is an advanced software-defined radio (SDR) platform that offers extensive flexibility and adaptability. It is characterized by its multi-channel capabilities and high-speed signal processing resources, allowing it to meet a diverse range of system requirements. Built on a core single board module, this radio can be configured for both embedded and standalone operations, supporting a wide frequency range. The GDR can operate with either one or two independent transceivers, with options for full or half duplex configurations. It supports single channel setups as well as multiple-input multiple-output (MIMO) configurations, providing significant adaptability in communication scenarios. This flexibility makes it an ideal choice for systems that require rapid reconfiguration or scalability. Known for its robust construction, the GDR is designed to address challenging signal processing needs in congested environments, making it suitable for a variety of applications. Whether used in defense, communications, or electronic warfare, the GDR's ability to seamlessly switch configurations ensures it meets the evolving demands of modern communications technology.
The ntLDPC_5GNR Base Graph Encoder IP Core is defined in 3GPP TS 38.212 standard document and it is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes. The specification defines two sets of LDPC Base Graphs and their respective derived Parity Check Matrices. Each Base Graph can be combined with 8 sets of lifting sizes (Zc) in a total of 51 different lifting sizes. This way by using the 2 Base Graphs, the 5G NR specification defines up to 102 possible distinct LDPC modes of operation to select from, for optimum decoding performance, depending on target application code block size and code rate (using the additional rate matching module features). For Base Graph 1 we have LDPC(N=66xZc,K=22xZc) sized code blocks, while for Base Graph 2 we have LDPC(N=50xZc,K=[6,8,9,10]xZc) sized code blocks. The ntLDPCE_5GNR Encoder IP implements a multi-parallel systematic LDPC encoder. Parallelism depends on the selected lifting sizes subsets chosen for implementation. Shortened blocks are supported with granularity at lifting size Zc-bit boundaries. Customizable modes generation is also supported beyond the scope of the 5G-NR specification with features such as: “flat parity bits puncturing instead of Rate Matching Bit Selection”, “maintaining the first 2xZc payload bits instead of eliminating it before transmission”, etc. The ntLDPCD_5GNR decoder IP implements a maximum lifting size of Zc_MAX-bit parallel systematic LDPC layered decoder. Each layer corresponds to Zc_MAX expanded rows of the original LDPC matrix. Each layer element corresponds to the active ZcxZc shifted identity sub-matrices within the layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit, in order to update the layers LLR estimates and extrinsic information iteratively until the required number of decoding iterations has been run. The decoder IP also features a powerful optional early termination (ET) criterion, to maintain practically equivalent error correction performance, while significantly increasing its throughput rate and/or reducing hardware cost. Additionally it reports how many decoding iterations have been performed when ET is activated, for system performance observation and calibration purposes. Finally a simple, yet robust, flow control handshaking mechanism is included in both IPs, which is used to communicate the IPs availability to adjacent system components. This logic is easily portable into any communication protocol, like AXI4 stream IF.
The CANmodule-III is a sophisticated full CAN controller designed to handle communication on the CAN bus with outstanding efficiency. Built upon Bosch's fundamental CAN architecture, this module is fully CAN 2.0B compliant, facilitating seamless communication transactions across the network. It is optimized for system-on-chip integrations, providing customizable options to cater to specific application requirements. The module stands out with its inherited functions which ensure uninterrupted main core operations, even when additional functionalities are layered around it. Having been deployed in various applications from aerospace to industrial control, the CANmodule-III's proven reliability makes it a preferred choice for developers seeking robust communication solutions in FPGA and ASIC technologies.
Ncore Cache Coherent Interconnect is designed to tackle the multifaceted challenges in multicore SoC systems by introducing heterogeneous coherence and efficient cache management. This NoC IP optimizes performance by ensuring high throughput and reliable data transmission across multiple cores, making it indispensable for sophisticated computing tasks. Leveraging advanced cache coherency, Ncore maintains data integrity, crucial for maintaining system stability and efficiency in operations involving heavy computational loads. With its ISO26262 support, it caters to automotive and industrial applications requiring high reliability and safety standards. This interconnect technology pairs well with diverse processor architectures and supports an array of protocols, providing seamless integration into existing systems. It enables a coherent and connected multicore environment, enhancing the performance of high-stakes applications across various industry verticals, from automotive to advanced computing environments.
This mmWave PLL is engineered to deliver exceptional performance in high-frequency applications, such as mmWave communications and advanced radar systems. The IP offers remarkable frequency synthesis capabilities, essential for the operation of modern communication networks and sensors, including the growing 5G infrastructure and automotive radar technologies. The design incorporates mechanisms to optimize phase noise and enhance frequency stability, which are critical in minimizing signal distortion in high-bandwidth transmissions. This PLL is compact yet powerful, making it an excellent choice for systems where space and performance are at a premium. Suitable for integration into a variety of RF and mmWave architectures, the mmWave PLL supports applications across telecommunications, automotive, and beyond. It helps designers achieve superior system performance while maintaining low latency and high data throughput.
The GNSS ICs AST 500 and AST GNSS-RF are crafted by Accord Software & Systems as part of their extensive lineup of GNSS-centric products. These ICs are pivotal for applications requiring precision navigation, especially where stringent environmental and operational parameters are paramount. Built for robustness and accuracy, these ICs thrive under challenging conditions, providing users with reliable GPS and GNSS solutions. The AST 500 and AST GNSS-RF are tailored for seamless integration into complex systems, ensuring they meet the high demands of precision and performance. They offer enhanced capabilities for both time-sensitive and location-critical applications across various sectors, including aerospace, defense, and commercial industries. These integrated circuits leverage Accord's cutting-edge technology to maintain precise positioning and timing, which is essential for applications demanding unfailing synchronization and navigation. These ICs support various navigation systems and are designed to accommodate multiple constellation signals, including GPS, GLONASS, and more. Their comprehensive design encompasses complete GNSS functionality, which includes signal acquisition, tracking, and data output, ensuring continuous performance even in environments with high interference or dynamics. Providing both user-friendly integration and exceptional performance, these ICs form the backbone for Accord's reliable GNSS modules. In addition to interoperability across a range of navigation systems, the ICs are optimized for low-power consumption, making them suitable for portable and power-sensitive applications. This energy efficiency, coupled with advanced signal processing capabilities, ensures that the AST 500 and AST GNSS-RF remain at the forefront of GNSS technology.
The TW330 distortion correction IP is tailored for use in applications requiring dynamic image transformations, such as VR headsets and automotive HUDs. Utilizing GPU-powered technologies, it offers real-time coordinate transformations, distortion corrections, and other modifications up to a resolution of 16K x 16K in both RGB and YUV formats. This IP is crucial for enhancing visual accuracy and display adaptability across varied markets.
The Polar ID Biometric Security System offers an advanced, secure face unlock capability for smartphones, utilizing groundbreaking meta-optics technology to capture the full polarization state of light. Unlike traditional biometric systems, Polar ID distinguishes the unique polarization signature of human facial features, which adds an additional security layer by detecting the presence of non-human elements like sophisticated 3D masks. This system eliminates the need for multiple complex optical modules, thus simplifying smartphone design while enhancing security. Designed to fit the most compact form factors, Polar ID uses a near-infrared polarization camera at 940nm paired with active illumination. This configuration ensures functionality across various lighting conditions, from bright outdoor environments to complete darkness, and operates effectively even when users wear sunglasses or face masks. Smartphone OEMs can integrate this secure and cost-effective solution onto a wide range of devices, surpassing traditional fingerprint sensors in reliability. Polar ID not only offers a higher resolution than existing solutions but does so at a reduced cost compared to structured light setups, democratizing access to secure biometric authentication across consumer devices. The system's efficiency and compactness are achieved through Metalenz's meta-optic innovations, offering consistent performance regardless of external impediments such as lighting changes.
Designed for seamless integration, High PHY Accelerators from AccelerComm encapsulate top-tier signal processing blocks critical for 5G solutions. Available as FPGA and ASIC ready IP cores, they are tailored for rapid deployment with minimal risk. These accelerators are supported by accurate simulation models and designed to use standardized interfaces for integration. Notably, they also provide support for space-hardened platforms, ensuring robust performance in diverse settings.
D2D® Technology, developed by ParkerVision, is a revolutionary approach to RF conversion that transforms how wireless communication operates. This technology eliminates traditional intermediary stages, directly converting RF signals to digital data. The result is a more streamlined and efficient communication process that reduces complexity and power consumption. By bypassing conventional analog-to-digital conversion steps, D2D® achieves higher data accuracy and reliability. Its direct conversion approach not only enhances data processing speeds but also minimizes energy usage, making it an ideal solution for modern wireless devices that demand both performance and efficiency. ParkerVision's D2D® technology continues to influence a broad spectrum of wireless applications. From improving the connectivity in smartphones and wearable devices to optimizing signal processing in telecommunication networks, D2D® is a cornerstone of ParkerVision's technological offerings, illustrating their commitment to advancing communication technology through innovative RF solutions.
AccelerComm’s LDPC solutions cater specifically to the 5G standards, offering high efficiency and leading performance in channel coding. The IP suite includes comprehensive encoder and decoder capabilities that enhance hardware efficiency for this critical component of the PHY layer. This facilitates a marked improvement in throughput and error reduction, aligning with 3GPP standards. Born from academic excellence at Southampton University, they incorporate cutting-edge algorithms for signal performance, achieving substantial decoder performance enhancement and minimizing error floors.
The RISCV SoC developed by Dyumnin Semiconductors is engineered with a 64-bit quad-core server-class RISCV CPU, aiming to bridge various application needs with an integrated, holistic system design. Each subsystem of this SoC, from AI/ML capabilities to automotive and multimedia functionalities, is constructed to deliver optimal performance and streamlined operations. Designed as a reference model, this SoC enables quick adaptation and deployment, significantly reducing the time-to-market for clients. The AI Accelerator subsystem enhances AI operations with its collaboration of a custom central processing unit, intertwined with a specialized tensor flow unit. In the multimedia domain, the SoC boasts integration capabilities for HDMI, Display Port, MIPI, and other advanced graphic and audio technologies, ensuring versatile application across various multimedia requirements. Memory handling is another strength of this SoC, with support for protocols ranging from DDR and MMC to more advanced interfaces like ONFI and SD/SDIO, ensuring seamless connectivity with a wide array of memory modules. Moreover, the communication subsystem encompasses a broad spectrum of connectivity protocols, including PCIe, Ethernet, USB, and SPI, crafting an all-rounded solution for modern communication challenges. The automotive subsystem, offering CAN and CAN-FD protocols, further extends its utility into automotive connectivity.
The LightningBlu solution from Blu Wireless is a premier mmWave technology specifically designed to cater to the rigorous demands of high-speed rail connectivity. It provides multi-gigabit, continuous communication solutions between tracksides and trains. This connectivity ensures reliable on-board services such as internet access, entertainment, and passenger information systems. The versatile solution is engineered to perform seamlessly even at speeds greater than 300 km/h, enhancing the passenger experience by delivering consistent, high-speed internet and data services. Built to leverage the 57-71 GHz mmWave spectrum, LightningBlu guarantees carrier-grade connectivity that accommodates the surge of digital devices passengers bring aboard. The technology facilitates a robust communication network that empowers high-speed rail services amidst challenging dynamics and ensures that passengers enjoy uninterrupted service across wide geographic expanses. This significant technical prowess positions LightningBlu as an indispensable asset for the future of rail transport, effectively shaping the industry's move towards digital transformation. With a focus on sustainability, LightningBlu also supports the transition to a carbon-free transport ecosystem, providing an advanced data communication solution that interlinks seamless connectivity with environmentally responsible operation. Its application in rail systems positions it at the heart of modernizing rail services, fostering an era of enhanced rider satisfaction and operational efficiency.
The ORC3990 is a groundbreaking LEO Satellite Endpoint SoC engineered for use in the Totum DMSS Network, offering exceptional sensor-to-satellite connectivity. This SoC operates within the ISM band and features advanced RF transceiver technology, power amplifiers, ARM CPUs, and embedded memory. It boasts a superior link budget that facilitates indoor signal coverage. Designed with advanced power management capabilities, the ORC3990 supports over a decade of battery life, significantly reducing maintenance requirements. Its industrial temperature range of -40 to +85 degrees Celsius ensures stable performance in various environmental conditions. The compact design of the ORC3990 fits seamlessly into any orientation, further enhancing its ease of use. The SoC's innovative architecture eliminates the need for additional GNSS chips, achieving precise location fixes within 20 meters. This capability, combined with its global LEO satellite coverage, makes the ORC3990 a highly attractive solution for asset tracking and other IoT applications where traditional terrestrial networks fall short.
The 802.11ah HaLow transceiver is designed to provide efficient and reliable connectivity for IoT devices, utilizing sub-GHz frequencies to ensure long-range transmission while maintaining minimal power consumption. This transceiver is a perfect fit for environments where traditional Wi-Fi bands fall short due to range or power constraints. Offering superior penetration through obstacles and walls, this transceiver is ideally suited for industrial IoT, smart agriculture, and connected home systems. Its long-range capabilities make it especially useful in applications requiring broad coverage across expansive areas or dense urban settings. Beyond range enhancements, the 802.11ah HaLow standard supported by this transceiver allows for interoperability with various IoT ecosystems, simplifying device integration and promoting scalability. By balancing power efficiency and connectivity, it supports seamless operation for battery-operated devices, aiding in the creation of sustainable IoT networks.
aiData is an automated data pipeline tailored for Advanced Driver-Assistance Systems (ADAS) and Autonomous Driving (AD). This system is crucial for processing and transforming extensive real-world driving data into meticulously annotated, training-ready datasets. Its primary focus is on efficiency and precision, significantly reducing the manual labor traditionally associated with data annotation. aiData dramatically speeds up the data preparation process, providing real-time feedback and minimizing data wastage. By employing the aiData Auto Annotator, the system offers superhuman precision in automatically identifying and labeling dynamic entities such as vehicles and pedestrians, achieving significant cost reductions. The implementation of AI-driven data curation and versioning ensures that only the most relevant data is used for model improvement, providing full traceability and customization throughout the data's lifecycle. The pipeline further includes robust metrics for automatically verifying new software outputs, ensuring that performance stays at an optimal level. With aiData, companies are empowered to streamline their ADAS and AD data workflows, ensuring rapid and reliable output from concept to application.
ntRSD core implements a time-domain Reed-Solomon decoding algorithm. The core is parameterized in terms of bits per symbol, maximum codeword length and maximum number of parity symbols. It also supports varying on the fly shortened codes. Therefore any desirable code-rate can be easily achieved rendering the decoder ideal for fully adaptive FEC applications. ntRSD core supports erasure decoding thus doubling its error correction capability. The core also supports continuous or burst decoding. The implementation is very low latency, high speed with a simple interface for easy integration in SoC applications.
The NaviSoC is an advanced GNSS receiver integrated with an application processor on a single silicon die. It offers robust solutions with exceptional jamming and spoofing resistance, crafted for the mass market. This system-on-chip is known for its high levels of precision, security, and low power usage while maintaining a compact form factor. The NaviSoC system is designed to be highly flexible, allowing for extensive customization to meet diverse user needs. Its diverse application spectrum makes the NaviSoC suitable for location-based services (LBS), Internet of Things (IoT) applications, and detailed lane-level navigation systems. It is equally efficient in handling asset tracking operations and is instrumental in time synchronization tasks. Moreover, the NaviSoC finds significant utility in emerging sectors like UAV and autonomous drones, providing smart platforms for agriculture and comprehensive surveying and mapping activities. What sets the NaviSoC apart is its ability to deliver high reliability and security in demanding environments, ensuring optimal performance regardless of application. Its small size paired with low power requirements makes it an ideal choice for portable and mobile devices, providing a robust platform for developers seeking versatile and powerful GNSS functionalities.
The Hyperspectral Imaging System by Imec offers enhanced imaging capabilities, chiefly used in space exploration and Earth observation for on-chip spectral imaging. This technology allows for efficient data capture across numerous spectral bands, giving a comprehensive view that is critical for scientific and commercial applications. With its compact and robust design, the system delivers high-resolution imaging while maintaining the portability needed for field applications. This advanced imaging system leverages on-chip technology that combines innovative hardware and software solutions, contributing to its high efficiency and accuracy in capturing detailed spectral information. The hyperspectral imaging achieved allows for assembling vast datasets rapidly, which is valuable in various applications ranging from environmental monitoring to agricultural assessments. Incorporating lead-free quantum dot photodiodes, the system ensures environmentally friendly operation and precise spectral capture. The modular design of the system facilitates easy integration into existing platforms, expanding its usability across different sectors requiring advanced imaging capabilities.
The FCM1401 Dual-Drive™ Power Amplifier is tailored for Ku-band applications, utilizing CMOS technology to deliver solutions between 12.4 to 16 GHz. This product is designed to optimize power output while maintaining a compact silicon footprint. Notable for its excellent efficiency, the FCM1401 addresses the specific demands of telecom and satellite communications applications. The amplifier provides reliable performance characterized by a gain of 22 dB and a Psat of 19.2 dBm, achieving a power-added efficiency of 47% while operating at a supply voltage of 1.8V. Through these specifications, it positions itself as an ideal solution for applications requiring high power output and minimal heat generation. This product benefits from world-class CMOS integration, ensuring compatibility with modern telecom systems, enhancing their range and reducing their energy costs. The FCM1401 is equipped with a QFN/EVB package, allowing for straightforward implementation in various industrial contexts. It sets itself apart by offering an increased frequency range while delivering robust power handling capabilities, facilitating the high RF power needs of contemporary communication systems. The dual-drive capability of the FCM1401 means that it can effectively double the input signal power into the output without losing efficiency, making it highly suited for use in mission-critical operations where reliability and performance are paramount. Its high power-added efficiency also translates to cooler operation, reducing the need for extensive thermal management solutions, thus lowering associated costs.
ZIA Image Signal Processing technology provides state-of-the-art solutions for optimizing image quality and enhancing vision-based systems. This technology is integral to applications requiring precise image analysis, such as surveillance cameras and automotive safety systems. It supports various image processing tasks, including de-noising, color correction, and sharpness enhancement, delivering superior visual output even under challenging conditions. ZIA's adaptable architecture supports integration into a range of devices, ensuring broad applicability across multiple sectors.
The 802.11n/ac/ax LDPC decoder is developed for high throughput WLAN applications. It features layered decoding, soft decision decoding, and is compliant with IEEE 802.11n/ac/ax standards. The decoder supports all LDPC code rates of ½, ⅔, ¾, and ⅚, as well as all LDPC codeword sizes of 648, 1296, and 1944 bits. This IP provides a high throughput design and allows for frame-to-frame on-the-fly configuration, offering configurable LDPC decoding iterations for a trade-off between throughput and error correction performance.
The Polar channel coding offering by AccelerComm is crafted for the 3GPP 5G NR, providing both uplink and downlink encoding and decoding capabilities. Designed for easy integration, it includes PC- and CRC-aided SCL polar decoding techniques to ensure uncompromised error correction. Key parameters of the decoding IP can be tuned to adjust parallelism, latency, and throughput, making it adaptable to specific application needs without sacrificing performance.
These customizable and power-efficient IP platforms are designed to accelerate the time-to-market for IoT products. Each platform includes essential building blocks for smart and secure IoT devices. They are available with ARM and RISC-V processors, supporting a range of applications such as beacons, smart sensors, and connected audio. Pre-validated and ready for integration, these platforms are the backbone for IoT device development, ensuring that prototypes transition smoothly to production with minimal power requirements and maximum efficiency.
The RFicient chip is designed to revolutionize the Internet of Things with its ultra-low power consumption. It enables devices to operate more sustainably by drastically reducing energy requirements. This is particularly important for devices in remote locations, where battery life is a critical concern. By leveraging energy harvesting and efficient power management, the RFicient chip significantly extends the operational life of IoT devices, making it ideal for widespread applications across industrial sectors.
The VoSPI Rx for FLIR Lepton IR Sensor is designed to cater to infrared sensor needs for various applications. Specially configured to support the FLIR Lepton sensor, this receiver facilitates effective and precise data handling of infrared signals, crucial in environments demanding high thermal accuracy. It provides real-time processing capabilities, aligning with the rigorous demands of security and monitoring applications. This receiver excels in maintaining data integrity, ensuring that the thermal data transmitted across platforms is of the highest accuracy. Its sophisticated engineering allows it to work seamlessly with other system components, enhancing system performance and reliability. The receiver is integrated with features that boost signal processing while minimizing latency, providing a seamless operational environment. This ensures that users can rely on it for consistent performance across various industry applications, boosting both efficiency and reliability.
LTE Lite is a streamlined PHY solution tailored for user equipment compliant with CAT 0/1 standards. The system offers versatile channel bandwidth selections, accommodating a wide range from 1.4 MHz to 20 MHz. Key functionalities include modulation support up to 64QAM, and time tracking measurement capabilities. The LTE Lite PHY integrates seamlessly with external RF tuners via an analog to digital converter, offering frequency correction for offsets up to 500 KHz and timing corrections for mismatches as large as 50ppm. Documented as Verilog-2001 IP, it enhances adaptability for LTE systems integration.
The transceiver is designed to be used together with an RF tuner, and ADC/DAC converters. The system has internal state machine to control the operation, and can be externally configured via the SPI interface. This design is a Mobile WiMAX baseband transceiver core for both Base station and Mobile station, supplied as a portable and synthesizable Verilog-2001 IP. The system was designed to be used in conjunction with a standard RF tuner. The operation of the transceiver is automated by a master finite state machine.
The L5-Direct GNSS Receiver by oneNav offers cutting-edge performance by exclusively leveraging L5-band signals for navigation. This receiver directly captures signals in the L5 band, bypassing traditional L1 signals, which are often susceptible to interference and jamming. Designed for modern GNSS applications, it provides unmatched accuracy and robustness in urban areas and other challenging environments. The L5-direct technology boasts innovative features such as an Application Specific Array Processor (ASAP), which ensures rapid location acquisition without sacrificing sensitivity. It supports over 70 satellite signals across multiple constellations, including GPS, Galileo, BeiDou, and QZSS. This capability guarantees reliable positioning, making it ideal for users who require accurate and tamper-resistant navigation data. One of the unique aspects of the L5-Direct GNSS Receiver is its low power consumption, thanks to its optimized processing efficiencies. It is crafted to cater to applications with stringent size and cost restrictions, such as wearables and IoT devices. Furthermore, the receiver offers a single RF chain design, simplifying integration and reducing system complexity. This innovation makes oneNav's solution a compelling choice for next-generation GNSS receivers in diverse technological contexts.
ntRSE core implements the Reed Solomon encoding algorithm and is parameterized in terms of bits per symbol, maximum codeword length and maximum number of parity symbols. It also supports varying on the fly shortened codes. Therefore any desirable code-rate can be easily achieved rendering the decoder ideal for fully adaptive FEC applications. ntRSE core supports continuous or burst decoding. The implementation is very low latency, high speed with a simple interface for easy integration in SoC applications.
In smartphone applications, ActLight’s Dynamic PhotoDetector (DPD) offers a step-change in photodetection technology, enhancing features such as proximity sensing and ambient light detection. This high sensitivity sensor, with its ability to detect subtle changes in light, supports functions like automatic screen brightness adjustments and energy-efficient proximity sensing. Designed for low voltage operation, the DPD effectively reduces power consumption, making it suitable for high-performance phones without increasing thermal load. The technology also facilitates innovative applications like 3D imaging and eye-tracking, adding richness to user experiences in gaming and augmented reality.
The ArrayNav Adaptive GNSS Solution ushers in an era of enhanced automotive navigation, leveraging advanced adaptive antenna technology. This solution expertly applies multiple antennas to increase antenna gain and diversity, offering substantial advancements in navigation precision and operational consistency within complex environments. By integrating array-based technology, ArrayNav is tailored to improve the sensitivity and coverage necessary for sophisticated automotive systems. ArrayNav's use of adaptive antennas translates to significant reductions in issues such as multipath fading, which often affects navigation accuracy in urban canyons. With these enhancements, the solution ensures more reliable performance, boosting accuracy even in challenging terrains or when faced with potential signal interference. This solution has been specifically engineered for applications that demand robustness and precision, such as automotive advanced driver-assistance systems (ADAS). By employing the ArrayNav technology, users can benefit from higher degrees of jamming resistance, leading to safer and more accurate navigation results across a broad range of environments.
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