All IPs > Processor > Building Blocks
Processor building blocks are fundamental components within the realm of semiconductor IPs that play a crucial role in the development and optimization of processors. These building blocks are indispensable for crafting sophisticated, high-performance processors required in a wide range of electronic devices, from handheld gadgets to large-scale computing systems.
Processor semiconductor IP building blocks include key elements such as arithmetic logic units (ALUs), registers, and control units, which integrate to form the central processing unit (CPU). Each of these components contributes to the overall functionality of the processor. ALUs enable the processor to perform arithmetic operations and logical decisions, while registers provide the necessary storage for quick data access. Control units are responsible for interpreting instructions and coordinating other components to execute tasks efficiently. Together, these building blocks ensure that processors perform at optimal levels, handling complex computational tasks with ease.
One of the primary uses of processor building blocks is in creating devices that require advanced computational power, such as smartphones, tablets, personal computers, and servers. These semiconductor IPs help in the design of custom processors that meet specific performance, power consumption, and cost requirements. By leveraging these building blocks, designers can develop processors that are tailored to particular applications, thereby enhancing the overall performance and efficiency of devices. This customizability also facilitates innovations in emerging technologies such as artificial intelligence, the Internet of Things (IoT), and autonomous vehicles, where processors need to handle rapidly growing workloads.
The processor building blocks category in our Silicon Hub encompasses a diverse range of semiconductor IPs that cater to different processing needs. From general-purpose processors with balanced performance to specialized processors with optimized functionalities, this category provides essential components for developing next-generation electronic solutions. By utilizing these building blocks, designers and engineers can push the boundaries of processing technology, creating more capable and efficient devices that meet the evolving demands of modern consumers and industries.
Addressing the need for high-performance AI processing, the Metis AIPU PCIe AI Accelerator Card from Axelera AI offers an outstanding blend of speed, efficiency, and power. Designed to boost AI workloads significantly, this PCIe card leverages the prowess of the Metis AI Processing Unit (AIPU) to deliver unparalleled AI inference capabilities for enterprise and industrial applications. The card excels in handling complex AI models and large-scale data processing tasks, significantly enhancing the efficiency of computational tasks within various edge settings. The Metis AIPU embedded within the PCIe card delivers high TOPs (Tera Operations Per Second), allowing it to execute multiple AI tasks concurrently with remarkable speed and precision. This makes it exceptionally suitable for applications such as video analytics, autonomous driving simulations, and real-time data processing in industrial environments. The card's robust architecture reduces the load on general-purpose processors by offloading AI tasks, resulting in optimized system performance and lower energy consumption. With easy integration capabilities supported by the state-of-the-art Voyager SDK, the Metis AIPU PCIe AI Accelerator Card ensures seamless deployment of AI models across various platforms. The SDK facilitates efficient model optimization and tuning, supporting a wide range of neural network models and enhancing overall system capabilities. Enterprises leveraging this card can see significant improvements in their AI processing efficiency, leading to faster, smarter, and more efficient operations across different sectors.
aiWare is a high-performance NPU designed to meet the rigorous demands of automotive AI inference, providing a scalable solution for ADAS and AD applications. This hardware IP core is engineered to handle a wide array of AI workloads, including the most advanced neural network structures like CNNs, LSTMs, and RNNs. By integrating cutting-edge efficiency and scalability, aiWare delivers industry-leading neural processing power tailored to automobile-grade specifications.\n\nThe NPU's architecture emphasizes hardware determinism and offers ISO 26262 ASIL-B certification, ensuring that aiWare meets stringent automotive safety standards. Its efficient design also supports up to 256 effective TOPS per core, and can scale to handle thousands of TOPS through multicore integration, minimizing power consumption effectively. The aiWare's system-level optimizations reduce reliance on external memory by leveraging local memory for data management, boosting performance efficiency across varied input data sizes and complexities.\n\naiWare’s development toolkit, aiWare Studio, is distinguished by its innovative ability to optimize neural network execution without the need for manual intervention by software engineers. This empowers ai engineers to focus on refining NNs for production, significantly accelerating iteration cycles. Coupled with aiMotive's aiDrive software suite, aiWare provides an integrated environment for creating highly efficient automotive AI applications, ensuring seamless integration and rapid deployment across multiple vehicle platforms.
Leveraging a high-performance RISC architecture, the eSi-3250 32-bit core efficiently integrates instruction and data caches. This makes it compatible with designs utilizing slower on-chip memories such as eFlash. The core not only supports MMU for address translation but also allows for user-defined custom instructions, greatly enhancing its flexibility for specialized and high-performance applications.
Chimera GPNPU is engineered to revolutionize AI/ML computational capabilities on single-core architectures. It efficiently handles matrix, vector, and scalar code, unifying AI inference and traditional C++ processing under one roof. By alleviating the need for partitioning AI workloads between different processors, it streamlines software development and drastically speeds up AI model adaptation and integration. Ideal for SoC designs, the Chimera GPNPU champions an architecture that is both versatile and powerful, handling complex parallel workloads with a single unified binary. This configuration not only boosts software developer productivity but also ensures an enduring flexibility capable of accommodating novel AI model architectures on the horizon. The architectural fabric of the Chimera GPNPU seamlessly blends the high matrix performance of NPUs with C++ programmability found in traditional processors. This core is delivered in a synthesizable RTL form, with scalability options ranging from a single-core to multi-cluster designs to meet various performance benchmarks. As a testament to its adaptability, the Chimera GPNPU can run any AI/ML graph from numerous high-demand application areas such as automotive, mobile, and home digital appliances. Developers seeking optimization in inference performance will find the Chimera GPNPU a pivotal tool in maintaining cutting-edge product offerings. With its focus on simplifying hardware design, optimizing power consumption, and enhancing programmer ease, this processor ensures a sustainable and efficient path for future AI/ML developments.
xcore.ai is XMOS Semiconductor's innovative programmable chip designed for advanced AI, DSP, and I/O applications. It enables developers to create highly efficient systems without the complexity typical of multi-chip solutions, offering capabilities that integrate AI inference, DSP tasks, and I/O control seamlessly. The chip architecture boasts parallel processing and ultra-low latency, making it ideal for demanding tasks in robotics, automotive systems, and smart consumer devices. It provides the toolset to deploy complex algorithms efficiently while maintaining robust real-time performance. With xcore.ai, system designers can leverage a flexible platform that supports the rapid prototyping and development of intelligent applications. Its performance allows for seamless execution of tasks such as voice recognition and processing, industrial automation, and sensor data integration. The adaptable nature of xcore.ai makes it a versatile solution for managing various inputs and outputs simultaneously, while maintaining high levels of precision and reliability. In automotive and industrial applications, xcore.ai supports real-time control and monitoring tasks, contributing to smarter, safer systems. For consumer electronics, it enhances user experience by enabling responsive voice interfaces and high-definition audio processing. The chip's architecture reduces the need for exterior components, thus simplifying design and reducing overall costs, paving the way for innovative solutions where technology meets efficiency and scalability.
The Metis AIPU M.2 Accelerator Module by Axelera AI is a compact and powerful solution designed for AI inference at the edge. This module delivers remarkable performance, comparable to that of a PCIe card, all while fitting into the streamlined M.2 form factor. Ideal for demanding AI applications that require substantial computational power, the module enhances processing efficiency while minimizing power usage. With its robust infrastructure, it is geared toward integrating into applications that demand high throughput and low latency, making it a perfect fit for intelligent vision applications and real-time analytics. The AIPU, or Artificial Intelligence Processing Unit, at the core of this module provides industry-leading performance by offloading AI workloads from traditional CPU or GPU setups, allowing for dedicated AI computation that is faster and more energy-efficient. This not only boosts the capabilities of the host systems but also drastically reduces the overall energy consumption. The module supports a wide range of AI applications, from facial recognition and security systems to advanced industrial automation processes. By utilizing Axelera AI’s innovative software solutions, such as the Voyager SDK, the Metis AIPU M.2 Accelerator Module enables seamless integration and full utilization of AI models and applications. The SDK offers enhancements like compatibility with various industry tools and frameworks, thus ensuring a smooth deployment process and quick time-to-market for advanced AI systems. This product represents Axelera AI’s commitment to revolutionizing edge computing with streamlined, effective AI acceleration solutions.
The N Class RISC-V CPU IP from Nuclei is tailored for applications where space efficiency and power conservation are paramount. It features a 32-bit architecture and is highly suited for microcontroller applications within the AIoT realm. The N Class processors are crafted to provide robust processing capabilities while maintaining a minimal footprint, making them ideal candidates for devices that require efficient power management and secure operations. By adhering to the open RISC-V standard, Nuclei ensures that these processors can be seamlessly integrated into various solutions, offering customizable options to fit specific system requirements.
Designed for efficient processing, the SCR3 microcontroller core offers a versatile solution for embedded environments. It comes equipped with a 5-stage in-order pipeline and supports both 32-bit and 64-bit symmetric multiprocessing (SMP) configurations, facilitating advanced applications. The core integrates privilege modes and includes memory protection units (MPUs), along with L1 and L2 caches, ensuring data integrity and performance. Its efficient architecture is optimized for energy-conscious applications, making it ideal for industrial, automotive, and IoT applications.
RAIV represents Siliconarts' General Purpose-GPU (GPGPU) offering, engineered to accelerate data processing across diverse industries. This versatile GPU IP is essential in sectors engaged in high-performance computing tasks, such as autonomous driving, IoT, and sophisticated data centers. With RAIV, Siliconarts taps into the potential of the fourth industrial revolution, enabling rapid computation and seamless data management. The RAIV architecture is poised to deliver unmatched efficiency in high-demand scenarios, supporting massive parallel processing and intricate calculations. It provides an adaptable framework that caters to the needs of modern computing, ensuring balanced workloads and optimized performance. Whether used for VR/AR applications or supporting the back-end infrastructure of data-intensive operations, RAIV is designed to meet and exceed industry expectations. RAIV’s flexible design can be tailored to enhance a broad spectrum of applications, promising accelerated innovation in sectors dependent on AI and machine learning. This GPGPU IP not only underscores Siliconarts' commitment to technological advancement but also highlights its capability to craft solutions that drive forward computational boundaries.
The Codasip RISC-V BK Core Series offers versatile, low-power, and high-performance solutions tailored for various embedded applications. These cores ensure efficiency and reliability by incorporating RISC-V compliance and are verified through advanced methodologies. Known for their adaptability, these cores can cater to applications needing robust performance while maintaining stringent power and area requirements.
The eSi-1650 is a compact, low-power 16-bit CPU core integrating an instruction cache, making it an ideal choice for mature process nodes reliant on OTP or Flash program memory. By omitting large on-chip RAMs, the IP core optimizes power and area efficiency and permits the CPU to capitalize on its maximum operational frequency beyond OTP/Flash constraints.
The SCR6 microcontroller core offers high performance within a microcontroller framework, featuring a sophisticated 12-stage dual-issue out-of-order pipeline. It's aimed at applications needing high processing power but within the constraints of embedded systems. The core includes a high-performance floating-point unit (FPU), making it suitable for computation-heavy tasks while also supporting real-time operating systems. Its design ensures its applicability across fields like industrial automation, sensor fusion, and automotive systems, where power efficiency and performance are critical.
The eSi-1600 is a 16-bit CPU core designed for cost-sensitive and power-efficient applications. It accords performance levels similar to that of 32-bit CPUs while maintaining a system cost comparable to 8-bit processors. This IP is particularly well-suited for control applications needing limited memory resources, demonstrating excellent compatibility with mature mixed-signal technologies.
The SCR1 microcontroller core is designed for deeply embedded applications, providing an efficient and compact solution. It features a 4-stage in-order pipeline and supports 32-bit processing, making it suitable for applications requiring low power and space efficiency. The core's design is open-source, allowing for easy customization and adaptation to specific project requirements. Additionally, it integrates seamlessly with a variety of development environments and software tools, simplifying the development process and reducing deployment time.
The eSi-3200, a 32-bit cacheless core, is tailored for embedded control with its expansive and configurable instruction set. Its capabilities, such as 64-bit multiply-accumulate operations and fixed-point complex multiplications, cater effectively to signal processing tasks like FFTs and FIRs. Additionally, it supports SIMD and single-precision floating point operations, coupled with efficient power management features, enhancing its utility for diverse embedded applications.
The ISPido on VIP Board is tailored specifically for Lattice Semiconductor's Video Interface Platform (VIP) and is designed to achieve clear and balanced real-time imaging. This ISPido variant supports automatic configuration options to provide optimal settings the moment the board is powered on. Alternatively, users can customize their settings through a menu interface, allowing for adjustments such as gamma table selection and convolutional filtering. Equipped with the CrossLink VIP Input Bridge, the board features dual Sony IMX 214 image sensors and an ECP5 VIP Processor. The ECP5-85 FPGA ensures reliable processing power while potential outputs include HDMI in YCrCb 4:2:2 format. This flexibility ensures users have a complete, integrated solution that supports runtime calibration and serial port menu configuration, making it an extremely practical choice for real-time applications. The ISPido on VIP Board is built to facilitate seamless integration and high interoperability, making it a suitable choice for those engaged in designing complex imaging solutions. Its adaptability and high-definition support make it particularly advantageous for users seeking to implement sophisticated vision technologies in a variety of industrial applications.
The iCan PicoPop® is a highly compact System on Module (SOM) based on the Zynq UltraScale+ MPSoC from Xilinx, suited for high-performance embedded applications in aerospace. Known for its advanced signal processing capabilities, it is particularly effective in video processing contexts, offering efficient data handling and throughput. Its compact size and performance make it ideal for integration into sophisticated systems where space and performance are critical.
The Prodigy Universal Processor by Tachyum is a groundbreaking innovation in the realm of computing, marked as the world's first processor that merges General Purpose Computing, High-Performance Computing, Artificial Intelligence, and various other AI disciplines into a single compact chip. This processor promises to revolutionize hyperscale data centers with its unprecedented processing capabilities and efficiency, pushing the boundaries of current computational power. With its superior performance per watt, Prodigy minimizes energy consumption while maximizing data processing abilities. Offering up to 21 times higher performance compared to its contemporaries, Prodigy stands out by providing a coherent multiprocessor architecture that simplifies the programming environment. It aims to overcome challenges like high power use and server underutilization, which have long plagued modern data centers. By addressing these core issues, it allows enterprises to manage workloads more effectively and sustainably. Furthermore, Prodigy's emulation platform broadens the scope of testing and evaluation, enabling developers to optimize their applications for better performance and low power consumption. With native support for the Prodigy instruction set architecture, the processor seamlessly integrates existing software packages, promising a smooth transition and robust application support. Through the integration of this versatile processor, Tachyum is leading the charge toward a sustainable technological future.
The SiFive Essential family is designed to deliver high customization for processors across varying applications, from standalone MCUs to deeply embedded systems. This family of processor cores provides a versatile solution, meeting diverse market needs with an optimal combination of power, area, and performance. Within this lineup, users can tailor processors for specific market requirements, ranging from simple MCUs to fully-featured, Linux-capable designs. With features such as high configurability, SiFive Essential processors offer flexible design points, allowing scaling from basic 2-stage pipelines to advanced dual-issue superscalar configurations. This adaptability makes SiFive Essential suitable for a wide variety of use cases in microcontrollers, IoT devices, and control plane processing. Additionally, their innovation is proven by billions of units shipped worldwide, highlighting their reliability and versatility. The Essential cores also provide advanced integration options within SoCs, enabling smooth interface and optimized performance. This includes pre-integrated trace and debug features, ensuring efficient development and deployment in diverse applications.
The Universal DSP Library is designed to simplify digital signal processing tasks within FPGA systems. This extensive collection of DSP algorithms and functions allows for efficient development and deployment of signal processing applications. Users can leverage this library to handle complex computations swiftly, making it perfect for industries requiring real-time processing power. It streamlines development by offering pre-tested routines that developers can integrate into their systems without extensive customization.
The xcore-200 chip from XMOS is a pivotal component for audio processing, delivering unrivaled performance for real-time, multichannel streaming applications. Tailored for professional and high-resolution consumer audio markets, xcore-200 facilitates complex audio processing with unparalleled precision and flexibility. This chip hosts XMOS's adept capabilities in deterministic and parallel processing, crucial for achieving zero-latency outputs in applications such as voice amplification systems, high-definition audio playback, and multipoint conferencing. Its architecture supports complex I/O operations, ensuring that all audio inputs and outputs are managed efficiently without sacrificing audio quality. The xcore-200 is crafted to handle large volumes of data effortlessly while maintaining the highest levels of integrity and clarity in audio outputs. It provides superior processing power to execute intensive tasks such as audio mixing, effects processing, and real-time equalization, crucial for both consumer electronics and professional audio gear. Moreover, xcore-200 supports a flexible integration into various systems, enhancing the functionality of audio interfaces, smart soundbars, and personalized audio solutions. It also sustains the robust performance demands needed in embedded AI implementations, thereby extending its utility beyond traditional audio systems. The xcore-200 is a testament to XMOS's dedication to pushing the boundaries of what's possible in audio engineering, blending high-end audio performance with cutting-edge processing power.
The NX Class RISC-V CPU IP by Nuclei is characterized by its 64-bit architecture, making it a robust choice for storage, AR/VR, and AI applications. This processing unit is designed to accommodate high data throughput and demanding computational tasks. By leveraging advanced capabilities, such as virtual memory and enhanced processing power, the NX Class facilitates cutting-edge technological applications and is adaptable for integration into a vast array of high-performance systems.
ISPido is a powerful and flexible image signal processing pipeline tailored for high-resolution image processing and tuning. It supports a comprehensive pipeline of image enhancement features such as defect correction, color filter array interpolation, and various color space conversions, all configurable via the AXI4-LITE protocol. Designed to handle input depths of 8, 10, or 12 bits, ISPido excels in processing high-definition resolutions up to 7680x7680 pixels, making it highly suitable for a variety of advanced vision applications. The architecture of ISPido is built to be highly compatible with AMBA AXI4 standards, ensuring that it can be seamlessly integrated into existing systems. Each module in the pipeline is individually configurable, allowing for extensive customization to optimize performance. Features such as auto-white balance, gamma correction, and HDR chroma resampling empower developers to produce precise and visually accurate outputs in complex environments. ISPido's modular and versatile design makes it an ideal choice for deploying in heterogeneous processing environments, ranging from low-power battery-operated devices to sophisticated vision systems capable of handling resolutions higher than 8K. This adaptability makes it a prime solution for developers working across various sectors demanding high-quality image processing.
The SCR4 microcontroller core enhances embedded processing with robust features tailored for demanding applications. This core is designed with a 5-stage in-order pipeline, privilege modes, and advanced support for floating-point units (FPUs). Accompanied by MPUs and comprehensive cache infrastructures, including L1 and L2 caches, it ensures high efficiency and performance. Its ability to handle both 32-bit and 64-bit SMP setups makes it versatile for various industries such as industrial control, IoT, and embedded network devices.
A robust platform offering a full spectrum of ARM Cortex-M microprocessors, perfect for integration across a broad scope of systems. These ASICs are finely tuned to accommodate various applications, demonstrating commendable performance in areas such as IoT, industrial automation, and consumer electronics. Known for their reliability and scalability, these ASICs enhance system capabilities by providing customizable features that match exclusive client criteria.
The Origin E1 is a compact yet powerful neural processing unit (NPU) designed for low-power applications in home appliances, smartphones, and security cameras. Specially tailored for always-on functions, the E1 offers unmatched power efficiency by utilizing Expedera's innovative packet-based architecture. This allows it to execute multiple layers in parallel, ensuring the optimal balance of performance and resource utilization. Engineered to operate with minimal to no external memory, the Origin E1 is ideal for cost-effective and area-sensitive designs. The LittleNPU processor within it is fine-tuned for sophisticated neural networks needed in always-sensing applications, maintaining privacy by keeping data on-board. This makes the E1 a robust choice for devices requiring dedicated AI processing without the penalty of high power consumption or large silicon area. In terms of technical specifications, the Origin E1 boasts a performance efficiency of up to 18 TOPS per Watt, with the capability to run various network types such as CNNs, RNNs, and DNNs. Its adaptability allows clients to customize features to meet specific needs, guaranteeing efficient deployments across numerous devices. The E1 leverages a full TVM-based software stack for seamless integration, further endorsing its versatility and effectiveness.
The UX Class RISC-V CPU IP epitomizes Nuclei's commitment to potent processing solutions suited for data centers and network environments. Equipped with a 64-bit architecture with integrated MMU capabilities, it is tailored for embedding into Linux-operated systems that demand high operational efficiency and reliability. The UX Class supports extensive data handling and computational tasks, ensuring seamless performance even under the rigors of data-intensive environments.
The Universal High-Speed SERDES core caters to applications demanding rapid data exchange across a range of standards, including RapidIO, Fibre Channel, and XAUI. This core is remarkable for its flexibility, accommodating data rates from 1Gbps to 12.5Gbps with variable data width options like 16bit, 20bit, 32bit, and 40bit. Designed with a pre-emphasis linear equalizer and an adaptive receiver equalizer, this SERDES solution ensures optimal signal integrity across various transmission distances and conditions, enhancing the robustness of the data link. It is also capable of operating without any external components, streamlining the design process and minimizing associated costs. Additionally, the core supports multiple packaging models and channel configurations, providing a highly adaptable platform for diverse applications. Whether for high-speed backplanes or chip-to-chip communications, this SERDES core delivers high performance and reliability, supported by process node flexibility including support for 28nm and larger nodes, facilitating integration into a wide range of semiconductor technologies.
The Cyclone V FPGA with Integrated PQC Processor by ResQuant is a specialized product that comes pre-equipped with a comprehensive NIST PQC cryptography suite. This FPGA is tailored for applications requiring a robust proof-of-concept for quantum-safe implementations. It ensures seamless integration into existing systems, providing a practical platform for testing and deployment in quantum-secure environments. This product is available at a competitive price and represents an ideal starting point for entities looking to explore and adopt quantum-resilient technologies. Its configuration allows for straightforward implementation in diverse hardware infrastructures while offering a reliable option for organizations aiming to stay ahead in the evolving cyber security landscape. By incorporating the latest in cryptographic standards and ensuring vendor independence, the Cyclone V FPGA with Integrated PQC Processor by ResQuant effectively bridges current hardware technologies and future-proof security needs. It supports industry-wide applications, from IoT and ICT to automotive and military sectors, underscoring ResQuant's versatility in hardware security solutions.
The eSi-3264 stands out with its support for both 32/64-bit operations, including 64-bit fixed and floating-point SIMD (Single Instruction Multiple Data) DSP extensions. Engineered for applications mandating DSP functionality, it does so with minimal silicon footprint. Its comprehensive instruction set includes specialized commands for various tasks, bolstering its practicality across multiple sectors.
The Neural Network Accelerator from Gyrus AI is designed to enhance edge computing capabilities through native graph processing. This innovative solution offers up to 30 TOPs/W, making it highly efficient by achieving 10-30 times lower clock-cycles than conventional processors. Its design supports low memory usage configurations, significantly reducing power consumption and enabling up to 20 times lower energy requirements. Designed for seamless integration, it supports diverse neural network models with superior utilization of over 80%, leading to enhanced performance and reduced die area by 10 to 8 times smaller than traditional designs.
Nuclei's U Class RISC-V CPU IP represents a versatile computing solution engineered to handle complex processing tasks. With a 32-bit architecture augmented by a Memory Management Unit (MMU), this class is optimized for Linux environments and excels in edge computing applications. Featuring extensive configuration options, the U Class processor ensures adaptability to varied computing demands, facilitating efficient task execution across diverse scenarios.
Optimized for Linux-capable applications, the SCR5 application core serves high-performance needs with a sophisticated 9-stage in-order pipeline. Designed to handle complex data processing tasks, it integrates memory management units (MMUs) and supports both L1 and L2 caches with cache coherency features. This makes it a suitable option for areas requiring efficient data processing while maintaining energy efficiency, such as artificial intelligence, mobile devices, and high-performance computing.
DolphinWare IPs is a versatile portfolio of intellectual property solutions that enable efficient SoC design. This collection includes various control logic components such as FIFO, arbiter, and arithmetic components like math operators and converters. In addition, the logic components span counters, registers, and multiplexers, providing essential functionalities for diverse industrial applications. The IPs in this lineup are meticulously designed to ensure data integrity, supported by robust verification IPs for AXI4, APB, SD4.0, and more. This comprehensive suite meets the stringent demands of modern electronic designs, facilitating seamless integration into existing design paradigms. Beyond their broad functionality, DolphinWare’s offerings are fundamental to applications requiring specific control logic and data integrity solutions, making them indispensable for enterprises looking to modernize or expand their product offerings while ensuring compliance with industry standards.
The TimbreAI T3 is meticulously designed to cater to ultra-low-power AI applications, notably in audio devices like headsets. Providing optimal noise reduction capabilities, the T3 performs efficient AI inference while utilizing minimal power, making it ideal for power-constrained environments. This AI engine achieves superior audio processing through 3.2 billion operations per second, while consuming less than 300 microWatts of power. The TimbreAI T3 supports full deployment across leading silicon processes, delivering seamless integration as soft IP to enhance audio experiences without extensive power requirements. With its focus on minimal footprint and maximized efficiency, the TimbreAI T3 allows developers to deploy neural networks without altering trained models, ensuring high accuracy and performance in tiny devices. Its flexibility and proven field deployment further solidify its credentials as a leading solution for the mobile audio market.
Targeting high-performance demands, the Origin E8 is built for sectors requiring robust AI capabilities, such as data centers and autonomous driving. It accommodates demanding applications for real-time processing tasks, offering up to 128 TOPS in a single core configuration. The E8 expedites complex AI workloads with its advanced packet-based architecture that enhances efficiency through concurrent multi-layer execution. The scalable design of the Origin E8 enables its use in diverse contexts, managing multiple AI networks simultaneously with minimal latency. Expedera's solution addresses the architectural needs of sectors where performance, area, and power efficiency are paramount, providing competitive advantages through optimal configuration. Including a comprehensive suite of development tools like a compiler, scheduler, and quantizer, the Origin E8 facilitates straightforward integration and adaptation to various AI models, thereby ensuring it can meet a broad range of application scenarios.
The Origin E2 NPU is engineered for power-sensitive devices requiring on-device AI processing. Suitable for smartphones and edge nodes, it supports various AI models and balances performance with low power consumption. By utilizing Expedera's packet-based architecture, the E2 achieves high efficiency and effective resource utilization, facilitating parallel execution across multiple layers to enhance computational throughput. The E2 is highly adaptable, supporting a broad performance range from 1 to 20 TOPS, making it well-suited for running neural networks like RNN, LSTM, CNN, and DNN without the need for hardware-specific modifications. This ensures seamless integration for customers looking to leverage their existing trained models. Equipped with a full TVM-based software stack, the Origin E2 simplifies network deployment while offering excellent customization capabilities to meet specific application requirements. Its design emphasizes field-proven reliability with its inclusion in over 10 million consumer devices globally.
ADICSYS, a subsidiary of EASii IC, provides advanced Field Programmable Gate Array (FPGA) solutions that blend the benefits of custom FPGA and embedded FPGA technologies. With over a decade's worth of expertise in FPGA development, ADICSYS offers soft eFPGA IP which is not only highly customizable and scalable but also seamlessly integrates into standard RTL design flows. This IP is designed to be technology-independent and supports a synthesis from RTL to FPGA bitstream conversion, catering to diverse application requirements. The soft eFPGA technology from ADICSYS is celebrated for its flexibility, allowing modifications to circuits even post-production and during service. This adaptability significantly reduces design times and risks associated with errors. By enabling Programmable IPs with immediate accessibility for customization, ADICSYS supports a range of architectural parameters, from LUT count to routing density, ensuring precise adaptation to area, performance, and power constraints. The Synthesizable Programmable Core (SPC) created by ADICSYS is particularly advantageous for reducing risks associated with design errors and specification changes, making it a pivotal component in many industrial applications. ADICSYS stands out for its application of industry-standard CAD tools, guaranteeing ease in integration and adaptability for varied semiconductor projects.
Designed for edge inference applications, the Origin E6 NPU offers a state-of-the-art solution supporting both traditional and generative AI models. With performance scaling from 16 to 32 TOPS, the E6 is tailored to meet the sophisticated demands of next-gen smartphones, AR/VR devices, and automotive applications. Expedera's packet-based architecture facilitates parallel operations, ensuring efficient resource use and reducing latency. The E6 is highly customizable, supporting a wide range of AI models and enabling seamless deployments across diverse hardware environments without the need for extensive hardware-specific tuning. Expedera offers the Origin E6 with a complete software stack that promotes ease of integration and supports advanced features like multiple job APIs and quantization options. By achieving up to 90% processor utilization, the E6 maximizes performance while minimizing dark silicon waste, positioning it as a leading choice for AI chip architects seeking power efficiency and scalability in their designs.
Optimized for demanding computational requirements, the Metis AIPU Quad-Core High-Performance PCIe Card from Axelera AI represents a leap forward in AI acceleration technology. Incorporating four robust Metis AIPUs on a single card, it offers an immense increase in processing capability, ideal for complex AI-driven applications in data-intensive sectors. This card is engineered to handle the most intricate AI inference tasks, providing swift execution and precise outcomes for critical applications across multiple industries. Each AIPU core on the card is capable of executing AI tasks at an impressive rate, allowing for highly parallel processing capabilities. This enables the card to manage sophisticated neural network models with ease, making it an excellent choice for applications such as photorealistic simulation environments, advanced robotics, and complex pattern recognition systems. By harnessing the latest AI developments, it provides businesses with the computational muscle needed to transform raw data into actionable insights. Further strengthening its versatility, the card is equipped with the Voyager SDK, which streamlines the deployment of AI models by offering flexible model integration and performance enhancements. This software support allows developers to swiftly transition from development to deployment, reducing time spent in integrating and optimizing AI models. With its extraordinary computational power and comprehensive software support, the Metis AIPU Quad-Core High-Performance PCIe Card is driving significant advancements in edge computing and AI innovation.
The Low Power RISC-V CPU IP from SkyeChip is engineered for applications necessitating efficient power usage without compromising performance. By leveraging the open-source RISC-V architecture, this CPU IP provides modular growth potential and customization to meet the specific demands of embedded and IoT systems. SkyeChip's design emphasizes scalability and power efficiency, making it an optimal choice for modern electronics.
iCEVision provides an adaptable platform for evaluating connectivity features within the iCE40 UltraPlus FPGA. By enabling rapid prototyping, iCEVision allows users to quickly develop, test, and confirm the design of user-defined functions, thereby reducing development time. The platform includes compatibility with prevalent camera interfaces such as ArduCam CSI and PMOD, ensuring ease of connection and expandability. With onboard features like programmable SPI Flash, SRAM, and multiple connectivity options, iCEVision is optimized for effortless connectivity and simple programming. The platform includes intuitive software tools like the Lattice Diamond Programmer and iCEcube2 for writing and refining custom code, simplifying the user experience and facilitating seamless integration. Ideal for applications requiring high flexibility and rapid deployment, iCEVision's robust processing capabilities are complemented by a compact 50mm x 50mm size, making it a versatile choice for various development needs. Pre-loaded applications and a user-friendly programming interface further contribute to its desirability as a core development kit for embedded system design.
The YVR is a sophisticated processor designed around the AVR Instruction Set Architecture, optimized with a 2-clock machine cycle. It capitalizes on the strengths of the AVR architecture, providing enhanced processing speeds while maintaining power efficiency—a key requirement for many modern electronics. Its design ensures that it can be integrated into a wide range of applications, particularly those that demand rapid data processing alongside reliable performance. The YVR supports a variety of technological environments, offering flexibility in both legacy systems and new developments requiring robust embedded processors. Systemyde provides a complete package of design and verification resources for the YVR, ensuring high performance and dependability. This processor is a versatile choice for designers seeking a balance between speed, efficiency, and reliability in their embedded applications, making it an integral part of Systemyde’s processor offerings.
CetraC.io's High-Performance FPGA & ASIC Networking Product is designed to offer unparalleled performance in distributed network architectures. Built on the foundation of hardware acceleration, it simplifies network design by embedding complex networking functionalities directly into ASICs and FPGAs. These products are optimized for high-bandwidth operations and ensure consistent network reliability. Utilizing advanced finite state machine technology, CetraC.io provides a solution that dramatically enhances data throughput and minimizes latency in data transmissions. With an ability to handle multiple data streams concurrently, networks using these products can efficiently process and manage large volumes of data, crucial for real-time operations in sectors like aerospace and defense. This networking product supports a broad array of protocols, ensuring seamless integration within existing systems while maintaining security and data integrity. Designed with high efficiency in mind, it reduces the overhead typically associated with software-based networking solutions, leading to improvements in energy consumption and overall system performance. CetraC.io's networking product is ideal for applications requiring robust data processing, such as those found in mission-critical environments. Its inherent support for future-ready networking standards positions it well within industries demanding cutting-edge technology with scalable features for expanding network demands.
**DRV64IMZicsr – 64-bit RISC-V Performance. Designed for Demanding Innovation.** The DRV64IMZicsr is a powerful and versatile 64-bit RISC-V CPU core, built to meet the performance and safety needs of next-generation embedded systems. Featuring the M (Multiply/Divide), Zicsr (Control and Status Registers), and External Debug extensions, this core is engineered to scale—from edge computing to mission-critical applications. As part of the DRVX Core Family, the DRV64IMZicsr embodies DCD’s philosophy of combining open-standard freedom with customizable IP excellence—making it a smart and future-proof alternative to legacy architectures. ✅ Why Choose RISC-V? * No license fees – open-source instruction set means reduced TCO * Unmatched flexibility – tailor the architecture to your specific needs * A global, thriving ecosystem – support from toolchains, OSes, and hardware vendors * Security & longevity – open and verifiable architecture ensures trust and sustainability 🚀 DRV64IMZicsr – Core Advantages: * 64-bit RISC-V ISA with M, Zicsr, and Debug support * Five-stage pipeline, Harvard architecture, and efficient branch prediction * Configurable memory size and allocation for program and data spaces Performance optimized: * **Up to 2.38 CoreMark/MHz** * **Up to 1.17 DMIPS/MHz** * Compact footprint starting from just 17.6k gates * Interface options: AXI, AHB, or native * Compatible with Classical CAN, CAN FD, and CAN XL through additional IPs 🛡️ Safety, Compatibility & Flexibility Built In: * Developed as an ISO 26262 Safety Element out of Context (SEooC) * Technology-agnostic – works seamlessly across all FPGA and ASIC vendors * Expandable with DCD’s IP portfolio: DMA, SPI, UART, I²C, CAN, PWM, and more 🔍 Robust Feature Set for Real Applications: * Full 64-bit processing – ideal for performance-intensive, memory-heavy tasks * M extension enables high-speed multiplication/division via dedicated hardware unit * Zicsr extension gives full access to Control and Status Registers, enabling: * Interrupts and exception handling (per RISC-V Privileged Spec) * Performance counters and timers * JTAG-compatible debug interface – compliant with RISC-V Debug Spec (0.13.2 & 1.0.0) 🧪 Ready for Development & Integration: * Comes with a fully automated testbench * Includes a comprehensive suite of validation tests for smooth SoC integration * Supported by industry-standard tools, ensuring a hassle-free dev experience Whether you’re designing for automotive safety, industrial control, IoT gateways, or AI-enabled edge devices, the DRV64IMZicsr gives you the performance, flexibility, and future-readiness of RISC-V—without compromise. 💡 Build smarter, safer systems—on your terms. 📩 Contact us today at info@dcd.pl to start your next RISC-V-powered project.
The DF6802 is an 8-bit synthesizable MPU IP Core, software-compatible with Motorola MC6802. It features an enhanced internal architecture for approximately 4 times faster execution than the original 6802 chip at the same clock frequency. Designed with two power-saving modes (WAIT and HALT), the DF6802 is ideal for automotive and battery-driven applications. It is fully customizable, allowing for a configuration that meets specific user needs, without extra costs for unused features. The IP Core comes equipped with a fully automated testbench and a comprehensive set of test cases for smooth package validation. Moreover, the DF6802 supports DCD’s Hardware Debug System, DoCD™, which offers real-time, non-intrusive debugging across the entire SoC, including the ability to halt, run, step into, or skip instructions, and read/write data to any part of the microprocessor. With support for a wide range of interfaces such as USB, Ethernet, I2C, SPI, UART, CAN, LIN, HDLC, and Smart Card, the DF6802 shows versatile connectivity while ensuring efficient power and performance optimization. The DF6802 is technology agnostic, ensuring compatibility with all FPGA and ASIC vendors. It comes with extensive deliverables including synthesizable RTL, testbench environment, simulation macros, synthesis scripts, and complete technical documentation along with 12 months of technical support.
DRV32IMZicsr – Scalable RISC-V Power. Tailored for Your Project. Ready for the Future. The DRV32IMZicsr is a high-performance, 32-bit RISC-V processor core, equipped with M (Multiply/Divide), Zicsr (Control and Status Registers), and External Debug support. Built as part of DCD’s latest DRVX Core Family, it delivers the full flexibility, openness, and innovation that RISC-V promises—without locking you into proprietary architectures. ✅ Why RISC-V? RISC-V is a rapidly growing open standard for modern computing—backed by a global ecosystem of developers and vendors. It brings: * Freedom from licensing fees and vendor lock-in * Scalability from embedded to high-performance systems * Customizability with standard and custom instruction sets * Strong toolchain & ecosystem support 🚀 DRV32IMZicsr Highlights: * Five-stage pipeline and Harvard architecture for optimized performance * Configurable memory architecture: size and address allocation tailored to your needs Performance metrics: * **Up to 1.15 DMIPS/MHz** * **Up to 2.36 CoreMark/MHz** * Minimal footprint starting from just 14k gates * Flexible interfaces: Choose from AXI, AHB, or native bus options 🛡️ Designed for Safety & Integration: * Developed as an ISO 26262 Safety Element out of Context (SEooC) * Fully technology-agnostic, compatible with all FPGA and ASIC platforms * Seamless integration with DCD’s rich portfolio of IPs: DMA, SPI, UART, PWM, CAN, and more 🔍 Advanced Feature Set: * 32 general-purpose registers * Support for arithmetic, logic, load/store, conditional and unconditional control flow * M extension enables efficient integer multiplication/division * Zicsr extension provides robust interrupt and exception handling, performance counters, and timers * External Debug via JTAG: compliant with RISC-V Debug Specification 0.13.2 and 1.0.0, compatible with all mainstream tools 🧪 Developer-Ready: * Delivered with a fully automated testbench * Includes a comprehensive validation test suite for smooth integration into your SoC flow Whether you're building for automotive, IoT, consumer electronics, or embedded systems, the DRV32IMZicsr offers a future-ready RISC-V solution—highly configurable, performance-optimized, and backed by DCD’s 25 years of experience. Interested? Let’s build the next generation together. 📩 Contact us at info@dcd.pl
DP8051CPU is an ultra high performance 8-bit soft core microcontroller designed by DCD-SEMI to be highly efficient in terms of speed and power consumption. With a pipelined RISC architecture, it can perform operations remarkably faster than the traditional 80C51, with its performance metrics standing up to 15.55 times its predecessor when benchmarked using Dhrystone 2.1. The architecture supports both Harvard and von Neumann configurations, increasing the flexibility for memory access and inclusion. The microcontroller is equipped with an advanced Power Management Unit, allowing it to maintain its high performance capabilities while optimizing power consumption. Targeted for carrying out operations with both fast on-chip memory and slower off-chip alternatives, it can process up to 300 million instructions per second while managing substantial code and data spaces efficiently. Furthermore, it is 100% compatible with the industry-standard 8051 microcontrollers in terms of binary operation, making it highly suitable for integration in existing systems. It boasts of supporting a wide variety of interfaces like USB, Ethernet, I2C, SPI, UART, and many others, which adds to the scope of applications, especially in portable and power-conscious devices. The microcontroller supports a comprehensive hardware debugging system (DoCD™), uniquely proposed to allow non-intrusive debugging of an operational application, offering a robust development and testing phase. With real-time capability and providing insights at various operational stages, it ensures that users can have a contained yet exhaustive overview of their designs. DCD ensures a technology-agnostic design, meaning that this IP core ensures compatibility across all prominent FPGA and ASIC vendors, providing flexibility and convenience for a wide array of users. The DP8051CPU is delivered with a complete test bench and a series of validation sets, ensuring a smooth integration within any workflow.
The EMSA5-FS is a 32-bit embedded RISC-V processor from CAST designed with functional safety in mind, aimed specifically at mission-critical applications. This processor supports ISO 26262 ASIL-D compliance, a stringent safety standard required in automotive, industrial, and medical sectors. Key features include dual/triple modular redundancy, lockstep operations, and error-correcting code (ECC) protection, making it a robust choice for systems demanding high reliability and safety assurance. The EMSA5-FS processor not only satisfies functional safety requirements but also delivers competitive performance with low power draw, addressing the needs of applications where both efficiency and system integrity are critical.
Digital Core Design presents the D68000-CPU32+, a soft core microprocessor compatible with the 68000's CPU32+ architecture. With a 32-bit data bus and address bus, this core is optimized for high performance program execution and includes a built-in DoCD-BDM debugger interface, making it ideal for debugging complete SoC systems. Its support for 8-, 16-, and 32-bit unaligned/aligned data-bus transfers and a vast array of addressing modes offers flexibility in complex application development. Designed for universal compatibility across FPGA and ASIC vendors, the D68000-CPU32+ is delivered with a comprehensive suite of testbenches, automatic validation tests, and sculpted documentation. The architecture boasts advanced arithmetic and logic capabilities, making it suitable for a wide array of applications, from embedded systems to complex SoCs. With licensing methods streamlined for ease of access, utilizing the D68000-CPU32+ in various contexts is both simple and efficient.
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