All IPs > Processor > Building Blocks
Processor building blocks are fundamental components within the realm of semiconductor IPs that play a crucial role in the development and optimization of processors. These building blocks are indispensable for crafting sophisticated, high-performance processors required in a wide range of electronic devices, from handheld gadgets to large-scale computing systems.
Processor semiconductor IP building blocks include key elements such as arithmetic logic units (ALUs), registers, and control units, which integrate to form the central processing unit (CPU). Each of these components contributes to the overall functionality of the processor. ALUs enable the processor to perform arithmetic operations and logical decisions, while registers provide the necessary storage for quick data access. Control units are responsible for interpreting instructions and coordinating other components to execute tasks efficiently. Together, these building blocks ensure that processors perform at optimal levels, handling complex computational tasks with ease.
One of the primary uses of processor building blocks is in creating devices that require advanced computational power, such as smartphones, tablets, personal computers, and servers. These semiconductor IPs help in the design of custom processors that meet specific performance, power consumption, and cost requirements. By leveraging these building blocks, designers can develop processors that are tailored to particular applications, thereby enhancing the overall performance and efficiency of devices. This customizability also facilitates innovations in emerging technologies such as artificial intelligence, the Internet of Things (IoT), and autonomous vehicles, where processors need to handle rapidly growing workloads.
The processor building blocks category in our Silicon Hub encompasses a diverse range of semiconductor IPs that cater to different processing needs. From general-purpose processors with balanced performance to specialized processors with optimized functionalities, this category provides essential components for developing next-generation electronic solutions. By utilizing these building blocks, designers and engineers can push the boundaries of processing technology, creating more capable and efficient devices that meet the evolving demands of modern consumers and industries.
Axelera AI has crafted a PCIe AI acceleration card, powered by their high-efficiency quad-core Metis AIPU, to tackle complex AI vision tasks. This card provides an extraordinary 214 TOPS, enabling it to process the most demanding AI workloads. Enhanced by the Voyager SDK's streamlined integration capabilities, this card promises quick deployment while maintaining superior accuracy and power efficiency. It is tailored for applications that require high throughput and minimal power consumption, making it ideal for edge computing.
The Metis M.2 AI accelerator module from Axelera AI is a cutting-edge solution for embedded AI applications. Designed for high-performance AI inference, this card boasts a single quad-core Metis AIPU that delivers industry-leading performance. With dedicated 1 GB DRAM memory, it operates efficiently within compact form factors like the NGFF M.2 socket. This capability unlocks tremendous potential for a range of AI-driven vision applications, offering seamless integration and heightened processing power.
The xcore.ai platform from XMOS is engineered to revolutionize the scope of intelligent IoT by offering a powerful yet cost-efficient solution that combines high-performance AI processing with flexible I/O and DSP capabilities. At its heart, xcore.ai boasts a multi-threaded architecture with 16 logical cores divided across two processor tiles, each equipped with substantial SRAM and a vector processing unit. This setup ensures seamless execution of integer and floating-point operations while facilitating high-speed communication between multiple xcore.ai systems, allowing for scalable deployments in varied applications. One of the standout features of xcore.ai is its software-defined I/O, enabling deterministic processing and precise timing accuracy, which is crucial for time-sensitive applications. It integrates embedded PHYs for various interfaces such as MIPI, USB, and LPDDR, enhancing its adaptability in meeting custom application needs. The device's clock frequency can be adjusted to optimize power consumption, affirming its cost-effectiveness for IoT solutions demanding high efficiency. The platform's DSP and AI performances are equally impressive. The 32-bit floating-point pipeline can deliver up to 1600 MFLOPS with additional block floating point capabilities, accommodating complex arithmetic computations and FFT operations essential for audio and vision processing. Its AI performance reaches peaks of 51.2 GMACC/s for 8-bit operations, maintaining substantial throughput even under intensive AI workloads, making xcore.ai an ideal candidate for AI-enhanced IoT device creation.
ISPido on VIP Board is a customized runtime solution tailored for Lattice Semiconductors’ Video Interface Platform (VIP) board. This setup enables real-time image processing and provides flexibility for both automated configuration and manual control through a menu interface. Users can adjust settings via histogram readings, select gamma tables, and apply convolutional filters to achieve optimal image quality. Equipped with key components like the CrossLink VIP input bridge board and ECP5 VIP Processor with ECP5-85 FPGA, this solution supports dual image sensors to produce a 1920x1080p HDMI output. The platform enables dynamic runtime calibration, providing users with interface options for active parameter adjustments, ensuring that image settings are fine-tuned for various applications. This system is particularly advantageous for developers and engineers looking to integrate sophisticated image processing capabilities into their devices. Its runtime flexibility and comprehensive set of features make it a valuable tool for prototyping and deploying scalable imaging solutions.
DolphinWare IPs is a versatile portfolio of intellectual property solutions that enable efficient SoC design. This collection includes various control logic components such as FIFO, arbiter, and arithmetic components like math operators and converters. In addition, the logic components span counters, registers, and multiplexers, providing essential functionalities for diverse industrial applications. The IPs in this lineup are meticulously designed to ensure data integrity, supported by robust verification IPs for AXI4, APB, SD4.0, and more. This comprehensive suite meets the stringent demands of modern electronic designs, facilitating seamless integration into existing design paradigms. Beyond their broad functionality, DolphinWare’s offerings are fundamental to applications requiring specific control logic and data integrity solutions, making them indispensable for enterprises looking to modernize or expand their product offerings while ensuring compliance with industry standards.
SCR1 is an open-source and silicon-proven microcontroller core, tailored for deeply embedded applications. This 32-bit RISC-V core supports the standard ISA with optional extensions for multiplication, division, and compressed instructions. The design comprises a simple in-order 4-stage pipeline, providing efficient interrupt handling with an IPIC unit. It connects seamlessly with various interfaces, including AXI4, AHB-Lite, and JTAG, enhancing its adaptability across different systems. The SCR1 core boasts a Tightly-Coupled Memory (TCM) subsystem supporting up to 64KB. It features up to 16 interrupt lines and a range of performance monitoring tools making it ideal for IoT, control systems, and smart card applications. Pre-configured software development tools, including IDEs like Eclipse and Visual Studio Code plugins, complement the core, enabling developers to quickly deploy applications tailored to SCR1’s architecture. Additionally, SCR1 comes packaged with a rich suite of documentation and pre-configured FPGA-based SDK, ensuring a smooth transition from development to implementation. Its GPL-compliant open-source license ensures flexibility for commercial and educational use, making it a versatile choice for a wide range of projects.
aiWare stands out as a premier hardware IP for high-performance neural processing, tailored for complex automotive AI applications. By offering exceptional efficiency and scalability, aiWare empowers automotive systems to harness the full power of neural networks across a wide variety of functions, from Advanced Driver Assistance Systems (ADAS) to fully autonomous driving platforms. It boasts an innovative architecture optimized for both performance and energy efficiency, making it capable of handling the rigorous demands of next-generation AI workloads. The aiWare hardware features an NPU designed to achieve up to 256 Effective Tera Operations Per Second (TOPS), delivering high performance at significantly lower power. This is made possible through a thoughtfully engineered dataflow and memory architecture that minimizes the need for external memory bandwidth, thus enhancing processing speed and reducing energy consumption. The design ensures that aiWare can operate efficiently across a broad range of conditions, maintaining its edge in both small and large-scale applications. A key advantage of aiWare is its compatibility with aiMotive's aiDrive software, facilitating seamless integration and optimizing neural network configurations for automotive production environments. aiWare's development emphasizes strong support for AI algorithms, ensuring robust performance in diverse applications, from edge processing in sensor nodes to high central computational capacity. This makes aiWare a critical component in deploying advanced, scalable automotive AI solutions, designed specifically to meet the safety and performance standards required in modern vehicles.
ISPido represents a fully configurable RTL Image Signal Processing Pipeline, adhering to the AMBA AXI4 standards and tailored through the AXI4-LITE protocol for seamless integration with systems such as RISC-V. This advanced pipeline supports a variety of image processing functions like defective pixel correction, color filter interpolation using the Malvar-Cutler algorithm, and auto-white balance, among others. Designed to handle resolutions up to 7680x7680, ISPido provides compatibility for both 4K and 8K video systems, with support for 8, 10, or 12-bit depth inputs. Each module within this pipeline can be fine-tuned to fit specific requirements, making it a versatile choice for adapting to various imaging needs. The architecture's compatibility with flexible standards ensures robust performance and adaptability in diverse applications, from consumer electronics to professional-grade imaging solutions. Through its compact design, ISPido optimizes area and energy efficiency, providing high-quality image processing while keeping hardware demands low. This makes it suitable for battery-operated devices where power efficiency is crucial, without sacrificing the processing power needed for high-resolution outputs.
The SCR6 is a high-performance microcontroller core optimized for demanding embedded applications requiring substantial computational power. Its out-of-order 12-stage pipeline, complemented by a superscalar architecture, enhances processing speeds, making it ideal for real-time systems. Supporting a wide range of RISC-V ISA extensions, including cryptography and bit manipulation, SCR6 caters to secure and efficient data operations. The SCR6's memory subsystem is robust, featuring dual-level caches augmented with an L3 network-on-chip option. This rich memory architecture, along with efficient interrupt processing via APLIC units, ensures smooth high-speed data throughput in intensive applications. The core supports heterogeneous multicore configurations, enhancing parallel task execution. Designed for industrial and IoT environments, SCR6 comes with extensive development support. Its toolkit includes simulations, FPGA-based SDKs, and integration resources, facilitated through industry-standard interfaces, ensuring rapid development cycles and application deployment.
The SCR4 core is a high-performance, area-efficient RISC-V processor with floating-point computation capabilities. Targeting mobile and industrial applications, it supports both single and double precision, adhering to IEEE 754-2008 standards. Its instruction set is complete with advanced extensions, including atomic and cryptography functions for secure and efficient operations. With a powerful 5-stage in-order pipeline and a dedicated FPU, the SCR4 can handle complex mathematical tasks swiftly. Its memory architecture features both L1 and L2 caches, alongside a TCM unit, enabling rapid data access and management essential in real-time environments. Incorporating a robust branch prediction unit and support for multicore setups, the SCR4 excels in environments demanding synchronized computing tasks across multiple processors. It’s supported by comprehensive development kits and detailed documentation to expedite the design and implementation processes across diverse platforms.
The UHS-II solution is crafted to enhance data transfer rates within low-voltage environments. It particularly supports high-definition content transmission, which is critical for modern mobile devices requiring seamless streaming and heavy data loads. Utilizing a modular design approach, it ensures a robust and efficient layout that facilitates optimal performance and reliability.
The SCR3 core by Syntacore is a silicon-proven microcontroller aimed at applications requiring both high performance and power efficiency. This 32/64-bit processor core supports a variety of RISC-V standard extensions, including atomic operations and bit manipulation, optimizing it for real-time applications needing reliable interrupt handling through its PLIC, ACLINT, and IPIC units. It features a 5-stage in-order pipeline paired with branch prediction and cache systems to enhance speed and execution efficiency. With considerable support for seamless memory operations, it includes both L1 and L2 caches and a TCM unit capable of housing up to 256KB of data, alongside an integrated Memory Protection Unit for executing multiple privilege modes. Ideal for industrial automation and IoT usage, the SCR3 core facilitates multicore operations with cache coherency for up to 4 simultaneous cores. Extensive development tools are provided, including simulators, IDE support, and a comprehensive FPGA-based SDK, allowing for immediate application development and deployment.
PACE, or Photonic Arithmetic Computing Engine, represents a significant leap forward in computing by using optical components to perform mathematical operations. This breakthrough allows for speed and efficiency improvements that are hard to replicate with traditional electronic designs. The PACE engine is engineered to accelerate the execution of complex algorithms, essential for high-performance applications such as artificial intelligence and large-scale data processing. With its ability to process computations at the speed of light, it opens new avenues for ultra-fast data analysis, making it a pivotal tool for industries relying on rapid data processing and intelligence. Emphasizing low energy consumption, PACE leverages the inherent energy efficiency of photonic processes, minimizing the power requirements compared to electronic counterparts. This feature is crucial for sustainability, reducing the overall energy footprint of data centers and large computing facilities. The engine's design is not only focused on speed but also on operational stability, ensuring consistent performance under intensive computational loads. Integration with existing systems is seamless, as PACE is compatible with current technological infrastructures. This compatibility ensures that businesses can adopt this advanced technology with minimal disruption, enhancing their computational capabilities without the need for extensive overhauls. The photonic nature of the PACE engine ensures future scalability, aligning with the evolving demands of data-driven industries.
The RISC-V CPU IP N Class from Nuclei System Technology offers a versatile 32-bit architecture designed for microcontroller units (MCUs) and AIoT applications. Engineered with the RISC-V open standard, this processor IP provides extensive configurability options, allowing users to tailor the IP to meet their specific system requirements. It supports a variety of security features and functional safety protocols, making it suitable for applications demanding reliable and robust performance. This CPU IP is perfect for those implementing advanced RISC-V technology in fields that require agility and cutting-edge functionality. Its ease of customization ensures seamless integration into existing systems, supporting an array of ecosystem resources such as tool-chains, SDKs, and support for operating systems including RTOS and Linux. With a local R&D team backing its development, the N Class IP sees rapid iteration and enhancement, aligning with the technological demands and trends in high-performance computing. This positions it as a leading choice for firms looking to adopt RISC-V technology in innovative and emergent applications.
Syntacore's SCR5 is an efficient application-class processor core, crafted to deliver exceptional performance with Linux compatibility. It integrates a 9-stage in-order pipeline along with floating-point capabilities, making it suitable for diverse processing tasks. Adopting the latest RISC-V ISA extensions, SCR5 ensures high-speed computations and secure operations equipped with bit manipulation and cryptography features. The SCR5’s robust memory subsystem ensures data integrity and rapid access, featuring L1 and L2 caches, a TCM, and an MMU. High-performance multicore support extends up to four cores, promoting parallel processing capabilities necessary in industrial and IoT environments. Its interface support, including JTAG and AXI4, streamlines integration into varied infrastructures. For developers, the SCR5 core is accompanied by advanced toolkits designed to accelerate application deployment. These include pre-built OS options and native toolchains, all backed by thorough documentation to enhance the development lifecycle.
Monolithic Microsystems represents a technological leap in integrated system design, featuring multiple micro-engineered elements within a single chip. This system leverages advanced CMOS technology to unify electronic, photonic, and micromechanical devices, creating a compact and efficient platform suited for a variety of applications. By integrating different functionalities within a single substrate, these Microsystems can enhance performance while reducing the overall system footprint. They are increasingly being used in fields such as telecommunications, medical devices, and consumer electronics, where precision, reliability, and miniaturization are of paramount importance.
The iCan PicoPop® System on Module (SOM) by Oxytronic is an ultra-compact computing solution designed for high-performance and space-constrained environments within the aerospace industry. Utilizing the Xilinx Zynq UltraScale+ MPSoC, this module delivers significant processing power ideal for complex signal processing and other demanding tasks. This module's design caters to embedded system applications, offering robust capabilities in avionics where size, weight, and power efficiency are critical considerations. It provides core functionalities that support advanced video processing, making it a pivotal component for those requiring cutting-edge technological support in minimal form factors. Oxytronic ensures that the iCan PicoPop® maintains compatibility with a wide range of peripherals, facilitating easy integration into existing systems. Its architectural innovation signifies Oxytronic's understanding of aviation challenges, providing solutions that are both technically superior and practically beneficial for modern aerospace applications.
The RAIV General Purpose GPU (GPGPU) epitomizes versatility and cutting-edge technology in the realm of data processing and graphics acceleration. It serves as a crucial technology enabler for various prominent sectors that are central to the fourth industrial revolution, such as autonomous driving, IoT, virtual reality/augmented reality (VR/AR), and sophisticated data centers. By leveraging the RAIV GPGPU, industries are able to process vast amounts of data more efficiently, which is paramount for their growth and competitive edge. Characterized by its advanced architectural design, the RAIV GPU excels in managing substantial computational loads, which is essential for AI-driven processes and complex data analytics. Its adaptability makes it suitable for a wide array of applications, from enhancing automotive AI systems to empowering VR environments with seamless real-time interaction. Through optimized data handling and acceleration, the RAIV GPGPU assists in realizing smoother and more responsive application workflows. The strategic design of the RAIV GPGPU focuses on enabling integrative solutions that enhance performance without compromising on power efficiency. Its functionality is built to meet the high demands of today’s tech ecosystems, fostering advancements in computational efficiency and intelligent processing capabilities. As such, the RAIV stands out not only as a tool for improved graphical experiences but also as a significant component in driving innovation within tech-centric industries worldwide. Its pioneering architecture thus supports a multitude of applications, ensuring it remains a versatile and indispensable asset in diverse technological landscapes.
The Universal DSP Library from Enclustra offers robust FPGA implementations for commonly used digital signal processing tasks, such as FIR and CIC filters, mixers, and function approximations. Designed to reduce development time, every component comes as VHDL source code and as a block in the AMD Vivado ML Design Suite IPI framework. This setup allows for rapid building of processing chains using either the GUI or direct VHDL instantiation. The library supports multi-channel data processing, both parallel and TDM, and is geared towards minimizing integration complexity while maximizing performance.
iCEVision facilitates rapid prototyping and evaluation of connectivity features using the Lattice iCE40 UltraPlus FPGA. Designers can take advantage of exposed I/Os for quick implementation and validation of solutions, while enjoying compatibility with common camera interfaces such as ArduCam CSI and PMOD. This flexibility is complemented by software tools such as the Lattice Diamond Programmer and iCEcube2, which allow designers to reprogram the onboard SPI Flash and develop custom solutions. The platform comes preloaded with a bootloader and an RGB demo application, making it quick and easy for users to begin experimenting with their projects. Its design includes features like a 50mmx50mm form factor, LED applications, and multiple connectivity options, ensuring broad usability across various rapid prototyping scenarios. With its user-friendly setup and comprehensive toolkit, iCEVision is perfect for developers who need a streamlined path from initial design to functional prototype, especially in environments where connectivity and sensor integration are key.
Engineered to deliver versatility and speed, the Universal High-Speed SERDES supports data rates ranging from 1G to 12.5Gbps, making it suitable for a variety of high-speed data applications. This SERDES core is designed to cater to multiple industry standards such as RapidIO, Fibre Channel, and XAUI, providing a flexible solution for high-bandwidth data transmission needs. The SERDES offers dynamic settings with programmable data widths of 16, 20, 32, and 40 bits, allowing customization to meet specific performance and power consumption targets. Featuring both fixed-feedforward equalization and adaptive receiver equalization, the SERDES maintains data integrity over long transmission channels while minimizing signal distortion. A critical aspect of this design is its ability to operate without any external components, which facilitates streamlined integration and reduces system complexity. Its capability to support various packaging and channel configurations further enhances its adaptability, making it a robust choice for a wide range of high-performance applications.
The RISC-V CPU IP NX Class offers a robust 64-bit architecture tailored for storage solutions, augmented reality/virtual reality (AR/VR), and artificial intelligence (AI) applications. This offering from Nuclei System Technology exemplifies scalability and flexibility, adhering to the RISC-V open standard to deliver a processor IP that is both versatile and high performing. This class of IP ensures that businesses can integrate sophisticated computational capabilities into their products, enhancing functionality in storage and emerging technology fields. The NX Class supports a wide array of security and functional safety features, ensuring reliable performance across various high-tech scenarios. With continued advancements and support from the local R&D team, the NX Class is equipped to meet the evolving demands of cutting-edge technology sectors, facilitating innovation and superior performance in complex environments where these attributes are crucial.
The Prodigy Universal Processor by Tachyum is a breakthrough in processor technology, integrating the functionalities of CPUs, GPGPUs, and TPUs within a single architecture to deliver exceptional performance and energy efficiency. With its ability to tackle different computing demands from AI to high-performance workloads, the Prodigy sets a new paradigm in processing capabilities. Tachyum's Prodigy processors deliver up to 18 times higher performance compared to conventional systems, while also achieving six times better performance per watt. This makes it a highly efficient option for data centers, reducing not only energy consumption but also operational costs significantly, an imperative in today's energy-conscious world. The Prodigy processor seamlessly supports standard software packages, allowing current applications to run without modifications. This capability ensures that enterprises can transition to more powerful computing environments without incurring additional development costs. Moreover, its inherent multipurpose design supports a broad spectrum of AI applications, from machine learning to advanced data analytics.
The BA51 represents an ultra-low-power RISC-V processor core, particularly optimized for deep embedding in a variety of applications. It is built on a 32-bit architecture with a 2-stage pipeline, facilitating reduced power consumption and minimized silicon area. This processor core caters to energy-constrained environments by incorporating advanced power management techniques like clock gating and frequency scaling. It can achieve clock speeds exceeding 500 MHz at 16nm technology, making it competitive for IoT devices and low-power consumer electronics, where minimal energy expenditure is crucial.
Nuclei's RISC-V CPU IP UX Class offers an advanced 64-bit architecture complete with MMU, engineered to cater to expansive applications such as Linux environments, data centers, and networking tasks. Built on the RISC-V open standard, it provides significant adaptability, ensuring it can be tailored to meet specific project and system requirements effectively. The UX Class processor IP is particularly suited for scenarios that require high-performance computing with enhanced capabilities in functional safety and security. This class facilitates seamless integration with leading ecosystem resources, offering an edge for teams developing in complex, data-intensive environments. By maintaining a focus on scalable solutions and user-definable extensions, Nuclei System Technology empowers clients with a rich set of features to drive innovation in their projects. Its adaptable architecture plays a pivotal role in ensuring efficient operation in modern technology landscapes, supporting critical infrastructures demanding substantial processing power and flexibility.
Utilizing the AVR Instruction Set Architecture, the YVR processor operates using a 2-clock machine cycle, providing a balanced performance for embedded applications. Its efficient processing capabilities make it suitable for projects requiring reliable, quick execution and maximum use of processing resources within the constraints of the AVR framework. This processor meets the needs of systems where fast operation is paramount without sacrificing computational integrity.
Nuclei's RISC-V CPU IP U Class is a powerful 32-bit architecture supplemented with a memory management unit (MMU), specifically targeting Linux-based and edge computing scenarios. This processor IP is constructed to support intricate applications that necessitate efficient resource handling and robust security measures. Designed under the RISC-V open standard, the U Class offers substantial flexibility in configuration, enabling precise tuning to align with diverse application requirements. It boasts support for critical aspects like security protocols and functional safety, catering to high-stakes environments that demand uncompromising reliability and performance. The U Class IP is integral for companies transitioning to more advanced computational solutions, offering enhancements that support complex operations while maintaining efficient power and resource usage. Its alignment with state-of-the-art ecosystem resources further elevates its functionality, ensuring seamless integration and execution in sophisticated technological applications.
The EMSA5-FS is a RISC-V-based functional safety processor core designed with a focus on high reliability and integration ease for any ASIC or FPGA deployment. It boasts a 5-stage pipeline architecture, supporting a wide range of RISC-V ISA configurations, including optional floating-point and vector extensions. Offering a comprehensive functional safety package, this core is tailored for automotive and industrial systems needing compliance with stringent safety standards, such as ISO 26262. Its dual or triple modular redundancy, alongside error-correcting code support, ensures high fault tolerance. The EMSA5-FS features flexible clock frequency scaling and dynamic power management, enhancing both its energy efficiency and performance.
The Cortex-A725 Processor is a high-efficiency, out-of-order CPU designed to elevate consumer devices like gaming consoles and smart TVs. Utilizing the latest Armv9.2 architecture, it provides enhanced performance within a constrained power envelope. It offers advanced support for AAA gaming, ensuring smooth operation in power-limited environments while providing sustained performance. Ideal for devices requiring a fine balance between computing power and energy efficiency.
The BA53 is a low-power RISC-V processor core engineered for deeply embedded applications requiring efficient performance with minimal energy usage. Built on a single-issue 32-bit 5-stage pipeline, this core can operate at speeds over 1 GHz using a 22nm fabrication process. Its small gate count, coupled with power-saving mechanisms such as clock gating and adjustable frequency, makes it an ideal choice for energy-conscious solutions in consumer electronics and device controllers. The BA53 is intended for applications that prioritize high computing performance within constrained power budgets, ensuring lasting operation even in battery-driven products.
Designed for high-performance and data-intensive computation, the Akeana 1000 Series delivers a versatile 64-bit RISC-V processor solution. These processors support a variety of applications, ranging from industrial automation to automotive sensing, thanks to their flexible configuration options. The architecture supports in-order and out-of-order execution strategies and multi-threaded capabilities, offering up to quad-issue instruction widths. This range of functionality ensures that customers have a powerful tool to tackle extensive computational tasks, making it ideal for scenarios demanding high throughput and efficiency.
The xcore-200 series stands out with its capability to offer robust solutions for the Internet of Things, providing phenomenal computation, DSP, IO, and control in a consolidated architecture. This series is divided into three device classes: the XU series supports USB interfaces, the XE series facilitates gigabit ethernet applications, and the XL series offers flash memory inclusion. This stratification allows designers to select solutions that are optimally aligned with their application's requirements, without compromising on performance. Within the xcore-200, processing efficiency is elevated via a dual-issue processor pipeline, which aids in boosting compute performance significantly, even under constrained conditions. The chip's design can house between 8 to 32 logical cores, supporting dynamic task executions that include but are not limited to, complex DSP and standard computational operations. This flexibility extends to its communication protocol with a high-speed internal switch facilitating inter-core data transfer, enhancing the chip's utility in multi-threaded workloads. Complementing its processing prowess, the xcore-200 features configurable I/O ports that bolster serial and parallel data operations, making it ideal for applications necessitating high-speed, real-time interaction with external systems. Additionally, the series incorporates secure boot features and on-chip memory ranging from 512KB to 1024KB, ensuring both operational security and ample data handling capacity.
Designed for use in a wide range of application processing needs, the BA25 is a 32-bit processor core from CAST's BA2X family. Famous for its versatile application processor capabilities, the BA25 excels in compute-intensive operations with its efficient pipeline architecture. It supports high-speed execution, thanks to its optimized instruction sets and scalable power management features. This core is well-suited for integration into complex systems requiring robust processing power without compromising on power efficiency, making it ideal for advanced consumer electronics and multi-functional IoT devices.
The Akeana 100 Series consists of 32-bit RISC-V processors tailored for deeply embedded applications. With a focus on highly customizability, these processors cater to requirements from basic microcontrollers to more complex edge gateways. Their architecture emphasizes ultra-small footprint and low power consumption, ideal for real-time applications. An efficient in-order pipeline and a variety of memory configurations, including closely-coupled memory, enhance performance for embedded applications such as smart devices and wearables. The series offers a wide range of standard configurations, ensuring versatility and adaptability for specific computational needs.
The 5000 Series from Akeana represents the pinnacle of performance in their processing lineup, suited for ultra-high performance tasks across cloud, data center, and mobile computing sectors. Built on a 64-bit RISC-V foundation, these processors are designed to support advanced operating systems and high-frequency operations. Featuring an elaborate out-of-order pipeline and extensive thread management capabilities, they handle substantial computational loads efficiently. The series supports a variety of virtualization and coherent processing needs, making it a prime choice for data-intensive environments requiring robust performance and scalability.
DRV32IMZicsr – Scalable RISC-V Power. Tailored for Your Project. Ready for the Future. The DRV32IMZicsr is a high-performance, 32-bit RISC-V processor core, equipped with M (Multiply/Divide), Zicsr (Control and Status Registers), and External Debug support. Built as part of DCD’s latest DRVX Core Family, it delivers the full flexibility, openness, and innovation that RISC-V promises—without locking you into proprietary architectures. ✅ Why RISC-V? RISC-V is a rapidly growing open standard for modern computing—backed by a global ecosystem of developers and vendors. It brings: * Freedom from licensing fees and vendor lock-in * Scalability from embedded to high-performance systems * Customizability with standard and custom instruction sets * Strong toolchain & ecosystem support 🚀 DRV32IMZicsr Highlights: * Five-stage pipeline and Harvard architecture for optimized performance * Configurable memory architecture: size and address allocation tailored to your needs Performance metrics: * **Up to 1.15 DMIPS/MHz** * **Up to 2.36 CoreMark/MHz** * Minimal footprint starting from just 14k gates * Flexible interfaces: Choose from AXI, AHB, or native bus options 🛡️ Designed for Safety & Integration: * Developed as an ISO 26262 Safety Element out of Context (SEooC) * Fully technology-agnostic, compatible with all FPGA and ASIC platforms * Seamless integration with DCD’s rich portfolio of IPs: DMA, SPI, UART, PWM, CAN, and more 🔍 Advanced Feature Set: * 32 general-purpose registers * Support for arithmetic, logic, load/store, conditional and unconditional control flow * M extension enables efficient integer multiplication/division * Zicsr extension provides robust interrupt and exception handling, performance counters, and timers * External Debug via JTAG: compliant with RISC-V Debug Specification 0.13.2 and 1.0.0, compatible with all mainstream tools 🧪 Developer-Ready: * Delivered with a fully automated testbench * Includes a comprehensive validation test suite for smooth integration into your SoC flow Whether you're building for automotive, IoT, consumer electronics, or embedded systems, the DRV32IMZicsr offers a future-ready RISC-V solution—highly configurable, performance-optimized, and backed by DCD’s 25 years of experience. Interested? Let’s build the next generation together. 📩 Contact us at info@dcd.pl
**DRV64IMZicsr – 64-bit RISC-V Performance. Designed for Demanding Innovation.** The DRV64IMZicsr is a powerful and versatile 64-bit RISC-V CPU core, built to meet the performance and safety needs of next-generation embedded systems. Featuring the M (Multiply/Divide), Zicsr (Control and Status Registers), and External Debug extensions, this core is engineered to scale—from edge computing to mission-critical applications. As part of the DRVX Core Family, the DRV64IMZicsr embodies DCD’s philosophy of combining open-standard freedom with customizable IP excellence—making it a smart and future-proof alternative to legacy architectures. ✅ Why Choose RISC-V? * No license fees – open-source instruction set means reduced TCO * Unmatched flexibility – tailor the architecture to your specific needs * A global, thriving ecosystem – support from toolchains, OSes, and hardware vendors * Security & longevity – open and verifiable architecture ensures trust and sustainability 🚀 DRV64IMZicsr – Core Advantages: * 64-bit RISC-V ISA with M, Zicsr, and Debug support * Five-stage pipeline, Harvard architecture, and efficient branch prediction * Configurable memory size and allocation for program and data spaces Performance optimized: * **Up to 2.38 CoreMark/MHz** * **Up to 1.17 DMIPS/MHz** * Compact footprint starting from just 17.6k gates * Interface options: AXI, AHB, or native * Compatible with Classical CAN, CAN FD, and CAN XL through additional IPs 🛡️ Safety, Compatibility & Flexibility Built In: * Developed as an ISO 26262 Safety Element out of Context (SEooC) * Technology-agnostic – works seamlessly across all FPGA and ASIC vendors * Expandable with DCD’s IP portfolio: DMA, SPI, UART, I²C, CAN, PWM, and more 🔍 Robust Feature Set for Real Applications: * Full 64-bit processing – ideal for performance-intensive, memory-heavy tasks * M extension enables high-speed multiplication/division via dedicated hardware unit * Zicsr extension gives full access to Control and Status Registers, enabling: * Interrupts and exception handling (per RISC-V Privileged Spec) * Performance counters and timers * JTAG-compatible debug interface – compliant with RISC-V Debug Spec (0.13.2 & 1.0.0) 🧪 Ready for Development & Integration: * Comes with a fully automated testbench * Includes a comprehensive suite of validation tests for smooth SoC integration * Supported by industry-standard tools, ensuring a hassle-free dev experience Whether you’re designing for automotive safety, industrial control, IoT gateways, or AI-enabled edge devices, the DRV64IMZicsr gives you the performance, flexibility, and future-readiness of RISC-V—without compromise. 💡 Build smarter, safer systems—on your terms. 📩 Contact us today at info@dcd.pl to start your next RISC-V-powered project.
Designed to push the boundaries of AI performance, this PCIe card from Axelera AI features four Metis AIPUs working in tandem. It accomplishes an impressive peak throughput of 856 TOPS. This solution is particularly suitable for handling challenging vision applications and supports a vast array of neural networks. Utilizing the Voyager SDK, developers can easily accelerate the deployment of AI applications. The card caters to industries that demand high-speed data processing and efficient power usage, thus proving essential for cutting-edge AI projects.
The DF6802 is an 8-bit synthesizable MPU IP Core, software-compatible with Motorola MC6802. It features an enhanced internal architecture for approximately 4 times faster execution than the original 6802 chip at the same clock frequency. Designed with two power-saving modes (WAIT and HALT), the DF6802 is ideal for automotive and battery-driven applications. It is fully customizable, allowing for a configuration that meets specific user needs, without extra costs for unused features. The IP Core comes equipped with a fully automated testbench and a comprehensive set of test cases for smooth package validation. Moreover, the DF6802 supports DCD’s Hardware Debug System, DoCD™, which offers real-time, non-intrusive debugging across the entire SoC, including the ability to halt, run, step into, or skip instructions, and read/write data to any part of the microprocessor. With support for a wide range of interfaces such as USB, Ethernet, I2C, SPI, UART, CAN, LIN, HDLC, and Smart Card, the DF6802 shows versatile connectivity while ensuring efficient power and performance optimization. The DF6802 is technology agnostic, ensuring compatibility with all FPGA and ASIC vendors. It comes with extensive deliverables including synthesizable RTL, testbench environment, simulation macros, synthesis scripts, and complete technical documentation along with 12 months of technical support.
The MIPS I8500 multiprocessor embodies a groundbreaking architecture tailored for environments seeking innovative solutions in high-demand computing arenas. Designed to optimize robust data handling, it employs a highly scalable multi-core setup with 4-way simultaneous multithreading capabilities. This feature-rich processing unit is aimed toward applications that necessitate aggressive computation, such as those found in industrial and automotive settings.\n\nEngineered to enhance system performance, the I8500 leverages triple-issue in-order logic, an attribute that boosts not just execution speed but also operational efficiency. Its support for extensive multithreading ensures that processes can be managed concurrently without delays, reducing latency and improving throughput. This characteristic is critical for real-time applications where performance reliability cannot be compromised.\n\nBesides building upon cutting-edge performance metrics, the I8500 adheres to high safety standards, incorporating ASIL-B certification for automotive uses. These enhancements make it an ideal candidate for leveraging AI capabilities and real-time data operations across disparate technology fields. Its architecture's adaptability further allows for seamless integration into existing systems, paving the path for scalable and customizable solutions in embedded and general-purpose computing markets.
Digital Core Design presents the D68000-CPU32+, a soft core microprocessor compatible with the 68000's CPU32+ architecture. With a 32-bit data bus and address bus, this core is optimized for high performance program execution and includes a built-in DoCD-BDM debugger interface, making it ideal for debugging complete SoC systems. Its support for 8-, 16-, and 32-bit unaligned/aligned data-bus transfers and a vast array of addressing modes offers flexibility in complex application development. Designed for universal compatibility across FPGA and ASIC vendors, the D68000-CPU32+ is delivered with a comprehensive suite of testbenches, automatic validation tests, and sculpted documentation. The architecture boasts advanced arithmetic and logic capabilities, making it suitable for a wide array of applications, from embedded systems to complex SoCs. With licensing methods streamlined for ease of access, utilizing the D68000-CPU32+ in various contexts is both simple and efficient.
DP8051CPU is an ultra high performance 8-bit soft core microcontroller designed by DCD-SEMI to be highly efficient in terms of speed and power consumption. With a pipelined RISC architecture, it can perform operations remarkably faster than the traditional 80C51, with its performance metrics standing up to 15.55 times its predecessor when benchmarked using Dhrystone 2.1. The architecture supports both Harvard and von Neumann configurations, increasing the flexibility for memory access and inclusion. The microcontroller is equipped with an advanced Power Management Unit, allowing it to maintain its high performance capabilities while optimizing power consumption. Targeted for carrying out operations with both fast on-chip memory and slower off-chip alternatives, it can process up to 300 million instructions per second while managing substantial code and data spaces efficiently. Furthermore, it is 100% compatible with the industry-standard 8051 microcontrollers in terms of binary operation, making it highly suitable for integration in existing systems. It boasts of supporting a wide variety of interfaces like USB, Ethernet, I2C, SPI, UART, and many others, which adds to the scope of applications, especially in portable and power-conscious devices. The microcontroller supports a comprehensive hardware debugging system (DoCD™), uniquely proposed to allow non-intrusive debugging of an operational application, offering a robust development and testing phase. With real-time capability and providing insights at various operational stages, it ensures that users can have a contained yet exhaustive overview of their designs. DCD ensures a technology-agnostic design, meaning that this IP core ensures compatibility across all prominent FPGA and ASIC vendors, providing flexibility and convenience for a wide array of users. The DP8051CPU is delivered with a complete test bench and a series of validation sets, ensuring a smooth integration within any workflow.
The XpressVUP-LP9PT3 deploys the power of the AMD Virtex® UltraScale+™ VU9P-3 FPGA in a low-profile PCIe form factor. This board is tailored for HFT (high frequency trading) and ultra-low latency operations, making it indispensable in finance and fintech applications that require rapid data processing and decision-making. Equipped with DDR4 and QDR2+ memory banks, it provides robust multi-threaded data handling capabilities and networking solutions for 10 GbE, 40 GbE, and 100 GbE environments. Its design incorporates a dual-slot active heatsink for significant heat management, supporting high-demand computational tasks. This PCIe board is geared for intensive environments, from HPC (high-performance computing) setups to cutting-edge networking infrastructures, ensuring top-tier performance and reliability.
The GR801 is an advanced neuromorphic AI engine designed to work alongside a core RISC-V processor. This IP is engineered specifically to enhance computational capacity for AI applications, especially in environments that are challenging or with limited resources. It offers a unique hybrid processing capability combining traditional RISC-V architecture with cutting-edge neuromorphic computing, significantly advancing the performance in data-intensive tasks. Harnessing the capabilities of neuromorphic engineering, the GR801 provides unparalleled support for machine learning tasks in space missions, enabling adaptive and intelligent processing that can handle unexpected scenarios or anomalies autonomously. Its architecture is optimized to process large volumes of data efficiently, making it suitable for real-time analytics and decision-making processes required in critical missions. The GR801's adaptability makes it a preferred choice for mission planners looking to integrate AI capabilities into their systems without compromising on power efficiency or reliability. By combining conventional microprocessor elements with AI-specific processing capabilities, it stands as a powerful tool for addressing the emerging needs of space exploration and various high-reliability applications.
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