All IPs > Processor > Building Blocks
Processor building blocks are fundamental components within the realm of semiconductor IPs that play a crucial role in the development and optimization of processors. These building blocks are indispensable for crafting sophisticated, high-performance processors required in a wide range of electronic devices, from handheld gadgets to large-scale computing systems.
Processor semiconductor IP building blocks include key elements such as arithmetic logic units (ALUs), registers, and control units, which integrate to form the central processing unit (CPU). Each of these components contributes to the overall functionality of the processor. ALUs enable the processor to perform arithmetic operations and logical decisions, while registers provide the necessary storage for quick data access. Control units are responsible for interpreting instructions and coordinating other components to execute tasks efficiently. Together, these building blocks ensure that processors perform at optimal levels, handling complex computational tasks with ease.
One of the primary uses of processor building blocks is in creating devices that require advanced computational power, such as smartphones, tablets, personal computers, and servers. These semiconductor IPs help in the design of custom processors that meet specific performance, power consumption, and cost requirements. By leveraging these building blocks, designers can develop processors that are tailored to particular applications, thereby enhancing the overall performance and efficiency of devices. This customizability also facilitates innovations in emerging technologies such as artificial intelligence, the Internet of Things (IoT), and autonomous vehicles, where processors need to handle rapidly growing workloads.
The processor building blocks category in our Silicon Hub encompasses a diverse range of semiconductor IPs that cater to different processing needs. From general-purpose processors with balanced performance to specialized processors with optimized functionalities, this category provides essential components for developing next-generation electronic solutions. By utilizing these building blocks, designers and engineers can push the boundaries of processing technology, creating more capable and efficient devices that meet the evolving demands of modern consumers and industries.
The Metis AIPU PCIe AI Accelerator Card offers exceptional performance for AI workloads demanding significant computational capacity. It is powered by a single Metis AIPU and delivers up to 214 TOPS, catering to high-demand applications such as computer vision and real-time image processing. This PCIe card is integrated with the Voyager SDK, providing developers with a powerful yet user-friendly software environment for deploying complex AI applications seamlessly. Designed for efficiency, this accelerator card stands out by providing cutting-edge performance without the excessive power requirements typical of data center equipment. It achieves remarkable speed and accuracy, making it an ideal solution for tasks requiring fast data processing and inference speeds. The PCIe card supports a wide range of AI application scenarios, from enhancing existing infrastructure capabilities to integrating with new, dynamic systems. Its utility in various industrial settings is bolstered by its compatibility with the suite of state-of-the-art neural networks provided in the Axelera AI ecosystem.
The Metis AIPU M.2 Accelerator Module is designed for edge AI applications that demand high-performance inference capabilities. This module integrates a single Metis AI Processing Unit (AIPU), providing an excellent solution for AI acceleration within constrained devices. Its capability to handle high-speed data processing with limited power consumption makes it an optimal choice for applications requiring efficiency and precision. With 1GB of dedicated DRAM memory, it seamlessly supports a wide array of AI pipelines, ensuring rapid integration and deployment. The design of the Metis AIPU M.2 module is centered around maximizing performance without excessive energy consumption, making it suitable for diverse applications such as real-time video analytics and multi-camera processing. Its compact form factor eases incorporation into various devices, delivering robust performance for AI tasks without the heat or power trade-offs typically associated with such systems. Engineered to problem-solve current AI demands efficiently, the M.2 module comes supported by the Voyager SDK, which simplifies the integration process. This comprehensive software suite empowers developers to build and optimize AI models directly on the Metis platform, facilitating a significant reduction in time-to-market for innovative solutions.
The Chimera GPNPU from Quadric is designed as a general-purpose neural processing unit intended to meet a broad range of demands in machine learning inference applications. It is engineered to perform both matrix and vector operations along with scalar code within a single execution pipeline, which offers significant flexibility and efficiency across various computational tasks. This product achieves up to 864 Tera Operations per Second (TOPs), making it suitable for intensive applications including automotive safety systems. Notably, the GPNPU simplifies system-on-chip (SoC) hardware integration by consolidating hardware functions into one processor core. This unification reduces complexity in system design tasks, enhances memory usage profiling, and optimizes power consumption when compared to systems involving multiple heterogeneous cores such as NPUs and DSPs. Additionally, its single-core setup enables developers to efficiently compile and execute diverse workloads, improving performance tuning and reducing development time. The architecture of the Chimera GPNPU supports state-of-the-art models with its Forward Programming Interface that facilitates easy adaptation to changes, allowing support for new network models and neural network operators. It’s an ideal solution for products requiring a mix of traditional digital signal processing and AI inference like radar and lidar signal processing, showcasing a rare blend of programming simplicity and long-term flexibility. This capability future-proofs devices, expanding their lifespan significantly in a rapidly evolving tech landscape.
xcore.ai is a powerful platform tailored for the intelligent IoT market, offering unmatched flexibility and performance. It boasts a unique multi-threaded micro-architecture that provides low-latency and deterministic performance, perfect for smart applications. Each xcore.ai contains 16 logical cores distributed across two multi-threaded processor tiles, each equipped with 512kB of SRAM and capable of both integer and floating-point operations. The integrated interprocessor communication allows high-speed data exchange, ensuring ultimate scalability across multiple xcore.ai SoCs within a unified development environment.
SCR1 is an open-source and silicon-proven microcontroller core, tailored for deeply embedded applications. This 32-bit RISC-V core supports the standard ISA with optional extensions for multiplication, division, and compressed instructions. The design comprises a simple in-order 4-stage pipeline, providing efficient interrupt handling with an IPIC unit. It connects seamlessly with various interfaces, including AXI4, AHB-Lite, and JTAG, enhancing its adaptability across different systems. The SCR1 core boasts a Tightly-Coupled Memory (TCM) subsystem supporting up to 64KB. It features up to 16 interrupt lines and a range of performance monitoring tools making it ideal for IoT, control systems, and smart card applications. Pre-configured software development tools, including IDEs like Eclipse and Visual Studio Code plugins, complement the core, enabling developers to quickly deploy applications tailored to SCR1’s architecture. Additionally, SCR1 comes packaged with a rich suite of documentation and pre-configured FPGA-based SDK, ensuring a smooth transition from development to implementation. Its GPL-compliant open-source license ensures flexibility for commercial and educational use, making it a versatile choice for a wide range of projects.
The RISC-V CPU IP N Class is designed to cater to the needs of 32-bit microcontroller units (MCUs) and AIoT (Artificial Intelligence of Things) applications. It is engineered to provide a balance of performance and power efficiency, making it suitable for a range of general computing needs. With its adaptable architecture, the N Class processor allows for customization, enabling developers to configure the core to meet specific application requirements while minimizing unnecessary overhead. Incorporating the RISC-V open standard, the N Class delivers robust functional features, supporting both security and functional safety needs. This processor core is ideal for applications that require reliable performance combined with low energy consumption. Developers benefit from an extensive set of resources and tools available in the RISC-V ecosystem to facilitate the integration and deployment of this processor across diverse use cases. The RISC-V CPU IP N Class demonstrates excellent scalability, allowing for configuration that aligns with the specific demands of IoT devices and embedded systems. Whether for implementing sophisticated sensor data processing or managing communication protocols within a smart device, the N Class provides the foundation necessary for developing innovative and efficient solutions.
aiWare represents aiMotive's advanced hardware intellectual property core for automotive neural network acceleration, pushing boundaries in efficiency and scalability. This neural processing unit (NPU) is tailored to meet the rigorous demands of automotive AI inference, providing robust support for various AI workloads, including CNNs, LSTMs, and RNNs. By achieving up to 256 Effective TOPS and remarkable scalability, aiWare caters to a wide array of applications, from edge processors in sensors to centralized high-performance modules.\n\nThe design of aiWare is particularly focused on enhancing efficiency in neural network operations, achieving up to 98% efficiency across diverse automotive applications. It features an innovative dataflow architecture, ensuring minimal external memory bandwidth usage while maximizing in-chip data processing. This reduces power consumption and enhances performance, making it highly adaptable for deployment in resource-critical environments.\n\nAdditionally, aiWare is embedded with comprehensive tools like the aiWare Studio SDK, which streamlines the neural network optimization and iteration process without requiring extensive NPU code adjustments. This ensures that aiWare can deliver optimal performance while minimizing development timelines by allowing for early performance estimations even before target hardware testing. Its integration into ASIL-B or higher certified solutions underscores aiWare's capability to power the most demanding safety applications in the automotive domain.
The RAIV General Purpose GPU (GPGPU) epitomizes versatility and cutting-edge technology in the realm of data processing and graphics acceleration. It serves as a crucial technology enabler for various prominent sectors that are central to the fourth industrial revolution, such as autonomous driving, IoT, virtual reality/augmented reality (VR/AR), and sophisticated data centers. By leveraging the RAIV GPGPU, industries are able to process vast amounts of data more efficiently, which is paramount for their growth and competitive edge. Characterized by its advanced architectural design, the RAIV GPU excels in managing substantial computational loads, which is essential for AI-driven processes and complex data analytics. Its adaptability makes it suitable for a wide array of applications, from enhancing automotive AI systems to empowering VR environments with seamless real-time interaction. Through optimized data handling and acceleration, the RAIV GPGPU assists in realizing smoother and more responsive application workflows. The strategic design of the RAIV GPGPU focuses on enabling integrative solutions that enhance performance without compromising on power efficiency. Its functionality is built to meet the high demands of today’s tech ecosystems, fostering advancements in computational efficiency and intelligent processing capabilities. As such, the RAIV stands out not only as a tool for improved graphical experiences but also as a significant component in driving innovation within tech-centric industries worldwide. Its pioneering architecture thus supports a multitude of applications, ensuring it remains a versatile and indispensable asset in diverse technological landscapes.
ISPido represents a fully configurable RTL Image Signal Processing Pipeline, adhering to the AMBA AXI4 standards and tailored through the AXI4-LITE protocol for seamless integration with systems such as RISC-V. This advanced pipeline supports a variety of image processing functions like defective pixel correction, color filter interpolation using the Malvar-Cutler algorithm, and auto-white balance, among others. Designed to handle resolutions up to 7680x7680, ISPido provides compatibility for both 4K and 8K video systems, with support for 8, 10, or 12-bit depth inputs. Each module within this pipeline can be fine-tuned to fit specific requirements, making it a versatile choice for adapting to various imaging needs. The architecture's compatibility with flexible standards ensures robust performance and adaptability in diverse applications, from consumer electronics to professional-grade imaging solutions. Through its compact design, ISPido optimizes area and energy efficiency, providing high-quality image processing while keeping hardware demands low. This makes it suitable for battery-operated devices where power efficiency is crucial, without sacrificing the processing power needed for high-resolution outputs.
The SCR6 is a high-performance microcontroller core optimized for demanding embedded applications requiring substantial computational power. Its out-of-order 12-stage pipeline, complemented by a superscalar architecture, enhances processing speeds, making it ideal for real-time systems. Supporting a wide range of RISC-V ISA extensions, including cryptography and bit manipulation, SCR6 caters to secure and efficient data operations. The SCR6's memory subsystem is robust, featuring dual-level caches augmented with an L3 network-on-chip option. This rich memory architecture, along with efficient interrupt processing via APLIC units, ensures smooth high-speed data throughput in intensive applications. The core supports heterogeneous multicore configurations, enhancing parallel task execution. Designed for industrial and IoT environments, SCR6 comes with extensive development support. Its toolkit includes simulations, FPGA-based SDKs, and integration resources, facilitated through industry-standard interfaces, ensuring rapid development cycles and application deployment.
The UHS-II solution for high-definition content is meticulously designed for rapid data transfer, catering predominantly to high-performance storage applications. This solution efficiently supports various high-definition content formats, ensuring seamless transmission and integration with sophisticated imaging devices. Its extensive compatibility with diverse storage systems and high-speed interfaces enables it to meet the rigorous demands of modern digital video and photographic environments.
DolphinWare IPs is a versatile portfolio of intellectual property solutions that enable efficient SoC design. This collection includes various control logic components such as FIFO, arbiter, and arithmetic components like math operators and converters. In addition, the logic components span counters, registers, and multiplexers, providing essential functionalities for diverse industrial applications. The IPs in this lineup are meticulously designed to ensure data integrity, supported by robust verification IPs for AXI4, APB, SD4.0, and more. This comprehensive suite meets the stringent demands of modern electronic designs, facilitating seamless integration into existing design paradigms. Beyond their broad functionality, DolphinWare’s offerings are fundamental to applications requiring specific control logic and data integrity solutions, making them indispensable for enterprises looking to modernize or expand their product offerings while ensuring compliance with industry standards.
The SCR3 core by Syntacore is a silicon-proven microcontroller aimed at applications requiring both high performance and power efficiency. This 32/64-bit processor core supports a variety of RISC-V standard extensions, including atomic operations and bit manipulation, optimizing it for real-time applications needing reliable interrupt handling through its PLIC, ACLINT, and IPIC units. It features a 5-stage in-order pipeline paired with branch prediction and cache systems to enhance speed and execution efficiency. With considerable support for seamless memory operations, it includes both L1 and L2 caches and a TCM unit capable of housing up to 256KB of data, alongside an integrated Memory Protection Unit for executing multiple privilege modes. Ideal for industrial automation and IoT usage, the SCR3 core facilitates multicore operations with cache coherency for up to 4 simultaneous cores. Extensive development tools are provided, including simulators, IDE support, and a comprehensive FPGA-based SDK, allowing for immediate application development and deployment.
ISPido on VIP Board is a customized runtime solution tailored for Lattice Semiconductors’ Video Interface Platform (VIP) board. This setup enables real-time image processing and provides flexibility for both automated configuration and manual control through a menu interface. Users can adjust settings via histogram readings, select gamma tables, and apply convolutional filters to achieve optimal image quality. Equipped with key components like the CrossLink VIP input bridge board and ECP5 VIP Processor with ECP5-85 FPGA, this solution supports dual image sensors to produce a 1920x1080p HDMI output. The platform enables dynamic runtime calibration, providing users with interface options for active parameter adjustments, ensuring that image settings are fine-tuned for various applications. This system is particularly advantageous for developers and engineers looking to integrate sophisticated image processing capabilities into their devices. Its runtime flexibility and comprehensive set of features make it a valuable tool for prototyping and deploying scalable imaging solutions.
Designed for high-performance computing environments, the RISC-V CPU IP UX Class incorporates a 64-bit architecture enriched with MMU capabilities, making it an excellent choice for Linux-based applications within data centers and network infrastructures. This class of processors is optimized to meet the demanding requirements of modern computing systems, where throughput and reliability are critical. The UX Class supports advanced features like multi-core designs, which enable it to efficiently manage parallel processing tasks. This capability allows for significant performance improvements in applications where simultaneous process execution is desired. Moreover, the UX Class adheres to the RISC-V open architecture, promoting flexibility and innovation among developers who require customized, high-performance processor cores. Accompanied by an extensive ecosystem, the UX Class provides developers with a wealth of resources needed to maximize the processor's capabilities. From toolchains to development kits, these resources streamline the deployment process, allowing for the quick adaptation and integration of UX Class processors into existing and new systems alike. The UX Class is instrumental in advancing the development of data-centric applications and infrastructures.
The PACE Photonic Arithmetic Computing Engine from Lightelligence represents a paradigm shift in computing technologies. By utilizing photonic processes, this product significantly boosts computing speeds while maintaining energy efficiency. PACE is designed to leverage the inherent capabilities of photonics to perform high-speed arithmetic calculations, which are essential for complex data processing tasks. It's an ideal solution for industries demanding rapid and intensive computational power without the typical energy overhead.<br> <br> This advanced engine is central to the development of next-generation computing environments, where performance metrics exceed traditional expectations. By converting light signals into computing potential, PACE ensures that intensive processes such as AI computations, data analyses, and real-time processing are handled more efficiently. This product is tailored for enterprises seeking to minimize latency and enhance throughput across various applications.<br> <br> PACE not only meets the requirements of current computational demands but also sets the stage for future innovations in the field. It's a promising tool for developers and researchers aiming to explore the unexplored realms of digital capabilities, fostering an era of optical computing that's faster and more efficient than ever before. This makes PACE an indispensable component in both current and upcoming technological advancements.
The SCR4 core is a high-performance, area-efficient RISC-V processor with floating-point computation capabilities. Targeting mobile and industrial applications, it supports both single and double precision, adhering to IEEE 754-2008 standards. Its instruction set is complete with advanced extensions, including atomic and cryptography functions for secure and efficient operations. With a powerful 5-stage in-order pipeline and a dedicated FPU, the SCR4 can handle complex mathematical tasks swiftly. Its memory architecture features both L1 and L2 caches, alongside a TCM unit, enabling rapid data access and management essential in real-time environments. Incorporating a robust branch prediction unit and support for multicore setups, the SCR4 excels in environments demanding synchronized computing tasks across multiple processors. It’s supported by comprehensive development kits and detailed documentation to expedite the design and implementation processes across diverse platforms.
Syntacore's SCR5 is an efficient application-class processor core, crafted to deliver exceptional performance with Linux compatibility. It integrates a 9-stage in-order pipeline along with floating-point capabilities, making it suitable for diverse processing tasks. Adopting the latest RISC-V ISA extensions, SCR5 ensures high-speed computations and secure operations equipped with bit manipulation and cryptography features. The SCR5’s robust memory subsystem ensures data integrity and rapid access, featuring L1 and L2 caches, a TCM, and an MMU. High-performance multicore support extends up to four cores, promoting parallel processing capabilities necessary in industrial and IoT environments. Its interface support, including JTAG and AXI4, streamlines integration into varied infrastructures. For developers, the SCR5 core is accompanied by advanced toolkits designed to accelerate application deployment. These include pre-built OS options and native toolchains, all backed by thorough documentation to enhance the development lifecycle.
The Universal DSP Library offers a comprehensive suite of digital signal processing components optimized for FPGA implementations. This library integrates seamlessly with the AMD Vivado ML Design Suite, providing essential components such as FIR filters, CIC decimating filters, mixers, and CORDIC function approximations. It includes tools that facilitate the connection of DSP systems together, allowing for rapid assembly of signal processing chains using Vivado’s GUI or direct VHDL instantiation. Each component within the library is accessible in both raw VHDL code and as an AMD Vivado ML Design Suite IPI block. This dual availability enables quick development and simulation of processing chains before moving to FPGA implementation. The Universal DSP Library is equipped with bit-true software models for each DSP block, allowing developers to evaluate and optimize systems in software to ensure precise functioning when deployed on hardware. Key features include support for multiple data channels, continuous wave, and pulse processing, as well as real and complex signal support. It utilizes the AXI4-Stream protocol, providing a standardized interface that simplifies integration and enhances the development of specific DSP solutions. The library is suitable for applications ranging from software-defined radio and communication systems to robotics and medical diagnostics, showcasing its versatility in various high-tech fields.
The iCan PicoPop® is a sophisticated System on Module (SOM) based on Xilinx's Zynq UltraScale+. This miniaturized module is pivotal in simulations requiring high-performance processes like video signal processing within aerospace applications. It serves as the backbone for complex embedded systems, ensuring reliable and efficient operation in demanding environments.
The Universal High-Speed SERDES ranging from 1G to 12.5G is a significant component for enabling rapid serial communication across digital systems. Its architecture is optimized for converting parallel data into serial streams, effectively reducing wiring complexity and simplifying chip design. This IP is essential for systems demanding high bandwidth and fast data rates, such as in data centers, networking equipment, and high-performance computing platforms. The product supports a wide range of data rates, starting from 1Gbps and scaling up to 12.5Gbps, ensuring adaptability across numerous applications. This capability is particularly advantageous in managing the dynamic bandwidth requirements seen in today's electronics landscape. As a result, it serves as a foundational IP for engineers seeking reliable and fast data transmission solutions. Additionally, this SERDES technology is critical for applications where data integrity and speed cannot be compromised. Its sophisticated design ensures efficient power usage, making it suitable for both power-sensitive and high-speed demanding environments. With its broad application scope, the Universal High-Speed SERDES is a go-to solution for implementers aiming to enhance connectivity and performance in advanced digital systems.
iCEVision facilitates rapid prototyping and evaluation of connectivity features using the Lattice iCE40 UltraPlus FPGA. Designers can take advantage of exposed I/Os for quick implementation and validation of solutions, while enjoying compatibility with common camera interfaces such as ArduCam CSI and PMOD. This flexibility is complemented by software tools such as the Lattice Diamond Programmer and iCEcube2, which allow designers to reprogram the onboard SPI Flash and develop custom solutions. The platform comes preloaded with a bootloader and an RGB demo application, making it quick and easy for users to begin experimenting with their projects. Its design includes features like a 50mmx50mm form factor, LED applications, and multiple connectivity options, ensuring broad usability across various rapid prototyping scenarios. With its user-friendly setup and comprehensive toolkit, iCEVision is perfect for developers who need a streamlined path from initial design to functional prototype, especially in environments where connectivity and sensor integration are key.
Tailored for 64-bit architectures, the RISC-V CPU IP NX Class is crafted to cater to demanding applications requiring advanced processing capabilities. It's particularly well-suited for storage solutions and the burgeoning fields of augmented reality (AR), virtual reality (VR), and artificial intelligence (AI). With its robust architecture, the NX Class processor is capable of handling intensive computational tasks efficiently. The NX Class offers an expansive feature set that ensures high performance and functionality across a diverse range of applications. Utilizing the RISC-V standards, the NX Class provides implementers with the flexibility to customize their solutions, ensuring that the processor meets specific operational and performance criteria essential for high-end applications. Developers benefit from a rich software ecosystem for the NX Class, which includes comprehensive tools and libraries that support rapid development and innovation. The processor is well-equipped to facilitate the development of next-generation products that require powerful processing cores, ensuring that integrators can deliver cutting-edge solutions to markets that demand reliability, speed, and scalability.
The Prodigy Universal Processor from Tachyum is a groundbreaking innovation designed to revolutionize data center performance. It remarkably integrates the power of CPUs, GPGPUs, and TPUs into a single homogeneous architecture. This processor architecture supports not only general computing tasks but also excels in high-performance computing, AI, and deep machine learning applications. The Prodigy is engineered to reduce power consumption drastically while significantly boosting server utilization and space efficiency, a much-needed advantage for modern data centers. One of its most praised attributes is its unrivaled performance per watt, being able to deliver up to 18 times higher performance and six times better energy efficiency compared to its peers. The processor's design overcomes the technological bottlenecks that have traditionally hindered data center efficiency, such as excessive power usage and low server utilization rates. Its streamlined architecture simplifies programming, offering a coherent multiprocessor model that easily integrates into existing data center infrastructures. Moreover, Tachyum's Universal Processor breaks free from the constraints imposed by Moore's Law, setting new standards in computational power and energy utilization. Its innovative approach allows seamless execution of traditional and high-demand AI tasks without necessitating significant overhauls in the software environment. As such, this processor is poised to be a key player in emerging technologies, driving future developments in AI and helping propel forward-thinking organizational strategies across the globe.
The ARM M-Class ASICs offered by ASIC North includes a wide range of ARM Cortex-M microcontrollers and processors. These chips can be integrated into a variety of existing systems across multiple industries. They are designed to offer flexibility and efficiency, providing solutions that meet the unique requirements of complex systems. The architectures are silicon-proven and include support for a variety of applications, from simple controller tasks to complex control systems.
The ONNC Compiler is an advanced suite of C++ libraries designed to enhance the efficiency of deep learning accelerators. It facilitates the transformation of neural networks into distinct machine instructions, optimizing across varying architectures from simple single-core systems to complex multicore systems with layered memory hierarchies. Supporting prominent frameworks such as PyTorch and TensorFlow, the compiler ensures seamless integration for a wide array of AI systems, particularly those focusing on heterogeneous multicore designs.
The BA51 is a 32-bit RISC-V processor core designed for ultra-low-power applications. It features a dual-stage pipeline capable of operating at frequencies over 500 MHz when implemented in smaller process nodes like 16nm. This core is ideally suited for energy-efficient embedded systems, providing a balance of performance and silicon resource conservation. The compact design leverages advanced power-saving techniques, including clock gating and frequency scaling, to minimize energy consumption and maximize battery life. The BA51 is excellent for IoT and portable device applications where power efficiency is paramount, and it delivers robust computational capabilities without compromising on power usage.
The RISC-V CPU IP U Class stands out with its 32-bit architecture integrated with an MMU, optimizing it for Linux-based operating systems and edge computing tasks. This class of processors is engineered to handle more complex computing needs, making it particularly suitable for sophisticated system applications where multitasking and high processing speeds are necessary. This processor class is designed with a keen focus on versatility and expansion, allowing it to effectively support a variety of applications. By utilizing the RISC-V open standard, the U Class processor enables high customizability, letting integrators tailor the processing core to fit their application-specific needs, ensuring an optimal balance between performance and power consumption. The RISC-V CPU IP U Class offers strong support for developers through an extensive ecosystem that includes compilers, SDKs, and other tools required to harness the processor's full capabilities. These resources enable efficient development processes and facilitate the deployment of edge computing solutions across many industries, from consumer electronics to industrial systems.
ADICSYS offers a robust array of Field Programmable Gate Array (eFPGA) solutions tailored for ASICs and SOCs. These solutions build on a wealth of experience spanning over a decade in custom FPGA and embedded FPGA projects. The eFPGA cores are designed to be synthesizable, technology-independent, and fully integrated into standard RTL design flows. ADICSYS' embedded FPGA provides high scalability and customization options, making them suitable for diverse applications across various technology nodes. By leveraging these features, clients can benefit from enhanced flexibility, reduced risks, and expedited time-to-market for their projects.
The EMSA5-FS is a 32-bit RISC-V embedded processor core optimized for functional safety applications, adhering to the ISO 26262 ASIL-D guidelines. It features a single-issue, in-order, 5-stage pipeline design. The core accommodates optional configurations such as the L0 instruction cache. Enhanced with fail-safe features like Dual Modular Redundancy (DMR) and Error Correcting Code (ECC), it's designed to deliver reliable performance in safety-critical environments. The EMSA5-FS excels in both ASIC and FPGA deployments, with the flexibility to operate at frequencies surpassing 1GHz in advanced node technologies. Its deliverables include a comprehensive Safety Manual and Failure Modes, Effects and Diagnostics Analysis (FMEDA) document, ensuring thorough functional safety compliance.
The YVR processor is designed with an AVR Instruction Set Architecture operating on a 2-clock machine cycle, providing an efficient structure suitable for various embedded applications. This design streamlines execution speed and improves power efficiency, making it a versatile choice for developers looking to leverage AVR architecture in their systems.
MosChip's Digital IP Solutions provide a range of high-performance solutions apt for integration in various applications. These include Interface IPs, Communication IPs, and Display IPs, targeting enhanced power efficiency and reduced development cycles. The designs are optimized to deliver superior performance, facilitating quick time-to-market for their clients. The company’s expertise in creating tailored digital IPs comes from years of experience in the semiconductor industry, enabling their clientele to produce competitive products swiftly and efficiently. Their offerings cater to a spectrum of device requirements, providing flexibility and adaptability across diverse digital applications. By blending advanced digital technology with their in-depth knowledge, MosChip ensures that their digital IP solutions meet the rigorous demands of modern industry standards, setting benchmarks for quality and performance. Each design undergoes strict quality checks to ensure reliability in high-use scenarios, making them a trusted partner for businesses looking to innovate.
The BA53 is a low-power, deeply embedded RISC-V processor core. This 32-bit processor employs a 5-stage pipeline architecture, ensuring efficient processing with a minimal power footprint. Operating frequencies can exceed 1GHz, particularly in 22nm process implementations. This makes the BA53 well-suited for applications requiring substantial processing power without the burden of high energy consumption. Optional features such as L0 instruction and data caches bolster its performance, making it a versatile choice for various embedded applications needing reliable and efficient operation.
Designed to offload graphical processing from the main CPU, the logiBITBLT is a 2D graphics accelerator optimized for AMD FPGAs and Zynq 7000 AP SoCs. It enables the creation of engaging graphics while reducing system strain, ensuring efficient rendering of 2D visual elements. This IP core is pivotal for applications requiring high-performance graphics with minimal processing overhead.
The PanAccelerator is Panmnesia's AI accelerator featuring an innovative CXL-enabled design that facilitates rapid scaling of AI services. It offers hardware acceleration through flexible memory resources composability, enabled by CXL technology. The accelerator's design allows for quick adaptation to evolving compute requirements by efficiently disaggregating compute and memory resources. Equipped with a robust compute unit optimized for parallel vector and tensor operations, PanAccelerator ensures the cost-effective deployment of large-scale AI services without sacrificing performance.
Akeana's 1000 Series processors are advanced 64-bit RISC-V cores designed for a spectrum of data computation needs. They are highly configurable, supporting high-performance applications such as Edge AI, industrial automation, and automotive sensing. Available in architectures supporting both in-order and out-of-order execution, these processors can handle substantial computational tasks efficiently. The 1000 Series processors feature a 9 to 12-stage pipeline and offer options for multi-threaded execution, allowing for single, dual, or quad-issue operation. These features make them particularly adept at managing high-throughput workloads requiring data precision and fast processing, such as those found in edge gateways and smart cameras. To accommodate such needs, these processors include options for comprehensive memory management, such as large TLBs and extensive instruction caches. This series is designed with flexibility in mind, offering modular add-ons like cryptographic and vector extensions, which are crucial for secure and efficient processing of complex data sets. The ability to scale with coherent many-core clusters enhances the processors' applicability to a broad range of sophisticated computational environments.
Enhance bitmap graphics processing with the logiBMP IP core designed for AMD FPGAs. This 2.5D graphics accelerator supports perspective-correct rendering, facilitating smooth and accurate display of bitmap-based scenes. It's ideal for graphics-demanding applications where real-time rendering is critical, offering robust performance in visual processing tasks.
The BA25 application processor is a powerful 32-bit core designed for high-performance tasks. With a sophisticated seven-stage pipeline, this processor is ideal for running complex software systems such as Linux or Android. It offers robust architectural features that support high-speed operation, making it suitable for demanding applications like multitasking in embedded systems. The BA25 is particularly beneficial in scenarios where off-chip memory access is required, providing the speed and efficiency necessary for modern consumer and industrial devices.
The Akeana 100 Series comprises 32-bit RISC-V processors designed for applications that demand small size and low power consumption. These processors are highly configurable and find their optimal use in deeply embedded systems like smart speakers, smart home appliances, drones, and wearable tech. Featuring an in-order, short pipeline length, the 100 Series offers low-latency, real-time processing capabilities. With a design catering to power and area-constrained environments, the Akeana 100 Series supports configurations with up to 64 KB L1 instruction cache and closely-coupled memory of up to 512 KB. The series includes options such as scalar cryptographic extensions, making it well-suited for IoT devices that require lightweight security. Its high configurability also includes custom instruction support, aligning with various application needs. Perfect for deeply embedded microcontrollers, this line offers various standard features, including Physical Memory Protection with multiple entries, and options to add custom instructions for specific use-cases. This flexibility extends its usability across different segments, ensuring optimal performance for a myriad of low power, real-time processing applications.
The xcore-200 series is engineered for embedded system designers aiming to innovate with specific interfaces and capabilities. This platform offers a high level of customization, supported by fast processing, low-latency performance, and scalability across a range of multicore options. Available with up to 32 cores and featuring on-chip memory, it supports applications requiring USB, RGMII Gigabit Ethernet, and Flash memory options, ensuring it meets modern IoT demands with ease. With integrated features like secure boot and support for multiple interfaces, xcore-200 is an ideal choice for today's dynamic and growing market.
DRV32IMZicsr – Scalable RISC-V Power. Tailored for Your Project. Ready for the Future. The DRV32IMZicsr is a high-performance, 32-bit RISC-V processor core, equipped with M (Multiply/Divide), Zicsr (Control and Status Registers), and External Debug support. Built as part of DCD’s latest DRVX Core Family, it delivers the full flexibility, openness, and innovation that RISC-V promises—without locking you into proprietary architectures. ✅ Why RISC-V? RISC-V is a rapidly growing open standard for modern computing—backed by a global ecosystem of developers and vendors. It brings: * Freedom from licensing fees and vendor lock-in * Scalability from embedded to high-performance systems * Customizability with standard and custom instruction sets * Strong toolchain & ecosystem support 🚀 DRV32IMZicsr Highlights: * Five-stage pipeline and Harvard architecture for optimized performance * Configurable memory architecture: size and address allocation tailored to your needs Performance metrics: * **Up to 1.15 DMIPS/MHz** * **Up to 2.36 CoreMark/MHz** * Minimal footprint starting from just 14k gates * Flexible interfaces: Choose from AXI, AHB, or native bus options 🛡️ Designed for Safety & Integration: * Developed as an ISO 26262 Safety Element out of Context (SEooC) * Fully technology-agnostic, compatible with all FPGA and ASIC platforms * Seamless integration with DCD’s rich portfolio of IPs: DMA, SPI, UART, PWM, CAN, and more 🔍 Advanced Feature Set: * 32 general-purpose registers * Support for arithmetic, logic, load/store, conditional and unconditional control flow * M extension enables efficient integer multiplication/division * Zicsr extension provides robust interrupt and exception handling, performance counters, and timers * External Debug via JTAG: compliant with RISC-V Debug Specification 0.13.2 and 1.0.0, compatible with all mainstream tools 🧪 Developer-Ready: * Delivered with a fully automated testbench * Includes a comprehensive validation test suite for smooth integration into your SoC flow Whether you're building for automotive, IoT, consumer electronics, or embedded systems, the DRV32IMZicsr offers a future-ready RISC-V solution—highly configurable, performance-optimized, and backed by DCD’s 25 years of experience. Interested? Let’s build the next generation together. 📩 Contact us at info@dcd.pl
**DRV64IMZicsr – 64-bit RISC-V Performance. Designed for Demanding Innovation.** The DRV64IMZicsr is a powerful and versatile 64-bit RISC-V CPU core, built to meet the performance and safety needs of next-generation embedded systems. Featuring the M (Multiply/Divide), Zicsr (Control and Status Registers), and External Debug extensions, this core is engineered to scale—from edge computing to mission-critical applications. As part of the DRVX Core Family, the DRV64IMZicsr embodies DCD’s philosophy of combining open-standard freedom with customizable IP excellence—making it a smart and future-proof alternative to legacy architectures. ✅ Why Choose RISC-V? * No license fees – open-source instruction set means reduced TCO * Unmatched flexibility – tailor the architecture to your specific needs * A global, thriving ecosystem – support from toolchains, OSes, and hardware vendors * Security & longevity – open and verifiable architecture ensures trust and sustainability 🚀 DRV64IMZicsr – Core Advantages: * 64-bit RISC-V ISA with M, Zicsr, and Debug support * Five-stage pipeline, Harvard architecture, and efficient branch prediction * Configurable memory size and allocation for program and data spaces Performance optimized: * **Up to 2.38 CoreMark/MHz** * **Up to 1.17 DMIPS/MHz** * Compact footprint starting from just 17.6k gates * Interface options: AXI, AHB, or native * Compatible with Classical CAN, CAN FD, and CAN XL through additional IPs 🛡️ Safety, Compatibility & Flexibility Built In: * Developed as an ISO 26262 Safety Element out of Context (SEooC) * Technology-agnostic – works seamlessly across all FPGA and ASIC vendors * Expandable with DCD’s IP portfolio: DMA, SPI, UART, I²C, CAN, PWM, and more 🔍 Robust Feature Set for Real Applications: * Full 64-bit processing – ideal for performance-intensive, memory-heavy tasks * M extension enables high-speed multiplication/division via dedicated hardware unit * Zicsr extension gives full access to Control and Status Registers, enabling: * Interrupts and exception handling (per RISC-V Privileged Spec) * Performance counters and timers * JTAG-compatible debug interface – compliant with RISC-V Debug Spec (0.13.2 & 1.0.0) 🧪 Ready for Development & Integration: * Comes with a fully automated testbench * Includes a comprehensive suite of validation tests for smooth SoC integration * Supported by industry-standard tools, ensuring a hassle-free dev experience Whether you’re designing for automotive safety, industrial control, IoT gateways, or AI-enabled edge devices, the DRV64IMZicsr gives you the performance, flexibility, and future-readiness of RISC-V—without compromise. 💡 Build smarter, safer systems—on your terms. 📩 Contact us today at info@dcd.pl to start your next RISC-V-powered project.
The Akeana 5000 Series represents the pinnacle of Akeana's processor IP offerings, delivering ultra-high performance for demanding computational tasks in data centers and cloud environments. These 64-bit RISC-V processors are optimized for extensive operations requiring high clock frequencies and rich operating systems like Android and Linux. Their design features a 12-stage out-of-order pipeline and supports multi-threaded execution with up to 10-wide instruction issue architecture. This makes the 5000 Series suitable for heavy-duty applications such as AI training, networking, and mobile computing. These processors are scalable, capable of forming fully coherent many-core clusters, allowing businesses to implement highly efficient processing units within expansive system architectures. Featuring advanced security and virtualization extensions, the 5000 Series ensures robust access control and efficient workload distribution across virtualized environments. Their configurability includes options for comprehensive L1 and L2 caching, enabling them to handle extensive data loads and reduce latency, which is critical in high-performance computing scenarios.
The Metis AIPU Quad-Core High-Performance PCIe Card is designed to provide industry-leading AI acceleration capabilities. With four Metis AIPUs at its core, this card delivers up to 856 TOPS, making it suitable for the most demanding AI applications, such as those found in complex vision systems and multi-channel data processing scenarios. The card's architecture allows it to efficiently handle high-throughput and low-latency tasks by leveraging its substantial processing power. What sets this PCIe card apart is its integration with the Voyager SDK, Axelera AI's advanced software stack. It allows for seamless deployment and optimization of AI models, supporting a wide array of AI frameworks and tooling environments. This level of integration ensures that developers can rapidly deploy high-performance AI solutions with reduced complexity and greater user experience. Furthermore, the card features leading energy efficiency, achieving significant reductions in power consumption without compromising performance. This balance of power and performance makes it an optimal choice for organizations looking to scale their edge computing applications efficiently.
The DF6802 is an 8-bit synthesizable MPU IP Core, software-compatible with Motorola MC6802. It features an enhanced internal architecture for approximately 4 times faster execution than the original 6802 chip at the same clock frequency. Designed with two power-saving modes (WAIT and HALT), the DF6802 is ideal for automotive and battery-driven applications. It is fully customizable, allowing for a configuration that meets specific user needs, without extra costs for unused features. The IP Core comes equipped with a fully automated testbench and a comprehensive set of test cases for smooth package validation. Moreover, the DF6802 supports DCD’s Hardware Debug System, DoCD™, which offers real-time, non-intrusive debugging across the entire SoC, including the ability to halt, run, step into, or skip instructions, and read/write data to any part of the microprocessor. With support for a wide range of interfaces such as USB, Ethernet, I2C, SPI, UART, CAN, LIN, HDLC, and Smart Card, the DF6802 shows versatile connectivity while ensuring efficient power and performance optimization. The DF6802 is technology agnostic, ensuring compatibility with all FPGA and ASIC vendors. It comes with extensive deliverables including synthesizable RTL, testbench environment, simulation macros, synthesis scripts, and complete technical documentation along with 12 months of technical support.
The MIPS I8500 Series leverages cutting-edge multiprocessor design to deliver superior computational performance across a range of demanding applications. Featuring a unique four-way simultaneous multithreading capability, this series is engineered to manage complex processing tasks efficiently, making it suitable for industries requiring high throughput and real-time data handling. This series is designed to perform optimally under the rigorous conditions of data centers, automotive gateways, and embedded applications, offering scalable solutions that can be tailored to specific needs. The 4-way simultaneous multithreading enhances the ability to execute multiple instructions in a single cycle, contributing to increased performance and responsiveness. Configurable for various process nodes, the I8500 can be integrated into existing system architectures with ease. Its ASIL-B compliance underscores its suitability for safety-critical applications in the automotive industry, while its energy-efficient design ensures better power management and reduces operational costs.
Digital Core Design presents the D68000-CPU32+, a soft core microprocessor compatible with the 68000's CPU32+ architecture. With a 32-bit data bus and address bus, this core is optimized for high performance program execution and includes a built-in DoCD-BDM debugger interface, making it ideal for debugging complete SoC systems. Its support for 8-, 16-, and 32-bit unaligned/aligned data-bus transfers and a vast array of addressing modes offers flexibility in complex application development. Designed for universal compatibility across FPGA and ASIC vendors, the D68000-CPU32+ is delivered with a comprehensive suite of testbenches, automatic validation tests, and sculpted documentation. The architecture boasts advanced arithmetic and logic capabilities, making it suitable for a wide array of applications, from embedded systems to complex SoCs. With licensing methods streamlined for ease of access, utilizing the D68000-CPU32+ in various contexts is both simple and efficient.
DP8051CPU is an ultra high performance 8-bit soft core microcontroller designed by DCD-SEMI to be highly efficient in terms of speed and power consumption. With a pipelined RISC architecture, it can perform operations remarkably faster than the traditional 80C51, with its performance metrics standing up to 15.55 times its predecessor when benchmarked using Dhrystone 2.1. The architecture supports both Harvard and von Neumann configurations, increasing the flexibility for memory access and inclusion. The microcontroller is equipped with an advanced Power Management Unit, allowing it to maintain its high performance capabilities while optimizing power consumption. Targeted for carrying out operations with both fast on-chip memory and slower off-chip alternatives, it can process up to 300 million instructions per second while managing substantial code and data spaces efficiently. Furthermore, it is 100% compatible with the industry-standard 8051 microcontrollers in terms of binary operation, making it highly suitable for integration in existing systems. It boasts of supporting a wide variety of interfaces like USB, Ethernet, I2C, SPI, UART, and many others, which adds to the scope of applications, especially in portable and power-conscious devices. The microcontroller supports a comprehensive hardware debugging system (DoCD™), uniquely proposed to allow non-intrusive debugging of an operational application, offering a robust development and testing phase. With real-time capability and providing insights at various operational stages, it ensures that users can have a contained yet exhaustive overview of their designs. DCD ensures a technology-agnostic design, meaning that this IP core ensures compatibility across all prominent FPGA and ASIC vendors, providing flexibility and convenience for a wide array of users. The DP8051CPU is delivered with a complete test bench and a series of validation sets, ensuring a smooth integration within any workflow.
The N-channel Multiplexed FIR Filter offers an efficient filtering solution for complex signal processing applications. By multiplexing multiple inputs through a shared filter architecture, this design significantly reduces the computational resources required compared to running independent filters for each channel. This makes it ideal for dual-channel inputs such as I/Q signals in communications systems. Easy to integrate within broad DSP applications, this filter's flexibility and resource efficiency makes it a valuable tool in signal processing workflows, where performance and economy are paramount.
The W65C02SOL-28 PragmatIC HDL SOL Design presents a compelling IP solution that extends the capabilities of the 6502 architecture. With its focus on HDL-based design, this IP is crafted to support scalable and cost-effective developments, ideal for educational and industrial applications alike. It promises reliability and high performance, making it a preferred choice among engineers seeking robust soft IP solutions.
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