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All IPs > Processor > Processor Cores > DRV32IMZicsr, a 32-bit RISC-V CPU with M, Zicsr extensions, and External Debug support.

DRV32IMZicsr, a 32-bit RISC-V CPU with M, Zicsr extensions, and External Debug support.

From DCD-SEMI

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Description

DRV32IMZicsr – Scalable RISC-V Power. Tailored for Your Project. Ready for the Future.
The DRV32IMZicsr is a high-performance, 32-bit RISC-V processor core, equipped with M (Multiply/Divide), Zicsr (Control and Status Registers), and External Debug support. Built as part of DCD’s latest DRVX Core Family, it delivers the full flexibility, openness, and innovation that RISC-V promises—without locking you into proprietary architectures.

✅ Why RISC-V?
RISC-V is a rapidly growing open standard for modern computing—backed by a global ecosystem of developers and vendors. It brings:

  • Freedom from licensing fees and vendor lock-in

  • Scalability from embedded to high-performance systems

  • Customizability with standard and custom instruction sets

  • Strong toolchain & ecosystem support

🚀 DRV32IMZicsr Highlights:
* Five-stage pipeline and Harvard architecture for optimized performance

  • Configurable memory architecture: size and address allocation tailored to your needs

Performance metrics:

  • Up to 1.15 DMIPS/MHz

  • Up to 2.36 CoreMark/MHz

  • Minimal footprint starting from just 14k gates

  • Flexible interfaces: Choose from AXI, AHB, or native bus options

🛡️ Designed for Safety & Integration:
* Developed as an ISO 26262 Safety Element out of Context (SEooC)

  • Fully technology-agnostic, compatible with all FPGA and ASIC platforms

  • Seamless integration with DCD’s rich portfolio of IPs: DMA, SPI, UART, PWM, CAN, and more

🔍 Advanced Feature Set:
* 32 general-purpose registers

  • Support for arithmetic, logic, load/store, conditional and unconditional control flow

  • M extension enables efficient integer multiplication/division

  • Zicsr extension provides robust interrupt and exception handling, performance counters, and timers

  • External Debug via JTAG: compliant with RISC-V Debug Specification 0.13.2 and 1.0.0, compatible with all mainstream tools

🧪 Developer-Ready:
* Delivered with a fully automated testbench

  • Includes a comprehensive validation test suite for smooth integration into your SoC flow

Whether you're building for automotive, IoT, consumer electronics, or embedded systems, the DRV32IMZicsr offers a future-ready RISC-V solution—highly configurable, performance-optimized, and backed by DCD’s 25 years of experience.

Interested? Let’s build the next generation together.
📩 Contact us at info@dcd.pl

Deliverables
Soft IP
  • Compliance
  • Synthesizable RTL
  • Verilog integration testbench
  • Sample synthesis script and constraints
  • Sample simulation script
  • Datasheet
  • Hardware user guide
  • Hardware implementation guide
  • Standard EDA tool flow scripts and support files
  • Verification test bench and test vectors
Hard IP
  • Verilog
  • Spice netlist
  • GDS
  • LEF/DEF
  • Timing (Lib file)
  • Extracted netlist
  • Datasheet
  • Integration guide
  • Test bench
Features
  • Five‐stage pipeline Harvard architecture RV32I Base RISC-V ISA M extension Zicsr extension External Debug support JTAG debug interface Conformance to the RISC-V Debug Specification 0.13.2 and 1.0.0 Highly configurable, including: Flexible memory size and allocation Interface selection: AXI, AHB, Native M privilege level support Interrupt and exception handling Performance counters and timer Wide range of supported peripherals, including: DMA SPI UART PWM and more • Developed as ISO26262 Safety Element out of Context (SEooC) • Technology independent HDL Source Code
Foundries & Process Nodes
Foundry Process Nodes
All Foundries All Process Nodes
Tech Specs
Image Gallery
DRV32IMZicsr, a 32-bit RISC-V CPU with M, Zicsr extensions, and External Debug support.
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