DRV64IMZicsr – 64-bit RISC-V Performance. Designed for Demanding Innovation.
The DRV64IMZicsr is a powerful and versatile 64-bit RISC-V CPU core, built to meet the performance and safety needs of next-generation embedded systems. Featuring the M (Multiply/Divide), Zicsr (Control and Status Registers), and External Debug extensions, this core is engineered to scale—from edge computing to mission-critical applications.
As part of the DRVX Core Family, the DRV64IMZicsr embodies DCD’s philosophy of combining open-standard freedom with customizable IP excellence—making it a smart and future-proof alternative to legacy architectures.
✅ Why Choose RISC-V?
* No license fees – open-source instruction set means reduced TCO
-
Unmatched flexibility – tailor the architecture to your specific needs
-
A global, thriving ecosystem – support from toolchains, OSes, and hardware vendors
-
Security & longevity – open and verifiable architecture ensures trust and sustainability
🚀 DRV64IMZicsr – Core Advantages:
* 64-bit RISC-V ISA with M, Zicsr, and Debug support
-
Five-stage pipeline, Harvard architecture, and efficient branch prediction
-
Configurable memory size and allocation for program and data spaces
Performance optimized:
-
Up to 2.38 CoreMark/MHz
-
Up to 1.17 DMIPS/MHz
-
Compact footprint starting from just 17.6k gates
-
Interface options: AXI, AHB, or native
-
Compatible with Classical CAN, CAN FD, and CAN XL through additional IPs
🛡️ Safety, Compatibility & Flexibility Built In:
* Developed as an ISO 26262 Safety Element out of Context (SEooC)
-
Technology-agnostic – works seamlessly across all FPGA and ASIC vendors
-
Expandable with DCD’s IP portfolio: DMA, SPI, UART, I²C, CAN, PWM, and more
🔍 Robust Feature Set for Real Applications:
* Full 64-bit processing – ideal for performance-intensive, memory-heavy tasks
-
M extension enables high-speed multiplication/division via dedicated hardware unit
-
Zicsr extension gives full access to Control and Status Registers, enabling:
-
Interrupts and exception handling (per RISC-V Privileged Spec)
-
Performance counters and timers
-
JTAG-compatible debug interface – compliant with RISC-V Debug Spec (0.13.2 & 1.0.0)
🧪 Ready for Development & Integration:
* Comes with a fully automated testbench
-
Includes a comprehensive suite of validation tests for smooth SoC integration
-
Supported by industry-standard tools, ensuring a hassle-free dev experience
Whether you’re designing for automotive safety, industrial control, IoT gateways, or AI-enabled edge devices, the DRV64IMZicsr gives you the performance, flexibility, and future-readiness of RISC-V—without compromise.
💡 Build smarter, safer systems—on your terms.
📩 Contact us today at info@dcd.pl to start your next RISC-V-powered project.
