All IPs > Memory & Logic Library
The Memory & Logic Library category in our semiconductor IP catalog offers a comprehensive range of intellectual property that is essential for creating efficient and high-performance semiconductor solutions. This category is pivotal for designers who require reliable and optimized components to be integrated into a wide array of electronic products.
Key offerings within this category include Embedded Memories, I/O Libraries, and Standard Cells, each playing a critical role in the functionality of integrated circuits (ICs). Embedded Memories are vital for storing data within semiconductor chips, ranging from simple storage solutions to complex memory architectures that support high-speed operations. These are used in everything from microcontrollers for consumer electronics to high-end processors for enterprise-grade applications.
I/O Libraries, on the other hand, provide the necessary interface between the semiconductor device and the outside world. They encompass a wide variety of input/output configurations and technologies, ensuring efficient communication and data transfer is maintained across the chip's interfaces.
Finally, Standard Cells form the building blocks of digital circuits. They provide pre-designed, pre-verified logic functions that simplify the design process, increase reliability, and reduce time to market. Standard cells are integral in the design of ASICs (Application-Specific Integrated Circuits) and other custom logic devices. Our Memory & Logic Library category thus enables semiconductor engineers to access a diverse set of IPs crucial for modern electronics design and innovation.
Dolphin Technology provides an extensive range of standard cell libraries that are critical for any SoC design project. These libraries include over 5,000 fully customizable cells, each precisely crafted to optimize speed, power, density, and routability. The standard cells are verified in silicon and designed for use across various process technologies, making them an ideal choice for a wide range of applications. The standard cell libraries support various process nodes such as 6-track, 7-track, and up to 14-track configurations, suitable for everything from high-performance to ultra-high density applications. Dolphin Technology’s standard cell IP offerings include Multi-VT (SVT, HVT, LVT) and multi-channel options, enabling flexibility in design to accommodate the specific needs of semiconductor projects. These cell libraries are tailored to support high-performance computing, provide efficiency in wafer yield, and ensure optimal SoC pricing. This high degree of customization, coupled with a focus on power and density, offers excellent options for semiconductor professionals aiming to create high-performance designs efficiently and cost-effectively.
The A25 processor model is a versatile CPU suitable for a variety of embedded applications. With its 5-stage pipeline and 32/64-bit architecture, it delivers high performance even with a low gate count, which translates to efficiency in power-sensitive environments. The A25 is equipped with Andes Custom Extensions that enable tailored instruction sets for specific application accelerations. Supporting robust high-frequency operations, this model shines in its ability to manage data prefetching and cache coherence in multicore setups, making it adept at handling complex processing tasks within constrained spaces.
NRAM Technology by Nantero represents a significant leap forward in memory technology, utilizing carbon nanotubes to create non-volatile memory that outperforms traditional solutions. This technology is designed to combine the speed and durability of DRAM with the non-volatility of flash, providing a much-needed enhancement in performance and efficiency. One of the core strengths of NRAM is its ability to function in extreme conditions, maintaining data integrity without the need for constant power. Its low power requirements make it an ideal choice for a variety of applications, ranging from consumer electronics to high-performance computing infrastructures. Furthermore, NRAM's inherent scalability ensures that it can be seamlessly integrated into existing manufacturing processes with minimal disruption, offering a path forward for industries looking to enhance their memory capabilities without prohibitive costs. Its versatility and robustness continue to make it a highly attractive alternative to current memory technologies.
Dolphin Technology offers a comprehensive range of memory IP products, catering to diverse requirements in semiconductor design. These products include a variety of memory compilers, specialty memory, and robust memory test and repair solutions such as Memory BIST. Designed to meet the demands of contemporary low-power and high-density applications, these IPs are built to work across a broad spectrum of process technologies. Advanced power management features, like light and deep sleep modes and dual rails, enable these products to tackle even the toughest low-leakage challenges. What sets these products apart is their flexibility and adaptability, evident in the support for different memory types and process nodes. Dolphin Technology’s memory IPs benefit from seasoned design teams that have proven their mettle in silicon across several generations. Thus, these IPs are not only versatile but also reliable in serving a wide variety of industry needs for technology firms worldwide. Clients can expect memory solutions that are fine-tuned for both power efficiency and performance. Additional capabilities such as power gating cater to ultra-low power devices while achieving a high level of device integration and compatibility. The specialized focus on low noise and rapid cycle times makes these memory solutions highly effective for performance-driven applications. These features collectively make Dolphin Technology’s memory IP an invaluable asset for semiconductor designers striving for innovation and excellence.
The xcore.ai platform from XMOS is engineered to revolutionize the scope of intelligent IoT by offering a powerful yet cost-efficient solution that combines high-performance AI processing with flexible I/O and DSP capabilities. At its heart, xcore.ai boasts a multi-threaded architecture with 16 logical cores divided across two processor tiles, each equipped with substantial SRAM and a vector processing unit. This setup ensures seamless execution of integer and floating-point operations while facilitating high-speed communication between multiple xcore.ai systems, allowing for scalable deployments in varied applications. One of the standout features of xcore.ai is its software-defined I/O, enabling deterministic processing and precise timing accuracy, which is crucial for time-sensitive applications. It integrates embedded PHYs for various interfaces such as MIPI, USB, and LPDDR, enhancing its adaptability in meeting custom application needs. The device's clock frequency can be adjusted to optimize power consumption, affirming its cost-effectiveness for IoT solutions demanding high efficiency. The platform's DSP and AI performances are equally impressive. The 32-bit floating-point pipeline can deliver up to 1600 MFLOPS with additional block floating point capabilities, accommodating complex arithmetic computations and FFT operations essential for audio and vision processing. Its AI performance reaches peaks of 51.2 GMACC/s for 8-bit operations, maintaining substantial throughput even under intensive AI workloads, making xcore.ai an ideal candidate for AI-enhanced IoT device creation.
The AndeShape Platforms are designed to streamline system development by providing a diverse suite of IP solutions for SoC architecture. These platforms encompass a variety of product categories, including the AE210P for microcontroller applications, AE300 and AE350 AXI fabric packages for scalable SoCs, and AE250 AHB platform IP. These solutions facilitate efficient system integration with Andes processors. Furthermore, AndeShape offers a sophisticated range of development platforms and debugging tools, such as ADP-XC7K160/410, which reinforce the system design and verification processes, providing a comprehensive environment for the innovative realization of IoT and other embedded applications.
Secure OTP offers a groundbreaking approach to data protection in semiconductor chips, employing an anti-fuse OTP memory to safeguard sensitive information. By combining hardware macros with digital RTL, it meticulously protects data at rest, in transit, or in use, making it a cornerstone of modern chip design. Its architecture supports various integrations across IC applications, providing robust and adaptable security solutions tailored for diverse markets.<br><br>This technology elevates the standard OTP solutions by incorporating advanced hardware encryption mechanisms and tamperproof designs. Secure OTP's seamless integration into multiple systems underscores its versatility, catering to demands across sectors such as automotive, industrial, and consumer electronics. Users benefit from secure key management and enhanced data integrity, mitigating the potential risks of traditional storage vulnerabilities.<br><br>The design philosophy behind Secure OTP centers on preventing data leakage, particularly for IoT devices that are prone to attacks. As devices face the growing menace of cyber threats, Secure OTP scales to meet these challenges head-on, providing fortified data storage solutions that are resistant to physical attacks and environmental variations. With the rising importance of secure encrypted storage, Secure OTP's role is vital in maintaining the integrity and confidentiality of critical chip information.
The AHB-Lite Memory core from Roa Logic is designed to implement on-chip memory that interfaces seamlessly with AHB-Lite based systems. This soft IP core fully adheres to the AMBA 3 AHB-Lite v1.0 specifications, ensuring compatibility and efficient operation within established system architectures. It supports a single host connection, providing configurable address and data widths, as well as memory depth and technology targets. Notably, this memory core can be tailored through various parameters to fit specific application requirements, including options for combinatorial or registered data output. The core is devised for optimal performance and resource management across different technology nodes, ensuring a balance between access speed and resource usage. This IP core is ideally suited for applications requiring fixed on-chip storage that assures high compatibility and adaptability to various system setups. Access to source code and comprehensive documentation through Roa Logic’s GitHub simplifies the integration and customization process for developers, facilitating swift implementation in diverse design environments.
SkyeChip's Configurable I/O module offers a versatile interface supporting high-speed signaling up to 3.2 GT/s. This component is compatible with several I/O standards including LVDS, HCSL, POD, and various CMOS levels, providing broad application utility in modern digital systems. Tailored for ease of integration into diverse electronic architectures, its configuration capabilities allow for precise adaptation to specific design needs, enhancing system performance and interoperability. This flexibility opens avenues for its utilization across numerous sectors, including telecommunications and general electronic device manufacturers.
The LEE Flash G1 is a highly cost-effective Flash memory solution, leveraging SONOS technology. Designed to support harsh automotive environments, this memory IP is scalable down to 40nm technology. It is ideal for applications necessitating medium memory capacity, providing long retention life and low power operation. This Flash memory solution requires only two to three additional masks, showcasing its compatibility with standard CMOS processes without altering the characteristics of logic transistors. Its short testing and bake time further reduce chip costs, facilitating low-cost implementation for various applications. LEE Flash G1’s efficiency extends to its program and erase operations, utilizing Fowler Nordheim tunneling to minimize power consumption dramatically. This technology ensures smooth integration into existing design frameworks, offering extended data retention and high-temperature resilience.
The YouDDR solution offered by Brite Semiconductor is a comprehensive sub-system that includes a DDR controller, PHY, and I/O. This solution is meticulously crafted to support various DDR technologies like LPDDR2, DDR3, LPDDR3, DDR4, and LPDDR4/4x, with data transfer rates ranging from 667Mbps to 4266Mbps. YouDDR is equipped with advanced dynamic self-calibration logic (DSCL) and dynamic adaptive bit calibration (DABC) technologies. These advancements allow for automatic adjustment to variations such as process, voltage, and temperature (PVT) changes, ensuring robust performance across different conditions. The system also supports training sequences for both read and write operations, ensuring optimized signal integrity and data accuracy. Brite's YouDDR technology guarantees high speed and low power consumption, making it ideal for applications requiring fast memory access and energy efficiency. Its design is highly flexible, supporting multiple configuration options to meet diverse application needs, including different interface types like AXI and AHB. These features make it particularly well-suited for use in high-performance computing systems, consumer electronics, and network systems where quick data retrieval is paramount. The YouDDR IP provides significant advantages over competing products due to its small area and power-efficient design. It also incorporates a comprehensive set of verification tools and support for seamless integration into larger system designs. This makes it a valuable asset for designers seeking a reliable and efficient memory subsystem with proven performance in varied industry applications.
Silvaco’s Embedded Memory Compilers are pivotal for meeting the growing demands of high-performance computing and AI memory solutions. Featuring a non-coherent cache architecture, these compilers strike an optimal balance between speed, efficiency, and cost-effectiveness, supporting multiple foundries and process nodes.<br><br>The memory compilers boast advanced power management features, facilitating low leakage and low voltage requirements. This adaptability makes them indispensable for designs requiring strict power consumption control, enabling high density and yield across varied process technologies.<br><br>Complementing this are multiple design architectures that cater to diverse applications. From ultra-high-speed cache to low-power SRAM and ROM, Silvaco's memory solutions offer extensive flexibility. By integrating redundancy and BIST-ready designs, these compilers not only enhance performance but also support testing and validation processes, ensuring reliability and ease of integration.
The NVMe Host Controller from iWave Global offers an advanced solution for managing NVMe drive interfaces in computing systems. This controller is designed to facilitate the high-speed data exchange that NVMe drives demand, streamlining operations across data-centric applications. Engineered for scalability and performance, the NVMe Host Controller supports high data throughput, ensuring quick access and transfer of data between storage devices and host systems. Its design caters to the demands of modern computational environments where rapid data retrieval and storage are critical. The controller is integral in systems requiring high-performance storage solutions, and its support for multiple interfaces underscores its adaptability and broad applicability in data-intensive industries such as enterprise storage and high-performance computing.
RegSpec is a comprehensive register specification tool that excels in generating Control Configuration and Status Register (CCSR) code. The tool is versatile, supporting various input formats like SystemRDL, IP-XACT, and custom formats via CSV, Excel, XML, or JSON. Its ability to output in formats such as Verilog RTL, System Verilog UVM code, and SystemC header files makes it indispensable for IP designers, offering extensive features for synchronization across multiple clock domains and interrupt handling. Additionally, RegSpec automates verification processes by generating UVM code and RALF files useful in firmware development and system modeling.
CodaCache is the last-level cache solution from Arteris, designed to solve significant system-on-chip design challenges, including performance bottlenecks, data access latency, and power efficiency constraints. By leveraging high-performance caching techniques, CodaCache effectively optimizes data flow and power consumption across complex SoC architectures, ensuring accelerated memory access times and improved overall system efficiency. This cache solution is highly configurable, enabling developers to fine-tune features such as cache associativity and partitioning, which is critical for maximizing performance in specific application scenarios. Moreover, CodaCache benefits from seamless integration with the Arteris NoC environment, facilitating streamlined data traffic management across integrated systems. The product supports real-time processing needs by enabling a scalable cache that addresses challenges in timing closure and system integration. Performance monitoring and hardware-supported coherency management features empower engineers with tools for enhanced control and monitoring, ensuring the cache operates at peak efficiency. CodaCache’s functional safety and resilience options further its use in critical applications where high reliability is mandatory.
The Flash Protection Series by PUFsecurity revolutionizes the way sensitive data is protected on semiconductor devices by extending the reach of the Hardware Root of Trust to flash memory. This series of IP solutions provides comprehensive protection for a range of memory types including embedded, NAND, and NOR flash solutions. It incorporates PUF-based technology to ensure secure encryption and decryption processes, crucial in safeguarding data integrity at every stage.<br><br>Each module within the Flash Protection Series serves a unique function; PUFef secures embedded flash by using a lite crypto engine, while PUFenc and PUFxip extend this protection to external NAND and NOR flash systems. These modules are designed to avert unauthorized access and leakage of critical data, making them essential components in securing the software and hardware ecosystems of SoCs.<br><br>These solutions allow chip manufacturers to implement robust fingerprinting mechanisms, enhancing the overall security capabilities of semiconductor devices. By facilitating execution-in-place and real-time decryption for flash memory, the Flash Protection Series empowers engineers with the tools needed to create advanced, secure semiconductor products. This provides manufacturers with the confidence that their products are protected against an array of cyber threats.
SRAM, or Static Random-Access Memory, is a critical component in semiconductor design, known for its high-speed data access and reliability. DXCorr’s SRAM solutions are built to maximize performance in a multitude of applications, offering significant advantages in power efficiency and operational speed. These memory arrays are adept at providing the rapid access necessary for high-performance computing environments, paving the way for enhanced data processing and storage capabilities. The flexibility and customizable nature of DXCorr’s SRAM offer clients the ability to tailor capabilities to specific application needs. This makes it an ideal choice for applications requiring low latency and high throughput, such as cache memory in processors and performance-critical applications in telecommunications. Its distinct architecture allows for robust integration into various systems, providing the foundational memory support essential for advanced computing solutions. Designed with leading-edge technology, DXCorr’s SRAM products not only optimize current computing requirements but also anticipate the needs of future technologies. The focus on efficiency ensures reduced power consumption, critical for battery-dependent applications and eco-friendly computing initiatives. SRAM's modular design also facilitates easy scalability, making it a preferred choice for developers aiming to expand functionality and performance consistently.
The APB4 GPIO core by Roa Logic offers highly customizable input/output capabilities for system designers looking to incorporate general-purpose bidirectional IO functionality into their designs. This core is fully compliant with the AMBA APB v2.0 protocol, more commonly known as APB4, and provides automatic synchronization of general inputs to the bus clock, ensuring reliable and seamless operation. Designed for maximum flexibility and configurability, this core allows users to set the number of IOs, operating modes for outputs (push-pull or open-drain), and manage inputs asynchronously to the core while maintaining synchronization through automatic processes. This flexibility makes it highly adaptable to a broad range of use cases where bidirectional communication is essential. The APB4 GPIO is particularly suitable for applications in systems where straightforward, cost-effective peripheral interfacing is required. Developers have access to detailed documentation and source code through Roa Logic's GitHub platform, making it easier to customize and integrate according to specific application needs.
The I/O solutions by Analog Bits encompass differential clocking, signaling, and crystal oscillator IPs. These low-power, high-quality signaling technologies are designed to minimize transistor usage while maximizing signaling performance. With solutions that are silicon-proven and customizable, these IPs are highly efficient and support various die-to-die communication needs.
Everspin's Toggle MRAM stands as a leading non-volatile memory solution, emphasizing simplicity and reliability. It utilizes a one transistor, one magnetic tunnel junction cell design, ensuring high durability and data integrity over 20 years. The patented Toggle MRAM cell employs a magnetic tunnel junction (MTJ) composed of a fixed magnetic layer, a dielectric tunnel barrier, and a free magnetic layer. This architecture allows data to be stored in a manner that combines the endurance of SRAM with the long-term reliability of Flash.\n\nToggle MRAM is fundamentally different from traditional volatile memory technologies. During read processes, the device activates the pass transistor, comparing the cell's resistance to a reference device to retrieve data, while write operations are conducted through magnetic field interactions, ensuring precision without disturbing adjacent cells. This unique setup offers 'instant-on' capabilities, providing reliable operation across a wide temperature range.\n\nThis technology is not only valued for its high performance but also for its versatility. With applications spanning from industrial control systems to consumer electronics, Toggle MRAM ensures data preservation in power-loss scenarios, offering a robust solution for increasing electronic system demands.
aiData introduces a fully automated data pipeline designed to streamline the workflow of automotive Machine Learning Operations (MLOps) for ADAS and autonomous driving development. Recognizing the enormous task of processing millions of kilometers of driving data, aiData employs automation from data collection to curation, annotation, and validation, enhancing the efficiency of data scientists and engineers. This crafted pipeline not only facilitates faster prototyping but also ensures higher quality in deploying machine learning models for autonomous applications. Key components of aiData include the aiData Versioning System, which provides comprehensive transparency and traceability over the data handling process, from recording to training dataset creation. This system efficiently manages metadata, which is integral for diverse use-cases, through advanced scene and context-based querying. In conjunction with the aiData Recorder, aiData automates data collection with precise sensor calibration and synchronization, significantly improving the quality of data for testing and validation. The aiData Auto Annotator further enhances operational efficiency by handling the traditionally labor-intensive process of data annotation using sophisticated AI algorithms. This process extends to multi-sensor data, offering high precision in dynamic and static object detection. Moreover, aiData Metrics tool evaluates neural network performance against baseline requirements, instantly detecting data gaps to optimize future data collection strategies. This makes aiData an essential tool for companies looking to enhance AI-driven driving solutions with robust, real-world data.
The Digital I/O offerings from Certus Semiconductor are meticulously designed to cater to a wide range of GPIO/ODIO standards involving various protocols such as I2C, I3C, and SPI among others. These solutions support 1.2V, 1.8V, 2.5V, 3.3V, and 5V configurations, ensuring adaptability across numerous nodes and foundries. They boast features such as ultra-low power consumption, minimal leakage, and multiple drive strengths, making them suitable for diverse applications. Advanced Electronic Distribution Systems (ESD) protection is a standout feature, capable of withstanding severe ESD stress way beyond common levels. The design includes comprehensive compliance with popular standards like eMMC, RGMII, and LPDDR, providing robustness in various scenarios. The Digital I/O solutions are engineered to be highly resilient, capable of adapting to challenging environmental and operational conditions while maintaining impressive performance metrics. These digital IO designs are complemented by a strong support for rad-hard applications, designed for high reliability and minimal failure rates even in extreme conditions. Certus's digital IO solutions embody a strategic blend of power efficiency and advanced ESD protection that guarantees exceptional performance across a myriad of implementations.
NuRAM Low Power Memory represents a breakthrough in memory technology, utilizing the reliable MRAM architecture to deliver fast access times while significantly reducing leakage power. This IP is a compelling choice for system designs looking to upgrade from traditional SRAM or nvRAM, as well as embedded Flash. Its innovative design allows for substantial size reduction, enabling more efficient memory footprints, which translates into reduced power needs and potentially minimal DDR memory access. Furthermore, the memory can be completely powered down without losing stored data, offering impressive power and latency optimizations that are critical for modern digital systems.
Engineered with SMIC 55nm 2P7M CMOS technology, this 16-bit Sigma-Delta ADC is tailored for precise audio applications. It offers flexible gain settings from 0 to 50dB and intuitive support for PDM, I2S, and TDM interfaces. The versatile design integrates a digital serial interface with selectable microphone bias ranging from -1.3V to 2.9V. Low power consumption is a hallmark, with typical values at 2.0mA for analog and 0.2mA for digital circuits. Ideal for audio, the ADC delivers a superb signal-to-noise ratio of 90 dB, ensuring clarity across uses.
The General Purpose Accelerator (Aptos) from Ascenium stands out as a redefining force in the realm of CPU technology. It seeks to overcome the limitations of traditional CPUs by providing a solution that tackles both performance inefficiencies and high energy demands. Leveraging compiler-driven architecture, this accelerator introduces a novel approach by simplifying CPU operations, making it exceptionally suited for handling generic code. Notably, it offers compatibility with the LLVM compiler, ensuring a wide range of applications can be adapted seamlessly without rewrites. The Aptos excels in performance by embracing a highly parallel yet simplified CPU framework that significantly boosts efficiency, reportedly achieving up to four times the performance of cutting-edge CPUs. Such advancements cater not only to performance-oriented tasks but also substantially mitigate energy consumption, providing a dual benefit of cost efficiency and reduced environmental impact. This makes Aptos a valuable asset for data centers seeking to optimize their energy footprint while enhancing computational capabilities. Additionally, the Aptos architecture supports efficient code execution by resolving tasks predominantly at compile-time, allowing the processor to handle workloads more effectively. This allows standard high-level language software to run with improved efficiency across diverse computing environments, aligning with an overarching goal of greener computing. By maximizing operational efficiency and reducing carbon emissions, Aptos propels Ascenium into a leading position in the sustainable and high-performance computing sector.
The LEE Flash G2 builds upon its predecessor, offering a Flash solution that harmoniously combines with logic circuits while minimizing costs and power consumption. It's based on a simple SONOS memory cell structure, allowing seamless integration with standard logic, thus converting volatile SRAM circuits into non-volatile versions. This innovation removes the need for isolation areas and additional high voltage requirements during read operations, enhancing layout flexibility and power efficiency. Capable of supporting large memory capacities up to a few Megabytes, LEE Flash G2 stands out for its compatibility with existing CMOS processes and its ability to maintain performance without altering design characteristics. The G2 utilizes a very low power Fowler-Nordheim tunneling mechanism, ensuring minimal current consumption during programming and erasing, which leads to significantly reduced testing time and expenses. Its architecture is particularly advantageous in automotive applications requiring high-temperature operations and long data retention periods.
SmartMem Subsystem IP enhances ease of use and scalability by optimizing power, performance, and endurance across a variety of memory types, including NuRAM and other MRAM technologies, as well as RRAM, PCRAM, and embedded Flash. This versatile memory subsystem is fully synthesizable and configurable, making it an excellent choice for SOC designs that require customizable compute-in-memory solutions. SmartMem supports high performance in demanding environments, providing essential features for adaptive memory management that greatly improve the deployed memory's operational efficiency and effectiveness. Its value lies in its ability to improve the utility of existing memory technologies while offering a robust framework for new developments.
I-fuse is designed for seamless integration into standard semiconductor processes, distinguished by its non-explosive mechanism. This one-time programmable memory (OTP) stands out for not requiring special processes or charge pumps, offering ease of use and high reliability. Encapsulated within it is a patented technology that spans processes from 0.7 µm to 22 nm, ensuring flexibility across various manufacturing environments. This innovative solution emphasizes robustness, qualifying to AEC-Q100 standards and making it ideal for automotive, industrial, and medical applications. Its compact design doesn't compromise on performance, providing low programming voltage and low power consumption. I-fuse's adaptability across multiple temperature ranges makes it suitable for both high and low-temperature environments. Incorporating I-fuse into products enhances their competitive edge, thanks to the extensive reliability and testability aspects intrinsically built into the design. It allows seamless product evolution, promoting innovation without sacrificing dependability.
Silvaco's Standard Cell Libraries are crafted for optimal performance, featuring numerous cells designed to maximize power, area, speed, and routing efficiency. Extended with Power Management Kits, these libraries set a standard by enabling late-stage design modifications through ECO Kits. The libraries cater to diverse needs, ensuring robust performance across applications.<br><br>Designed for GlobalFoundries 55nm processes, Silvaco's libraries incorporate low-voltage cells optimized for modern SoC designs. These libraries support flexible power management, allowing designers to achieve significant power efficiency, especially suited for complex, high-performance chips.<br><br>Silvaco offers extensive customization with multi-height and multi-bit standard cells, enhancing routing density and functional capacity. With each variant carefully optimized, these libraries provide power-efficient solutions, accommodating various applications such as low power, high speed, or minimal area.
The Ncore Cache Coherent Interconnect by Arteris addresses the multifaceted challenges of multi-core ASIC design, offering a production-ready, highly configurable coherent NoC interconnect solution. Ncore is tailored for high-performance applications, supporting a variety of protocols compatible with Arm and RISC-V processors while enhancing inter-core communication and synchronization. Ncore is designed with functional safety in mind, making it suitable for ISO 26262 certification, a crucial factor for safety-critical applications such as automotive systems. It ensures credible operation in these environments with built-in safety and reliability features, including FMEDA data and ASIL certification. The IP supports multi-protocol coherency with CHI-B, CHI-E, and ACE alongside I/O coherent agent interfaces, providing versatility and backward compatibility for diverse SoC architectures. Enhanced with unique proxy caches, Ncore lowers power requirements while maintaining high performance, offering a scalable, power-efficient interconnect fabric suitable for a wide array of system scales, from small embedded solutions to extensive multi-billion transistor designs.
The LEE Fuse ZA is a specialized Anti-Fuse memory solution, optimized for one-time programming needs such as memory redundancy and trimming applications. Its design philosophy embraces ease of implementation and cost effectiveness, requiring no additional masks or process steps beyond standard CMOS workflows. With capabilities extending from advanced nodes of sub-10nm to more classic 180nm processes, this memory is versatile across various technology scales. The LEE Fuse ZA stands out due to its high-temperature and long data retention attributes, aligned with the demands of automotive-grade applications. Its efficient design supports widespread application opportunities, enabling manufacturers to integrate this technology into existing systems without significant architectural overhaul. LEE Fuse ZA addresses critical memory needs while maintaining cost efficiency and reliability in challenging environments.
Monolithic Microsystems represents a technological leap in integrated system design, featuring multiple micro-engineered elements within a single chip. This system leverages advanced CMOS technology to unify electronic, photonic, and micromechanical devices, creating a compact and efficient platform suited for a variety of applications. By integrating different functionalities within a single substrate, these Microsystems can enhance performance while reducing the overall system footprint. They are increasingly being used in fields such as telecommunications, medical devices, and consumer electronics, where precision, reliability, and miniaturization are of paramount importance.
DRAM modules are essential components used in a range of electronics, from gaming machines to medical devices. Avant's DRAM offerings are particularly noted for their compliance with JEDEC standards, which ensures interoperability and reliability across different systems and environments. Available in various configurations and designed to manage both low voltage and high power demands, Avant's DRAM caters to industrial, commercial, and consumer needs. Their embedded series of DIMMs offers extensive options, enabling a wide application spectrum, including use in point-of-sale and automation systems.
The iCan PicoPop® System on Module (SOM) by Oxytronic is an ultra-compact computing solution designed for high-performance and space-constrained environments within the aerospace industry. Utilizing the Xilinx Zynq UltraScale+ MPSoC, this module delivers significant processing power ideal for complex signal processing and other demanding tasks. This module's design caters to embedded system applications, offering robust capabilities in avionics where size, weight, and power efficiency are critical considerations. It provides core functionalities that support advanced video processing, making it a pivotal component for those requiring cutting-edge technological support in minimal form factors. Oxytronic ensures that the iCan PicoPop® maintains compatibility with a wide range of peripherals, facilitating easy integration into existing systems. Its architectural innovation signifies Oxytronic's understanding of aviation challenges, providing solutions that are both technically superior and practically beneficial for modern aerospace applications.
Everspin's Parallel Interface MRAM offers a robust solution for environments demanding high-speed data access with non-volatility. This MRAM is SRAM-compatible, ensuring seamless integration with existing systems. With access timings as swift as 35ns, it stands out for its rapid response time and ability to endure numerous read/write cycles without degradation.\n\nThis MRAM design ensures data retention for over two decades, even in the absence of power. Through its low-voltage inhibit circuitry, data integrity is guarded by preventing unintended write actions during voltage fluctuations. Its compatibility with an 8-bit/16-bit interface further enhances its adaptability across diverse technological ecosystems.\n\nThe Parallel Interface MRAM is engineered for high reliability in mission-critical applications. Its structure effectively counteracts power loss scenarios, maintaining data integrity and availability. Such features make it ideal for sectors requiring fail-safe operation, including automotive, aerospace, and medical devices.
TwinBit Gen-1 represents an advanced non-volatile memory solution that is embedded within logic-based semiconductor designs, adapting seamlessly to CMOS logic processes without necessitating additional masks or process steps. This IP supports a range of process nodes from 180nm to 55nm, demonstrating high endurance through over 10,000 program and erase cycles. The memory solution excels in flexibility and efficiency, providing a sizeable range of memory density from 64 bits to 512K bits. Particularly beneficial for applications like analog trimming, security key storage, and system switches for ASIC and ASSP, it helps reduce manufacturing costs while maintaining compatibility with modern semiconductors. TwinBit Gen-1's remarkable features also include low-voltage, low-power operations, complemented by an automotive grade under AEC-Q100 conditions. Additionally, this technology's built-in test circuits streamline stress-free test environments, ensuring its integration doesn't hamper production. Compared to other technologies such as eFuses, TwinBit Gen-1 saves silicon area and simplifies test procedures without sacrificing operational capacity. Its design is particularly poised for embedded applications needing secure reprogrammable memory.
The Rabbit 2000 microprocessor is a compact yet powerful design consisting of 19K gates and supports 100 pins. Tailored for seamless integration across various technologies, this microprocessor offers platform independence that ensures high adaptability in design implementation. It exemplifies a balanced architecture, achieving efficient performance while maintaining modest resource usage, making it ideal for a range of applications requiring robust control and processing capabilities.
PermSRAM is a versatile non-volatile memory solution integrated into foundry standard CMOS platforms accommodating process nodes from 180nm to 22nm and beyond. This memory technology offers various functionalities, such as one-time programmable ROM and pseudo multi-time PROM, which feature a multi-page configuration spread across memory sizes from 64 bits to 512K bits. A notable aspect of PermSRAM is its non-rewritable hardware safety lock that ensures the secure storage of critical security codes. In addition to its security features, PermSRAM delivers high reliability and a stable yield, making it suitable for automotive applications that require data retention at temperatures exceeding 150 degrees Celsius. This memory type is designed for seamless integration with existing system infrastructures as it doesn't need additional read operation circuitry like charge pumps. Its built-in self-test circuit is pivotal for supporting stress-free testing environments, ensuring ease of implementation in various applications like DRM and HDMI decoding, security code storage, and program storage. The benefits of PermSRAM extend to a smaller silicon footprint, achieved through a tamper-resistant design mechanism that uses an invisible charge trap memory system. This compactness is complemented by a fully testable architecture using conventional equipment. PermSRAM beams with capabilities that cater significantly to secure and reliable memory demands, whether for market differentiation or meeting stringent automotive standards.
Tower Semiconductor's Bipolar-CMOS-DMOS (BCD) technology provides high power density and advanced integration capabilities for power management applications. This technology excels in delivering solutions for diverse applications, like motor drivers and DC-DC converters, through various isolation methods and high digital integration options.\n\nDesigned for efficiency across a voltage range up to 700V, the BCD platforms support low Rdson LDMOS for efficient power conversions. They are integral to developing state-of-the-art semiconductor devices tailored for consumers, automotive, and industrial applications. The optimized power handling ensures high performance, enabling devices to deliver the power needed without compromising on energy efficiency.\n\nThe BCD technology is adaptable with Tower's Power platforms available on both 8-inch and 12-inch production wafers, allowing it to meet high-volume production requirements. Such flexibility underpins its application in high-power environments, reinforcing Tower Semiconductor’s leadership in nurturing innovative power management solutions.
EverOn offers a silicon-proven Single Port Ultra Low Voltage (ULV) SRAM solution, providing up to 80% dynamic power savings and up to 75% static power reductions when operated within its voltage range of 0.6V to 1.21V. This high-performing SRAM meets the needs of cutting-edge applications, with cycle times as low as 20MHz at its minimum voltage, scaling up to over 300MHz. Its innovation lies in achieving remarkable power reductions while maintaining flexibility for applications in wearables and IoT, ensuring that devices remain functional across a wide range of power conditions.
The GCRAM offers a cutting-edge on-chip memory solution, designed to meet the growing demand for efficient memory in high-performance applications. Featuring up to a 50% reduction in silicon area and up to 10 times lower power consumption compared to traditional SRAM, this memory technology supports modern applications like artificial intelligence and machine learning. It is seamlessly integrated into standard CMOS process flows, avoiding additional fabrication steps or increased production costs. A standout feature of GCRAM is its high-density capacity, allowing semiconductor companies to achieve significant efficiency improvements without sacrificing performance. The patented technology provides a scalable and flexible solution for extending Moore's Law for on-chip memories, making it a viable replacement for SRAM in a variety of devices. Designed for numerous high-demand applications, GCRAM is tailored to fit the needs of sectors such as automotive, virtual/augmented reality, and high-performance computing. Its compatibility with standard processes and its substantial performance advantages make it a valuable asset in the latest generation of semiconductor technology.
The LEE Flash ZT is crafted for trimming and parameter storage, especially focusing on automotive and analog IC applications. It boasts a Zero Additional Mask technology, requiring no new process steps, thus ensuring ease of implementation and significantly reduced cost. Operating efficiently in harsh environments, the ZT memory supports a wide temperature range and long retention life. It utilizes FN tunneling to achieve exceptionally low power consumption, which greatly shortens testing time and therefore contributes to cost savings. Flexible and robust, the LEE Flash ZT is compatible with standard CMOS processes, allowing existing design and IP reuse. This makes it an optimal solution for applications seeking minimal disruption in existing manufacturing workflows while requiring durable memory solutions for critical settings.
Tailored towards specialty memory architectures, Spectral CustomIP delivers a versatile range suited for various IC applications. Its architecture supports Binary and Ternary CAMs, Multi-Ported memories, and Low Voltage SRAMs, among others, with high-density and low-power designs core to its offering. By using proprietary bit cells, this IP ensures robust performance across operations, coupled with high speed facilitated by performance-oriented circuitry. Spectral CustomIP, supporting standard CMOS, SOI, and embedded Flash processes, offers flexibility through its Memory Development Platform. Users can modify IP designs, supporting diverse technological needs while maintaining high density and low power consumption. This adaptability meets the varied demands of IC designs, suitable for consumer electronics, graphically intensive applications, and mission-critical devices. Providing rich specialty memory selections, Spectral's offerings promote differentiation for IC products within competitive markets. The memory compilers developed under platforms like MemoryCanvas and MemoryTime afford customizable options, including power management, multi-port configurations, and test mode integrations, aligning with intricate design requirements across technological fields.
The Stream Buffer Controller from Enclustra is an efficient IP core designed for high-performance data management in FPGA systems. It functions as a Stream to Memory Mapped DMA bridge, managing up to 16 independent streams with configurable buffer sizes and addresses. This IP core allows for seamless data buffering in external memory, providing virtual FIFO capabilities, all while offering versatile operation modes suited for various applications. Integrated with AMBA AXI4-Stream interfaces and highly configurable, this IP adeptly manages data width conversion and supports robust, independent implementations.
Spectral MemoryIP is a comprehensive set of silicon-proven memory solutions that combine high-density and low-power architectures, ideal for a vast array of storage needs in complex systems. Comprising standard 6 compiler architectures like Single Port and Dual Port SRAMs, ROM, and various Register Files, Spectral MemoryIP leverages both foundry and tailor-made bit cells for reliable operation. Its architecture focuses on performance optimization and minimal power consumption, aimed at integrating high-speed functionality efficiently. The IP is built to adapt to standard CMOS technologies and is augmented by institutions like MemoryCanvas and MemoryTime, which aid in memory development and compilers. Users benefit from its customizable nature, with source code access allowing design modifications and technology porting, tailored to specific needs while optimizing embedded storage solutions. In addressing embedded memory requirements, Spectral's solutions like SpectralSPSRAM and SpectralDPSRAM are designed for sizable monolithic instances, with capabilities extending from scratch pad memories to nonvolatile storage needs. The innovations encompass low dynamic power usage and superior speed, ensuring the adaptability and efficiency necessary for advanced applications like IoT and AI.
Stereax is a series of solid-state batteries, specifically developed for medical and industrial applications. These micro-scale batteries are designed to power next-generation active implanted medical devices and small-scale industrial IoT sensors. Stereax batteries are ultra-thin, rechargeable, and possess a high cycle life, making them ideal for long-duration applications in challenging environments. A standout feature of Stereax batteries is their ability to provide consistent power in a miniature form with a footprint as small as an integrated circuit. The batteries are safe and offer no risk of leakage, thanks to the absence of liquid or polymer components. These batteries support advanced medical applications, such as neurostimulation, cardiac sensing, and smart medical devices. The collaboration with Cirtec Medical ensures the manufacture and commercialization of Stereax batteries for MedTech applications, further expanding their reach and applicability in the healthcare industry. This partnership exemplifies Ilika’s focus on advancing battery technology for secure and reliable medical devices.
The High-Speed Low-Power SRAM by Xenergic presents a balance of power efficiency and performance, making it ideal for a broad range of applications. Known for its ability to reduce dynamic power by up to 40% and leakage power by 55%, this SRAM variant ensures that low-power devices like sensors and wearables maximize their power budgets, thus enhancing user convenience. Especially notable is its suitability for IoT operations at the edge, where the low-power characteristics help to mitigate power constraints associated with edge computing. This ensures faster computations are achievable closer to the edge, significantly reducing latency. Such capabilities are increasingly important with the global expansion of IoT systems. The always-on applicability of this SRAM is another standout feature, enabling it to facilitate cost-efficient power usage in mobile and IoT devices. By cutting down retention leakage, this memory solution ensures that power consumption remains optimally low, even in constantly operating systems like MEMS sensors in mobile technology.
ReRAM, or Resistive RAM, is a revolutionary memory technology developed by CrossBar. It utilizes a unique structure, comprising a simple three-layer design that leverages a top electrode, a switching medium, and a bottom electrode. This assembly allows for the formation of a filament within the switching material when a voltage is applied, resulting in efficient and stable resistance switching. One of the remarkable features of ReRAM is its capability to scale beyond traditional limits, making it highly adaptable in terms of its integration with logic processes across various foundries and down to technology nodes smaller than 10nm. This technology powers a new era of memory storage, offering terabytes of data capacity directly on a single chip through its ability to stack in 3D formations. ReRAM's compatibility with CMOS processes facilitates its deployment in both standalone memory devices and System-on-Chip (SoC) designs. Moreover, it boasts an impressive endurance, with over a million write cycles and a decade-long retention period at elevated temperatures of 85°C, making it an excellent choice for high-performance and high-density applications, including artificial intelligence and secure computing. By offering multifaceted ReRAM IP cores, CrossBar caters to a variety of applications ranging from automotive and industrial to mobile and consumer electronics. Its advantages over conventional Flash memory are evident in reduced latency, faster write speeds, and lower energy consumption, which collectively contribute to enhanced lifetime and performance of storage solutions in modern digital environments.
ASIC North's Sensor Interface Derivatives cater to the advanced needs of modern sensor-based products. These derivatives are designed to integrate with wearable technology and other applications demanding multi-sensor integration. By bridging the gap between sensor inputs and processing needs, they provide exceptional flexibility and accuracy in data handling. Leveraging expertise in Analog to Digital (ADC) and Digital to Analog Converters (DAC), these interfaces can accurately measure and report on parameters such as voltage, current, and resistance, making them versatile tools for engineers engaged in diverse product development projects. Focused on maximizing performance while minimizing energy consumption, these solutions are ideal for use in sectors requiring precise measurement and minimal power use, including consumer electronics and advanced industrial controls.
The 65nm ADC is optimized for low-power operations, offering a 12-bit resolution over eight channels with a conversion rate up to 1MSPS. It takes advantage of a 2.4V to 3.6V analog voltage supply and a 1.08V to 1.32V digital supply. Ideal for data acquisition and portable systems, the ADC comes with a power-efficient design, consuming 1.1mA in typical use and dropping below 0.1µA in power-save mode. Thanks to its precision performance, it achieves 72dB of SNR and maintains accuracy with 11.0 / 12.0 LSB for DNL and INL, respectively.
Join the world's most advanced semiconductor IP marketplace!
It's free, and you'll get all the tools you need to discover IP, meet vendors and manage your IP workflow!