All IPs > Interface Controller & PHY > MIPI
The MIPI category under Interface Controller & PHY encompasses a broad range of semiconductor IPs tailored for high-speed data transfer between components in mobile and IoT devices. MIPI, which stands for Mobile Industry Processor Interface, is an industry-driven standard aimed at simplifying the integration of different advanced technologies into small form factor devices while ensuring optimal communication efficiency and power consumption.
Within this category, you will find semiconductor IPs that address the critical need for reducing latency and increasing the bandwidth of data communication across various internal components. These MIPI interfaces are vital in smartphones, tablets, and other portable electronics, where space is at a premium, yet there's a demand for high-performance data exchange and energy efficiency. The IPs provide solutions for connecting processors to modems, sensors, displays, and cameras, enabling manufacturers to build devices with faster data processing capabilities and higher battery life.
MIPI semiconductor IPs in this category include MIPI D-PHY, C-PHY, and M-PHY, among others. These IPs are designed to support versatile and scalable designs, allowing for personalization depending on the specific requirements of the end product. MIPI D-PHY, for instance, is often used in applications requiring video transmission with high-quality imaging sensors, providing a robust method to deliver both power and data through the same interface.
By leveraging MIPI semiconductor IPs, designers can ensure that their products adhere to the latest industry standards, providing a competitive edge in the technology market. These IPs support a seamless interface experience, enhance data transmission efficiencies, and reduce both development time and costs. Integrating MIPI interface controller and PHY solutions will drive innovation and bring sophisticated electronic products to market faster and more efficiently than ever before.
Silicon Creations' SerDes Interfaces are crafted to handle high-speed data transmission challenges over varied processes, ranging from 12nm to 180nm. Addressing multiple protocols such as CPRI, PCIe, and SATA, these interfaces demonstrate flexibility by supporting data transmission speeds from 100 Mbps to beyond 32 Gbps. The architecture incorporates a host of advanced features including adaptive equalization techniques and programmable de-serialization widths, making it stand out in terms of performance and signal integrity even under challenging conditions. With ultra-low latency PMAs, they sustain excellent operational speed and efficiency, imperative for sophisticated communication applications. Moreover, Silicon Creations partners with leading entities to provide comprehensive solutions, including complete PCIe PHY integrations. This synergy ensures that SerDes Interfaces are fully optimized for operational excellence, delivering stable and reliable communication signals. With an emphasis on low power and minimized area requirements, they cater to burgeoning industry needs for power-efficient and space-conservative designs.
The Mixel MIPI C-PHY IP (MXL-CPHY) is a high-frequency, low-power, low cost, physical layer. (Learn more about Mixel’s MIPI ecosystem at Mixel MIPI Central which gives you access to Mixel’s best of class MIPI ecosystem supply chain partners.) The C-PHY configuration consists of up to three lane modules and is based on 3-Phase symbol encoding technology, delivering 2.28 bits per symbol over three-wire trios and targeting a maximum rate of 2.5 Gsps, 5.7Gbps. The C-PHY is partitioned into a digital module – CIL (Control and Interface Logic) and a mixed-signal module. The PHY IP is provided as a combination of soft IP views (RTL, and STA Constraints) for the digital module, and hard IP views (GDSII/CDL/LEF/LIB) for the mixed-signal module. This unique offering of both soft and hard IP permits architectural design flexibility and seamless implementation in customer-specific design flow. The CIL module interfaces with the protocol layer and determines the global operation of the module. The interface between the PHY and the protocol is using the PHY-Protocol Interface (PPI). The mixed-signal module includes high-speed signaling mode for fast-data traffic and low-power signaling mode for control purposes. During normal operation, a lane switches between low-power and high-speed mode. Bidirectional lanes can also switch communication direction. The change of operating mode or direction requires enabling and disabling of certain electrical functions. These enable and disable events do not cause glitches on the lines that would result in a detection of incorrect signal levels. All mode and direction changes are smooth to always ensure a proper detection of the line signals. Mixel’s C-PHY is a complete PHY, silicon-proven at multiple foundries and multiple nodes. It is built to support the MIPI Camera Serial Interface (CSI) and Display Serial Interface (DSI).
The Mixel MIPI D-PHY IP (MXL-DPHY) is a high-frequency low-power, low cost, source-synchronous, physical layer compliant with the MIPI® Alliance Standard for D-PHY. (Learn more about Mixel’s MIPI ecosystem at Mixel MIPI Central which gives you access to Mixel’s best of class MIPI ecosystem supply chain partners.) Although primarily used for connecting cameras and display devices to a core processor, this MIPI PHY can also be used for many other applications. It is used in a master-slave configuration, where high-speed signals have a low voltage swing, and low-power signals have large swing. High-speed functions are used for high-speed data traffic while low-power functions are mostly used for control. The D-PHY is partitioned into a Digital Module – CIL (Control and Interface Logic) and a Mixed Signal Module. It is provided as a combination of Soft IP views (RTL, and STA Constraints) for Digital Module, and Hard IP views (GDSII/CDL/LEF/LIB) for the Mixed Signal Module. This unique offering of Soft and Hard IP permits architectural design flexibility and seamless implementation in customer-specific design flow. The CIL module interfaces with the protocol layer and determines the global operation of the lane module. The interface between the D-PHY and the protocol is called the PHY-Protocol Interface (PPI). During normal operation, the data lane switches between low-power mode and high-speed mode. Bidirectional lanes can also switch communication direction. The change of operating mode or direction requires enabling and disabling certain electrical functions. These enable and disable events do not cause glitches on the lines that would otherwise result in detections of incorrect signal levels. Therefore, all mode and direction changes occur smoothly, ensuring proper detection of the line signals. Mixel’s D-PHY is a complete PHY, silicon-proven at multiple foundries and multiple nodes. This MIPI PHY is fully integrated and has analog circuitry, digital, and synthesizable logic. Our D-PHY is built to support the MIPI Camera Serial Interface (CSI) and Display Serial Interface (DSI) using the PHY Protocol Interface (PPI). Mixel has provided this IP in many different configurations to accommodate different applications. The Universal Lane configuration can be used to support any allowed use-case, while other configurations are optimized for many different use cases such as Transmit only, Receive only, DSI, CSI, TX+ and RX+. Both TX+ and RX+ configurations support full-speed loopback operation without the extra area associated with a universal lane configuration.
The NuLink Die-to-Die PHY is a state-of-the-art IP solution designed to facilitate efficient die-to-die communication on standard organic/laminate packaging. It supports multiple industry standards, including UCIe and Bunch of Wires (BoW) protocols, and features advanced bidirectional signaling capabilities to enhance data transfer rates. The NuLink technology enables exceptional performance, power economy, and reduced area footprint, which elevates its utility in AI applications and complex chiplet systems. A unique feature of this PHY is its simultaneous bidirectional signaling (SBD), that allows data to be sent and received simultaneously on the same physical line, effectively doubling the available bandwidth. This capacity is crucial for applications needing high interconnect performance, such as AI training or inference workloads, without requiring advanced packaging techniques like silicon interposers. The PHY's design supports 64 data lanes configured for optimal placement and bump map layout. With a focus on power efficiency, the NuLink achieves competitive performance metrics even in standard packaging, making it particularly suitable for high-density systems-in-package solutions.
The Mixel MIPI C/D-PHY combo IP (MXL-CPHY-DPHY) is a high-frequency low-power, low cost, physical layer compliant with the MIPI® Alliance Standard for C-PHY and D-PHY. (Learn more about Mixel’s MIPI ecosystem at Mixel MIPI Central which gives you access to Mixel’s best of class MIPI ecosystem supply chain partners.) The PHY can be configured as a MIPI Master or MIPI Slave, supporting camera interface CSI-2 v1.2 or display interface DSI v1.3 applications in the D-PHY mode. It also supports camera interface CSI-2 v1.3 and display interface DSI-2 v1.0 applications in the C-PHY mode. The high-speed signals have a low voltage swing, while low-power signals have large swing. High-Speed functions are used for high-speed data traffic while low-power functions are mostly used for control. The C-PHY is based on 3-Phase symbol encoding technology, delivering 2.28 bits per symbol over three-wire trios, operating with a symbol rate range of 80 to 4500 Msps per lane, which is the equivalent of about 182.8 to 10260 Mbps per lane. The D-PHY supports a bit rate range of 80 to 1500 Mbps per Lane without deskew calibration, and up to 4500 Mbps with deskew calibration. The low-power mode and escape mode are the same in both the D-PHY and C-PHY modes. To minimize EMI, the drivers for low-power mode are slew-rate controlled and current limited. The data rate in low-power mode is 10 Mbps. For a fixed clock frequency, the available data capacity of a PHY configuration can be increased by using more lanes. Effective data throughput can be reduced by employing burst mode communication. Mixel’s C-PHY/D-PHY combo is a complete PHY, silicon-proven at multiple foundries and multiple nodes. The C/D-PHY is fully integrated and has analog circuitry, digital, and synthesizable logic.
Overview: The MIPI I3C Controller IP Core is fully compliant with the latest I3C specification, offering high bandwidth and scalability for integrating multiple sensors into mobile, automotive, and IoT system-on-chips (SoCs). This controller support in-band interrupts within the 2-wire interface, reducing pin count, simplifying board design, and lowering power and system costs. Backward compatibility with I2C ensures future-proof designs, and the controller's operating modes enable efficient connectivity for systems with multiple ICs and sensors on a single I3C bus. The ARM® AMBA® Advanced High-Performance Bus (AHB) facilitates seamless integration of the IP into the SoC. Key Features: Compliance with MIPI-I3C Basic v1.0 Backward compatibility with I2C Two-wire serial interface up to 12.5MHz using Push-Pull Dynamic and Static Addressing support Single Data Rate messaging (SDR) Broadcast and Direct Common Command Code (CCC) Messages support In-Band Interrupt capability Hot-Join Support Applications: Consumer Electronics Defense Aerospace Virtual Reality Augmented Reality Medical Biometrics (Fingerprints, etc.) Automotive Devices Sensor Devices
The Multi-Protocol SERDES offered by Pico Semiconductor is a versatile solution capable of handling a variety of communication protocols. This series of SERDES includes a 4-channel configuration that supports data rates up to 32Gbps, designed for integration with XAUI, RXAUI, and SGMII. It is compatible with multiple process nodes provided by foundries like TSMC and GF, offering robust performance across different semiconductor environments. These SERDES are crafted to meet high-performance metrics, capturing speeds up to 16Gbps and 6.5Gbps across various models, with advanced versions reaching up to 32Gbps. This exceptional range not only ensures compatibility with current technologies but also prepares systems for future updates, sustaining high data throughput. By delivering reliable high-speed data transmission capabilities, the Multi-Protocol SERDES from Pico Semiconductor is integral for networking, high-speed computing, and data storage applications, where efficient and speedy data transfer is paramount.
The CT25205 is a comprehensive digital controller designed for 10BASE-T1S Ethernet applications, providing seamless integration with Ethernet MACs and offering essential PMA, PCS, and PLCA Reconciliation Sublayer components. Crafted in Verilog 2005 HDL, this core is fully synthesizable on standard cells and FPGA systems, ensuring versatile deployment in various network architectures. The IP also supports PLCA RS, enabling advanced Ethernet features without the need for additional MAC extensions. It's developed to function with the OPEN Alliance 10BASE-T1S PMD interface, making it a robust solution for modern Ethernet-based systems.
Overview: The MIPI CSI-2 (Camera Serial Interface) defines an interface between a peripheral device (camera) and host processor (application engine) for mobile applications. It offers the mobile industry a standard, robust, scalable, low-power, high-speed, and cost-effective interface that supports a wide range of imaging solutions for mobile devices. Key Features: Compliance with MIPI-CSI-2 version 3.0 Compliance with C-PHY 2.0 for MIPI CSI-2 Version 3.0 Compliance with D-PHY 2.5 for MIPI CSI-2 Version 3.0 Compatibility with I2C and I3C (SDR, DDR) for CCI interface Support for C-PHY 2.0, D-PHY 2.5, A-PHY, M-PHY with configurable PHY layer Processor Interfaces: AHB Lite/APB/AXI for configuration Lane Merging Function for consolidating packet data in CSI-2 Receiver De-skew detection in D-PHY and sync word detection in C-PHY Pixel Formats Supported: YUV, RGB, and RAW data Virtual Channels: 16 for D-PHY, 32 for C-PHY Error detection, interleaving, scrambling, and descrambling support Byte to pixel conversion in LLP layer Applications: Imaging Surveillance Gaming Sensor devices Internet of Things (IoT) Wearable devices Virtual Reality Augmented Reality Automotive Systems
Overview: The MIPI DSI Transmitter IP is designed to transmit data to the host processor, providing the mobile industry with a standard, robust, scalable, low-power, high-speed, and cost-effective interface that supports a wide range of imaging solutions for mobile devices. Key Features: Compliance with MIPI-DSI-2 version 2.0 Compliance with C-PHY version 2.0 for DSI-2 Version-2 Compliance with D-PHY version 1.2 for DSI-2 Version-2.0 Compliance with D-PHY version 2.0 for DSI-2 Version-2.0 Compliance with D-PHY version 3.0 for DSI-2 Version-2.0 Compliance with MIPI SDF specification Compliance with DBI-2 and DPI-2 Pixel to Byte conversion support from Application layer to LLP layer Support for Command Mode and Video Mode Continuous clock behavior in clock lane for D-PHY physical layer De-skew sequence pattern for video mode support Lane Distribution Function for distributing packet bytes across N-Lanes Connectivity with two, three, or four DSI Receivers HS mode and Escape mode support for transmission of Packets in both C-PHY and D-PHY Symbol slip detection code and sync symbol insertion in C-PHY physical layer Target Applications: Imaging Surveillance Gaming Sensor devices Internet of Things (IoT) Wearable devices Virtual Reality Augmented Reality Automotive Systems
Time-Triggered Ethernet (TTE) combines the robustness of Ethernet technology with the precision of time-triggered communication. Designed for critical applications that demand reliability and synchronized communication, TTE finds its place in aerospace and industrial sectors. TTE operates by affording secure, deterministic data transmission over Ethernet networks. It achieves this by dedicating specific time slots for high-priority traffic, ensuring latency and jitter are minimized. This segregation allows time-sensitive data to safely coexist with traditional Ethernet traffic, without sacrificing normal network operations. The protocol's architecture underlies a mixed-criticality networking environment, supporting integration with standard Ethernet devices. TTE's scheduling mechanism guarantees timely delivery of critical messages, crucial in environments where even microsecond delays can impact overall system performance. Its application ensures Ethernet networks meet the stringent requirements of real-time operations synonymous with safety-critical systems.
Overview: The SPD5 Hub controller IP is designed to interface with the I3C/I2C Host Bus, allowing for the isolation of local devices such as Temperature Sensors (TS) from the master host bus. It features a Two-wire serial interface with SCL and SDA busses. Key Features: Compliance with JEDEC's JESD300-5 Support for speeds up to 12.5MHz Bus Reset functionality SDA arbitration support Enabled Parity Check Support for Packet Error Check (PEC) Switch between I2C and I3C Basic Mode Default Read address pointer Mode Write and read operations for SPD5 Hub with or without PEC In-band Interrupt (IBI) support Write Protection for NVM memory blocks Arbitration for Interrupts Clearing of Device Status and IBI Status Registers Error handling for Packet Error Check and Parity Errors Common Command Codes (CCC) for I3C Basic Mode Dynamic IO Operation Mode Switching Bus Clear and Bus Reset capabilities SPD5 Command features for NVM memory and Register Space Read and Write access to NVM memory Support for Offline Tester operation Applications: DDR5 DIMM Application Environment DDR5 NVDIMM Application Environment Automotive Devices Memory Devices Power Management Devices Defense/Aerospace/Customer Electronics
The HOTLink II Product Suite is another remarkable offering from Great River Technology. Built to complement their ARINC 818 suite, HOTLink II provides an integrated framework for crafting high-performance digital data links. This suite ensures seamless, secure, and reliable data transmission over fiber or copper cables across various platforms. Developed with a focus on flexibility and functionality, the HOTLink II capabilities enhance system integrators' ability to deploy effective communication solutions within aircraft and other demanding environments. The emphasis on robust, low-latency data transfer makes it an ideal choice for real-time applications where precision and reliability are paramount. Broad compatibility is a hallmark of HOTLink II, facilitating integration into diverse infrastructures. Backed by Great River Technology's expertise and support, customers are empowered to advance their system communication capabilities efficiently and cost-effectively.
MIPI I3C Controller IP Core is fully compliant with the latest I3C specification and delivers high bandwidth and scalability for integration of multiple sensors into mobile, automotive and IoT system-on-chips (SoCs). The MIPI I3C Controller supports in-band interrupts within the 2-wire interface provides significantly lower pin count, simplifying board design and reducing power and cost of the system. The MIPI I3C Controller IP is fully backward compatible with I2C, allowing designers to future proof their design, and the I3C controller IP operating modes enable systems with several ICs to efficiently connect to all sensors on a single I3C bus. The standard-based ARM® AMBA® Advanced High Performance Bus (AHB) connects the IP to the rest of the SoC offering easy IP integration. MIPI I3C Controller IP is designed to easily integrate into any SoC offering lowest gate count and quickly fit into any Chip development flow.
Silicon Creations crafts highly reliable LVDS interfaces designed to meet diverse application needs, going from bi-directional I/Os to specialized uni-directional configurations. Spanning process compatibilities from 90nm CMOS to advanced 7nm FinFET, these interfaces are a cornerstone for high-speed data communication systems, thriving particularly in video data transmission and chip-to-chip communications. Supporting robust data rates over multiple channels, the LVDS Interfaces guarantee flexible programmability and protocol compatibility with standards such as FPD-Link and Camera-Link. They capitalize on proven PLL and CDR architectures for superior signal integrity and error-free data transfers. Operating efficiently in various technology nodes, they remain highly effective across collaborative chipset environments. The interfaces are fortified with adaptable features like dynamic phase alignment to stabilize data sequences and on-die termination options for superior signal integrity. Their proven record places them as a critical enabler in applications where consistent high-speed data transfer is paramount, demonstrating Silicon Creations’ prowess in delivering industry-leading communication solutions.
The 10G TCP Offload Engine with MAC and PCIe interface is engineered for ultra-low latency environments, serving as a robust solution for efficient data transmission in high-speed networks. By offloading TCP processing from the host CPU, it significantly reduces processing demands, enabling data centers and network infrastructures to streamline operations and enhance throughput. This offload engine demonstrates impressive scalability, supporting a variety of session capacities with consistent, minimal latency. Implemented using advanced architecture techniques, this offload engine offers a comprehensive TCP stack with MAC interface capabilities, ensuring seamless data flow across network devices. Its hardware-centric design further eliminates system bottlenecks, delivering high bandwidth and reliable data transmission even under high-load conditions. The PCIe integration allows for rapid, efficient communication within network systems, improving overall data handling efficiency. This solution is designed to minimize jitter and operates effectively in various network setups, making it ideal for cloud computing, large-scale data centers, and other demanding environments. Its robust configuration options and support for multiple sessions simultaneously make it a versatile choice for enterprises looking to maximize their network performance while reducing overhead costs.
The 1G to 224G SerDes is a state-of-the-art SerDes solution designed for applications requiring a wide array of data rates and signaling schemes. Supporting speeds from 1 Gbps up to an impressive 224 Gbps, this SerDes IP caters to multiple industry standard protocols such as Ethernet, PCIe, and CXL. The flexibility of this SerDes allows for integration into a wide range of devices, from data centers to network switches, where high data throughput and reliability are crucial.\n\nAt its core, this SerDes IP utilizes advanced modulation schemes including PAM2 (also known as NRZ), PAM4, and even more advanced techniques like PAM6 and PAM8. This flexibility in modulation ensures that the IP can adapt to different signal integrity requirements and channel conditions, making it an ideal choice for high-performance computing environments.\n\nMoreover, the 1G to 224G SerDes is engineered to deliver leading-edge performance with minimal power consumption, maintaining connectivity efficiency across various operational spectrums. Its robust design ensures that signal integrity is preserved, reducing bit error rates significantly, which is critical in maintaining the reliability of high-speed networks.
Overview: The MIPI CSI-2 (Camera Serial Interface) Transmitter IP establishes an interface between a peripheral device (camera) and host processor (application engine) for mobile applications. It offers the mobile industry a standard, robust, scalable, low-power, high-speed, and cost-effective interface that caters to a wide range of imaging solutions for mobile devices. Key Features: Compliance with MIPI-CSI-2 version 3.0 Compliance with C-PHY 2.0 for MIPI CSI-2 Version 3.0 Compliance with D-PHY 2.5 for MIPI CSI-2 Version 3.0 Compatibility with I2C and I3C (SDR, DDR) for CCI interface Pixel to Byte conversion support from Application layer to LLP layer Continuous clock behavior in clock lane for D-PHY physical layer De-skew sequence pattern in Data Lane Module Lane Distribution Function for distributing packet bytes across N-Lanes Sync word insertion through PPI command in C-PHY physical layer Insertion of Filler bytes in LLP layer for packet footer alignment Setting specific bits in packet header Defining frame blanking period Seed selection in scrambler and de-scrambler by Sync word Support for C-PHY/D-PHY/A-PHY/M-PHY with one PHY layer configuration Target Applications: Imaging Surveillance Gaming Sensor devices Internet of Things (IoT) Wearable devices Virtual Reality Augmented Reality Automotive Systems
Overview: The Power Management IC (PMIC) is specifically designed for DDR5 RDIMM, DDR5 LRDIMM, and DDR5 NVDIMM applications. It includes switching and LDO regulators to efficiently manage power distribution. The PMIC utilizes a MIPI-I3C Interface to select appropriate power settings for various application environments and is capable of operating at speeds up to 12.5MHz. Key Features: Maximum Operating speed of 12.5MHz Flexible Open-Drain IO (I2C) and Push-Pull (I3C) IO Support Multi-Time Programmable Non-Volatile Memory Interface Programmable and DIMM-specific registers for customization Error log registers for tracking Packet Error Check (PEC) and Parity Error Check functions Bus Reset function Support I3C Basic mode In-Band Interrupt (IBI) support Write, read, and default read operations in I2C mode Error handling for PEC, Parity errors, and CCC errors I3C Basic Common Command Codes (CCC) support Applications: DDR5 DIMM Application Environment DDR5 NVDIMM Application Environment Automotive Devices Memory Devices Power Management Devices Defense/Aerospace/Customer Electronics
The Nerve IIoT Platform is a comprehensive solution for machine builders, offering cloud-managed edge computing capabilities. This innovative platform delivers high levels of openness, security, flexibility, and real-time data handling, enabling businesses to embark on their digital transformation journeys. Nerve's architecture allows for seamless integration with a variety of hardware devices, from basic gateways to advanced IPCs, ensuring scalability and operational efficiency across different industrial settings. Nerve facilitates the collection, processing, and analysis of machine data in real-time, which is crucial for optimizing production and enhancing operational efficiency. By providing robust remote management functionalities, businesses can efficiently handle device operations and application deployments from any location. This capacity to manage data flows between the factory floor and the cloud transitions enterprises into a new era of digital management, thereby minimizing costs and maximizing productivity. The platform also supports multiple cloud environments, empowering businesses to select their preferred cloud service while maintaining operational continuity. With its secure, IEC 62443-4-1 certified infrastructure, Nerve ensures that both data and applications remain protected from cyber threats. Its integration of open technologies, such as Docker and virtual machines, further facilitates rapid implementation and prototyping, enabling businesses to adapt swiftly to ever-changing demands.
The C100 is designed to enhance IoT connectivity and performance with its highly integrated architecture. Built around a robust 32-bit RISC-V CPU running up to 1.5GHz, this chip offers powerful processing capabilities ideal for IoT applications. Its architecture includes embedded RAM and ROM memory, facilitating efficient data handling and computations. A prime feature of the C100 is its integration of Wi-Fi components and various transmission interfaces, enhancing its utility in diverse IoT environments. The inclusion of an ADC, LDO, and a temperature sensor supports myriad applications, ensuring devices can operate in a wide range of conditions and applications. The chip's low power consumption is a critical factor in this design, enabling longer operation duration in connected devices and reducing maintenance frequency due to less charging or battery replacement needs. This makes the C100 chip suitable for secure smart home systems, interactive toys, and healthcare devices.
The MXL-LVDS-MIPI-RX is a high-frequency, low-power, low-cost, source-synchronous, Physical Layer that supports the MIPI® Alliance Standard for D-PHY and compatible with the TIA/EIA-644 LVDS standard. (Learn more about Mixel’s MIPI ecosystem at Mixel MIPI Central which gives you access to Mixel’s best of class MIPI ecosystem supply chain partners.) The IP is configured as a MIPI slave and consists of 5 lanes: 1 Clock lane and 4 data lanes, which make it suitable for display serial interface applications (DSI). The High-Speed signals have a low voltage swing, while Low-Power signals have large swing. High-Speed functions are used for High-Speed Data traffic while low power functions are mostly used for control.
The MXL-LVDS-DPHY-DSI-TX is a combo PHY that consists of a high-frequency low-power, low-cost, source-synchronous, Physical Layer supporting the MIPI® Alliance Standard for D-PHY and a high performance 4-channel LVDS Serializer implemented using digital CMOS technology. (Learn more about Mixel’s MIPI ecosystem at Mixel MIPI Central which gives you access to Mixel’s best of class MIPI ecosystem supply chain partners.) In LVDS mode, both the serial and parallel data are organized into 4 channels. The parallel data is 7 bits wide per channel. The input clock is 25MHz to 150MHz. The serializer is highly integrated and requires no external components. The circuit is designed in a modular fashion and desensitized to process variations. This facilitates process migration, and results in a robust design.
The THOR platform is a versatile tool for developing application-specific NFC sensor and data logging solutions. It incorporates silicon-proven IP blocks, creating a comprehensive ASIC platform suitable for rigorous monitoring and continuous data logging applications across various industries. THOR is designed for accelerated development timelines, leveraging low power and high-security features. Equipped with multi-protocol NFC capabilities and integrated temperature sensors, the THOR platform supports a wide range of external sensors, enhancing its adaptability to diverse monitoring needs. Its energy-efficient design allows operations via energy harvesting or battery power, ensuring sustainability in its applications. This platform finds particular utility in sectors demanding precise environmental monitoring and data management, such as logistics, pharmaceuticals, and industrial automation. The platform's capacity for AES/DES encrypted data logging ensures secure data handling, making it a reliable choice for sectors with stringent data protection needs.
The ARINC 818 Streaming solution is engineered to provide unrivaled real-time streaming conversion between a pixel bus and ARINC 818 formatted serial data streams. This solution allows seamless transition from traditional pixel data to advanced ARINC standards, facilitating comprehensive image and data transmissions across avionics systems. This solution is crucial for systems requiring high-performance graphic data management, maximizing efficiency in data handling while maintaining impeccable integrity of transmitted streams. Its processing efficiency ensures minimized latency, which is pivotal for real-time operations where timing accuracy is non-negotiable. Serving the demanding requirements of avionics communication platforms, this core manages intricate data flows effortlessly. The ARINC 818 Streaming solution embodies a tradition of excellence in data management, tailored to bolster the capabilities of aviation systems with its adept data transformation properties.
The MXL-SR-LVDS is a high performance 4-channel LVDS Serializer implemented using digital CMOS technology. Both the serial and parallel data are organized into four channels. The parallel data width is programmable, and the input clock is 25MHz to 165MHz. The Serializer is highly integrated and requires no external components. It employs optional pre-emphasis to enable transmission over a longer distance while achieving low BER. The circuit is designed in a modular fashion and desensitized to process variations. This facilitates process migration, and results in a robust design.
The GNSS VHDL Library is a cornerstone offering from GNSS Sensor Ltd, engineered to provide a potent solution for those integrating Global Navigation Satellite System functionalities. This library is lauded for its configurability, allowing developers to harness the power of satellite navigation on-chip efficiently. It facilitates the incorporation of GPS, GLONASS, and Galileo systems into digital designs with minimum fuss. Designed to be largely independent from specific CPU platforms, the GNSS VHDL Library stands out for its flexibility. It employs a single configuration file to adapt to different hardware environments, ensuring broad compatibility and ease of implementation. Whether for research or commercial application, this library allows for rapid prototyping of reliable GNSS systems, providing essential building blocks for precise navigation capabilities. Integrating fast search engines and offering configurable signal processing capabilities, the library supports scalability across platforms, making it a crucial component for industries requiring high-precision navigation technology. Its architecture supports both 32-bit SPARC-V8 and 64-bit RISC-V system-on-chips, highlighting its adaptability and cutting-edge design.
The Time-Triggered Protocol (TTP) is an advanced communication protocol designed to enable high-reliability data transmission in embedded systems. It is widely used in mission-critical environments such as aerospace and automotive industries, where it supports deterministic message delivery. By ensuring precise time coordination across various control units, TTP helps enhance system stability and predictability, which are essential for real-time operations. TTP operates on a time-triggered architecture that divides time into fixed-length intervals, known as communication slots. These slots are assigned to specific tasks, enabling precise scheduling of messages and eliminating the possibility of data collision. This deterministic approach is crucial for systems that require high levels of safety and fault tolerance, allowing them to operate effectively under stringent conditions. Moreover, TTP supports fault isolation and recovery mechanisms that significantly improve system reliability. Its ability to detect and manage faults without operator intervention is key in maintaining continuous system operations. Deployment is also simplified by its modular structure, which allows seamless integration into existing networks.
The Mixel MIPI M-PHY (MXL-MPHY) is a high-frequency low-power, Physical Layer IP that supports the MIPI® Alliance Standard for M-PHY. (Learn more about Mixel’s MIPI ecosystem at Mixel MIPI Central which gives you access to Mixel’s best of class MIPI ecosystem supply chain partners.) The IP can be used as a physical layer for many applications, connecting flash memory-based storage, cameras and RF subsystems, and for providing chip-to-chip inter-processor communications (IPC). It supports MIPI UniPro and JEDEC Universal Flash Storage (UFS) standard. By using efficient BURST mode operation with scalable speeds, significant power savings can be obtained. Selection of signal slew rate and amplitude allows reduction of EMI/RFI, while maintaining low bit error rates.
The FC Upper Layer Protocol (ULP) provides a hardware-based solution for implementing FC-AE-RDMA or FC-AV standards, designed for seamless full-network stack integration. This IP solution ensures rigorous buffer mapping, delivering advanced DMA controllers and message chain engines that streamline data integrity management processes. As it aligns with F-18 and F-15 compatible interface modes, it is particularly suited for high-demand aviation data management applications where precision and performance are pivotal. The ULP IP core offers enhanced control over fiber channel-based communication infrastructures, promoting superior data processing capabilities tailored to intricate defense systems. The dependable handling of protocol processes underpins the core's design, offering the ideal balance of accuracy and efficiency needed in today's highly dynamic communication landscapes. With consistent reliability and integration ease, it represents a culmination of mastery in fiber channel data solutions tailored for military applications.
The ARINC 818 Direct Memory Access (DMA) component provides a thorough hardware IP solution tailored for the transmission and reception of the ARINC 818 protocol. Engineered for use in embedded systems applications, it optimizes formatting, timing, and buffer management, crucial for maintaining seamless operations. This core takes significant responsibilities off the main processor, boosting efficiency across embedded environments by handling demanding protocol requirements robustly. Its architecture is optimized to enhance embedded application performance, promoting smooth and efficient interactions between diverse system components. Critical for protocol offloading, this solution delivers substantial improvements in processing times and data management within advanced communication infrastructures. The ARINC 818 DMA is essential for systems faced with complex data engagements, ensuring resource maximization without compromise on performance or reliability.
Arasan's MIPI DSI-2 Transmitter IP is an advanced solution catering to high-definition display technologies. Built to conform to the latest MIPI standards, this IP ensures vigilant data transmission from processors to display panels, a necessity in the evolving domains of automotive electronics, smart devices, and high-end consumer electronics. The DSI-2 Transmitter stands out for its support of ultra-high-definition display protocols, which are pivotal in applications demanding crisp, vivid visuals. This transmitter IP is designed with adaptability in mind, allowing for customization that meets specific display requirements. By incorporating power-saving features, it ensures optimal performance without compromising on energy efficiency, a critical consideration for battery-powered devices. It is also scalable, accommodating future advancements in display technology seamlessly. Designed to maintain data fidelity and minimal latency, the DSI-2 Transmitter reliably facilitates the delivery of high-bandwidth video and image data across other media. Its robust design guarantees effective performance across applications, setting the stage for next-generation visual experiences.
The FC Anonymous Subscriber Messaging (ASM) IP Core offers a full-network stack hardware implementation of FC-AE-ASM, tailored to enable hardware-based label lookup, DMA controllers, and message chain engines, optimizing defense communication processes. Specifically engineered for F-35 system compatibility, the ASM core ensures seamless integration and reliable data flow management across intricate aviation systems. By providing real-time processing efficiency and robust communication controls, it addresses complex data interactions inherent in military-grade communication channels, ensuring high precision and execution reliability. This core empowers operational frameworks with advanced data management potency, ensuring that mission-critical messaging systems operate smoothly and efficiently. The ASM IP reflects a commitment to excellence in communication integrity and operation reliability, serving as a crucial component for integrated defense communication infrastructures.
The Multi-Protocol SerDes provided by Silicon Creations serves as an essential component for high-speed data interfaces across multiple industry protocols. This SerDes portfolio accommodates a vast array of protocols such as PCIe, JESD204, XAUI, and many more, facilitating broad compatibility with industry standards. Operating across 12nm to 180nm processes, these interfaces support data rates from 100 Mbps to an impressive 32.75 Gbps. Incorporating advanced features like programmable de-serialization widths and adaptive equalization, the Multi-Protocol SerDes ensures optimal signal integrity and performance even in demanding environments. The design includes jitter cleaner functions and employs low-latency optimized PMAs, delivering high precision and speed across various operational scenarios. This comprehensive adaptability ensures seamless integration into a wide range of applications from communications to high-performance computing. Supported by robust architectures, the SerDes enables enhanced efficiency and reliability, featuring low power consumption and reduced area overheads. With a commitment to customer satisfaction, Silicon Creations offers complete solutions through partnerships with leading controller vendors, cementing its products as high-value choices for modern electronic systems.
Dyumnin Semiconductors' RISCV SoC is a robust solution built around a 64-bit quad-core server-class RISC-V CPU, designed to meet advanced computing demands. This chip is modular, allowing for the inclusion of various subsystems tailored to specific applications. It integrates a sophisticated AI/ML subsystem that features an AI accelerator tightly coupled with a TensorFlow unit, streamlining AI operations and enhancing their efficiency. The SoC supports a multimedia subsystem equipped with IP for HDMI, Display Port, and MIPI, as well as camera and graphic accelerators for comprehensive multimedia processing capabilities. Additionally, the memory subsystem includes interfaces for DDR, MMC, ONFI, NorFlash, and SD/SDIO, ensuring compatibility with a wide range of memory technologies available in the market. This versatility makes it a suitable choice for devices requiring robust data storage and retrieval capabilities. To address automotive and communication needs, the chip's automotive subsystem provides connectivity through CAN, CAN-FD, and SafeSPI IPs, while the communication subsystem supports popular protocols like PCIe, Ethernet, USB, SPI, I2C, and UART. The configurable nature of this SoC allows for the adaptation of its capabilities to meet specific end-user requirements, making it a highly flexible tool for diverse applications.
The DisplayPort 1.4 provides a comprehensive solution for DisplayPort needs by offering both source (DPTX) and sink (DPRX) configurations. It supports various link rates from 1.62 Gbps to 8.1 Gbps, including embedded DisplayPort (eDP) rates. This versatility makes it ideal for a wide range of applications, including those requiring either Single Stream Transport (SST) or Multi Stream Transport (MST). With support for dual and quad pixels per clock, as well as 8 & 10-bit video in RGB and YUV 4:4:4 color spaces, the DisplayPort 1.4 is well-equipped to handle high-resolution video tasks. The robust features of DisplayPort 1.4 include a Secondary Data Packet Interface designed for audio and metadata transport, ensuring comprehensive support for multimedia applications. Parretto also enhances the IP with a Video Toolbox containing a timing generator, test pattern generator, and video clock recovery functions. These components facilitate seamless integration and operational efficiency within a wide array of systems. This product supports numerous FPGA devices, such as AMD UltraScale+, Intel Cyclone 10 GX, and Lattice CertusPro-NX, giving users flexibility in their choice of hardware. The availability of source code on GitHub allows users to tailor the IP specifically to their design requirements, broadening the scope of customization and ensuring a perfect fit in various applications.
The Dynamic PhotoDetector for Smartphone Applications is ActLight's state-of-the-art solution for enhancing mobile light sensing technology. This component integrates cutting-edge Dynamic PhotoDetector capabilities, utilizing a unique mode of operation that offers unprecedented levels of sensitivity and performance in detecting light changes. Aimed at applications like proximity and ambient light sensing, the DPD ensures that smartphones can dynamically adjust functions such as screen brightness and feature activation based on environmental lighting, thereby offering users a richer, more adaptive experience. It is particularly efficient in optimizing power consumption due to its ability to operate at lower voltages than traditional sensors, which not only preserves battery life but also supports sustainable device usage. The sensor's design allows for seamless incorporation into existing smartphone architectures without necessitating major redesigns, enabling manufacturers to easily enhance their devices with high-precision light sensing capabilities. Its ability to capture highly accurate 3D data further paves the way for innovative applications in augmented and virtual realities, making the DPD a versatile tool for future-looking smartphone features.
The MIPI interface from Silicon Library Inc. is engineered to accommodate intra-system data transfer with optimal efficiency, employing DPHY-Tx and DPHY-Rx standards to facilitate smooth communication between devices' components. This component is indispensable for mobile and camera applications, where high-speed communication is paramount. MIPI interfaces are integral to high-bandwidth data transmission, often found in smartphones and tablets where they manage the interplay between cameras, displays, and the main processing units. This allows for fast, reliable data exchange vital for real-time image processing and display rendering. The MIPI solution exemplifies Silicon Library Inc.'s commitment to high-performance digital connectivity solutions, enabling manufacturers to enhance and optimize critical workflows in handheld devices. By reducing latency and increasing data throughput, this IP plays a key role in today’s tech devices meeting consumer demand for speed and efficiency.
The BlueLynx Chiplet Interconnect is a sophisticated die-to-die interconnect solution that offers industry-leading performance and flexibility for both advanced and conventional packaging applications. As an adaptable subsystem, BlueLynx supports the integration of Universal Chiplet Interconnect Express (UCIe) as well as Bunch of Wires (BoW) standards, facilitating high bandwidth capabilities essential for contemporary chip designs.\n\nBlueLynx IP emphasizes seamless connectivity to on-die buses and network-on-chip (NoCs) using standards such as AMBA, AXI, and ACE among others, thereby accelerating the design process from system-on-chip (SoC) architectures to chiplet-based designs. This innovative approach not only allows for faster deployment but also mitigates development risks through a predictable and silicon-friendly design process with comprehensive support for rapid first-pass silicon success.\n\nWith BlueLynx, designers can take advantage of a highly optimized performance per watt, offering customizable configurations tailored to specific application needs across various markets like AI, high-performance computing, and mobile technologies. The IP is crafted to deliver outstanding bandwidth density and energy efficiency, bridging the requirements of advanced nodal technologies with compatibility across several foundries, ensuring extensive applicability and cost-effectiveness for diverse semiconductor solutions.
The ARINC 818 Product Suite offered by Great River Technology is designed to support the entire lifecycle of ARINC 818 enabled systems. This suite offers tools for the development, qualification, and testing of ARINC 818 products. With robust simulation capabilities and expert guidance, clients benefit from a streamlined process to bring complex ARINC 818-based systems to functional reality. Whether for airborne, ground, or naval applications, the suite provides comprehensive support in implementing ARINC 818 protocols. Great River Technology's ARINC 818 tools are the cornerstone for organizations needing to integrate advanced video and data systems operationally. The product suite includes a development suite and flyable products, offering resources for learning, implementing, and testing ARINC 818 standards. Their unique ability to productize every aspect of the ARINC 818 standard demonstrates unparalleled commitment to customer success in avionic technology. Clients can access specialized interface solutions that facilitate easy integration into varied technological environments. As a leading supplier of ARINC 818 tools globally, Great River Technology supports the development and qualification of systems to assure performance in demanding operational circumstances.
The FC Link Layer (LL) IP core is designed to offer a comprehensive hardware solution for the Fiber Channel (FC) link's FC-1 and FC-2 layers. This flexibly integrates into various data flow processes necessary for high-resource environments, ensuring efficient and systematic data transfer. With accuracy poised as its foundation, this core enhances data processing functions across military and aerospace communication platforms requiring precision. Embedded in the core is a design to handle multifaceted communication scenarios which are pivotal for systematic data management within high-performance environments. Tailored for defense-related operations, the IP core supports smooth, real-time signal processing, enabling optimal alignment of system resources while adhering to rigorous fiber channel standards. The FC Link Layer solution represents the high-standard engineering necessary to meet sophisticated communication needs of today's defense networks.
The MIPI D-PHY solution from SkyeChip offers a fully integrated macro that complies with the MIPI D-PHY spec v2.5. This IP is pivotal for developers looking to integrate high-speed data transmission capabilities into devices, supporting up to 2.5 Gbps per lane. It incorporates low-power escape modes and ultra-low power states, which significantly enhance its suitability for battery-operated devices with varying performance demands. The D-PHY’s configurability allows customization to meet specific system requirements, offering flexibility in design. Capable of handling intricate data flows with precision, this IP is a core component for mobile and consumer electronics that demand efficient and reliable data communication channels. It is widely applicable for cameras, display interfaces, and various other high-speed serial protocols.
The MXL-DS-LVDS is a high performance 4-channel LVDS Deserializer implemented using digital CMOS technology. Both the serial and parallel data are organized into four channels. The parallel data can be 7 or 10 bits wide per channel. The input clock is 25MHz to 165MHz. The De-serializer is highly integrated and requires no external components. Great care was taken to insure matching between the Data and Clock channels to maximize the deserializer margin. The circuit is designed in a modular fashion and desensitized to process variations. This facilitates process migration, and results in a robust design.
The MIPITM SVRPlus2500 provides an efficient solution for high-speed 4-lane video reception. It's compliant with CSI2 rev 2.0 and DPHY rev 1.2 standards, designed to facilitate easy timing closure with a low clock rating. This receiver supports PRBS, boasts calibration capabilities, and offers a versatile output of 4/8/16 pixels per clock. It features 16 virtual channels and 1:16 input deserializers per lane, handling data rates up to 10Gbps, making it ideal for complex video processing tasks.
The MIPITM CSI2MUX-A1F is an innovative video multiplexor designed to manage and aggregate multiple video streams effortlessly. It supports CSI2 rev 1.3 and DPHY rev 1.2 standards, handling inputs from up to four CSI2 cameras and producing a single aggregated video output. With data rates of 4 x 1.5Gbps, it is optimal for applications requiring efficient video stream management and consolidation.
Analog Bits provides a range of I/O solutions that are designed to meet the needs of high-speed, low-power applications. Featuring differential clocking/signaling and crystal oscillator IPs, these solutions are optimized for minimal transistor use and maximum signal integrity. Proven on silicon processes of 5nm with development underway for 3nm, they offer one of the lowest power I/O portfolios customizable to specific die-to-die connectivity requirements. Developed with expertise, these IPs are readily deployable at leading fabs, playing critical roles in applications that demand high signal quality and low power consumption.
With an emphasis on performance, the MIPITM SVTPlus2500 is a robust 4-lane video transmitter adhering to CSI2 rev 2.0 and DPHY rev 1.2 standards. It facilitates timing closure with its low clock rating and supports PRBS for precise data management. The transmitter can handle 8/16 pixel inputs per clock and offers programmable timing parameters. Equipped with 16 virtual channels, this IP is engineered for high-speed video transmission.
The second-generation MIPITM SVRPlus-8L-F is a high performance serial video receiver built for FPGAs. Complying with CSI2 revision 2.0 and DPHY revision 1.2 standards, it supports 8 lanes and 16 virtual channels, offering efficient communication with 12Gbps data throughput. This receiver comes with features like 4 pixel output per clock, calibration support, and communication error statistics, making it suitable for high-speed video transmission and processing applications.
YouMIPI includes comprehensive solutions for MIPI CSI and DSI interface implementations, enabling high-quality data stream management for cameras and displays. This ensures optimal performance in digital image processing, making it ideal for multimedia applications that require seamless data interface efficiency.
The Serializer/Deserializer (SerDes) IP core from Advinno offers transformative data transmission capabilities for high-speed applications. It plays a crucial function in converting data between serial and parallel interfaces effectively, optimizing both design complexity and data transfer efficiency. This facilitates seamless communication paths inherently necessary for sophisticated electronic systems.\n\nAdvinno's SerDes is especially integral to systems requiring compact design footprints and low power consumption, making it an appropriate choice for use in communications infrastructure, consumer electronics, and computing environments. Its efficiency in reducing pin counts and simultaneously improving data transmission speeds is often a pivotal advantage in high-bandwidth system designs.\n\nThe SerDes IP also enhances bandwidth utilization by significantly improving data rates, aligning with modern demands for rapid data transfer. The robust architecture it embodies assures reliable and fast data exchange, which is crucial for maintaining optimal performance in real-time applications.
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