All IPs > Interface Controller & PHY > MIPI
The MIPI category under Interface Controller & PHY encompasses a broad range of semiconductor IPs tailored for high-speed data transfer between components in mobile and IoT devices. MIPI, which stands for Mobile Industry Processor Interface, is an industry-driven standard aimed at simplifying the integration of different advanced technologies into small form factor devices while ensuring optimal communication efficiency and power consumption.
Within this category, you will find semiconductor IPs that address the critical need for reducing latency and increasing the bandwidth of data communication across various internal components. These MIPI interfaces are vital in smartphones, tablets, and other portable electronics, where space is at a premium, yet there's a demand for high-performance data exchange and energy efficiency. The IPs provide solutions for connecting processors to modems, sensors, displays, and cameras, enabling manufacturers to build devices with faster data processing capabilities and higher battery life.
MIPI semiconductor IPs in this category include MIPI D-PHY, C-PHY, and M-PHY, among others. These IPs are designed to support versatile and scalable designs, allowing for personalization depending on the specific requirements of the end product. MIPI D-PHY, for instance, is often used in applications requiring video transmission with high-quality imaging sensors, providing a robust method to deliver both power and data through the same interface.
By leveraging MIPI semiconductor IPs, designers can ensure that their products adhere to the latest industry standards, providing a competitive edge in the technology market. These IPs support a seamless interface experience, enhance data transmission efficiencies, and reduce both development time and costs. Integrating MIPI interface controller and PHY solutions will drive innovation and bring sophisticated electronic products to market faster and more efficiently than ever before.
The Mixel MIPI C-PHY IP (MXL-CPHY) is a high-frequency, low-power, low cost, physical layer. (Learn more about Mixel’s MIPI ecosystem at Mixel MIPI Central which gives you access to Mixel’s best of class MIPI ecosystem supply chain partners.) The C-PHY configuration consists of up to three lane modules and is based on 3-Phase symbol encoding technology, delivering 2.28 bits per symbol over three-wire trios and targeting a maximum rate of 2.5 Gsps, 5.7Gbps. The C-PHY is partitioned into a digital module – CIL (Control and Interface Logic) and a mixed-signal module. The PHY IP is provided as a combination of soft IP views (RTL, and STA Constraints) for the digital module, and hard IP views (GDSII/CDL/LEF/LIB) for the mixed-signal module. This unique offering of both soft and hard IP permits architectural design flexibility and seamless implementation in customer-specific design flow. The CIL module interfaces with the protocol layer and determines the global operation of the module. The interface between the PHY and the protocol is using the PHY-Protocol Interface (PPI). The mixed-signal module includes high-speed signaling mode for fast-data traffic and low-power signaling mode for control purposes. During normal operation, a lane switches between low-power and high-speed mode. Bidirectional lanes can also switch communication direction. The change of operating mode or direction requires enabling and disabling of certain electrical functions. These enable and disable events do not cause glitches on the lines that would result in a detection of incorrect signal levels. All mode and direction changes are smooth to always ensure a proper detection of the line signals. Mixel’s C-PHY is a complete PHY, silicon-proven at multiple foundries and multiple nodes. It is built to support the MIPI Camera Serial Interface (CSI) and Display Serial Interface (DSI).
The Mixel MIPI C/D-PHY combo IP (MXL-CPHY-DPHY) is a high-frequency low-power, low cost, physical layer compliant with the MIPI® Alliance Standard for C-PHY and D-PHY. (Learn more about Mixel’s MIPI ecosystem at Mixel MIPI Central which gives you access to Mixel’s best of class MIPI ecosystem supply chain partners.) The PHY can be configured as a MIPI Master or MIPI Slave, supporting camera interface CSI-2 v1.2 or display interface DSI v1.3 applications in the D-PHY mode. It also supports camera interface CSI-2 v1.3 and display interface DSI-2 v1.0 applications in the C-PHY mode. The high-speed signals have a low voltage swing, while low-power signals have large swing. High-Speed functions are used for high-speed data traffic while low-power functions are mostly used for control. The C-PHY is based on 3-Phase symbol encoding technology, delivering 2.28 bits per symbol over three-wire trios, operating with a symbol rate range of 80 to 4500 Msps per lane, which is the equivalent of about 182.8 to 10260 Mbps per lane. The D-PHY supports a bit rate range of 80 to 1500 Mbps per Lane without deskew calibration, and up to 4500 Mbps with deskew calibration. The low-power mode and escape mode are the same in both the D-PHY and C-PHY modes. To minimize EMI, the drivers for low-power mode are slew-rate controlled and current limited. The data rate in low-power mode is 10 Mbps. For a fixed clock frequency, the available data capacity of a PHY configuration can be increased by using more lanes. Effective data throughput can be reduced by employing burst mode communication. Mixel’s C-PHY/D-PHY combo is a complete PHY, silicon-proven at multiple foundries and multiple nodes. The C/D-PHY is fully integrated and has analog circuitry, digital, and synthesizable logic.
Silicon Creations' SerDes Interfaces are crafted to handle high-speed data transmission challenges over varied processes, ranging from 12nm to 180nm. Addressing multiple protocols such as CPRI, PCIe, and SATA, these interfaces demonstrate flexibility by supporting data transmission speeds from 100 Mbps to beyond 32 Gbps. The architecture incorporates a host of advanced features including adaptive equalization techniques and programmable de-serialization widths, making it stand out in terms of performance and signal integrity even under challenging conditions. With ultra-low latency PMAs, they sustain excellent operational speed and efficiency, imperative for sophisticated communication applications. Moreover, Silicon Creations partners with leading entities to provide comprehensive solutions, including complete PCIe PHY integrations. This synergy ensures that SerDes Interfaces are fully optimized for operational excellence, delivering stable and reliable communication signals. With an emphasis on low power and minimized area requirements, they cater to burgeoning industry needs for power-efficient and space-conservative designs.
The Mixel MIPI D-PHY IP (MXL-DPHY) is a high-frequency low-power, low cost, source-synchronous, physical layer compliant with the MIPI® Alliance Standard for D-PHY. (Learn more about Mixel’s MIPI ecosystem at Mixel MIPI Central which gives you access to Mixel’s best of class MIPI ecosystem supply chain partners.) Although primarily used for connecting cameras and display devices to a core processor, this MIPI PHY can also be used for many other applications. It is used in a master-slave configuration, where high-speed signals have a low voltage swing, and low-power signals have large swing. High-speed functions are used for high-speed data traffic while low-power functions are mostly used for control. The D-PHY is partitioned into a Digital Module – CIL (Control and Interface Logic) and a Mixed Signal Module. It is provided as a combination of Soft IP views (RTL, and STA Constraints) for Digital Module, and Hard IP views (GDSII/CDL/LEF/LIB) for the Mixed Signal Module. This unique offering of Soft and Hard IP permits architectural design flexibility and seamless implementation in customer-specific design flow. The CIL module interfaces with the protocol layer and determines the global operation of the lane module. The interface between the D-PHY and the protocol is called the PHY-Protocol Interface (PPI). During normal operation, the data lane switches between low-power mode and high-speed mode. Bidirectional lanes can also switch communication direction. The change of operating mode or direction requires enabling and disabling certain electrical functions. These enable and disable events do not cause glitches on the lines that would otherwise result in detections of incorrect signal levels. Therefore, all mode and direction changes occur smoothly, ensuring proper detection of the line signals. Mixel’s D-PHY is a complete PHY, silicon-proven at multiple foundries and multiple nodes. This MIPI PHY is fully integrated and has analog circuitry, digital, and synthesizable logic. Our D-PHY is built to support the MIPI Camera Serial Interface (CSI) and Display Serial Interface (DSI) using the PHY Protocol Interface (PPI). Mixel has provided this IP in many different configurations to accommodate different applications. The Universal Lane configuration can be used to support any allowed use-case, while other configurations are optimized for many different use cases such as Transmit only, Receive only, DSI, CSI, TX+ and RX+. Both TX+ and RX+ configurations support full-speed loopback operation without the extra area associated with a universal lane configuration.
Intilop offers a sophisticated 10G TCP Offload Engine that integrates MAC, PCIe, and Host IF to deliver ultra-low latency performance. This engine is designed to significantly reduce CPU workload by offloading TCP/IP processing onto the hardware, ensuring faster data transmission with minimal delay. It efficiently supports extensive data flow and high-speed connectivity through its advanced architecture, making it an optimal solution for enterprises seeking high-performance network infrastructure. The engine is specifically engineered to handle up to 10 Gbps speed, maintaining consistent levels of performance even under heavy data loads. Its robust design supports full state offload, checksum offload, and large send offload, making it adept at managing high volumes of data without compromising speed or reliability. By including features like dual 10G SFP+ ports, it offers users flexibility and increased bandwidth, catering to the needs of bandwidth-intensive applications. Additional highlights include zero jitter and the ability to manage multiple sessions simultaneously, thereby enhancing data throughput while minimizing network latency. The integration of features such as kernel bypass and no-CPU-needed architecture underscores its design geared towards efficiency and resource optimization. Ideal for data centers, cloud computing environments, and high-speed network servers, this offload engine is structured to provide significant improvements in cost, space, and overall network infrastructure efficiency.
The NuLink Die-to-Die PHY for Standard Packaging represents Eliyan's cornerstone technology, engineered to harness the power of standard packaging for die-to-die interconnects. This technology circumvents the limitations of advanced packaging by providing superior performance and power efficiencies traditionally associated only with high-end solutions. Designed to support multiple standards, such as UCIe and BoW, the NuLink D2D PHY is an ideal solution for applications requiring high bandwidth and low latency without the cost and complexity of silicon interposers or silicon bridges. In practical terms, the NuLink D2D PHY enables chiplets to achieve unprecedented bandwidth and power efficiency, allowing for increased flexibility in chiplet configurations. It supports a diverse range of substrates, providing advantages in thermal management, production cycle, and cost-effectiveness. The technology's ability to split a Network on Chip (NoC) across multiple chiplets, while maintaining performance integrity, makes it invaluable in ASIC designs. Eliyan's NuLink D2D PHY is particularly beneficial for systems requiring physical separation between high-performance ASICs and heat-sensitive components. By delivering interposer-like bandwidth and power in standard organic or laminate packages, this product ensures optimal system performance across varied applications, including those in AI, data processing, and high-speed computing.
The ARINC 818 Product Suite is a comprehensive solution set designed to support the entire lifecycle of ARINC 818 enabled equipment. This suite offers tools and resources essential for developing, qualifying, testing, and simulating ARINC 818 products. It is recognized for its robust design and ability to address the complexities of high-performance avionics systems. Within the product suite, users can access the ARINC 818 Development Suite and Flyable Products, providing a framework for both development and in-field application. The suite is indispensable for organizations aiming to integrate ARINC 818 into their systems, ensuring precise data handling and compatibility. Great River Technology's experience in crafting over 100 mission-critical systems is embedded into the suite, offering unmatched expertise and dependability. By leveraging this suite, companies can ensure the reliable operation and seamless integration of ARINC 818 technologies.
Time-Triggered Ethernet (TTEthernet) is an advanced form of Ethernet designed for applications that require high levels of determinism and redundancy, particularly evident in aerospace and space projects. TTEthernet offers an integrated solution for complex systems that mandates reliable time-sensitive operations, such as those required in human spaceflight where triple redundancy is crucial for mission-critical environments. This technology supports dual fault-tolerance by using triple-redundant networks, ensuring that the system continues to function if failures occur. It's exceptionally suited for systems with rigorous safety-critical requirements and has been employed in ventures like NASA's Orion spacecraft thanks to its robust standard compliance and support for fault-tolerant synchronization protocols. Adhering to the ECSS engineering standards, TTEthernet facilitates seamless integration and enables bandwidth efficiencies that are significant for both onboard and ground-based operations. TTTech's TTEthernet solutions have been further complemented by their proprietary scheduling tools and chip IP offerings, which continue to set industry benchmarks in network precision and dependability.
Overview: The MIPI I3C Controller IP Core is fully compliant with the latest I3C specification, offering high bandwidth and scalability for integrating multiple sensors into mobile, automotive, and IoT system-on-chips (SoCs). This controller support in-band interrupts within the 2-wire interface, reducing pin count, simplifying board design, and lowering power and system costs. Backward compatibility with I2C ensures future-proof designs, and the controller's operating modes enable efficient connectivity for systems with multiple ICs and sensors on a single I3C bus. The ARM® AMBA® Advanced High-Performance Bus (AHB) facilitates seamless integration of the IP into the SoC. Key Features: Compliance with MIPI-I3C Basic v1.0 Backward compatibility with I2C Two-wire serial interface up to 12.5MHz using Push-Pull Dynamic and Static Addressing support Single Data Rate messaging (SDR) Broadcast and Direct Common Command Code (CCC) Messages support In-Band Interrupt capability Hot-Join Support Applications: Consumer Electronics Defense Aerospace Virtual Reality Augmented Reality Medical Biometrics (Fingerprints, etc.) Automotive Devices Sensor Devices
Overview: The MIPI CSI-2 (Camera Serial Interface) defines an interface between a peripheral device (camera) and host processor (application engine) for mobile applications. It offers the mobile industry a standard, robust, scalable, low-power, high-speed, and cost-effective interface that supports a wide range of imaging solutions for mobile devices. Key Features: Compliance with MIPI-CSI-2 version 3.0 Compliance with C-PHY 2.0 for MIPI CSI-2 Version 3.0 Compliance with D-PHY 2.5 for MIPI CSI-2 Version 3.0 Compatibility with I2C and I3C (SDR, DDR) for CCI interface Support for C-PHY 2.0, D-PHY 2.5, A-PHY, M-PHY with configurable PHY layer Processor Interfaces: AHB Lite/APB/AXI for configuration Lane Merging Function for consolidating packet data in CSI-2 Receiver De-skew detection in D-PHY and sync word detection in C-PHY Pixel Formats Supported: YUV, RGB, and RAW data Virtual Channels: 16 for D-PHY, 32 for C-PHY Error detection, interleaving, scrambling, and descrambling support Byte to pixel conversion in LLP layer Applications: Imaging Surveillance Gaming Sensor devices Internet of Things (IoT) Wearable devices Virtual Reality Augmented Reality Automotive Systems
The Multi-Protocol SERDES offered by Pico Semiconductor is a versatile solution capable of handling a variety of communication protocols. This series of SERDES includes a 4-channel configuration that supports data rates up to 32Gbps, designed for integration with XAUI, RXAUI, and SGMII. It is compatible with multiple process nodes provided by foundries like TSMC and GF, offering robust performance across different semiconductor environments. These SERDES are crafted to meet high-performance metrics, capturing speeds up to 16Gbps and 6.5Gbps across various models, with advanced versions reaching up to 32Gbps. This exceptional range not only ensures compatibility with current technologies but also prepares systems for future updates, sustaining high data throughput. By delivering reliable high-speed data transmission capabilities, the Multi-Protocol SERDES from Pico Semiconductor is integral for networking, high-speed computing, and data storage applications, where efficient and speedy data transfer is paramount.
The CT25205 is a robust digital IP core designed for IEEE 802.3cg 10BASE-T1S Ethernet Physical Layer. It includes PMA, PCS, and PLCA Reconciliation Sublayer blocks, enhancing compatibility with standard IEEE MACs via the MII. Featuring a fully synthesizable Verilog design, it is deployable on standard cells and FPGAs. With integrated PLCA RS, this IP provides advanced features without necessitating additional extensions, making it a vital component for Zonal Gateways SoCs.
Silicon Creations crafts highly reliable LVDS interfaces designed to meet diverse application needs, going from bi-directional I/Os to specialized uni-directional configurations. Spanning process compatibilities from 90nm CMOS to advanced 7nm FinFET, these interfaces are a cornerstone for high-speed data communication systems, thriving particularly in video data transmission and chip-to-chip communications. Supporting robust data rates over multiple channels, the LVDS Interfaces guarantee flexible programmability and protocol compatibility with standards such as FPD-Link and Camera-Link. They capitalize on proven PLL and CDR architectures for superior signal integrity and error-free data transfers. Operating efficiently in various technology nodes, they remain highly effective across collaborative chipset environments. The interfaces are fortified with adaptable features like dynamic phase alignment to stabilize data sequences and on-die termination options for superior signal integrity. Their proven record places them as a critical enabler in applications where consistent high-speed data transfer is paramount, demonstrating Silicon Creations’ prowess in delivering industry-leading communication solutions.
Overview: The MIPI DSI Transmitter IP is designed to transmit data to the host processor, providing the mobile industry with a standard, robust, scalable, low-power, high-speed, and cost-effective interface that supports a wide range of imaging solutions for mobile devices. Key Features: Compliance with MIPI-DSI-2 version 2.0 Compliance with C-PHY version 2.0 for DSI-2 Version-2 Compliance with D-PHY version 1.2 for DSI-2 Version-2.0 Compliance with D-PHY version 2.0 for DSI-2 Version-2.0 Compliance with D-PHY version 3.0 for DSI-2 Version-2.0 Compliance with MIPI SDF specification Compliance with DBI-2 and DPI-2 Pixel to Byte conversion support from Application layer to LLP layer Support for Command Mode and Video Mode Continuous clock behavior in clock lane for D-PHY physical layer De-skew sequence pattern for video mode support Lane Distribution Function for distributing packet bytes across N-Lanes Connectivity with two, three, or four DSI Receivers HS mode and Escape mode support for transmission of Packets in both C-PHY and D-PHY Symbol slip detection code and sync symbol insertion in C-PHY physical layer Target Applications: Imaging Surveillance Gaming Sensor devices Internet of Things (IoT) Wearable devices Virtual Reality Augmented Reality Automotive Systems
Overview: The SPD5 Hub controller IP is designed to interface with the I3C/I2C Host Bus, allowing for the isolation of local devices such as Temperature Sensors (TS) from the master host bus. It features a Two-wire serial interface with SCL and SDA busses. Key Features: Compliance with JEDEC's JESD300-5 Support for speeds up to 12.5MHz Bus Reset functionality SDA arbitration support Enabled Parity Check Support for Packet Error Check (PEC) Switch between I2C and I3C Basic Mode Default Read address pointer Mode Write and read operations for SPD5 Hub with or without PEC In-band Interrupt (IBI) support Write Protection for NVM memory blocks Arbitration for Interrupts Clearing of Device Status and IBI Status Registers Error handling for Packet Error Check and Parity Errors Common Command Codes (CCC) for I3C Basic Mode Dynamic IO Operation Mode Switching Bus Clear and Bus Reset capabilities SPD5 Command features for NVM memory and Register Space Read and Write access to NVM memory Support for Offline Tester operation Applications: DDR5 DIMM Application Environment DDR5 NVDIMM Application Environment Automotive Devices Memory Devices Power Management Devices Defense/Aerospace/Customer Electronics
The HOTLink II Product Suite is engineered to deliver advanced capabilities in high-speed data and video link technologies. It serves as an essential toolset for developing and implementing HOTLink II protocols effectively, catering to the specific needs of modern avionics systems requiring reliable and high-throughput data transfer. This suite includes various components that enable the seamless transmission and conversion of data, supporting both development and operational phases. Its design incorporates technologies that enhance data integrity and efficiency, making it integral to systems where performance and reliability are critical. Great River Technology ensures that each component of the HOTLink II suite is crafted with precision, providing comprehensive support and simplifying integration processes. The suite redounds to the extensive expertise of Great River Technology in the sector, reinforcing their standing as providers of pioneering solutions.
MIPI I3C Controller IP Core is fully compliant with the latest I3C specification and delivers high bandwidth and scalability for integration of multiple sensors into mobile, automotive and IoT system-on-chips (SoCs). The MIPI I3C Controller supports in-band interrupts within the 2-wire interface provides significantly lower pin count, simplifying board design and reducing power and cost of the system. The MIPI I3C Controller IP is fully backward compatible with I2C, allowing designers to future proof their design, and the I3C controller IP operating modes enable systems with several ICs to efficiently connect to all sensors on a single I3C bus. The standard-based ARM® AMBA® Advanced High Performance Bus (AHB) connects the IP to the rest of the SoC offering easy IP integration. MIPI I3C Controller IP is designed to easily integrate into any SoC offering lowest gate count and quickly fit into any Chip development flow.
The Chipchain C100 is a pioneering solution in IoT applications, providing a highly integrated single-chip design that focuses on low power consumption without compromising performance. Its design incorporates a powerful 32-bit RISC-V CPU which can reach speeds up to 1.5GHz. This processing power ensures efficient and capable computing for diverse IoT applications. This chip stands out with its comprehensive integrated features including embedded RAM and ROM, making it efficient in both processing and computing tasks. Additionally, the C100 comes with integrated Wi-Fi and multiple interfaces for transmission, broadening its application potential significantly. Other notable features of the C100 include an ADC, LDO, and a temperature sensor, enabling it to handle a wide array of IoT tasks more seamlessly. With considerations for security and stability, the Chipchain C100 facilitates easier and faster development in IoT applications, proving itself as a versatile component in smart devices like security systems, home automation products, and wearable technology.
Overview: The MIPI CSI-2 (Camera Serial Interface) Transmitter IP establishes an interface between a peripheral device (camera) and host processor (application engine) for mobile applications. It offers the mobile industry a standard, robust, scalable, low-power, high-speed, and cost-effective interface that caters to a wide range of imaging solutions for mobile devices. Key Features: Compliance with MIPI-CSI-2 version 3.0 Compliance with C-PHY 2.0 for MIPI CSI-2 Version 3.0 Compliance with D-PHY 2.5 for MIPI CSI-2 Version 3.0 Compatibility with I2C and I3C (SDR, DDR) for CCI interface Pixel to Byte conversion support from Application layer to LLP layer Continuous clock behavior in clock lane for D-PHY physical layer De-skew sequence pattern in Data Lane Module Lane Distribution Function for distributing packet bytes across N-Lanes Sync word insertion through PPI command in C-PHY physical layer Insertion of Filler bytes in LLP layer for packet footer alignment Setting specific bits in packet header Defining frame blanking period Seed selection in scrambler and de-scrambler by Sync word Support for C-PHY/D-PHY/A-PHY/M-PHY with one PHY layer configuration Target Applications: Imaging Surveillance Gaming Sensor devices Internet of Things (IoT) Wearable devices Virtual Reality Augmented Reality Automotive Systems
The THOR platform is a versatile tool for developing application-specific NFC sensor and data logging solutions. It incorporates silicon-proven IP blocks, creating a comprehensive ASIC platform suitable for rigorous monitoring and continuous data logging applications across various industries. THOR is designed for accelerated development timelines, leveraging low power and high-security features. Equipped with multi-protocol NFC capabilities and integrated temperature sensors, the THOR platform supports a wide range of external sensors, enhancing its adaptability to diverse monitoring needs. Its energy-efficient design allows operations via energy harvesting or battery power, ensuring sustainability in its applications. This platform finds particular utility in sectors demanding precise environmental monitoring and data management, such as logistics, pharmaceuticals, and industrial automation. The platform's capacity for AES/DES encrypted data logging ensures secure data handling, making it a reliable choice for sectors with stringent data protection needs.
The Multi-Protocol SerDes provided by Silicon Creations serves as an essential component for high-speed data interfaces across multiple industry protocols. This SerDes portfolio accommodates a vast array of protocols such as PCIe, JESD204, XAUI, and many more, facilitating broad compatibility with industry standards. Operating across 12nm to 180nm processes, these interfaces support data rates from 100 Mbps to an impressive 32.75 Gbps. Incorporating advanced features like programmable de-serialization widths and adaptive equalization, the Multi-Protocol SerDes ensures optimal signal integrity and performance even in demanding environments. The design includes jitter cleaner functions and employs low-latency optimized PMAs, delivering high precision and speed across various operational scenarios. This comprehensive adaptability ensures seamless integration into a wide range of applications from communications to high-performance computing. Supported by robust architectures, the SerDes enables enhanced efficiency and reliability, featuring low power consumption and reduced area overheads. With a commitment to customer satisfaction, Silicon Creations offers complete solutions through partnerships with leading controller vendors, cementing its products as high-value choices for modern electronic systems.
The Time-Triggered Protocol (TTP) is a technology that offers deterministic communication for distributed real-time systems. This protocol is vital in applications where timing precision is crucial, such as in the aerospace industry, ensuring tasks are executed at precisely scheduled intervals. TTP is known for its reliability, configuring data communication parameters by defining send/receive slots within a network, and is adaptable for use in high-integrity systems like those found in avionics and deep space missions. This protocol underpins systems where fault-tolerance and coordination are necessary across diverse nodes within the network, offering a redundant communication pathway that safeguards against data loss. With this protocol, TTTech ensures that methodologies for verification and scheduling are incorporated into the systems, facilitating smoother qualification and certification in civil aviation projects. TTP is also SAE AS6003 compliant, meeting the stringent requirements needed for critical applications and ensuring compatibility with various forms of systems, including both integrated circuits and more complex system-on-chip arrangements. Widely acknowledged in industries demanding high reliability, TTP continues to support industry needs for robust protocol solutions.
The Mixel MIPI M-PHY (MXL-MPHY) is a high-frequency low-power, Physical Layer IP that supports the MIPI® Alliance Standard for M-PHY. (Learn more about Mixel’s MIPI ecosystem at Mixel MIPI Central which gives you access to Mixel’s best of class MIPI ecosystem supply chain partners.) The IP can be used as a physical layer for many applications, connecting flash memory-based storage, cameras and RF subsystems, and for providing chip-to-chip inter-processor communications (IPC). It supports MIPI UniPro and JEDEC Universal Flash Storage (UFS) standard. By using efficient BURST mode operation with scalable speeds, significant power savings can be obtained. Selection of signal slew rate and amplitude allows reduction of EMI/RFI, while maintaining low bit error rates.
Overview: The Power Management IC (PMIC) is specifically designed for DDR5 RDIMM, DDR5 LRDIMM, and DDR5 NVDIMM applications. It includes switching and LDO regulators to efficiently manage power distribution. The PMIC utilizes a MIPI-I3C Interface to select appropriate power settings for various application environments and is capable of operating at speeds up to 12.5MHz. Key Features: Maximum Operating speed of 12.5MHz Flexible Open-Drain IO (I2C) and Push-Pull (I3C) IO Support Multi-Time Programmable Non-Volatile Memory Interface Programmable and DIMM-specific registers for customization Error log registers for tracking Packet Error Check (PEC) and Parity Error Check functions Bus Reset function Support I3C Basic mode In-Band Interrupt (IBI) support Write, read, and default read operations in I2C mode Error handling for PEC, Parity errors, and CCC errors I3C Basic Common Command Codes (CCC) support Applications: DDR5 DIMM Application Environment DDR5 NVDIMM Application Environment Automotive Devices Memory Devices Power Management Devices Defense/Aerospace/Customer Electronics
The DisplayPort 1.4 IP core by Parretto is designed for efficient video signal transmission, providing comprehensive solutions for both source (DPTX) and sink (DPRX) configurations. Supporting link rates from 1.62 to 8.1 Gbps, this core offers flexibility for different applications, including embedded DisplayPort (eDP) rates. It can handle 1, 2, and 4 DP lanes, and supports diverse video interfaces such as native video and AXI stream. This IP core accommodates Single Stream Transport (SST) and Multi Stream Transport (MST) modes, adapting to different output requirements. Its dual and quad pixels per clock with rich color managing capabilities—including RGB and various YCbCr formats—enable it to meet high-quality video standards. A secondary data packet interface allows for straightforward audio and metadata transport. Equipped with a Video Toolbox (VTB), it simplifies video processing tasks, including clock recovery and pattern generation. The core is compatible with several FPGA devices like AMD's UltraScale+ and Artix-7, as well as Intel's Cyclone 10 GX and Arria 10 GX.
Designed for the FC-AE-ASM protocol, this ASM Core offers hardware-based solutions including label lookup, DMA controllers, and message chains, compatible with F-35 applications. Its robust architecture ensures secure and reliable communication, reinforcing its critical role in secure military data transmission tasks.
GNSS Sensor Ltd offers the GNSS VHDL Library, a powerful suite designed to support the integration of GNSS capabilities into FPGA and ASIC products. The library encompasses a range of components, including configurable GNSS engines, Viterbi decoders, RF front-end control modules, and a self-test module, providing a comprehensive toolkit for developers. This library is engineered to be highly flexible and adaptable, supporting a wide range of satellite systems such as GPS, GLONASS, and Galileo, across various configurations. Its architecture aims to ensure independence from specific CPU platforms, allowing for easy adoption across different systems. The GNSS VHDL Library is instrumental in developing cost-effective and simplified system-on-chip solutions, with capabilities to support extensive configurations and frequency bandwidths. It facilitates rapid prototyping and efficient verification processes, crucial for deploying reliable GNSS-enabled devices.
The MXL-LVDS-MIPI-RX is a high-frequency, low-power, low-cost, source-synchronous, Physical Layer that supports the MIPI® Alliance Standard for D-PHY and compatible with the TIA/EIA-644 LVDS standard. (Learn more about Mixel’s MIPI ecosystem at Mixel MIPI Central which gives you access to Mixel’s best of class MIPI ecosystem supply chain partners.) The IP is configured as a MIPI slave and consists of 5 lanes: 1 Clock lane and 4 data lanes, which make it suitable for display serial interface applications (DSI). The High-Speed signals have a low voltage swing, while Low-Power signals have large swing. High-Speed functions are used for High-Speed Data traffic while low power functions are mostly used for control.
The MXL-LVDS-DPHY-DSI-TX is a combo PHY that consists of a high-frequency low-power, low-cost, source-synchronous, Physical Layer supporting the MIPI® Alliance Standard for D-PHY and a high performance 4-channel LVDS Serializer implemented using digital CMOS technology. (Learn more about Mixel’s MIPI ecosystem at Mixel MIPI Central which gives you access to Mixel’s best of class MIPI ecosystem supply chain partners.) In LVDS mode, both the serial and parallel data are organized into 4 channels. The parallel data is 7 bits wide per channel. The input clock is 25MHz to 150MHz. The serializer is highly integrated and requires no external components. The circuit is designed in a modular fashion and desensitized to process variations. This facilitates process migration, and results in a robust design.
The Hyperspectral Imaging System by Imec enables detailed spectral imaging by capturing data across multiple wavelengths. This technology is pivotal for applications requiring precise material composition analysis and object identification, such as in agriculture and environmental monitoring. The system uses a compact and integrated design making it adaptable and efficient for various uses. Imec's hyperspectral imaging technology paves the way for advancements in remote sensing, where it can provide critical insights into land usage and resource management. Its high spectral resolution coupled with Imec's cutting-edge integration methods allows users to discern more nuanced differences in material compositions, fostering innovation across sectors. Engineered for flexibility, this imaging system boasts features that support rapid data analysis and integration into larger systems. Its robust design ensures it can withstand challenging operational conditions, making it a reliable choice for continuous and demanding applications.
This core offers a comprehensive hardware solution for FC-AE-RDMA or FC-AV protocols, incorporating buffer mapping, DMA controllers, and message chain engines. Its compatibility with F-18/F-15 interfaces makes it pivotal for military communication operations, ensuring robust data handling and streamlined communication channels.
Dyumnin's RISCV SoC is a versatile platform centered around a 64-bit quad-core server-class RISCV CPU, offering extensive subsystems, including AI/ML, automotive, multimedia, memory, cryptographic, and communication systems. This test chip can be reviewed in an FPGA format, ensuring adaptability and extensive testing possibilities. The AI/ML subsystem is particularly noteworthy due to its custom CPU configuration paired with a tensor flow unit, accelerating AI operations significantly. This adaptability lends itself to innovations in artificial intelligence, setting it apart in the competitive landscape of processors. Additionally, the automotive subsystem caters robustly to the needs of the automotive sector with CAN, CAN-FD, and SafeSPI IPs, all designed to enhance systems connectivity within vehicles. Moreover, the multimedia subsystem boasts a complete range of IPs to support HDMI, Display Port, MIPI, and more, facilitating rich audio and visual experiences across devices.
The MXL-SR-LVDS is a high performance 4-channel LVDS Serializer implemented using digital CMOS technology. Both the serial and parallel data are organized into four channels. The parallel data width is programmable, and the input clock is 25MHz to 165MHz. The Serializer is highly integrated and requires no external components. It employs optional pre-emphasis to enable transmission over a longer distance while achieving low BER. The circuit is designed in a modular fashion and desensitized to process variations. This facilitates process migration, and results in a robust design.
The MIPI D-PHY by SkyeChip aligns with the MIPI D-PHY specification v2.5, providing a fully integrated hard macro with robust lane control and interface logic. It supports data rates of up to 1.5 Gbps per lane with options for upgrades reaching 2.5 Gbps per lane, offering versatile performance for high-speed data lanes. Engineered for low-power operations, this PHY features escape modes and ultra low-power state modes, essential for power-sensitive applications. The PHY Protocol Interface (PPI) further ensures compatibility with various MIPI specifications, enabling seamless integration in advanced imaging and display applications. The D-PHY’s design enhances the ability to manage high-speed signaling efficiently, accommodating diverse I/O standards. Its architectural resiliency and power-efficient modes make it ideal for applications in speed-sensitive environments like mobile and multimedia devices.
The BlueLynx Chiplet Interconnect is a sophisticated die-to-die interconnect solution that offers industry-leading performance and flexibility for both advanced and conventional packaging applications. As an adaptable subsystem, BlueLynx supports the integration of Universal Chiplet Interconnect Express (UCIe) as well as Bunch of Wires (BoW) standards, facilitating high bandwidth capabilities essential for contemporary chip designs.\n\nBlueLynx IP emphasizes seamless connectivity to on-die buses and network-on-chip (NoCs) using standards such as AMBA, AXI, and ACE among others, thereby accelerating the design process from system-on-chip (SoC) architectures to chiplet-based designs. This innovative approach not only allows for faster deployment but also mitigates development risks through a predictable and silicon-friendly design process with comprehensive support for rapid first-pass silicon success.\n\nWith BlueLynx, designers can take advantage of a highly optimized performance per watt, offering customizable configurations tailored to specific application needs across various markets like AI, high-performance computing, and mobile technologies. The IP is crafted to deliver outstanding bandwidth density and energy efficiency, bridging the requirements of advanced nodal technologies with compatibility across several foundries, ensuring extensive applicability and cost-effectiveness for diverse semiconductor solutions.
The MIPI interface from Silicon Library Inc. represents a versatile solution for mobile and embedded systems. This IP supports the MIPI DPHY-Tx and DPHY-Rx standards, essential for devices requiring rapid data transfer such as smartphones, tablets, and digital cameras. It's designed to deliver high-speed connectivity whilst maintaining low power operations, crucial for battery-operated devices. Silicon Library's MIPI provides robust data lanes for high-speed communication, enhancing both input and output capabilities in devices where form factor and power efficiency are critical. Its adaptability allows for seamless integration in a wide range of applications, ensuring both backward compatibility with existing systems and forward compatibility with emerging technologies. Incorporating energy-efficient technology, the MIPI interface excels in minimizing energy usage during high-speed operations, supporting the development of eco-friendly technology solutions. Its flexible architecture ensures it can cater to different market demands, providing a reliable backbone for modern connected devices.
The FC Link Layer Core implements the FC-1 and FC-2 layers, offering a full suite IP solution for Fibre Channel communication. Its design ensures high-reliability data transmission, crucial for military and aerospace applications requiring dependable networking capabilities.
The Dynamic PhotoDetector (DPD) by ActLight specifically designed for smartphone applications marks a considerable advancement in mobile light sensing technology. This sensor is crafted with enhanced sensitivity and efficiency, capable of adjusting its operational parameters dynamically based on ambient light conditions. It ensures the optimum performance of smartphone features reliant on light sensing, such as automatic screen brightness adjustment and camera functionalities. Notably, the DPD achieves this while maintaining a lower power consumption profile than conventional alternatives, which is a significant advantage for today's power-hungry smartphones that demand long battery life. Its state-of-the-art design encapsulates high-performance metrics in a small, cost-effective package, allowing manufacturers to integrate it into devices without substantial adjustments in design and costs. This technology not only improves user experience by providing smoother, more responsive control over light-related smartphone features but also supports the burgeoning trend towards more eco-friendly, energy-efficient consumer electronics, reducing the overall energy footprint of modern mobile devices.
The MIPITM CSI2MUX-A1F is an innovative video multiplexor designed to manage and aggregate multiple video streams effortlessly. It supports CSI2 rev 1.3 and DPHY rev 1.2 standards, handling inputs from up to four CSI2 cameras and producing a single aggregated video output. With data rates of 4 x 1.5Gbps, it is optimal for applications requiring efficient video stream management and consolidation.
The MIPITM SVRPlus2500 provides an efficient solution for high-speed 4-lane video reception. It's compliant with CSI2 rev 2.0 and DPHY rev 1.2 standards, designed to facilitate easy timing closure with a low clock rating. This receiver supports PRBS, boasts calibration capabilities, and offers a versatile output of 4/8/16 pixels per clock. It features 16 virtual channels and 1:16 input deserializers per lane, handling data rates up to 10Gbps, making it ideal for complex video processing tasks.
The Satellite Navigation SoC Integration offering by GNSS Sensor Ltd is a comprehensive solution designed to integrate sophisticated satellite navigation capabilities into System-on-Chip (SoC) architectures. It utilizes GNSS Sensor's proprietary VHDL library, which includes modules like the configurable GNSS engine, Fast Search Engine for satellite systems, and more, optimized for maximum CPU independence and flexibility. This SoC integration supports various satellite navigation systems like GPS, Glonass, and Galileo, with efficient hardware designs that allow it to process signals across multiple frequency bands. The solution emphasizes reduced development costs and streamlining the navigation module integration process. Leveraging FPGA platforms, GNSS Sensor's solution integrates intricate RF front-end components, allowing for a robust and adaptable GNSS receiver development. The system-on-chip solution ensures high performance, with features like firmware stored on ROM blocks, obviating the need for external memory.
The MXL-DS-LVDS is a high performance 4-channel LVDS Deserializer implemented using digital CMOS technology. Both the serial and parallel data are organized into four channels. The parallel data can be 7 or 10 bits wide per channel. The input clock is 25MHz to 165MHz. The De-serializer is highly integrated and requires no external components. Great care was taken to insure matching between the Data and Clock channels to maximize the deserializer margin. The circuit is designed in a modular fashion and desensitized to process variations. This facilitates process migration, and results in a robust design.
Analog Bits provides advanced I/O solutions tailored for high-speed data transfer and die-to-die communication. Their I/O offerings are designed to minimize power consumption while delivering optimal signaling quality through differential clocking and signaling techniques. These solutions are crafted to ensure effective integration with modern SoC architectures, providing customization options to meet specific technical requirements. The I/O technologies developed by Analog Bits are proven in high-volume production at nodes as small as 5nm, ensuring reliability and performance. Manufactured using state-of-the-art processes, Analog Bits' I/O IP supports a broad range of applications, from consumer electronics to complex server environments. Their expertise in transistor-efficient architecture further boosts signaling capabilities while maintaining compact die areas, making them an ideal choice for next-generation semiconductor development.
Silicon Creations' Bi-Directional LVDS Interfaces are engineered to offer high-speed data transmission with exceptional signal integrity. These interfaces are designed to complement FPGA-to-ASIC conversions and include broad compatibility with industry standards like FPD-Link and Camera-Link. Operating efficiently over processes from 90nm to 12nm, the LVDS interfaces achieve data rates exceeding 3Gbps using advanced phase alignment techniques. A standout feature of this IP is its capability to handle independent LVCMOS input and output functions while maintaining high compatibility with TIA/EIA644A standards. The bi-directional nature allows for seamless data flow in chip-to-chip communications, essential for modern integrated circuits requiring high data throughput. The design is further refined with trimmable on-die termination, enhancing signal integrity during operations. The LVDS interfaces are versatile and highly programmable, meeting bespoke application needs with ease. The interfaces ensure robust error rate performance across varying phase selections, making them ideal for video data applications, controllers, and other high-speed data interfaces where reliability and performance are paramount.
Matterhorn is a USB4 Retimer that revolutionizes next-generation data transfer, allowing devices to achieve faster and more efficient communication. By implementing advanced retiming techniques, the Matterhorn enables improved performance for USB4 interfaces, ensuring higher data throughput while maintaining signal quality. This product is tailored for tech enthusiasts seeking the full capabilities of USB4 technology.
The 1394b PHY Core provides a hardware-based implementation of the AS5643 PHY layer, including a standard PHY-Link interface. Tailored for aerospace applications, this core facilitates reliable and high-speed data transmission, vital for systems requiring fail-safe operations in demanding environments.
Serializer/Deserializer (SerDes) technology is essential in converting data between serial and parallel interfaces, facilitating efficient data transmission over limited bandwidth channels. Advinno's SerDes offers high-speed data transfer capabilities that enhance communication between chips and systems with minimal latency. Key features of Advinno's SerDes include advanced signal modulation techniques that ensure high data integrity and reduce signal degradation over distance. These SerDes solutions are designed for flexibility, accommodating various data rates and channel lengths, making them ideal for a wide range of high-performance applications, including data centers, storage networks, and high-speed computing. The robustness of Advinno's SerDes technology is further exemplified by its ability to function in diverse environments, thanks to its adaptive equalization techniques and clock recovery systems. These features ensure consistent performance and reliability, crucial for applications where data integrity and speed are paramount, such as telecommunications and enterprise networking.
The Universal High-Speed SERDES ranging from 1G to 12.5G is a significant component for enabling rapid serial communication across digital systems. Its architecture is optimized for converting parallel data into serial streams, effectively reducing wiring complexity and simplifying chip design. This IP is essential for systems demanding high bandwidth and fast data rates, such as in data centers, networking equipment, and high-performance computing platforms. The product supports a wide range of data rates, starting from 1Gbps and scaling up to 12.5Gbps, ensuring adaptability across numerous applications. This capability is particularly advantageous in managing the dynamic bandwidth requirements seen in today's electronics landscape. As a result, it serves as a foundational IP for engineers seeking reliable and fast data transmission solutions. Additionally, this SERDES technology is critical for applications where data integrity and speed cannot be compromised. Its sophisticated design ensures efficient power usage, making it suitable for both power-sensitive and high-speed demanding environments. With its broad application scope, the Universal High-Speed SERDES is a go-to solution for implementers aiming to enhance connectivity and performance in advanced digital systems.
The YouMIPI solution from Brite Semiconductor provides comprehensive interfaces for MIPI protocols, specifically CSI and DSI solutions. These are crafted to enable seamless image signal processing from camera modules in multimedia applications.<br><br>With a strong emphasis on performance optimization and usability, YouMIPI enhances the integration of visual data, making it a cornerstone in high-definition video recording and streaming devices. The technology is tailored to boost the capabilities of modern digital cameras and display technologies.<br><br>YouMIPI supports efficient transmission speeds and clear signal pathways, ensuring that device manufacturers can achieve high-quality visual outputs without compromising on speed or efficiency.
The second-generation MIPITM SVRPlus-8L-F is a high performance serial video receiver built for FPGAs. Complying with CSI2 revision 2.0 and DPHY revision 1.2 standards, it supports 8 lanes and 16 virtual channels, offering efficient communication with 12Gbps data throughput. This receiver comes with features like 4 pixel output per clock, calibration support, and communication error statistics, making it suitable for high-speed video transmission and processing applications.
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