All IPs > Interface Controller & PHY > MIPI
The MIPI category under Interface Controller & PHY encompasses a broad range of semiconductor IPs tailored for high-speed data transfer between components in mobile and IoT devices. MIPI, which stands for Mobile Industry Processor Interface, is an industry-driven standard aimed at simplifying the integration of different advanced technologies into small form factor devices while ensuring optimal communication efficiency and power consumption.
Within this category, you will find semiconductor IPs that address the critical need for reducing latency and increasing the bandwidth of data communication across various internal components. These MIPI interfaces are vital in smartphones, tablets, and other portable electronics, where space is at a premium, yet there's a demand for high-performance data exchange and energy efficiency. The IPs provide solutions for connecting processors to modems, sensors, displays, and cameras, enabling manufacturers to build devices with faster data processing capabilities and higher battery life.
MIPI semiconductor IPs in this category include MIPI D-PHY, C-PHY, and M-PHY, among others. These IPs are designed to support versatile and scalable designs, allowing for personalization depending on the specific requirements of the end product. MIPI D-PHY, for instance, is often used in applications requiring video transmission with high-quality imaging sensors, providing a robust method to deliver both power and data through the same interface.
By leveraging MIPI semiconductor IPs, designers can ensure that their products adhere to the latest industry standards, providing a competitive edge in the technology market. These IPs support a seamless interface experience, enhance data transmission efficiencies, and reduce both development time and costs. Integrating MIPI interface controller and PHY solutions will drive innovation and bring sophisticated electronic products to market faster and more efficiently than ever before.
The Mixel MIPI C-PHY IP (MXL-CPHY) is a high-frequency, low-power, low cost, physical layer. (Learn more about Mixel’s MIPI ecosystem at Mixel MIPI Central which gives you access to Mixel’s best of class MIPI ecosystem supply chain partners.) The C-PHY configuration consists of up to three lane modules and is based on 3-Phase symbol encoding technology, delivering 2.28 bits per symbol over three-wire trios and targeting a maximum rate of 2.5 Gsps, 5.7Gbps. The C-PHY is partitioned into a digital module – CIL (Control and Interface Logic) and a mixed-signal module. The PHY IP is provided as a combination of soft IP views (RTL, and STA Constraints) for the digital module, and hard IP views (GDSII/CDL/LEF/LIB) for the mixed-signal module. This unique offering of both soft and hard IP permits architectural design flexibility and seamless implementation in customer-specific design flow. The CIL module interfaces with the protocol layer and determines the global operation of the module. The interface between the PHY and the protocol is using the PHY-Protocol Interface (PPI). The mixed-signal module includes high-speed signaling mode for fast-data traffic and low-power signaling mode for control purposes. During normal operation, a lane switches between low-power and high-speed mode. Bidirectional lanes can also switch communication direction. The change of operating mode or direction requires enabling and disabling of certain electrical functions. These enable and disable events do not cause glitches on the lines that would result in a detection of incorrect signal levels. All mode and direction changes are smooth to always ensure a proper detection of the line signals. Mixel’s C-PHY is a complete PHY, silicon-proven at multiple foundries and multiple nodes. It is built to support the MIPI Camera Serial Interface (CSI) and Display Serial Interface (DSI).
The 1G to 224G SerDes technology by Alphawave Semi is a robust connectivity solution designed for high-speed data transmission. It integrates seamlessly into various applications including Ethernet, PCI Express, and die-to-die connections, enabling fast and reliable data transfer. This technology supports a broad spectrum of signaling schemes such as PAM2, PAM4, PAM6, and PAM8, ensuring compatibility with over 30 different industry protocols and standards. As the demand for high-performance data centers and networking solutions increases, the 1G to 224G SerDes proves indispensable, delivering the speed and bandwidth required by modern systems. Alphawave Semi's SerDes supports data rates from as low as 1Gbps to a staggering 224Gbps, making it highly versatile for a multitude of configurations. Its application extends beyond traditional data centers, also covering areas like AI and 5G communication networks where latency and data throughput are critical. This flexibility is further enhanced by its low power consumption, which is essential for efficient data processing in today's power-conscious technological environment. Incorporating the 1G to 224G SerDes into your chip designs guarantees reduced latency and increased data throughput, which is vital for applications that demand real-time data processing. By ensuring high data integrity and reducing signal degradation, this SerDes solution aids in maintaining steadfast connectivity, even under heavy data loads, promising a future-ready component in the evolving tech landscape.
The Mixel MIPI C/D-PHY combo IP (MXL-CPHY-DPHY) is a high-frequency low-power, low cost, physical layer compliant with the MIPI® Alliance Standard for C-PHY and D-PHY. (Learn more about Mixel’s MIPI ecosystem at Mixel MIPI Central which gives you access to Mixel’s best of class MIPI ecosystem supply chain partners.) The PHY can be configured as a MIPI Master or MIPI Slave, supporting camera interface CSI-2 v1.2 or display interface DSI v1.3 applications in the D-PHY mode. It also supports camera interface CSI-2 v1.3 and display interface DSI-2 v1.0 applications in the C-PHY mode. The high-speed signals have a low voltage swing, while low-power signals have large swing. High-Speed functions are used for high-speed data traffic while low-power functions are mostly used for control. The C-PHY is based on 3-Phase symbol encoding technology, delivering 2.28 bits per symbol over three-wire trios, operating with a symbol rate range of 80 to 4500 Msps per lane, which is the equivalent of about 182.8 to 10260 Mbps per lane. The D-PHY supports a bit rate range of 80 to 1500 Mbps per Lane without deskew calibration, and up to 4500 Mbps with deskew calibration. The low-power mode and escape mode are the same in both the D-PHY and C-PHY modes. To minimize EMI, the drivers for low-power mode are slew-rate controlled and current limited. The data rate in low-power mode is 10 Mbps. For a fixed clock frequency, the available data capacity of a PHY configuration can be increased by using more lanes. Effective data throughput can be reduced by employing burst mode communication. Mixel’s C-PHY/D-PHY combo is a complete PHY, silicon-proven at multiple foundries and multiple nodes. The C/D-PHY is fully integrated and has analog circuitry, digital, and synthesizable logic.
The Mixel MIPI D-PHY IP (MXL-DPHY) is a high-frequency low-power, low cost, source-synchronous, physical layer compliant with the MIPI® Alliance Standard for D-PHY. (Learn more about Mixel’s MIPI ecosystem at Mixel MIPI Central which gives you access to Mixel’s best of class MIPI ecosystem supply chain partners.) Although primarily used for connecting cameras and display devices to a core processor, this MIPI PHY can also be used for many other applications. It is used in a master-slave configuration, where high-speed signals have a low voltage swing, and low-power signals have large swing. High-speed functions are used for high-speed data traffic while low-power functions are mostly used for control. The D-PHY is partitioned into a Digital Module – CIL (Control and Interface Logic) and a Mixed Signal Module. It is provided as a combination of Soft IP views (RTL, and STA Constraints) for Digital Module, and Hard IP views (GDSII/CDL/LEF/LIB) for the Mixed Signal Module. This unique offering of Soft and Hard IP permits architectural design flexibility and seamless implementation in customer-specific design flow. The CIL module interfaces with the protocol layer and determines the global operation of the lane module. The interface between the D-PHY and the protocol is called the PHY-Protocol Interface (PPI). During normal operation, the data lane switches between low-power mode and high-speed mode. Bidirectional lanes can also switch communication direction. The change of operating mode or direction requires enabling and disabling certain electrical functions. These enable and disable events do not cause glitches on the lines that would otherwise result in detections of incorrect signal levels. Therefore, all mode and direction changes occur smoothly, ensuring proper detection of the line signals. Mixel’s D-PHY is a complete PHY, silicon-proven at multiple foundries and multiple nodes. This MIPI PHY is fully integrated and has analog circuitry, digital, and synthesizable logic. Our D-PHY is built to support the MIPI Camera Serial Interface (CSI) and Display Serial Interface (DSI) using the PHY Protocol Interface (PPI). Mixel has provided this IP in many different configurations to accommodate different applications. The Universal Lane configuration can be used to support any allowed use-case, while other configurations are optimized for many different use cases such as Transmit only, Receive only, DSI, CSI, TX+ and RX+. Both TX+ and RX+ configurations support full-speed loopback operation without the extra area associated with a universal lane configuration.
Silicon Creations' SerDes Interfaces are crafted to handle high-speed data transmission challenges over varied processes, ranging from 12nm to 180nm. Addressing multiple protocols such as CPRI, PCIe, and SATA, these interfaces demonstrate flexibility by supporting data transmission speeds from 100 Mbps to beyond 32 Gbps. The architecture incorporates a host of advanced features including adaptive equalization techniques and programmable de-serialization widths, making it stand out in terms of performance and signal integrity even under challenging conditions. With ultra-low latency PMAs, they sustain excellent operational speed and efficiency, imperative for sophisticated communication applications. Moreover, Silicon Creations partners with leading entities to provide comprehensive solutions, including complete PCIe PHY integrations. This synergy ensures that SerDes Interfaces are fully optimized for operational excellence, delivering stable and reliable communication signals. With an emphasis on low power and minimized area requirements, they cater to burgeoning industry needs for power-efficient and space-conservative designs.
The Mixel MIPI M-PHY (MXL-MPHY) is a high-frequency low-power, Physical Layer IP that supports the MIPI® Alliance Standard for M-PHY. (Learn more about Mixel’s MIPI ecosystem at Mixel MIPI Central which gives you access to Mixel’s best of class MIPI ecosystem supply chain partners.) The IP can be used as a physical layer for many applications, connecting flash memory-based storage, cameras and RF subsystems, and for providing chip-to-chip inter-processor communications (IPC). It supports MIPI UniPro and JEDEC Universal Flash Storage (UFS) standard. By using efficient BURST mode operation with scalable speeds, significant power savings can be obtained. Selection of signal slew rate and amplitude allows reduction of EMI/RFI, while maintaining low bit error rates.
Time-Triggered Ethernet (TTEthernet) is a pioneering development by TTTech that offers deterministic Ethernet capabilities for safety-critical applications. This technology supports real-time communication between network nodes while maintaining the standard Ethernet infrastructure. TTEthernet enables reliable data delivery, with built-in mechanisms for fault tolerance that are vital for spaces like aviation, industrial automation, and space missions. One of the key aspects of TTEthernet is its ability to provide triple-redundant communication, ensuring network reliability even in the case of multiple failures. Licensed for significant projects such as NASA's Orion spacecraft, TTEthernet demonstrates its efficacy in environments that require dual fault-tolerance. As part of the ECSS engineering standard, the protocol supports human spaceflight standards and integrates seamlessly into space-based and terrestrial networks. The application of TTEthernet spans across multiple domains due to its robust nature and compliance with industry standards. It is particularly esteemed in markets that emphasize the importance of precise time synchronization and high availability. By using TTEthernet, companies can secure communications in networks without compromising on the speed and flexibility inherent to Ethernet-based systems.
Great River Technology offers the ARINC 818 Product Suite, a comprehensive collection of tools and products designed to cover the full spectrum of ARINC 818 applications. This suite is pivotal for engineers and designers who are focused on the aviation sector, providing solutions necessary for the creation, testing, and deployment of high-speed digital interfaces in avionics. The suite supports design and implementation phases by offering robust support tools tailored for ARINC 818 development, including detailed implementers' guides and simulation resources. What's unique about this suite is its ability to facilitate process integrations for ARINC 818 standards across various platforms, making it adaptable for differing needs in aviation systems. The integration tools provided ensure that systems can efficiently manage data and video transmissions, providing clarity, speed, and reliability, all essential factors in mission-critical environments. Great River Technology’s ARINC 818 Product Suite is engineered to ensure seamless interoperability, offering support from initial project development through to practical operation, thus enabling avionic systems to function optimally in both standard and specialized conditions.
Overview: The MIPI CSI-2 (Camera Serial Interface) defines an interface between a peripheral device (camera) and host processor (application engine) for mobile applications. It offers the mobile industry a standard, robust, scalable, low-power, high-speed, and cost-effective interface that supports a wide range of imaging solutions for mobile devices. Key Features: Compliance with MIPI-CSI-2 version 3.0 Compliance with C-PHY 2.0 for MIPI CSI-2 Version 3.0 Compliance with D-PHY 2.5 for MIPI CSI-2 Version 3.0 Compatibility with I2C and I3C (SDR, DDR) for CCI interface Support for C-PHY 2.0, D-PHY 2.5, A-PHY, M-PHY with configurable PHY layer Processor Interfaces: AHB Lite/APB/AXI for configuration Lane Merging Function for consolidating packet data in CSI-2 Receiver De-skew detection in D-PHY and sync word detection in C-PHY Pixel Formats Supported: YUV, RGB, and RAW data Virtual Channels: 16 for D-PHY, 32 for C-PHY Error detection, interleaving, scrambling, and descrambling support Byte to pixel conversion in LLP layer Applications: Imaging Surveillance Gaming Sensor devices Internet of Things (IoT) Wearable devices Virtual Reality Augmented Reality Automotive Systems
The NuLink Die-to-Die PHY for Standard Packaging by Eliyan is engineered to facilitate superior die-to-die interconnectivity on standard organic/laminate package substrates. This innovative PHY IP supports key industry standards such as UCIe and BoW, and includes proprietary technologies like UMI and SBD. The NuLink PHY delivers leading performance and power efficiency, comparable to advanced packaging technologies, but at a fraction of the cost. It features configurations with up to 64 data lanes, supporting a data rate per lane of up to 64Gbps, making it ideal for applications demanding high bandwidth and low latency. The implementation enhances system design while reducing the necessary area and thermal load, which significantly eases integration into existing hardware ecosystems.
This product offers an extensive range of high-speed interface IP solutions developed using an array of process technologies from 28nm to 90nm nodes. It supports various technology needs and provides tailored services for IP customization and transfer, enhancing adaptability for state-of-the-art processes or more mature ones ranging from 90-180nm. These encompass technologies like USB, DDR, and MIPI, ensuring robust solutions for advanced data communication requirements.
Overview: The MIPI DSI Transmitter IP is designed to transmit data to the host processor, providing the mobile industry with a standard, robust, scalable, low-power, high-speed, and cost-effective interface that supports a wide range of imaging solutions for mobile devices. Key Features: Compliance with MIPI-DSI-2 version 2.0 Compliance with C-PHY version 2.0 for DSI-2 Version-2 Compliance with D-PHY version 1.2 for DSI-2 Version-2.0 Compliance with D-PHY version 2.0 for DSI-2 Version-2.0 Compliance with D-PHY version 3.0 for DSI-2 Version-2.0 Compliance with MIPI SDF specification Compliance with DBI-2 and DPI-2 Pixel to Byte conversion support from Application layer to LLP layer Support for Command Mode and Video Mode Continuous clock behavior in clock lane for D-PHY physical layer De-skew sequence pattern for video mode support Lane Distribution Function for distributing packet bytes across N-Lanes Connectivity with two, three, or four DSI Receivers HS mode and Escape mode support for transmission of Packets in both C-PHY and D-PHY Symbol slip detection code and sync symbol insertion in C-PHY physical layer Target Applications: Imaging Surveillance Gaming Sensor devices Internet of Things (IoT) Wearable devices Virtual Reality Augmented Reality Automotive Systems
The C100 IoT chip by Chipchain is engineered to meet the diverse needs of modern IoT applications. It integrates a powerful 32-bit RISC-V CPU capable of reaching speeds up to 1.5GHz, with built-in RAM and ROM to facilitate efficient data processing and computational capabilities. This sophisticated single-chip solution is known for its low power consumption, making it ideal for a variety of IoT devices. This chip supports seamless connectivity through embedded Wi-Fi and multiple transmission interfaces, allowing it to serve broad application areas with minimal configuration complexity. Additionally, it boasts integrated ADCs, LDOs, and temperature sensors, offering a comprehensive toolkit for developers looking to innovate across fields like security, healthcare, and smart home technology. Notably, the C100 simplifies the development process with its high level of integration and performance. It stands as a testament to Chipchain's commitment to providing reliable, high-performance solutions for the rapidly evolving IoT landscape. The chip's design focuses on ensuring stability and security, which are critical in IoT installations.
Silicon Creations crafts highly reliable LVDS interfaces designed to meet diverse application needs, going from bi-directional I/Os to specialized uni-directional configurations. Spanning process compatibilities from 90nm CMOS to advanced 7nm FinFET, these interfaces are a cornerstone for high-speed data communication systems, thriving particularly in video data transmission and chip-to-chip communications. Supporting robust data rates over multiple channels, the LVDS Interfaces guarantee flexible programmability and protocol compatibility with standards such as FPD-Link and Camera-Link. They capitalize on proven PLL and CDR architectures for superior signal integrity and error-free data transfers. Operating efficiently in various technology nodes, they remain highly effective across collaborative chipset environments. The interfaces are fortified with adaptable features like dynamic phase alignment to stabilize data sequences and on-die termination options for superior signal integrity. Their proven record places them as a critical enabler in applications where consistent high-speed data transfer is paramount, demonstrating Silicon Creations’ prowess in delivering industry-leading communication solutions.
The Multi-Protocol SerDes provided by Silicon Creations serves as an essential component for high-speed data interfaces across multiple industry protocols. This SerDes portfolio accommodates a vast array of protocols such as PCIe, JESD204, XAUI, and many more, facilitating broad compatibility with industry standards. Operating across 12nm to 180nm processes, these interfaces support data rates from 100 Mbps to an impressive 32.75 Gbps. Incorporating advanced features like programmable de-serialization widths and adaptive equalization, the Multi-Protocol SerDes ensures optimal signal integrity and performance even in demanding environments. The design includes jitter cleaner functions and employs low-latency optimized PMAs, delivering high precision and speed across various operational scenarios. This comprehensive adaptability ensures seamless integration into a wide range of applications from communications to high-performance computing. Supported by robust architectures, the SerDes enables enhanced efficiency and reliability, featuring low power consumption and reduced area overheads. With a commitment to customer satisfaction, Silicon Creations offers complete solutions through partnerships with leading controller vendors, cementing its products as high-value choices for modern electronic systems.
Overview: The MIPI I3C Controller IP Core is fully compliant with the latest I3C specification, offering high bandwidth and scalability for integrating multiple sensors into mobile, automotive, and IoT system-on-chips (SoCs). This controller support in-band interrupts within the 2-wire interface, reducing pin count, simplifying board design, and lowering power and system costs. Backward compatibility with I2C ensures future-proof designs, and the controller's operating modes enable efficient connectivity for systems with multiple ICs and sensors on a single I3C bus. The ARM® AMBA® Advanced High-Performance Bus (AHB) facilitates seamless integration of the IP into the SoC. Key Features: Compliance with MIPI-I3C Basic v1.0 Backward compatibility with I2C Two-wire serial interface up to 12.5MHz using Push-Pull Dynamic and Static Addressing support Single Data Rate messaging (SDR) Broadcast and Direct Common Command Code (CCC) Messages support In-Band Interrupt capability Hot-Join Support Applications: Consumer Electronics Defense Aerospace Virtual Reality Augmented Reality Medical Biometrics (Fingerprints, etc.) Automotive Devices Sensor Devices
Overview: The SPD5 Hub controller IP is designed to interface with the I3C/I2C Host Bus, allowing for the isolation of local devices such as Temperature Sensors (TS) from the master host bus. It features a Two-wire serial interface with SCL and SDA busses. Key Features: Compliance with JEDEC's JESD300-5 Support for speeds up to 12.5MHz Bus Reset functionality SDA arbitration support Enabled Parity Check Support for Packet Error Check (PEC) Switch between I2C and I3C Basic Mode Default Read address pointer Mode Write and read operations for SPD5 Hub with or without PEC In-band Interrupt (IBI) support Write Protection for NVM memory blocks Arbitration for Interrupts Clearing of Device Status and IBI Status Registers Error handling for Packet Error Check and Parity Errors Common Command Codes (CCC) for I3C Basic Mode Dynamic IO Operation Mode Switching Bus Clear and Bus Reset capabilities SPD5 Command features for NVM memory and Register Space Read and Write access to NVM memory Support for Offline Tester operation Applications: DDR5 DIMM Application Environment DDR5 NVDIMM Application Environment Automotive Devices Memory Devices Power Management Devices Defense/Aerospace/Customer Electronics
The Multi-Protocol SERDES offered by Pico Semiconductor is a versatile solution capable of handling a variety of communication protocols. This series of SERDES includes a 4-channel configuration that supports data rates up to 32Gbps, designed for integration with XAUI, RXAUI, and SGMII. It is compatible with multiple process nodes provided by foundries like TSMC and GF, offering robust performance across different semiconductor environments. These SERDES are crafted to meet high-performance metrics, capturing speeds up to 16Gbps and 6.5Gbps across various models, with advanced versions reaching up to 32Gbps. This exceptional range not only ensures compatibility with current technologies but also prepares systems for future updates, sustaining high data throughput. By delivering reliable high-speed data transmission capabilities, the Multi-Protocol SERDES from Pico Semiconductor is integral for networking, high-speed computing, and data storage applications, where efficient and speedy data transfer is paramount.
The DisplayPort 1.4 core provides a comprehensive solution for DisplayPort requirements, implementing both source and sink capabilities. It supports link rates ranging from 1.62 Gbps to 8.1 Gbps, fitting standard DisplayPort and eDP scenarios efficiently. Users can take advantage of its support for multiple lanes, specifically 1, 2, and 4 lanes configurations, enabling versatile video interface options such as Native and AXI stream interfaces. This facilitates a strong multimedia performance, catering to both Single Stream Transport (SST) and Multi Stream Transport (MST) modes. The video processing toolkit accompanying this IP aims at aiding users in diverse video operations. These tools include a timing generator, a versatile test pattern generator, and crucial video clock recovery mechanisms. To simplify the integration into various systems, the IP is supported across a broad range of FPGA devices, including AMD and Intel lines, providing users with choice and flexibility for their specific application needs. Notably, it supports diverse video formats and color spaces, such as RGB, YCbCr 4:4:4, 4:2:2, and 4:2:0 at pixel depths of 8 and 10 bits. Secondary data packets handling audio and metadata enhance its multimedia capabilities. Furthermore, Parretto offers the source code on GitHub for ease of custom development, ensuring developers have the tools they need to adapt the IP to their unique systems.
The Time-Triggered Protocol (TTP) is a cornerstone of TTTech's offerings, designed for high-reliability environments such as aviation. TTP ensures precise synchronization and communication between systems, leveraging a time-controlled approach to data exchange. This makes it particularly suitable for safety-critical applications where timing and order of operations are paramount. The protocol minimizes risks associated with communication errors, thus enhancing operational reliability and determinism. TTP is deployed in various platforms, providing the foundation for time-deterministic operations necessary for complex systems. Whether in avionics or in industries requiring strict adherence to real-time data processing, TTP adapts to the specific demands of each application. By using this protocol, industries can achieve dependable execution of interconnected systems, promoting increased safety and reliability. In particular, TTP's influence extends into integrated circuits where certifiable IP cores are essential, ensuring compliance with stringent industry standards such as RTCA DO-254. Ongoing developments in TTP also include tools and methodologies that facilitate verification and qualification, ensuring that all system components communicate effectively and as intended across all operating conditions.
The 10G TCP Offload Engine is a sophisticated high-performance solution designed to offload TCP processing from the host CPU. Utilizing ultra-low latency technology, this IP incorporates a TCP/UDP stack integrated into high-speed FPGA hardware, ideal for networking environments demanding efficient processing and high throughput. Designed to handle up to 16,000 concurrent sessions, it manages TCP stacks within an impressive 77 nanoseconds, offering unmatched performance without straining the CPU. The engine supports 10 Gigabit Ethernet connectivity, ensuring seamless network integration and optimal data flow. With features like full TCP stack implementation and zero host CPU processing requirement, the offload engine is perfect for real-time cloud computing and AI networking applications, significantly reducing power consumption and enhancing bandwidth utilization. Equipped with a range of additional functions, such as large send offload and checksum offload, it optimizes network operations by eliminating bottlenecks typically associated with software-based solutions. It's an excellent choice for data centers and enterprise environments struggling with CPU bottlenecks.
The THOR platform is a versatile tool for developing application-specific NFC sensor and data logging solutions. It incorporates silicon-proven IP blocks, creating a comprehensive ASIC platform suitable for rigorous monitoring and continuous data logging applications across various industries. THOR is designed for accelerated development timelines, leveraging low power and high-security features. Equipped with multi-protocol NFC capabilities and integrated temperature sensors, the THOR platform supports a wide range of external sensors, enhancing its adaptability to diverse monitoring needs. Its energy-efficient design allows operations via energy harvesting or battery power, ensuring sustainability in its applications. This platform finds particular utility in sectors demanding precise environmental monitoring and data management, such as logistics, pharmaceuticals, and industrial automation. The platform's capacity for AES/DES encrypted data logging ensures secure data handling, making it a reliable choice for sectors with stringent data protection needs.
Overview: The MIPI CSI-2 (Camera Serial Interface) Transmitter IP establishes an interface between a peripheral device (camera) and host processor (application engine) for mobile applications. It offers the mobile industry a standard, robust, scalable, low-power, high-speed, and cost-effective interface that caters to a wide range of imaging solutions for mobile devices. Key Features: Compliance with MIPI-CSI-2 version 3.0 Compliance with C-PHY 2.0 for MIPI CSI-2 Version 3.0 Compliance with D-PHY 2.5 for MIPI CSI-2 Version 3.0 Compatibility with I2C and I3C (SDR, DDR) for CCI interface Pixel to Byte conversion support from Application layer to LLP layer Continuous clock behavior in clock lane for D-PHY physical layer De-skew sequence pattern in Data Lane Module Lane Distribution Function for distributing packet bytes across N-Lanes Sync word insertion through PPI command in C-PHY physical layer Insertion of Filler bytes in LLP layer for packet footer alignment Setting specific bits in packet header Defining frame blanking period Seed selection in scrambler and de-scrambler by Sync word Support for C-PHY/D-PHY/A-PHY/M-PHY with one PHY layer configuration Target Applications: Imaging Surveillance Gaming Sensor devices Internet of Things (IoT) Wearable devices Virtual Reality Augmented Reality Automotive Systems
The RISCV SoC - Quad Core Server Class is engineered for high-performance applications requiring robust processing capabilities. Designed around the RISC-V architecture, this SoC integrates four cores to offer substantial computing power. It's ideal for server-class operations, providing both performance efficiency and scalability. The RISCV architecture allows for open-source compatibility and flexible customization, making it an excellent choice for users who demand both power and adaptability. This SoC is engineered to handle demanding workloads efficiently, making it suitable for various server applications.
MIPI I3C Controller IP Core is fully compliant with the latest I3C specification and delivers high bandwidth and scalability for integration of multiple sensors into mobile, automotive and IoT system-on-chips (SoCs). The MIPI I3C Controller supports in-band interrupts within the 2-wire interface provides significantly lower pin count, simplifying board design and reducing power and cost of the system. The MIPI I3C Controller IP is fully backward compatible with I2C, allowing designers to future proof their design, and the I3C controller IP operating modes enable systems with several ICs to efficiently connect to all sensors on a single I3C bus. The standard-based ARM® AMBA® Advanced High Performance Bus (AHB) connects the IP to the rest of the SoC offering easy IP integration. MIPI I3C Controller IP is designed to easily integrate into any SoC offering lowest gate count and quickly fit into any Chip development flow.
Ventana's System IP is a critical component for next-generation RISC-V platforms, providing essential support for integrating high-performance CPUs into sophisticated computing architectures. This IP block enables system-level functionality that aligns with the stringent demands of modern computing environments, from cloud infrastructures to advanced automotive systems. Equipped with comprehensive system management capabilities, the System IP includes crucial components such as memory management units and I/O handling protocols that enhance the overall efficiency and reliability of RISC-V-based systems. It is optimized for virtualization and robust security, essential for maintaining integrity in high-traffic data centers. The System IP supports seamless integration with Ventana's Veyron processor families, ensuring scalability and consistent performance under demanding workloads. Its design allows for easy customization, making it an ideal choice for companies looking to innovate and expand within the rapidly evolving field of high-performance computing.
The BlueLynx Chiplet Interconnect system provides an advanced die-to-die connectivity solution designed to meet the demanding needs of diverse packaging configurations. This interconnect solution stands out for its compliance with recognized industry standards like UCIe and BoW, while offering unparalleled customization to fit specific applications and workloads. By enabling seamless connection to on-die buses and Networks-on-Chip (NoCs) through standards such as AMBA, AXI, ACE, and CHI, BlueLynx facilitates faster and cost-effective integration processes. The BlueLynx system is distinguished by its adaptive architecture that maximizes silicon utilization, ensuring high bandwidth along with low latency and power efficiency. Designed for scalability, the system supports a remarkable range of data rates from 2 to 40+ Gb/s, with an impressive bandwidth density of 15+ Tbps/mm. It also provides support for multiple serialization and deserialization ratios, ensuring flexibility for various packaging methods, from 2D to 3D applications. Compatible with numerous process nodes, including today’s most advanced nodes like 3nm and 4nm, BlueLynx offers a progressive pathway for chiplet designers aiming to streamline transitions from traditional SoCs to advanced chiplet architectures.
The MIPI solutions offered are comprehensive design and verification intellectual properties, continually updated to align with the latest specifications while maintaining backward compatibility. They cover an extensive range of standards such as CSI-2, DSI, UNIPRO, I3C, RFFE, Soundwire, BIF, and SPMI. These solutions are critical for high-speed interfaces required in mobile and automotive devices, ensuring robust performance across various applications.\n\nMIPI CSI-2 solutions, for example, support transmitter functionalities for Combo C/DPHY and receiver capabilities, offering complete solutions from version 1.0 through to 3.0. Each specification version builds on the last, ensuring that users can maintain compatibility with older systems while accessing cutting-edge features. DSI and DSI-2 offer similar comprehensive support, providing critical tools for display interfacing.\n\nOn top of this, auxiliary standards like I3C, RFFE, and Soundwire reinforce PRSsemicon's capacity to equip the latest devices with advanced communication capabilities. Their design includes master and slave functionality, ensuring comprehensive inter-device compatibility and communication efficiency. The continuous advancements in these IPs make them integral for any semiconductor-driven market, especially in technologically dynamic fields like automotive and consumer electronics.
Overview: The Power Management IC (PMIC) is specifically designed for DDR5 RDIMM, DDR5 LRDIMM, and DDR5 NVDIMM applications. It includes switching and LDO regulators to efficiently manage power distribution. The PMIC utilizes a MIPI-I3C Interface to select appropriate power settings for various application environments and is capable of operating at speeds up to 12.5MHz. Key Features: Maximum Operating speed of 12.5MHz Flexible Open-Drain IO (I2C) and Push-Pull (I3C) IO Support Multi-Time Programmable Non-Volatile Memory Interface Programmable and DIMM-specific registers for customization Error log registers for tracking Packet Error Check (PEC) and Parity Error Check functions Bus Reset function Support I3C Basic mode In-Band Interrupt (IBI) support Write, read, and default read operations in I2C mode Error handling for PEC, Parity errors, and CCC errors I3C Basic Common Command Codes (CCC) support Applications: DDR5 DIMM Application Environment DDR5 NVDIMM Application Environment Automotive Devices Memory Devices Power Management Devices Defense/Aerospace/Customer Electronics
Silicon Creations' Bi-Directional LVDS Interfaces are engineered to offer high-speed data transmission with exceptional signal integrity. These interfaces are designed to complement FPGA-to-ASIC conversions and include broad compatibility with industry standards like FPD-Link and Camera-Link. Operating efficiently over processes from 90nm to 12nm, the LVDS interfaces achieve data rates exceeding 3Gbps using advanced phase alignment techniques. A standout feature of this IP is its capability to handle independent LVCMOS input and output functions while maintaining high compatibility with TIA/EIA644A standards. The bi-directional nature allows for seamless data flow in chip-to-chip communications, essential for modern integrated circuits requiring high data throughput. The design is further refined with trimmable on-die termination, enhancing signal integrity during operations. The LVDS interfaces are versatile and highly programmable, meeting bespoke application needs with ease. The interfaces ensure robust error rate performance across varying phase selections, making them ideal for video data applications, controllers, and other high-speed data interfaces where reliability and performance are paramount.
The Hyperspectral Imaging System developed by Imec is designed to capture images across numerous wavelengths, enabling detailed analysis of spectral information beyond conventional imaging. This hyperspectral imaging technology is pivotal in extracting valuable insights in fields such as precision agriculture, environmental monitoring, and industrial inspection. With its versatile applications, it offers enhanced capabilities in material identification, chemical analysis, and quality control processes. This system incorporates state-of-the-art sensors that capture data with high spectral and spatial resolution, providing a comprehensive spectral fingerprint of the imaged scene. It excels in distinguishing subtle differences in material properties by analyzing the light reflected from different surfaces across various spectral bands. By using this advanced imaging system, users can perform complex analyses such as vegetation monitoring, pollution detection, and mineral mapping with unprecedented precision. It allows for non-destructive testing, which is crucial for industries like food safety, pharmaceutical production, and environmental science.
The MXL-LVDS-MIPI-RX is a high-frequency, low-power, low-cost, source-synchronous, Physical Layer that supports the MIPI® Alliance Standard for D-PHY and compatible with the TIA/EIA-644 LVDS standard. (Learn more about Mixel’s MIPI ecosystem at Mixel MIPI Central which gives you access to Mixel’s best of class MIPI ecosystem supply chain partners.) The IP is configured as a MIPI slave and consists of 5 lanes: 1 Clock lane and 4 data lanes, which make it suitable for display serial interface applications (DSI). The High-Speed signals have a low voltage swing, while Low-Power signals have large swing. High-Speed functions are used for High-Speed Data traffic while low power functions are mostly used for control.
Glasswing Ultra-Short Reach SerDes leverages the power of Chord Signaling, significantly enhancing data transfer efficiency and power management in chip-to-chip communications. With its ability to provide high bidirectional throughput, Glasswing is ideal for applications that require substantial data bandwidth but must minimize power consumption. This advanced technology employs the innovative CNRZ-5 signaling technique to double data throughput while halving power usage, paving the way for more sustainable and efficient networking and high-performance computing environments. With a low pin count and high signal integrity, Glasswing helps simplify the design of complex systems without compromising performance. The Glasswing SerDes supports significant bandwidth capabilities, reaching up to 500 Gbit/s per pin, and its modular design allows it to be tiled in multiple configurations, offering flexibility and scalability. Its robust diagnostics and reliability make it a powerful tool for developing next-generation telecommunications and data processing systems.
The MXL-LVDS-DPHY-DSI-TX is a combo PHY that consists of a high-frequency low-power, low-cost, source-synchronous, Physical Layer supporting the MIPI® Alliance Standard for D-PHY and a high performance 4-channel LVDS Serializer implemented using digital CMOS technology. (Learn more about Mixel’s MIPI ecosystem at Mixel MIPI Central which gives you access to Mixel’s best of class MIPI ecosystem supply chain partners.) In LVDS mode, both the serial and parallel data are organized into 4 channels. The parallel data is 7 bits wide per channel. The input clock is 25MHz to 150MHz. The serializer is highly integrated and requires no external components. The circuit is designed in a modular fashion and desensitized to process variations. This facilitates process migration, and results in a robust design.
The MIPI D-PHY offering by SkyeChip enhances high-speed data communication between chips, supporting image sensors, display panels, and camera designs. This PHY layer is tailored to provide efficient data transfer mechanisms while maintaining low power consumption, suited for mobile and multimedia electronics where high bandwidth and energy efficiency are critical.
In smartphone applications, ActLight’s Dynamic PhotoDetector (DPD) offers a step-change in photodetection technology, enhancing features such as proximity sensing and ambient light detection. This high sensitivity sensor, with its ability to detect subtle changes in light, supports functions like automatic screen brightness adjustments and energy-efficient proximity sensing. Designed for low voltage operation, the DPD effectively reduces power consumption, making it suitable for high-performance phones without increasing thermal load. The technology also facilitates innovative applications like 3D imaging and eye-tracking, adding richness to user experiences in gaming and augmented reality.
The Camera PHY Interface for Advanced Processes is an advanced interface solution supporting various transmission standards for high-speed data transfer in image sensor applications. It offers robust performance by integrating sub-LVDS, MIPI D-PHY, and HiSPi protocols, among others, ensuring versatile compatibility with advanced semiconductor manufacturing processes. This interface IP is instrumental in facilitating the seamless integration of CMOS image sensors in high-resolution and high-frame-rate cameras, enabling superior image capture quality and efficiency. The Camera PHY Interface is engineered to support high-speed data rates up to 5Gbps, making it suitable for applications requiring rapid data transmission and processing capabilities, such as in professional photography or high-end surveillance equipment. The use of advanced process nodes ensures that the interface maintains its high performance while supporting low power consumption, which is critical for portable and power-sensitive applications. Incorporating this IP within camera systems enhances the overall data throughput and integrity, minimizing latency and ensuring real-time image processing. It is particularly beneficial in devices that demand quick image data transmission without degradation, paving the way for smoother video recording and image capturing experiences. The adaptability of this PHY interface to various standards and process variations further enhances its applicability across multiple platforms and use cases, promoting a high degree of design flexibility.
The MIPITM SVRPlus2500 provides an efficient solution for high-speed 4-lane video reception. It's compliant with CSI2 rev 2.0 and DPHY rev 1.2 standards, designed to facilitate easy timing closure with a low clock rating. This receiver supports PRBS, boasts calibration capabilities, and offers a versatile output of 4/8/16 pixels per clock. It features 16 virtual channels and 1:16 input deserializers per lane, handling data rates up to 10Gbps, making it ideal for complex video processing tasks.
The Universal High-Speed SERDES core caters to applications demanding rapid data exchange across a range of standards, including RapidIO, Fibre Channel, and XAUI. This core is remarkable for its flexibility, accommodating data rates from 1Gbps to 12.5Gbps with variable data width options like 16bit, 20bit, 32bit, and 40bit. Designed with a pre-emphasis linear equalizer and an adaptive receiver equalizer, this SERDES solution ensures optimal signal integrity across various transmission distances and conditions, enhancing the robustness of the data link. It is also capable of operating without any external components, streamlining the design process and minimizing associated costs. Additionally, the core supports multiple packaging models and channel configurations, providing a highly adaptable platform for diverse applications. Whether for high-speed backplanes or chip-to-chip communications, this SERDES core delivers high performance and reliability, supported by process node flexibility including support for 28nm and larger nodes, facilitating integration into a wide range of semiconductor technologies.
Analog Bits' I/O solutions are engineered for flexibility and high performance, addressing a wide range of input/output demands across semiconductor applications. These solutions deliver robust signal integrity measures alongside low latency, facilitating dynamic connection between different systems efficiently. Designed with adaptability in mind, their I/O IPs encompass numerous configurations suitable for diverse design requirements. The I/O IPs from Analog Bits are characterized by improved signal robustness and vitality even under strenuous operational conditions, supporting fast-changing, high-volume data tasks. Their ability to seamlessly adjust to various bus standards makes them indispensable for applications that require adaptability without compromising speed or reliability. Key applications include data conversion and facilitating communication between different semiconductor components. With strategic compatibility for a multitude of foundry process nodes, these I/O modules ensure ease of integration while maintaining high electromagnetic compatibility. This scope of adaptability combined with their technical superiority secures their role as a crucial component in the optimization of semiconductor device efficiency and performance.
The JESD204B Multi-Channel PHY is a highly advanced high-speed interface core designed for multi-channel applications, offering data rates up to 12.5Gbps. It excels in supporting deterministic latency features and SYSREF functionality, which are crucial for synchronizing data transfer across channels in high-performance systems. The core implements 8b/10b encoding/decoding and scrambling for reliable data transmission, ensuring robust performance in diverse applications. This IP is adaptable to a range of system needs with its independent design for both transmission and reception, facilitating seamless integration into existing hardware architectures. It supports a variety of data flow packet configurations, offering flexible channel arrangements tailored to specific application requirements. The core’s versatility is further enhanced by its support for multiple process technologies, including 65nm, 55nm, 40nm, and 28nm nodes, allowing for integration with different semiconductor platforms. The JESD204B PHY is engineered to meet the needs of applications such as telecommunications and data acquisition systems, where high-speed data transfer and reliability are paramount. Its design is optimized to provide not only speed and efficiency but also compatibility with different deployment environments, making it an essential component for cutting-edge electronic systems.
The RF-SOI and RF-CMOS platform is distinguished by its ability to optimize wireless communication components for high frequencies and low power consumption applications. Building on Silicon on Insulator (SOI) technology, this platform allows for improved isolation and reduced parasitic capacitance, enhancing RF performance. This combination of SOI and CMOS technology provides the versatility needed to address stringent requirements in RF signal processing, making it a prime choice for designing cutting-edge wireless devices. The technology's capabilities support advancements in 5G networks and IoT devices, where precision and efficiency are critical. Designed for scalability, the RF-SOI and RF-CMOS platform empowers engineers to leverage component miniaturization while maintaining excellent performance, catering to the demands of complex infrastructure requirements in the telecommunications industry.
The MXL-DS-LVDS is a high performance 4-channel LVDS Deserializer implemented using digital CMOS technology. Both the serial and parallel data are organized into four channels. The parallel data can be 7 or 10 bits wide per channel. The input clock is 25MHz to 165MHz. The De-serializer is highly integrated and requires no external components. Great care was taken to insure matching between the Data and Clock channels to maximize the deserializer margin. The circuit is designed in a modular fashion and desensitized to process variations. This facilitates process migration, and results in a robust design.
Matterhorn USB4 Retimer is a state-of-the-art component designed to optimize data transfer rates for USB4 technology, enabling devices to perform at unprecedented speeds. This retimer is crucial for modern USB communications, where high throughput and low latency are essential for seamless user experiences. Its advanced design ensures that the Matterhorn Retimer can handle the most demanding data transfer requirements, making it ideal for use in cutting-edge consumer electronics and professional computing environments. The Matterhorn provides the stability and speed necessary to support the next generation of USB-driven technologies. By ensuring high signal integrity across extended cable lengths and complex system environments, the Matterhorn Retimer facilitates efficient data exchanges, helping to maximize device functionality and performance. Its incorporation into electronic devices represents a commitment to maintaining connectivity standards that keep pace with ever-evolving user needs.
The MXL-SR-LVDS is a high performance 4-channel LVDS Serializer implemented using digital CMOS technology. Both the serial and parallel data are organized into four channels. The parallel data width is programmable, and the input clock is 25MHz to 165MHz. The Serializer is highly integrated and requires no external components. It employs optional pre-emphasis to enable transmission over a longer distance while achieving low BER. The circuit is designed in a modular fashion and desensitized to process variations. This facilitates process migration, and results in a robust design.
StreamDSP's MIPI Video Processing Pipeline offers a comprehensive solution for integrating video streams into FPGA-based environments. Supporting Avalon and AXI-4 Streaming protocols, it is highly adaptable to different sensor video formats and frame rates, extending capability to 4K resolutions at 60fps. The pipeline is adept at handling complex processing tasks, including Bayer demosaicing and gamma correction, designed to enhance video output while maintaining minimal latency through optional frame buffering.
The MIPI D-PHY IP developed by Silicon Library Inc. is specifically designed for mobile and high-speed data communication applications. It is characteristically used in devices that manage significant data transfers, such as smartphones, tablets, and digital cameras, providing a high-throughput interface for image and video data. Engineered to support the MIPI D-PHY standard, this IP ensures efficient data transfer and minimal latency, making it ideally suited for applications that rely on real-time video processing. Its configuration allows flexibility in design, accommodating various data lane configurations to suit specific project requirements. Moreover, the MIPI D-PHY IP is designed to be scalable, supporting a multiplicity of performance needs while ensuring low power consumption, which is crucial in battery-operated devices. For manufacturers aiming to integrate advanced multimedia capabilities into their products, Silicon Library's offering provides a comprehensive solution.
Time-Sensitive Networking (TSN) represents TTTech's continued leadership in the field of data communication standards. Particularly beneficial in sectors requiring high bandwidth and interoperability, TSN facilitates the establishment of networks where timing precision and control over data traffic are critical. TSN supports synchronization across devices, using a strict traffic scheduling system that ensures data packets are transmitted in a timely manner. TSN's versatile architecture allows it to be adopted in various industries, such as automotive, industrial automation, and information technology. As a bridge between operational technology and information technology domains, TSN enables seamless data flow, fostering a more connected ecosystem. Its implementation ensures not only enhanced performance but also the incorporation of advanced features such as redundancy for reliability and the prioritization of critical data streams. Designed for modern network requirements, TSN technologies developed by TTTech come with extensive tools and resources that aid in the configuration and deployment of networks. By aligning with IEEE standards, TSN protocols promote interoperability across numerous platforms, thereby supporting the convergence of diverse network systems into a single, cohesive architecture.
The MIPITM SVTPlus-8L-F is a cutting-edge serial video transmitter designed for FPGAs. This transmitter adheres to CSI2 rev 2.0 and DPHY rev 1.2, featuring 8 lanes and capable of handling data rates of up to 12Gbps. It's engineered for high-performance video applications, boasting robust processing capabilities. Its support for advanced transmission protocols ensures seamless integration and compatibility with a wide range of video systems.
The 100BASE-T1 Ethernet PHY is designed to support high-speed communication in automotive and industrial applications while using a single twisted pair cable. This technology enables reduced wiring costs and simplifies system integration. With its low power consumption and small footprint, it is ideal for use in space-constrained environments where maintaining robust connectivity is critical. Designed to comply with IEEE standards, the 100BASE-T1 Ethernet PHY offers a reliable solution for long cable applications without sacrificing performance. It delivers a maximum data rate of 100 Mbps, which is ample for many contemporary network needs. The PHY leverages low power technology to enhance energy efficiency, making it suitable for applications where power conservation is a necessity. The compact design of the 100BASE-T1 Ethernet PHY ensures easy integration into existing systems, providing flexibility in a wide range of applications. Its ability to support high data rates over a simple UTP cable makes it a cost-effective solution for the deployment of Ethernet in applications where traditional Ethernet cabling is impractical.
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