All IPs > Interface Controller & PHY > MIPI
The MIPI category under Interface Controller & PHY encompasses a broad range of semiconductor IPs tailored for high-speed data transfer between components in mobile and IoT devices. MIPI, which stands for Mobile Industry Processor Interface, is an industry-driven standard aimed at simplifying the integration of different advanced technologies into small form factor devices while ensuring optimal communication efficiency and power consumption.
Within this category, you will find semiconductor IPs that address the critical need for reducing latency and increasing the bandwidth of data communication across various internal components. These MIPI interfaces are vital in smartphones, tablets, and other portable electronics, where space is at a premium, yet there's a demand for high-performance data exchange and energy efficiency. The IPs provide solutions for connecting processors to modems, sensors, displays, and cameras, enabling manufacturers to build devices with faster data processing capabilities and higher battery life.
MIPI semiconductor IPs in this category include MIPI D-PHY, C-PHY, and M-PHY, among others. These IPs are designed to support versatile and scalable designs, allowing for personalization depending on the specific requirements of the end product. MIPI D-PHY, for instance, is often used in applications requiring video transmission with high-quality imaging sensors, providing a robust method to deliver both power and data through the same interface.
By leveraging MIPI semiconductor IPs, designers can ensure that their products adhere to the latest industry standards, providing a competitive edge in the technology market. These IPs support a seamless interface experience, enhance data transmission efficiencies, and reduce both development time and costs. Integrating MIPI interface controller and PHY solutions will drive innovation and bring sophisticated electronic products to market faster and more efficiently than ever before.
The Mixel MIPI C-PHY IP (MXL-CPHY) is a high-frequency, low-power, low cost, physical layer. (Learn more about Mixel’s MIPI ecosystem at Mixel MIPI Central which gives you access to Mixel’s best of class MIPI ecosystem supply chain partners.) The C-PHY configuration consists of up to three lane modules and is based on 3-Phase symbol encoding technology, delivering 2.28 bits per symbol over three-wire trios and targeting a maximum rate of 2.5 Gsps, 5.7Gbps. The C-PHY is partitioned into a digital module – CIL (Control and Interface Logic) and a mixed-signal module. The PHY IP is provided as a combination of soft IP views (RTL, and STA Constraints) for the digital module, and hard IP views (GDSII/CDL/LEF/LIB) for the mixed-signal module. This unique offering of both soft and hard IP permits architectural design flexibility and seamless implementation in customer-specific design flow. The CIL module interfaces with the protocol layer and determines the global operation of the module. The interface between the PHY and the protocol is using the PHY-Protocol Interface (PPI). The mixed-signal module includes high-speed signaling mode for fast-data traffic and low-power signaling mode for control purposes. During normal operation, a lane switches between low-power and high-speed mode. Bidirectional lanes can also switch communication direction. The change of operating mode or direction requires enabling and disabling of certain electrical functions. These enable and disable events do not cause glitches on the lines that would result in a detection of incorrect signal levels. All mode and direction changes are smooth to always ensure a proper detection of the line signals. Mixel’s C-PHY is a complete PHY, silicon-proven at multiple foundries and multiple nodes. It is built to support the MIPI Camera Serial Interface (CSI) and Display Serial Interface (DSI).
The Mixel MIPI C/D-PHY combo IP (MXL-CPHY-DPHY) is a high-frequency low-power, low cost, physical layer compliant with the MIPI® Alliance Standard for C-PHY and D-PHY. (Learn more about Mixel’s MIPI ecosystem at Mixel MIPI Central which gives you access to Mixel’s best of class MIPI ecosystem supply chain partners.) The PHY can be configured as a MIPI Master or MIPI Slave, supporting camera interface CSI-2 v1.2 or display interface DSI v1.3 applications in the D-PHY mode. It also supports camera interface CSI-2 v1.3 and display interface DSI-2 v1.0 applications in the C-PHY mode. The high-speed signals have a low voltage swing, while low-power signals have large swing. High-Speed functions are used for high-speed data traffic while low-power functions are mostly used for control. The C-PHY is based on 3-Phase symbol encoding technology, delivering 2.28 bits per symbol over three-wire trios, operating with a symbol rate range of 80 to 4500 Msps per lane, which is the equivalent of about 182.8 to 10260 Mbps per lane. The D-PHY supports a bit rate range of 80 to 1500 Mbps per Lane without deskew calibration, and up to 4500 Mbps with deskew calibration. The low-power mode and escape mode are the same in both the D-PHY and C-PHY modes. To minimize EMI, the drivers for low-power mode are slew-rate controlled and current limited. The data rate in low-power mode is 10 Mbps. For a fixed clock frequency, the available data capacity of a PHY configuration can be increased by using more lanes. Effective data throughput can be reduced by employing burst mode communication. Mixel’s C-PHY/D-PHY combo is a complete PHY, silicon-proven at multiple foundries and multiple nodes. The C/D-PHY is fully integrated and has analog circuitry, digital, and synthesizable logic.
Silicon Creations' SerDes Interfaces are crafted to handle high-speed data transmission challenges over varied processes, ranging from 12nm to 180nm. Addressing multiple protocols such as CPRI, PCIe, and SATA, these interfaces demonstrate flexibility by supporting data transmission speeds from 100 Mbps to beyond 32 Gbps. The architecture incorporates a host of advanced features including adaptive equalization techniques and programmable de-serialization widths, making it stand out in terms of performance and signal integrity even under challenging conditions. With ultra-low latency PMAs, they sustain excellent operational speed and efficiency, imperative for sophisticated communication applications. Moreover, Silicon Creations partners with leading entities to provide comprehensive solutions, including complete PCIe PHY integrations. This synergy ensures that SerDes Interfaces are fully optimized for operational excellence, delivering stable and reliable communication signals. With an emphasis on low power and minimized area requirements, they cater to burgeoning industry needs for power-efficient and space-conservative designs.
The Mixel MIPI D-PHY IP (MXL-DPHY) is a high-frequency low-power, low cost, source-synchronous, physical layer compliant with the MIPI® Alliance Standard for D-PHY. (Learn more about Mixel’s MIPI ecosystem at Mixel MIPI Central which gives you access to Mixel’s best of class MIPI ecosystem supply chain partners.) Although primarily used for connecting cameras and display devices to a core processor, this MIPI PHY can also be used for many other applications. It is used in a master-slave configuration, where high-speed signals have a low voltage swing, and low-power signals have large swing. High-speed functions are used for high-speed data traffic while low-power functions are mostly used for control. The D-PHY is partitioned into a Digital Module – CIL (Control and Interface Logic) and a Mixed Signal Module. It is provided as a combination of Soft IP views (RTL, and STA Constraints) for Digital Module, and Hard IP views (GDSII/CDL/LEF/LIB) for the Mixed Signal Module. This unique offering of Soft and Hard IP permits architectural design flexibility and seamless implementation in customer-specific design flow. The CIL module interfaces with the protocol layer and determines the global operation of the lane module. The interface between the D-PHY and the protocol is called the PHY-Protocol Interface (PPI). During normal operation, the data lane switches between low-power mode and high-speed mode. Bidirectional lanes can also switch communication direction. The change of operating mode or direction requires enabling and disabling certain electrical functions. These enable and disable events do not cause glitches on the lines that would otherwise result in detections of incorrect signal levels. Therefore, all mode and direction changes occur smoothly, ensuring proper detection of the line signals. Mixel’s D-PHY is a complete PHY, silicon-proven at multiple foundries and multiple nodes. This MIPI PHY is fully integrated and has analog circuitry, digital, and synthesizable logic. Our D-PHY is built to support the MIPI Camera Serial Interface (CSI) and Display Serial Interface (DSI) using the PHY Protocol Interface (PPI). Mixel has provided this IP in many different configurations to accommodate different applications. The Universal Lane configuration can be used to support any allowed use-case, while other configurations are optimized for many different use cases such as Transmit only, Receive only, DSI, CSI, TX+ and RX+. Both TX+ and RX+ configurations support full-speed loopback operation without the extra area associated with a universal lane configuration.
Designed to cater to high-performance networking needs, this offload engine integrates multiple functionalities including TCP offloading, MAC, PCIe, and host interface in one low-latency package. It enables a complete bypass of the host CPU processing, drastically reducing the load and enhancing data throughput. The solution boasts an ultra-low latency of 77 ns, ensuring robust performance suited for critical applications that demand high-speed data processing. The architecture of this offload engine supports a vast number of concurrent TCP and UDP sessions, offering a consistent latency and impressive data transfer rate per session. By offloading network processing tasks, this solution frees up CPU resources, thus achieving efficient operation and lower power consumption. It is particularly advantageous for deployment in data-intensive environments such as cloud computing infrastructures and modern data centers. Equipped with dual-10G ports and advanced features like enterprise-class reliability and scalability, it has been widely adopted for its capability to execute networking tasks efficiently while consuming minimal resources. This engine integrates architecture that is designed to be immune to network jitter, providing a seamless networking experience across multiple ports.
Time-Triggered Ethernet (TTEthernet) is a cutting-edge data communication solution tailored for aviation and space sectors requiring dual fault-tolerance and redundancy. Critically designed to support environments with high safety-criticality, TTEthernet embodies an evolutionary step in Ethernet communication by integrating deterministic behavior with conventional Ethernet benefits. This blend of technologies facilitates the transfer of data with precision timing, ensuring that all communications occur as scheduled—a vital feature for mission-critical operations. TTEthernet is particularly advantageous in applications requiring high levels of data integrity and latency control. Its deployment across triple-redundant network architectures ensures that even in case of component failures, the network continues to function seamlessly. Such redundancy is necessary in scenarios like human space missions, where data loss or delay is not an option. TTTech's TTEthernet offerings, which also include ASIC designs, meet the European Cooperation for Space Standardization (ECSS) standards, reinforcing their reliability and suitability for the most demanding applications. Supporting both end systems and more intricate system-on-chip designs, this technology synchronizes all data flow to maintain continuity and consistency throughout the network infrastructure.
The ARINC 818 Product Suite is a comprehensive collection of tools and resources designed to support the full development lifecycle for ARINC 818 enabled equipment. This suite assists in the implementation and testing of ARINC 818 protocols, which are crucial for systems that require high-performance video and data transmission, such as in avionics and defense applications. The product suite is built to facilitate not only the development and qualification but also the simulation of ARINC 818 products, ensuring effective integration into mission-critical environments. The suite’s tools include development software and Implementer's guides, enabling seamless access to ARINC 818 capabilities.
Overview: The MIPI CSI-2 (Camera Serial Interface) defines an interface between a peripheral device (camera) and host processor (application engine) for mobile applications. It offers the mobile industry a standard, robust, scalable, low-power, high-speed, and cost-effective interface that supports a wide range of imaging solutions for mobile devices. Key Features: Compliance with MIPI-CSI-2 version 3.0 Compliance with C-PHY 2.0 for MIPI CSI-2 Version 3.0 Compliance with D-PHY 2.5 for MIPI CSI-2 Version 3.0 Compatibility with I2C and I3C (SDR, DDR) for CCI interface Support for C-PHY 2.0, D-PHY 2.5, A-PHY, M-PHY with configurable PHY layer Processor Interfaces: AHB Lite/APB/AXI for configuration Lane Merging Function for consolidating packet data in CSI-2 Receiver De-skew detection in D-PHY and sync word detection in C-PHY Pixel Formats Supported: YUV, RGB, and RAW data Virtual Channels: 16 for D-PHY, 32 for C-PHY Error detection, interleaving, scrambling, and descrambling support Byte to pixel conversion in LLP layer Applications: Imaging Surveillance Gaming Sensor devices Internet of Things (IoT) Wearable devices Virtual Reality Augmented Reality Automotive Systems
The NuLink Die-to-Die PHY for Standard Packaging represents Eliyan's cornerstone technology, engineered to harness the power of standard packaging for die-to-die interconnects. This technology circumvents the limitations of advanced packaging by providing superior performance and power efficiencies traditionally associated only with high-end solutions. Designed to support multiple standards, such as UCIe and BoW, the NuLink D2D PHY is an ideal solution for applications requiring high bandwidth and low latency without the cost and complexity of silicon interposers or silicon bridges. In practical terms, the NuLink D2D PHY enables chiplets to achieve unprecedented bandwidth and power efficiency, allowing for increased flexibility in chiplet configurations. It supports a diverse range of substrates, providing advantages in thermal management, production cycle, and cost-effectiveness. The technology's ability to split a Network on Chip (NoC) across multiple chiplets, while maintaining performance integrity, makes it invaluable in ASIC designs. Eliyan's NuLink D2D PHY is particularly beneficial for systems requiring physical separation between high-performance ASICs and heat-sensitive components. By delivering interposer-like bandwidth and power in standard organic or laminate packages, this product ensures optimal system performance across varied applications, including those in AI, data processing, and high-speed computing.
Silicon Creations crafts highly reliable LVDS interfaces designed to meet diverse application needs, going from bi-directional I/Os to specialized uni-directional configurations. Spanning process compatibilities from 90nm CMOS to advanced 7nm FinFET, these interfaces are a cornerstone for high-speed data communication systems, thriving particularly in video data transmission and chip-to-chip communications. Supporting robust data rates over multiple channels, the LVDS Interfaces guarantee flexible programmability and protocol compatibility with standards such as FPD-Link and Camera-Link. They capitalize on proven PLL and CDR architectures for superior signal integrity and error-free data transfers. Operating efficiently in various technology nodes, they remain highly effective across collaborative chipset environments. The interfaces are fortified with adaptable features like dynamic phase alignment to stabilize data sequences and on-die termination options for superior signal integrity. Their proven record places them as a critical enabler in applications where consistent high-speed data transfer is paramount, demonstrating Silicon Creations’ prowess in delivering industry-leading communication solutions.
The Mixel MIPI M-PHY (MXL-MPHY) is a high-frequency low-power, Physical Layer IP that supports the MIPI® Alliance Standard for M-PHY. (Learn more about Mixel’s MIPI ecosystem at Mixel MIPI Central which gives you access to Mixel’s best of class MIPI ecosystem supply chain partners.) The IP can be used as a physical layer for many applications, connecting flash memory-based storage, cameras and RF subsystems, and for providing chip-to-chip inter-processor communications (IPC). It supports MIPI UniPro and JEDEC Universal Flash Storage (UFS) standard. By using efficient BURST mode operation with scalable speeds, significant power savings can be obtained. Selection of signal slew rate and amplitude allows reduction of EMI/RFI, while maintaining low bit error rates.
Overview: The MIPI I3C Controller IP Core is fully compliant with the latest I3C specification, offering high bandwidth and scalability for integrating multiple sensors into mobile, automotive, and IoT system-on-chips (SoCs). This controller support in-band interrupts within the 2-wire interface, reducing pin count, simplifying board design, and lowering power and system costs. Backward compatibility with I2C ensures future-proof designs, and the controller's operating modes enable efficient connectivity for systems with multiple ICs and sensors on a single I3C bus. The ARM® AMBA® Advanced High-Performance Bus (AHB) facilitates seamless integration of the IP into the SoC. Key Features: Compliance with MIPI-I3C Basic v1.0 Backward compatibility with I2C Two-wire serial interface up to 12.5MHz using Push-Pull Dynamic and Static Addressing support Single Data Rate messaging (SDR) Broadcast and Direct Common Command Code (CCC) Messages support In-Band Interrupt capability Hot-Join Support Applications: Consumer Electronics Defense Aerospace Virtual Reality Augmented Reality Medical Biometrics (Fingerprints, etc.) Automotive Devices Sensor Devices
The Multi-Protocol SERDES offered by Pico Semiconductor is a versatile solution capable of handling a variety of communication protocols. This series of SERDES includes a 4-channel configuration that supports data rates up to 32Gbps, designed for integration with XAUI, RXAUI, and SGMII. It is compatible with multiple process nodes provided by foundries like TSMC and GF, offering robust performance across different semiconductor environments. These SERDES are crafted to meet high-performance metrics, capturing speeds up to 16Gbps and 6.5Gbps across various models, with advanced versions reaching up to 32Gbps. This exceptional range not only ensures compatibility with current technologies but also prepares systems for future updates, sustaining high data throughput. By delivering reliable high-speed data transmission capabilities, the Multi-Protocol SERDES from Pico Semiconductor is integral for networking, high-speed computing, and data storage applications, where efficient and speedy data transfer is paramount.
Overview: The SPD5 Hub controller IP is designed to interface with the I3C/I2C Host Bus, allowing for the isolation of local devices such as Temperature Sensors (TS) from the master host bus. It features a Two-wire serial interface with SCL and SDA busses. Key Features: Compliance with JEDEC's JESD300-5 Support for speeds up to 12.5MHz Bus Reset functionality SDA arbitration support Enabled Parity Check Support for Packet Error Check (PEC) Switch between I2C and I3C Basic Mode Default Read address pointer Mode Write and read operations for SPD5 Hub with or without PEC In-band Interrupt (IBI) support Write Protection for NVM memory blocks Arbitration for Interrupts Clearing of Device Status and IBI Status Registers Error handling for Packet Error Check and Parity Errors Common Command Codes (CCC) for I3C Basic Mode Dynamic IO Operation Mode Switching Bus Clear and Bus Reset capabilities SPD5 Command features for NVM memory and Register Space Read and Write access to NVM memory Support for Offline Tester operation Applications: DDR5 DIMM Application Environment DDR5 NVDIMM Application Environment Automotive Devices Memory Devices Power Management Devices Defense/Aerospace/Customer Electronics
Overview: The MIPI DSI Transmitter IP is designed to transmit data to the host processor, providing the mobile industry with a standard, robust, scalable, low-power, high-speed, and cost-effective interface that supports a wide range of imaging solutions for mobile devices. Key Features: Compliance with MIPI-DSI-2 version 2.0 Compliance with C-PHY version 2.0 for DSI-2 Version-2 Compliance with D-PHY version 1.2 for DSI-2 Version-2.0 Compliance with D-PHY version 2.0 for DSI-2 Version-2.0 Compliance with D-PHY version 3.0 for DSI-2 Version-2.0 Compliance with MIPI SDF specification Compliance with DBI-2 and DPI-2 Pixel to Byte conversion support from Application layer to LLP layer Support for Command Mode and Video Mode Continuous clock behavior in clock lane for D-PHY physical layer De-skew sequence pattern for video mode support Lane Distribution Function for distributing packet bytes across N-Lanes Connectivity with two, three, or four DSI Receivers HS mode and Escape mode support for transmission of Packets in both C-PHY and D-PHY Symbol slip detection code and sync symbol insertion in C-PHY physical layer Target Applications: Imaging Surveillance Gaming Sensor devices Internet of Things (IoT) Wearable devices Virtual Reality Augmented Reality Automotive Systems
The HOTLink II Product Suite constitutes a range of resources specifically tailored for systems utilizing HOTLink II™ technology. This suite is engineered to manage high-speed video and data communication in environments where reliability and precision are paramount. It is ideal for applications in aerospace where maintaining high data integrity is critical. The suite provides robust solutions for both the development and operational stages, enhancing system performance. With its extensive support for different phases of product lifecycle management, the HOTLink II suite ensures that products meet the high standards required for mission-critical military and industrial applications.
The Multi-Protocol SerDes provided by Silicon Creations serves as an essential component for high-speed data interfaces across multiple industry protocols. This SerDes portfolio accommodates a vast array of protocols such as PCIe, JESD204, XAUI, and many more, facilitating broad compatibility with industry standards. Operating across 12nm to 180nm processes, these interfaces support data rates from 100 Mbps to an impressive 32.75 Gbps. Incorporating advanced features like programmable de-serialization widths and adaptive equalization, the Multi-Protocol SerDes ensures optimal signal integrity and performance even in demanding environments. The design includes jitter cleaner functions and employs low-latency optimized PMAs, delivering high precision and speed across various operational scenarios. This comprehensive adaptability ensures seamless integration into a wide range of applications from communications to high-performance computing. Supported by robust architectures, the SerDes enables enhanced efficiency and reliability, featuring low power consumption and reduced area overheads. With a commitment to customer satisfaction, Silicon Creations offers complete solutions through partnerships with leading controller vendors, cementing its products as high-value choices for modern electronic systems.
The Time-Triggered Protocol (TTP) stands out as a robust framework for ensuring synchronous communication in embedded control systems. Developed to meet stringent aerospace industry criteria, TTP offers a high degree of reliability with its fault-tolerant configuration, integral to maintaining synchrony across various systems. This technology excels in environments where timing precision and data integrity are critical, facilitating accurate information exchange across diverse subsystems. TTTech’s TTP implementation adheres to the SAE AS6003 standard, making it a trusted component among industry leaders. As part of its wide-ranging applications, this protocol enhances system communication within commercial avionic solutions, providing dependable real-time data handling that ensures system stability. Beyond aviation, TTP's applications can also extend into the energy sector, demonstrating its versatility and robustness. Characterized by its deterministic nature, TTP provides a framework where every operation is scheduled, leading to predictable data flow without unscheduled interruptions. Its suitability for field-programmable gate arrays (FPGAs) allows for easy adaptation into existing infrastructures, making it a versatile tool for companies aiming to upgrade their communication systems without a complete overhaul. For engineers and developers, TTP provides a dependable foundation that streamlines the integration process while safeguarding communication integrity.
The Chipchain C100 is a pioneering solution in IoT applications, providing a highly integrated single-chip design that focuses on low power consumption without compromising performance. Its design incorporates a powerful 32-bit RISC-V CPU which can reach speeds up to 1.5GHz. This processing power ensures efficient and capable computing for diverse IoT applications. This chip stands out with its comprehensive integrated features including embedded RAM and ROM, making it efficient in both processing and computing tasks. Additionally, the C100 comes with integrated Wi-Fi and multiple interfaces for transmission, broadening its application potential significantly. Other notable features of the C100 include an ADC, LDO, and a temperature sensor, enabling it to handle a wide array of IoT tasks more seamlessly. With considerations for security and stability, the Chipchain C100 facilitates easier and faster development in IoT applications, proving itself as a versatile component in smart devices like security systems, home automation products, and wearable technology.
MIPI I3C Controller IP Core is fully compliant with the latest I3C specification and delivers high bandwidth and scalability for integration of multiple sensors into mobile, automotive and IoT system-on-chips (SoCs). The MIPI I3C Controller supports in-band interrupts within the 2-wire interface provides significantly lower pin count, simplifying board design and reducing power and cost of the system. The MIPI I3C Controller IP is fully backward compatible with I2C, allowing designers to future proof their design, and the I3C controller IP operating modes enable systems with several ICs to efficiently connect to all sensors on a single I3C bus. The standard-based ARM® AMBA® Advanced High Performance Bus (AHB) connects the IP to the rest of the SoC offering easy IP integration. MIPI I3C Controller IP is designed to easily integrate into any SoC offering lowest gate count and quickly fit into any Chip development flow.
The THOR platform is a versatile tool for developing application-specific NFC sensor and data logging solutions. It incorporates silicon-proven IP blocks, creating a comprehensive ASIC platform suitable for rigorous monitoring and continuous data logging applications across various industries. THOR is designed for accelerated development timelines, leveraging low power and high-security features. Equipped with multi-protocol NFC capabilities and integrated temperature sensors, the THOR platform supports a wide range of external sensors, enhancing its adaptability to diverse monitoring needs. Its energy-efficient design allows operations via energy harvesting or battery power, ensuring sustainability in its applications. This platform finds particular utility in sectors demanding precise environmental monitoring and data management, such as logistics, pharmaceuticals, and industrial automation. The platform's capacity for AES/DES encrypted data logging ensures secure data handling, making it a reliable choice for sectors with stringent data protection needs.
The DisplayPort 1.4 core by Parretto offers a comprehensive solution for implementing DisplayPort functionalities in electronic designs. This IP supports both source (DPTX) and sink (DPRX) configurations, making it a versatile choice for any DisplayPort application. It operates at link rates of 1.62, 2.7, 5.4, and 8.1 Gbps, including embedded DisplayPort rates, and supports 1, 2, and 4 DP lanes. The IP core is built with adaptability in mind, featuring native video and AXI stream video interfaces. It supports both Single Stream Transport (SST) and Multi Stream Transport (MST) modes, accommodating diverse video streaming needs. With dual and quad pixels per clock transmission, it can deliver up to 10-bit video in various colorspaces such as RGB, YCbCr 4:4:4, YCbCr 4:2:2, and YCbCr 4:2:0. Additionally, the DisplayPort 1.4 IP core includes a secondary data packet interface for audio and metadata transport, enhancing multimedia performance. It comes with an accessible Video Toolbox that includes a timing generator, test pattern generator, and video clock recovery feature. Parretto provides full source code access, ensuring customizable integration and increased product reliability.
GNSS Sensor Ltd offers the GNSS VHDL Library, a powerful suite designed to support the integration of GNSS capabilities into FPGA and ASIC products. The library encompasses a range of components, including configurable GNSS engines, Viterbi decoders, RF front-end control modules, and a self-test module, providing a comprehensive toolkit for developers. This library is engineered to be highly flexible and adaptable, supporting a wide range of satellite systems such as GPS, GLONASS, and Galileo, across various configurations. Its architecture aims to ensure independence from specific CPU platforms, allowing for easy adoption across different systems. The GNSS VHDL Library is instrumental in developing cost-effective and simplified system-on-chip solutions, with capabilities to support extensive configurations and frequency bandwidths. It facilitates rapid prototyping and efficient verification processes, crucial for deploying reliable GNSS-enabled devices.
Overview: The MIPI CSI-2 (Camera Serial Interface) Transmitter IP establishes an interface between a peripheral device (camera) and host processor (application engine) for mobile applications. It offers the mobile industry a standard, robust, scalable, low-power, high-speed, and cost-effective interface that caters to a wide range of imaging solutions for mobile devices. Key Features: Compliance with MIPI-CSI-2 version 3.0 Compliance with C-PHY 2.0 for MIPI CSI-2 Version 3.0 Compliance with D-PHY 2.5 for MIPI CSI-2 Version 3.0 Compatibility with I2C and I3C (SDR, DDR) for CCI interface Pixel to Byte conversion support from Application layer to LLP layer Continuous clock behavior in clock lane for D-PHY physical layer De-skew sequence pattern in Data Lane Module Lane Distribution Function for distributing packet bytes across N-Lanes Sync word insertion through PPI command in C-PHY physical layer Insertion of Filler bytes in LLP layer for packet footer alignment Setting specific bits in packet header Defining frame blanking period Seed selection in scrambler and de-scrambler by Sync word Support for C-PHY/D-PHY/A-PHY/M-PHY with one PHY layer configuration Target Applications: Imaging Surveillance Gaming Sensor devices Internet of Things (IoT) Wearable devices Virtual Reality Augmented Reality Automotive Systems
Overview: The Power Management IC (PMIC) is specifically designed for DDR5 RDIMM, DDR5 LRDIMM, and DDR5 NVDIMM applications. It includes switching and LDO regulators to efficiently manage power distribution. The PMIC utilizes a MIPI-I3C Interface to select appropriate power settings for various application environments and is capable of operating at speeds up to 12.5MHz. Key Features: Maximum Operating speed of 12.5MHz Flexible Open-Drain IO (I2C) and Push-Pull (I3C) IO Support Multi-Time Programmable Non-Volatile Memory Interface Programmable and DIMM-specific registers for customization Error log registers for tracking Packet Error Check (PEC) and Parity Error Check functions Bus Reset function Support I3C Basic mode In-Band Interrupt (IBI) support Write, read, and default read operations in I2C mode Error handling for PEC, Parity errors, and CCC errors I3C Basic Common Command Codes (CCC) support Applications: DDR5 DIMM Application Environment DDR5 NVDIMM Application Environment Automotive Devices Memory Devices Power Management Devices Defense/Aerospace/Customer Electronics
The Hyperspectral Imaging System developed by Imec is a revolutionary tool for capturing and analyzing light across a wide range of wavelengths. This system is particularly valuable for applications requiring detailed spectral analysis, such as agricultural inspection, environmental monitoring, and medical diagnostics. By capturing hundreds of narrow spectral bands, the system provides a comprehensive spectral profile of the subject, enabling precise identification of materials and substances. What sets Imec's Hyperspectral Imaging System apart is its ability to integrate seamlessly into existing devices, allowing for versatile use across various industries. The compact and efficient design ensures that it can be deployed in field conditions, offering real-time analysis capabilities that are crucial for immediate decision-making processes. The Hyperspectral Imaging System is designed with cutting-edge CMOS technology, ensuring high sensitivity and accuracy. This integration with CMOS technology not only enhances the performance but also ensures that the system is cost-effective and accessible to a broader range of applications and markets. As hyperspectral imaging continues to evolve, Imec's system stands as a leader in the field, providing unmatched resolution and reliability.
The MXL-LVDS-MIPI-RX is a high-frequency, low-power, low-cost, source-synchronous, Physical Layer that supports the MIPI® Alliance Standard for D-PHY and compatible with the TIA/EIA-644 LVDS standard. (Learn more about Mixel’s MIPI ecosystem at Mixel MIPI Central which gives you access to Mixel’s best of class MIPI ecosystem supply chain partners.) The IP is configured as a MIPI slave and consists of 5 lanes: 1 Clock lane and 4 data lanes, which make it suitable for display serial interface applications (DSI). The High-Speed signals have a low voltage swing, while Low-Power signals have large swing. High-Speed functions are used for High-Speed Data traffic while low power functions are mostly used for control.
SkyeChip's MIPI D-PHY is a fully integrated hard macro solution compliant with the MIPI D-PHY v2.5 specification, intended for high-speed, low-power connectivity. It operates at up to 1.5 Gbps per lane, with options to upgrade to 2.5 Gbps, allowing for high-speed data transfer essential for efficient peripheral communication. The PHY solution comes with lane control and interface logic fully integrated, facilitating easy implementation in a variety of electronic applications. It features low-power escape modes and ultra-low power state modes, crucial for reducing energy consumption without compromising performance. The D-PHY architecture is versatile, supporting a plethora of connectivity standards and providing robust signal integrity. This makes it particularly beneficial for applications requiring reliable data transmission at high speeds, such as mobile devices and multimedia systems.
Dyumnin's RISCV SoC is a versatile platform centered around a 64-bit quad-core server-class RISCV CPU, offering extensive subsystems, including AI/ML, automotive, multimedia, memory, cryptographic, and communication systems. This test chip can be reviewed in an FPGA format, ensuring adaptability and extensive testing possibilities. The AI/ML subsystem is particularly noteworthy due to its custom CPU configuration paired with a tensor flow unit, accelerating AI operations significantly. This adaptability lends itself to innovations in artificial intelligence, setting it apart in the competitive landscape of processors. Additionally, the automotive subsystem caters robustly to the needs of the automotive sector with CAN, CAN-FD, and SafeSPI IPs, all designed to enhance systems connectivity within vehicles. Moreover, the multimedia subsystem boasts a complete range of IPs to support HDMI, Display Port, MIPI, and more, facilitating rich audio and visual experiences across devices.
The MXL-LVDS-DPHY-DSI-TX is a combo PHY that consists of a high-frequency low-power, low-cost, source-synchronous, Physical Layer supporting the MIPI® Alliance Standard for D-PHY and a high performance 4-channel LVDS Serializer implemented using digital CMOS technology. (Learn more about Mixel’s MIPI ecosystem at Mixel MIPI Central which gives you access to Mixel’s best of class MIPI ecosystem supply chain partners.) In LVDS mode, both the serial and parallel data are organized into 4 channels. The parallel data is 7 bits wide per channel. The input clock is 25MHz to 150MHz. The serializer is highly integrated and requires no external components. The circuit is designed in a modular fashion and desensitized to process variations. This facilitates process migration, and results in a robust design.
Silicon Creations' Bi-Directional LVDS Interfaces are engineered to offer high-speed data transmission with exceptional signal integrity. These interfaces are designed to complement FPGA-to-ASIC conversions and include broad compatibility with industry standards like FPD-Link and Camera-Link. Operating efficiently over processes from 90nm to 12nm, the LVDS interfaces achieve data rates exceeding 3Gbps using advanced phase alignment techniques. A standout feature of this IP is its capability to handle independent LVCMOS input and output functions while maintaining high compatibility with TIA/EIA644A standards. The bi-directional nature allows for seamless data flow in chip-to-chip communications, essential for modern integrated circuits requiring high data throughput. The design is further refined with trimmable on-die termination, enhancing signal integrity during operations. The LVDS interfaces are versatile and highly programmable, meeting bespoke application needs with ease. The interfaces ensure robust error rate performance across varying phase selections, making them ideal for video data applications, controllers, and other high-speed data interfaces where reliability and performance are paramount.
The BlueLynx Chiplet Interconnect is a sophisticated die-to-die interconnect solution that offers industry-leading performance and flexibility for both advanced and conventional packaging applications. As an adaptable subsystem, BlueLynx supports the integration of Universal Chiplet Interconnect Express (UCIe) as well as Bunch of Wires (BoW) standards, facilitating high bandwidth capabilities essential for contemporary chip designs.\n\nBlueLynx IP emphasizes seamless connectivity to on-die buses and network-on-chip (NoCs) using standards such as AMBA, AXI, and ACE among others, thereby accelerating the design process from system-on-chip (SoC) architectures to chiplet-based designs. This innovative approach not only allows for faster deployment but also mitigates development risks through a predictable and silicon-friendly design process with comprehensive support for rapid first-pass silicon success.\n\nWith BlueLynx, designers can take advantage of a highly optimized performance per watt, offering customizable configurations tailored to specific application needs across various markets like AI, high-performance computing, and mobile technologies. The IP is crafted to deliver outstanding bandwidth density and energy efficiency, bridging the requirements of advanced nodal technologies with compatibility across several foundries, ensuring extensive applicability and cost-effectiveness for diverse semiconductor solutions.
The MXL-SR-LVDS is a high performance 4-channel LVDS Serializer implemented using digital CMOS technology. Both the serial and parallel data are organized into four channels. The parallel data width is programmable, and the input clock is 25MHz to 165MHz. The Serializer is highly integrated and requires no external components. It employs optional pre-emphasis to enable transmission over a longer distance while achieving low BER. The circuit is designed in a modular fashion and desensitized to process variations. This facilitates process migration, and results in a robust design.
In the domain of smartphone applications, ActLight's Dynamic PhotoDetector (DPD) technology offers transformative capabilities for light sensing. Its advanced 3D Time-of-Flight (ToF) sensor capabilities enhance proximity and ambient light sensing, optimizing user experience by adjusting screen brightness and detecting object proximity with precision. This low-voltage technology ensures smartphones are not only feature-rich but also energy-efficient. The DPD's compact design integrates easily into smartphones, enabling high-quality imaging and sensor functionalities with minimal impact on device power consumption.
Matterhorn USB4 Retimer stands as an advanced engineering marvel, redefining the data transfer potential of USB4 technologies. This retimer allows for optimized data transfer rates, pushing the boundaries set by new-gen USB4 specifications. As technology rapidly evolves, the Matterhorn positions itself as a versatile component, capable of enhancing everyday consumer laptops and devices into high-performance units fit for gaming. Key to its operation is Matterhorn's ability to manage power effectively, maintaining low active power consumption and reducing the bill of materials cost. It achieves full USB4 compliance, ensuring devices can achieve top speeds while retaining backward compatibility with older USB standards like USB 3.2. This ensures it meets the diverse demands of end-users, enhancing the performance of a wide array of peripherals. Matterhorn's design is compact, maximizing maneuverability in system assembly with packages up to 50% smaller than competing products. As a plug-and-play solution, it requires minimal tuning, offering seamless integration into systems that demand high-speed data transactions. The embedded diagnostics tools further add to its usability, providing real-time insights into the retimer's performance and health, making it a top choice for achieving high data integrity in complex designs.
Silicon Library's MIPI interfaces provide crucial connectivity solutions for mobile and embedded device ecosystems. These interfaces are designed to accommodate the rigorous demands of multimedia data transfer, supporting a wide array of devices from smartphones to advanced automotive systems. Offering support for the MIPI DPHY-Tx and DPHY-Rx standards, these interfaces are crafted to facilitate efficient data transmission between processors and peripherals. Their low-power consumption and high-speed capabilities make them optimal for real-time video and image processing applications. The MIPI solutions by Silicon Library emphasize compatibility and adaptability, allowing seamless integration into existing system architectures. They ensure that devices can handle the bandwidth-heavy requirements of present-day applications while maintaining operational efficiency and low power usage.
System IP from Ventana is designed to complement the high-performance Veyron CPU series, offering necessary support for creating custom and highly efficient computing platforms. These IP blocks are integral in ensuring seamless operation within complex computing structures, bridging innovative processor cores with system-wide functionalities. Engineered for flexibility, the System IP provides essential infrastructural capabilities such as memory management, interconnectivity, and peripheral support. These IPs are fully compatible with RISC-V standards, enabling easy integration and fostering an open, creative environment for system architects. They are pivotal in optimizing the performance of bespoke systems, crafted to handle specific operational demands. The inclusion of System IP in a computing setup enhances stability, performance, and capacity across diverse applications. It empowers engineers to create solutions that are not only robust but also scalable, adhering to future-ready architecture principles. With System IP, Ventana continues to support progressive technological advancement, providing the foundational blocks required for cutting-edge technological ecosystems.
The MIPITM SVRPlus2500 provides an efficient solution for high-speed 4-lane video reception. It's compliant with CSI2 rev 2.0 and DPHY rev 1.2 standards, designed to facilitate easy timing closure with a low clock rating. This receiver supports PRBS, boasts calibration capabilities, and offers a versatile output of 4/8/16 pixels per clock. It features 16 virtual channels and 1:16 input deserializers per lane, handling data rates up to 10Gbps, making it ideal for complex video processing tasks.
The MXL-DS-LVDS is a high performance 4-channel LVDS Deserializer implemented using digital CMOS technology. Both the serial and parallel data are organized into four channels. The parallel data can be 7 or 10 bits wide per channel. The input clock is 25MHz to 165MHz. The De-serializer is highly integrated and requires no external components. Great care was taken to insure matching between the Data and Clock channels to maximize the deserializer margin. The circuit is designed in a modular fashion and desensitized to process variations. This facilitates process migration, and results in a robust design.
The Camera PHY Interface tailored for advanced semiconductor processes is integral for optimizing high-speed data transmission between image sensors and processors. Specialized to accommodate the latest advancements in process technology, this interface IP ensures superior performance while maintaining minimal power consumption and enhanced data integrity. By leveraging cutting-edge technology, it is engineered to handle multiple data lanes simultaneously, providing flexibility and adaptability across various applications in the visual data industry. This interface finds its utility in high-definition imaging solutions, contributing significantly to industries such as automotive, consumer electronics, medical imaging, and surveillance systems. Its design is aimed at simplifying integration in complex systems while providing robust data throughput and decreasing electromagnetic interference to ensure unmitigated signal clarity. With compatibility extending to the sub-LVDS, MIPI D-PHY, and HiSPi standards, this Camera PHY Interface IP is adaptable for evolving interface technologies, ensuring that devices can benefit from advanced connectivity protocols without compromising on performance metrics. The adoption of this IP supports industry trends towards miniaturization and reduced device footprints, thus making it indispensable for modern imaging solutions.
Tower Semiconductor’s RF-SOI and RF-CMOS platforms are crucial for developing state-of-the-art wireless communication systems. These technologies offer enhanced performance for RF applications, featuring efficient power handling and reduced interference, which are critical for high-frequency wireless communication. RF-SOI technology provides isolation benefits that enhance overall RF performance by minimizing crosstalk and interference. Meanwhile, RF-CMOS backs this with lower power consumption and integration capability, pivotal for the stringent demands of modern wireless protocols. The versatility of these platforms allows their application in next-generation wireless technologies and infrastructure, supporting everything from consumer devices to telecommunications equipment. The collaboration of SOI and CMOS technologies in radio frequency align with industry trends towards miniaturization and energy efficiency in wireless communication devices.
The Satellite Navigation SoC Integration offering by GNSS Sensor Ltd is a comprehensive solution designed to integrate sophisticated satellite navigation capabilities into System-on-Chip (SoC) architectures. It utilizes GNSS Sensor's proprietary VHDL library, which includes modules like the configurable GNSS engine, Fast Search Engine for satellite systems, and more, optimized for maximum CPU independence and flexibility. This SoC integration supports various satellite navigation systems like GPS, Glonass, and Galileo, with efficient hardware designs that allow it to process signals across multiple frequency bands. The solution emphasizes reduced development costs and streamlining the navigation module integration process. Leveraging FPGA platforms, GNSS Sensor's solution integrates intricate RF front-end components, allowing for a robust and adaptable GNSS receiver development. The system-on-chip solution ensures high performance, with features like firmware stored on ROM blocks, obviating the need for external memory.
The I/O semiconductor solutions from Analog Bits are designed to interface with multiple systems, ensuring seamless signal transmission across a variety of applications. These solutions offer a comprehensive range of features, including differential signaling and CMOS compatibility, enabling optimal communication within integrated circuits. By providing robust I/O management, these solutions help maintain signal integrity and efficiency. Analog Bits' I/O IP is distinguished by its adaptability to various process nodes, making it highly versatile in applications ranging from consumer electronics to industrial automation systems. The technology supports robust data transfer and is tailored to meet the demands of modern high-performance computing environments where quick, reliable communication interfaces are crucial. The solutions align with the complex requirements of contemporary digital systems, facilitating superior performance and power management. With features designed to minimize electromagnetic interference and ensure high fidelity in signal transmission, the I/O IP from Analog Bits is a pivotal component in the deployment of advanced semiconductor technologies.
The MIPITM CSI2MUX-A1F is an innovative video multiplexor designed to manage and aggregate multiple video streams effortlessly. It supports CSI2 rev 1.3 and DPHY rev 1.2 standards, handling inputs from up to four CSI2 cameras and producing a single aggregated video output. With data rates of 4 x 1.5Gbps, it is optimal for applications requiring efficient video stream management and consolidation.
The MIPITM SVTPlus-8L-F is a cutting-edge serial video transmitter designed for FPGAs. This transmitter adheres to CSI2 rev 2.0 and DPHY rev 1.2, featuring 8 lanes and capable of handling data rates of up to 12Gbps. It's engineered for high-performance video applications, boasting robust processing capabilities. Its support for advanced transmission protocols ensures seamless integration and compatibility with a wide range of video systems.
The Universal High-Speed SERDES from 1G to 12.5G is a flexible interface solution for high-speed data transfer applications. This SERDES is engineered to handle a broad range of data rates, providing versatility across numerous high-performance digital systems. Its design accommodates multiple data protocol standards such as RapidIO, FC, and XAUI, allowing seamless integration across diverse technological ecosystems. One of the standout features of this SERDES is its parameterizable data width options, offering bit widths like 16-bit, 20-bit, 32-bit, and 40-bit. This adaptability ensures it can cater to specific data handling requirements, enhancing the efficiency of electronic systems. Its programmable front-end equalizers and adaptive receiver equalizers further its robustness in dealing with varying signal integrity challenges. The SERDES maintains functionality independent of crystal oscillators, eliminating the need for additional external components, which simplifies system design and reduces costs. It supports various packaging modes and channel configurations, underpinning its flexibility in diverse application scenarios.
The 1394b PHY IP Core provides a hardware foundation for high-speed IEEE-1394b data transmission, delivering critical support for physical-layer data processing. It integrates smoothly within existing data frameworks, supporting the standard PHY-Link interface. Essential for maintaining high-speed data integrity, it is designed for complex systems that require dependable and efficient data transfer, ensuring seamless implementation in demanding applications.
The High-Speed Interface Technology from VeriSyno is engineered to meet the evolving needs of modern semiconductor design. Built to facilitate rapid data transfer, this technology supports a wide array of protocols including USB, DDR, MIPI, HDMI, PCIe, SATA, and XAUI. By providing robust IP that can operate under 28-90nm process nodes, it ensures compatibility and flexibility for diverse applications. This interface technology is not only defined by its speed but also by its adaptability, offering IP customization and migration to serve advanced process needs. It enables seamless communication between high-performance chips, addressing various industrial and consumer demands. With focus on reliability and performance, the High-Speed Interface Technology helps manufacturers achieve desired speed and efficiency in their products, fostering advancements in electronic design and integrated circuit functionality. It lays the groundwork for powerful connectivity essential in today’s fast-paced tech landscape.
MIPI Solutions offered by PRSsemicon are designed to meet the most recent version specifications while ensuring backward compatibility with earlier standards. This comprehensive suite includes various MIPI modules such as CSI-2 and DSI transmitters and receivers for Combo C/DPHY, supporting versions from 1.0 through 3.0 and up to DSI-2 v2.0. Other components under MIPI Solutions include the UniPro, I3C, RFFE, Soundwire, BIF, and SPMI interfaces, all available in master and slave configurations. These modules offer robust and flexible support for a wide range of applications in industries like mobile, imaging, and more.
With an emphasis on performance, the MIPITM SVTPlus2500 is a robust 4-lane video transmitter adhering to CSI2 rev 2.0 and DPHY rev 1.2 standards. It facilitates timing closure with its low clock rating and supports PRBS for precise data management. The transmitter can handle 8/16 pixel inputs per clock and offers programmable timing parameters. Equipped with 16 virtual channels, this IP is engineered for high-speed video transmission.
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