All IPs > Security IP
Security IPs are an integral category within the semiconductor industry focusing on the protection of electronic data and hardware. As technological advancements continue to proliferate across critical sectors like finance, healthcare, and automotive, securing data and hardware has never been more paramount. Security IPs are designed to provide essential security features such as encryption, secure communications, and access control to safeguard sensitive information and devices from unauthorized access and cyber threats.
Within the Security IP category, you will find robust offerings that include both hardware and software-based solutions tailored to various security needs. Content Protection Software enables secure data transmission and protects digital content from piracy and unauthorized distribution. Cryptography Cores and Cryptography Software Libraries offer foundational tools for implementing strong encryption algorithms that are crucial for securing communications and data storage.
Embedded Security Modules are integrated within semiconductor devices to facilitate secure data processing and enhance trust in device operations by preventing code tampering and unauthorized hardware modification. Platform Security solutions encompass a broad range of protective measures designed to secure the entire hardware and software ecosystem, ensuring that devices are safe from potential vulnerabilities at every level.
Additionally, Security Protocol Accelerators and Security Subsystems act as dedicated processing units to efficiently handle complex security algorithms and protocols, enhancing the performance of security operations while reducing the burden on primary CPUs. With an unpredictable security landscape, leveraging a range of specialized Security IPs allows designers and engineers to build robust, secure, and reliable semiconductor solutions that can withstand evolving cyber threats.
Akida Neural Processor IP is a groundbreaking component offering a self-contained AI processing solution capable of locally executing AI/ML workloads without reliance on external systems. This IP's configurability allows it to be tailored to various applications, emphasizing space-efficient and power-conscious designs. Supporting both convolutional and fully-connected layers, along with multiple quantization formats, it addresses the data movement challenge inherent in AI, significantly curtailing power usage while maintaining high throughput rates. Akida is designed for deployment scalability, supporting as little as two nodes up to extensive networks where complex models can thrive.
The second generation of BrainChip's Akida platform expands upon its predecessor with enhanced features for even greater performance, efficiency, and accuracy in AI applications. This platform leverages advanced 8-bit quantization and advanced neural network support, including temporal event-based neural nets and vision transformers. These advancements allow for significant reductions in model size and computational requirements, making the Akida 2nd Generation a formidable component for edge AI solutions. The platform effectively supports complex neural models necessary for a wide range of applications, from advanced vision tasks to real-time data processing, all while minimizing cloud interaction to protect data privacy.
Overview: Cybersecurity IPs offer a range of essential security features to protect your digital assets and sensitive information. From True Random Number Generators (TRNG) to advanced encryption algorithms like AES, DES, 3DES, and cryptographic hash functions like SHA, as well as RSA for secure key exchange and digital signatures, the IPs provide a comprehensive suite of tools to safeguard your data. Key Features: True Random Number Generator (TRNG): Generates unpredictable and unbiased random numbers for cryptographic applications. Advanced Encryption Standard (AES): Provides robust encryption with symmetric key algorithms for securing data. Data Encryption Standard (DES) and Triple DES (3DES): Implement legacy encryption algorithms for data protection. Hash Functions: Includes secure cryptographic hash functions like SHA (Secure Hash Algorithm) for data integrity verification. RSA: Enables secure key exchange, encryption, and digital signatures for secure communication. These cybersecurity IPs are designed to meet the stringent security requirements of modern applications, ensuring the confidentiality, integrity, and authenticity of your data.
Overview: The Secure Enclave IPs are Common Criteria (CC) EAL5+PP0084/PP0117 and EAL5+PP0117 certification-ready Secure Enclaves, respectively. They are available as hard macros for seamless integration into SoCs. These Secure Enclave IPs provide the highest level of security for an SoC, incorporating patented design techniques and countermeasures against side-channel and perturbation attacks to ensure robust security while minimizing power consumption. Key Features: Cryptographic Hardware Accelerators: Efficiently support standard cryptography and security operations to increase throughput while adhering to power constraints and security requirements. BootROM and Secondary Boot Loader: Manage the certified life cycle of the Secure Enclave, enforcing and assuring security from manufacturing to deployment. Proprietary IP: Based on proprietary IP that is free of 3rd party rights and royalties. Benefits: The Secure Enclave IPs offer robust security measures, efficient cryptographic support, and secure life cycle management, making them ideal for applications that require the highest levels of security and reliability. Applications: The Secure Enclave IP is versatile and suitable for a wide range of applications, including but not limited to: Secured and Certified iSIM & iUICC EMVco Payment Hardware Cryptocurrency Wallets FIDO2 Web Authentication V2X HSM Protocols Smart Car Access Secured Boot Secure OTA Firmware Updates Secure Debug Any design requiring a Secure Enclave, Secure Element, or Hardware Root of Trust protected against side-channel and perturbation fault attacks. Compliance and Support: The Secure Enclave is compliant with and ready for CC EAL5+ and EMVCo certification. It is delivered with an SDK and pre-certified CryptoLibrary and secure Boot Loader for seamless integration and enhanced security.
Overview: The Secure Boot IP is a turnkey solution that provides a secure boot facility for an SoC. It implements the Post Quantum secure Leighton-Micali Signature (LMS) as specified in NIST SP800-208. The Secure Boot IP operates as a master or slave peripheral to an Application Processor, serving as a secure enclave that securely stores keys to ensure their integrity and the integrity of the firmware authentication process. Features: Post Quantum Secure LMS Signature: Utilizes a robust Post-Quantum secure algorithm for enhanced security. Firmware Updates: Supports up to 32 thousand firmware updates with a minimal signature size of typically less than 5KBytes. SESIP Level 3 Pre-Certification: Pre-certified to SESIP Level 3 for added security assurance. RTL Delivery: Delivered as RTL for ease of integration into SoC designs. Proprietary IP: Based on proprietary IP with no 3rd party rights or royalties. Operation: The Secure Boot IP operates as a master, managing the boot process of the Application Processor to ensure that it only boots from and executes validated and authenticated firmware. The Secure Boot IP also functions as a slave peripheral, where the Application Processor requests validation of the firmware as part of its boot process, eliminating the need for managing keys and simplifying the boot process. Applications: The Secure Boot IP is versatile and suitable for a wide range of applications, including but not limited to: Wearables Smart/Connected Devices Metrology Entertainment Applications Networking Equipment Consumer Appliances Automotive Industrial Control Systems Security Systems Any SoC application that requires executing authenticated firmware in a simple but secure manner.
Focused on the advancement of autonomous mobility, KPIT's ADAS and Autonomous Driving solutions aim to address the multifaceted challenges that come with higher levels of vehicle autonomy. Safety remains the top priority, necessitating comprehensive testing and robust security protocols to ensure consumer trust. Current development practices often miss crucial corner cases by concentrating largely on standard conditions. KPIT tackles these issues through a holistic, multi-layered approach. Their solutions integrate state-of-the-art AI-driven decision-making systems that extend beyond basic perception, enhancing system reliability and intelligence. They've established robust simulation environments to ensure feature development covers all conceivable driving scenarios, contributing to the broader adoption of Level 3 and up autonomous systems. The company also offers extensive validation frameworks combining various testing methodologies to continually refine and prove their systems. This ensures each autonomous feature is thoroughly vetted before deployment, firmly positioning KPIT as a trusted partner for automakers aiming to bring safe, reliable, and highly autonomous vehicles to market.
The AHB-Lite APB4 Bridge from Roa Logic is a versatile interconnect solution, designed to serve as a bridge between the AMBA 3 AHB-Lite v1.0 and the APB v2.0 (APB4) bus protocols. This soft IP core facilitates the connection of multiple APB4 peripherals through a single bridge, optimizing system design by reducing complexity and cost. The core is fully parameterized, supporting various APB4 address and data widths, and offers the capability to handle burst transfers automatically. It also supports different clock domains per interface, efficiently managing cross-domain timing with ease. This flexibility in design makes it suitable for a wide range of applications, especially those requiring efficient, cost-effective interconnect solutions. The AHB-Lite APB4 Bridge is ideal for use in applications requiring high integration and efficient communication between high-speed processors and peripheral devices. Source code and detailed documentation are readily available for download from Roa Logic's GitHub repository, ensuring developers have all necessary resources for seamless integration.
The RV12 is a versatile, single-issue RISC-V compliant processor core, designed for the embedded market. With compliance to both RV32I and RV64I specifications, this core is part of Roa Logic's 32/64-bit CPU offerings. Featuring a Harvard architecture, it efficiently handles simultaneous instruction and data memory operations. The architecture is enhanced with an optimizing folded 4-stage pipeline, maximizing the overlap of execution with memory access to reduce latency and boost throughput. Flexibility is a cornerstone of the RV12 processor, offering numerous configuration options to tailor performance and efficiency. Users can select optional components such as branch prediction units, instruction and data caches, and a debug unit. This configurability allows designers to balance trade-offs between speed, power consumption, and area, optimizing the core for specific applications. The processor core supports a variety of standard software tools and comes with a full suite of development resources, including support for the Eclipse Integrated Development Environment (IDE) and GNU toolchain. The RV12 design emphasizes a small silicon footprint and power-efficient operation, making it ideal for a wide range of embedded applications.
The AHB-Lite Multilayer Switch by Roa Logic is engineered to provide a high-performance, low-latency interconnect fabric for systems employing numerous AHB-Lite bus masters and slaves. This IP core enables configurations that support virtually unlimited bus connections, facilitated by slave-side arbitration for each slave port, thereby eliminating the need for individual bus masters to implement arbitration logic. A standout feature of this switch is its use of priority and round-robin based arbitration methods to efficiently manage multiple bus requests. Typically achieving arbitration within a single clock cycle, this design ensures minimal delay in data transfer across the network, promoting seamless communication in complex systems. With a fully parameterized architecture, it allows for the customization of bus interfaces to meet specific design needs, ensuring compatibility and optimal performance across varied configurations. Complete source code and comprehensive documentation are made available through Roa Logic’s GitHub repository, providing developers with the resources needed for successful integration and deployment.
BrainChip's Akida IP is an innovative neuromorphic processor that emulates the human brain's functionalities to analyze essential sensor inputs at the acquisition point. By maintaining AI/ML processes on-chip, Akida IP minimizes cloud dependency, reducing latency and enhancing data privacy. The scalable architecture supports up to 256 nodes interconnected over a mesh network, each node equipped with configurable Neural Network Layer Engines (NPEs). This event-based processor leverages data sparsity to decrease operational requirements significantly, which in turn improves performance and energy efficiency. With robust customization and the ability to perform on-chip learning, Akida IP adeptly supports a wide range of edge AI applications while maintaining a small silicon footprint.
This ultra-compact and high-speed H.264 core is engineered for FPGA platforms, boasting industry-leading size and performance. Capable of providing 1080p60 H.264 Baseline support, it accommodates various customization needs, including different pixel depths and resolutions. The core is particularly noted for its minimal latency of less than 1ms at 1080p30, a significant advantage over competitors. Its flexibility allows integration with a range of FPGA systems, ensuring efficient compression without compromising on speed or size. In one versatile package, users have access to a comprehensive set of encoding features including variable and fixed bit-rate options. The core facilitates simultaneous processing of multiple video streams, adapting to various compression ratios and frame types (I and P frames). Its support for advanced video input formats and compliance with ITAR guidelines make it a robust choice for both military and civilian applications. Moreover, the availability of low-cost evaluation licenses invites experimentation and custom adaptation, promoting broad application and ease of integration in diverse projects. These cores are especially optimized for low power consumption, drawing minimal resources in contrast to other market offerings due to their efficient FPGA design architecture. They include a suite of enhanced features such as an AXI wrapper for simple system integration and significantly reduced Block RAM requirements. Embedded systems benefit from its synchronous design and wide support for auxiliary functions like simultaneous stream encoding, making it a versatile addition to complex signal processing environments.
Up to 1M KeyEnc/sec with improved power efficiency PQPerform-Lattice is a powerful hardware-based product designed for high throughput, high-performance, and high speed. It adds post-quantum cryptography for applications that typically handle a large number of transactions, such as high-capacity network hardware applications and secure key management HSMs. Optimizable for secure boot, as well as other use-cases, PQPerform-Lattice supports FIPS 204 ML-DSA for quantum-secure digital signature verification, as well as FIPS 203 ML-KEM for quantum key exchange. PQPerform-Lattice supports AXI4, PCIe, and is deployable in multiple instances, making it a powerful solution for existing systems and infrastructure requirements.
Polar ID offers an advanced solution for secure facial recognition in smartphones. This system harnesses the revolutionary capabilities of meta-optics to capture a unique polarization signature from human faces, adding a distinct layer of security against sophisticated spoofing methods like 3D masks. With its compact design, Polar ID replaces the need for bulky optical modules and costly time-of-flight sensors, making it a cost-effective alternative for facial authentication. The Polar ID system operates efficiently under diverse lighting conditions, ensuring reliable performance both in bright sunlight and in total darkness. This adaptability is complemented by the system’s high-resolution capability, surpassing that of traditional facial recognition technologies, allowing it to function seamlessly even when users are wearing face coverings, such as glasses or masks. By incorporating this high level of precision and security, Polar ID provides an unprecedented user experience in biometric solutions. As an integrated solution, Polar ID leverages state-of-the-art polarization imaging, combined with near-infrared technology operating at 940nm, which provides robust and secure face unlock functionality for an increasing range of mobile devices. This innovation delivers enhanced digital security and convenience, significantly reducing complexity and integration costs for manufacturers, while setting a new standard for biometric authentication in smartphones and beyond.
The NaviSoC by ChipCraft is a highly integrated GNSS system-on-chip (SoC) designed to bring navigation technologies to a single die. Combining a GNSS receiver with an application processor, the NaviSoC delivers unmatched precision in a dependable, scalable, and cost-effective package. Designed for minimal energy consumption, it caters to cutting-edge applications in location-based services (LBS), the Internet of Things (IoT), and autonomous systems like UAVs and drones. This innovative product facilitates a wide range of customizations, adaptable to varied market needs. Whether the application involves precise lane-level navigation or asset tracking and management, the NaviSoC meets and exceeds market expectations by offering enhanced security and reliability, essential for synchronization and smart agricultural processes. Its compact design, which maintains high efficiency and flexibility, ensures that clients can tailor their systems to exact specifications without compromise. NaviSoC stands as a testament to ChipCraft's pioneering approach to GNSS technologies.
The Platform-Level Interrupt Controller (PLIC) from Roa Logic is a highly adaptable interrupt management system, crafted in accordance with the RISC-V Privileged v1.10 specification. This core seamlessly integrates with AHB-Lite, supporting a wide range of interrupt sources and targets. It provides a robust foundation for managing complex interrupt architectures, essential in modern embedded systems. The PLIC core is meticulously designed for configurability, offering custom parameters for address and data widths, as well as the capacity to set unique priority levels per interrupt source. It includes features like programmable priority thresholds and an interrupt pending queue, allowing for tailored performance to meet the specific needs of an application. This controller ensures efficient handling of interrupt masking using a priority threshold system, further enabling sophisticated event management in multi-tasking environments. With comprehensive documentation and source code available through Roa Logic's GitHub, the PLIC is an accessible solution for developers looking to integrate reliable interrupt control in their RISC-V based systems.
PUFrt stands as a bastion of semiconductor security, serving as a Hardware Root of Trust (HRoT) with unparalleled credibility. Its architecture is designed to generate and store hardware root keys securely within the chip, utilizing Physically Unclonable Functions (PUF) and a true random number generator (TRNG). These features ensure that cryptographic operations are fortified with a unique and unclonable identity, mitigating risks of physical tampering and creating a robust defense against reverse engineering.<br><br>Integral to its design is the secure OTP (One-Time Programmable) memory, which stores sensitive keys and data, adding a layer of protection that has been validated through rigorous security certifications. The PUFrt's anti-tamper technology guards against unauthorized access, ensuring the integrity of both hardware and software environments. Moreover, its design facilitates easy integration with various system architectures, expanding its applications beyond traditional security implementations.<br><br>Applications of PUFrt span from IoT devices to sophisticated computing systems, where its role as a secure entry point into connected ecosystems is crucial. By embedding a secure foundation, PUFrt not only strengthens semiconductor reliability but also enhances performance efficiency. This holistic approach to security makes it a linchpin in modern semiconductor design, supporting each stage of the device lifecycle with comprehensive, hardware-anchored security protocols.
The HDCP Encryption-Decryption Engine developed by Trilinear Technologies is designed to protect digital audio and video content from unauthorized access during transmission. It aligns with the HDCP 2.2 standard, ensuring that all data exchanged between a display source and receiver remains secure and resistant to interception. This solution is vital for industries where content protection is paramount, such as in premium consumer electronics, professional audiovisual setups, and sensitive government or military communication channels. This engine supports the authentication protocols necessary for protected transactions over DisplayPort interfaces, using sophisticated AUX channels to seal data transfer securely. It is engineered to reduce the processing load by offloading encryption tasks from the system processor, thereby enhancing the overall system performance while maintaining robust security. Capable of integrating into a range of devices from set-top boxes to large multimedia systems, the HDCP Encryption-Decryption Engine offers developers a trustworthy method to shield content from piracy and unauthorized dissemination. Its implementation ensures that content providers can operate freely with the assurance that their digital rights are upheld across all endpoints.
Secure OTP offers a groundbreaking approach to data protection in semiconductor chips, employing an anti-fuse OTP memory to safeguard sensitive information. By combining hardware macros with digital RTL, it meticulously protects data at rest, in transit, or in use, making it a cornerstone of modern chip design. Its architecture supports various integrations across IC applications, providing robust and adaptable security solutions tailored for diverse markets.<br><br>This technology elevates the standard OTP solutions by incorporating advanced hardware encryption mechanisms and tamperproof designs. Secure OTP's seamless integration into multiple systems underscores its versatility, catering to demands across sectors such as automotive, industrial, and consumer electronics. Users benefit from secure key management and enhanced data integrity, mitigating the potential risks of traditional storage vulnerabilities.<br><br>The design philosophy behind Secure OTP centers on preventing data leakage, particularly for IoT devices that are prone to attacks. As devices face the growing menace of cyber threats, Secure OTP scales to meet these challenges head-on, providing fortified data storage solutions that are resistant to physical attacks and environmental variations. With the rising importance of secure encrypted storage, Secure OTP's role is vital in maintaining the integrity and confidentiality of critical chip information.
The Dynamic Neural Accelerator (DNA) II offers a groundbreaking approach to enhancing edge AI performance. This neural network architecture core stands out due to its runtime reconfigurable architecture that allows for efficient interconnections between compute components. DNA II supports both convolutional and transformer network applications, accommodating an extensive array of edge AI functions. By leveraging scalable performance, it makes itself a valuable asset in the development of systems-on-chip (SoC) solutions. DNA II is spearheaded by EdgeCortix's patented data path architecture, focusing on technical optimization to maximize available computing resources. This architecture uniquely allows DNA II to maintain low power consumption while flexibly adapting to various task demands across diverse AI models. Its higher utilization rates and faster processing set it apart from traditional IP core solutions, addressing industry demands for more efficient and effective AI processing. In concert with the MERA software stack, DNA II optimally sequences computation tasks and resource distribution, further refining efficiency and effectiveness in processing neural networks. This integration of hardware and software not only aids in reducing on-chip memory bandwidth usage but also enhances the parallel processing ability of the system, catering to the intricate needs of modern AI computing environments.
DolphinWare IPs is a versatile portfolio of intellectual property solutions that enable efficient SoC design. This collection includes various control logic components such as FIFO, arbiter, and arithmetic components like math operators and converters. In addition, the logic components span counters, registers, and multiplexers, providing essential functionalities for diverse industrial applications. The IPs in this lineup are meticulously designed to ensure data integrity, supported by robust verification IPs for AXI4, APB, SD4.0, and more. This comprehensive suite meets the stringent demands of modern electronic designs, facilitating seamless integration into existing design paradigms. Beyond their broad functionality, DolphinWare’s offerings are fundamental to applications requiring specific control logic and data integrity solutions, making them indispensable for enterprises looking to modernize or expand their product offerings while ensuring compliance with industry standards.
The eSi-Crypto suite offers a comprehensive set of encryption and authentication solutions, optimized for ASIC and FPGA applications with low resource demands and high throughput. It features essential components such as a True Random Number Generator (TRNG), compliant with NIST 800-22, available as a hard macro. The IP includes a variety of encryption algorithms including CRYSTALS Kyber, CRYSTALS Dilithium, ECC/ECDSA, RSA, AES, and SHA1-SHA3. These algorithms are designed for robust security and can be integrated as standalone cores or with AMBA APB/AHB or AXI bus interfaces, serving diverse applications like secure communications and financial transactions.
aiWare stands out as a premier hardware IP for high-performance neural processing, tailored for complex automotive AI applications. By offering exceptional efficiency and scalability, aiWare empowers automotive systems to harness the full power of neural networks across a wide variety of functions, from Advanced Driver Assistance Systems (ADAS) to fully autonomous driving platforms. It boasts an innovative architecture optimized for both performance and energy efficiency, making it capable of handling the rigorous demands of next-generation AI workloads. The aiWare hardware features an NPU designed to achieve up to 256 Effective Tera Operations Per Second (TOPS), delivering high performance at significantly lower power. This is made possible through a thoughtfully engineered dataflow and memory architecture that minimizes the need for external memory bandwidth, thus enhancing processing speed and reducing energy consumption. The design ensures that aiWare can operate efficiently across a broad range of conditions, maintaining its edge in both small and large-scale applications. A key advantage of aiWare is its compatibility with aiMotive's aiDrive software, facilitating seamless integration and optimizing neural network configurations for automotive production environments. aiWare's development emphasizes strong support for AI algorithms, ensuring robust performance in diverse applications, from edge processing in sensor nodes to high central computational capacity. This makes aiWare a critical component in deploying advanced, scalable automotive AI solutions, designed specifically to meet the safety and performance standards required in modern vehicles.
ZIA Stereo Vision by Digital Media Professionals Inc. revolutionizes three-dimensional image processing by delivering exceptional accuracy and performance. This stereo vision technology is particularly designed for use in autonomous systems and advanced robotics, where precise spatial understanding is crucial. It incorporates deep learning algorithms to provide robust 3D mapping and object recognition capabilities. The IP facilitates extensive depth perception and analyzed spatial data for applications in areas like automated surveillance and navigation. Its ability to create detailed 3D maps of environments assists machines in interpreting and interacting with their surroundings effectively. By applying sophisticated AI algorithms, it enhances the ability of devices to make intelligent decisions based on rich visual data inputs. Integration into existing systems is simplified due to its compatibility with a variety of platforms and configurations. By enabling seamless deployment in sectors demanding high reliability and accuracy, ZIA Stereo Vision stands as a core component in the ongoing evolution towards more autonomous and smart digital environments.
Highly-optimized PQC implementations, capable of running PQC in < 15kb RAM PQCryptoLib-Emebedded is a versatile, CAVP-compliant version of PQCryptoLib, PQShield’s CMVP-certified library of post-quantum cryptographic algorithms. With its design focused on ultra-small area efficiency, PQCryptoLib-Embedded has been specifically designed for embedded systems, microcontrollers and memory-constrained devices. It could be the first step towards a hardware solution for providing PQC integration to devices already in the field.
Secure Protocol Engines from Secure-IC are designed to enhance network and security processing in data centers by offloading heavy computational tasks. These engines feature some of the industry's fastest SSL/TLS handshaking capabilities, paired with ultra-high-performance MACsec and IPsec processing. By managing demanding network tasks, Secure Protocol Engines enable data centers to optimize resources and improve system performance significantly. As data transmission and sensitive information exchange become increasingly common, these engines provide crucial support in maintaining robust security measures against interception and unauthorized access. The Secure Protocol Engines are optimized to integrate seamlessly with existing infrastructures, ensuring minimized impact on overall system efficiency and maximizing throughput and security.
The Titanium Ti375 is a flagship FPGA product that balances high density and low power consumption, making it ideal for a range of applications requiring significant computational capabilities with energy efficiency. This FPGA includes Efinix's Quantum™ compute fabric, which provides advanced I/O interfaces including SerDes transceivers, LPDDR4 DRAM controllers, and MIPI D-PHY interfaces. These features make the Ti375 a versatile choice for system designers aiming to integrate complex interfaces in a compact footprint.\n\nThe Ti375 FPGA excels in areas such as edge computing and high-performance data processing, supporting a wide range of applications from industrial automation to consumer electronics. With its hardened RISC-V block, the Titanium Ti375 can handle demanding tasks without external processors, offering an on-chip solution that reduces both footprint and power usage. Furthermore, it includes capabilities like stream encryption and authentication, ensuring secure data processing in sensitive environments.\n\nDesigned with future-proofing in mind, the Ti375 supports integration into systems with rigorous longevity requirements. It aligns with Efinix's commitment to deliver reliable technology over extended product lifecycles, catering to industries that necessitate stability and long-term support. With a process node efficiently structured at 16nm, the Titanium Ti375 offers a compact size without compromising on performance, making it an excellent choice for ongoing innovations in embedded systems, communications, and power-sensitive applications.
802.11 LDPC from Wasiela represents a significant advancement in error correction technologies for wireless communication. Engineered to support high-throughput connections, this module allows dynamic adjustment with on-the-fly configuration between frames. The design achieves a well-balanced performance by fine-tuning the number of LDPC decoding iterations, offering a scalable trade-off between throughput and error correction strength. This module is tailored to meet the stringent specifications necessary for high performance in modern wireless networks. It excels at delivering reliable bit-error-rate and packet-error-rate metrics that align with current industry benchmarks. Wasiela’s 802.11 LDPC product underlines their innovation in pushing the boundaries of what forward error correction technologies can achieve, ensuring communications are both robust and efficient.
FIPS 140-3 CMVP compliant, CAVP PQC cryptographic library designed for PQ/T Hybrid PQCryptoLib is a general-purpose FIPS 140-3 CMVP and CAVP-certified cryptographic library. It’s been designed for a wide variety of applications and provides the latest NIST-standardized post-quantum and classical algorithms in a software environment. With a configurable, secure, and easy-to-use API, PQCryptoLib is optimized for crypto-agility, particularly when it comes to FIPS-compliant hybrid PQ/T solutions, and with crypto-agility in mind, it’s built to protect against the threat of ‘harvest-now-decrypt-later’ attacks. The aim of PQCryptoLib is to help organizations transition smoothly and securely to quantum resistance in a manageable, easy-to-integrate solution.
The Alcora V-by-One HS Daughter Card is tailored for high-speed digital interfacing, specifically aligning with FPGA development boards via FMC connectors. The card features 8 RX and 8 TX lanes, with the option to combine two FMC cards for a total of 16 lanes. This configuration supports video resolutions up to 4K at 120Hz or 8K at 30Hz, demonstrating its capability to handle large volumes of data efficiently. Designed to meet the demanding requirements of high-resolution and high-frame-rate applications, the Alcora card integrates dual clock generators to optimize signal clarity by synthesizing the transceiver reference clock and minimizing jitter. This characteristic is crucial in maintaining data integrity and ensuring smooth video performance, making the Alcora an optimal choice for flat panel display integration. Featuring flexible connectivity options, the Alcora card is available in both 51-pin and 41-pin header variants. This design ensures that it can provide a comprehensive interface to meet various technical challenges, advancing the capabilities of high-speed digital communications within FPGA systems.
The Flash Protection Series by PUFsecurity revolutionizes the way sensitive data is protected on semiconductor devices by extending the reach of the Hardware Root of Trust to flash memory. This series of IP solutions provides comprehensive protection for a range of memory types including embedded, NAND, and NOR flash solutions. It incorporates PUF-based technology to ensure secure encryption and decryption processes, crucial in safeguarding data integrity at every stage.<br><br>Each module within the Flash Protection Series serves a unique function; PUFef secures embedded flash by using a lite crypto engine, while PUFenc and PUFxip extend this protection to external NAND and NOR flash systems. These modules are designed to avert unauthorized access and leakage of critical data, making them essential components in securing the software and hardware ecosystems of SoCs.<br><br>These solutions allow chip manufacturers to implement robust fingerprinting mechanisms, enhancing the overall security capabilities of semiconductor devices. By facilitating execution-in-place and real-time decryption for flash memory, the Flash Protection Series empowers engineers with the tools needed to create advanced, secure semiconductor products. This provides manufacturers with the confidence that their products are protected against an array of cyber threats.
The HOTLink II IP Core is a highly sophisticated implementation of layer 2 hardware for High-Speed Interconnect (HSI) systems. It provides a comprehensive and robust platform for data communication, ensuring seamless integration into systems through an intuitive frame interface. The core is compatible with various operational rates, including full-rate, half-rate, and quarter-rate, as explicitly specified by the associated standard. Engineered for compatibility with F-18 interface requirements, the HOTLink II IP Core enhances system reliability and efficiency. It empowers engineers to achieve reliable high-speed data links necessary for modern defense and aerospace applications. This core is designed to operate under diverse conditions, providing resilient support for complex networking needs. The HOTLink II IP Core stands out with its ease of integration and operational flexibility, making it invaluable for enterprises looking to enhance high-speed data communication capabilities. With its robust design, it can handle intensive demand cycles, ensuring uninterrupted performance even in critical environments.
The Aeonic Integrated Droop Response System sets a new standard for droop management in sophisticated integrated circuits. With its innovative dual-focus on droop detection and mitigation coupled with fine-tuned DVFS capability, this turnkey solution ensures efficient power management for SoCs. The system's fast response time, extensive observability features, and configurability make it a critical component in silicon health management, easily integrating with leading analytic frameworks.
Securyzr iSSP is a versatile platform that aims to provide a comprehensive security lifecycle management solution. This embedded security service platform ensures that devices are protected from the chip level throughout their lifecycle. It features security operations like secure boot, firmware updates, and intrusion detection, all managed from the cloud, enabling secure deployment and management across fleets of devices. Its design caters to complex security challenges by offering a scalable, end-to-end solution for managing device security without manual intervention, known as zero-touch security services. The Securyzr iSSP is optimized to handle critical operations securely across different hardware and software environments, ensuring integrity and confidentiality.
ArrayNav represents a significant leap forward in navigation technology through the implementation of multiple antennas which greatly enhances GNSS performance. With its capability to recognize and eliminate multipath signals or those intended for jamming or spoofing, ArrayNav ensures a high degree of accuracy and reliability in diverse environments. Utilizing four antennas along with specialized firmware, ArrayNav can place null signals in the direction of unwanted interference, thus preserving the integrity of GNSS operations. This setup not only delivers a commendable 6-18dB gain in sensitivity but also ensures sub-meter accuracy and faster acquisition times when acquiring satellite data. ArrayNav is ideal for urban canyons and complex terrains where signal integrity is often compromised by reflections and multipath. As a patented solution from EtherWhere, it efficiently remedies poor GNSS performance issues associated with interference, making it an invaluable asset in high-reliability navigation systems. Moreover, the system provides substantial improvements in sensitivity, allowing for robust navigation not just in clear open skies but also in challenging urban landscapes. Through this additive capability, ArrayNav promotes enhanced vehicular ADAS applications, boosting overall system performance and achieving higher safety standards.
The SiFive Intelligence X280 processor is crafted for the demands of AI and ML within edge computing environments. It integrates high-performance scalar and vector computing capabilities, making it ideal for data-heavy AI tasks like management, object detection, and speech processing. The X280 leverages the RISC-V architecture's open standards, bringing a high level of customizability and performance efficiency to AI applications. Equipped with SiFive's Matrix Engine, the X280 is capable of handling sophisticated AI workloads with its impressive maximum throughput of 16 TOPS for INT8 operations. This performance is achieved without compromising on power efficiency, maintaining a small footprint that makes it suitable for diverse deployment scenarios. The processor's scalability is a key feature, supporting vector lengths up to 512 bits to accommodate the demands of intensive machine learning operations. SiFive Intelligence X280 stands out for its role in reshaping the possibilities of AI at the edge, pushing forward the capabilities of machine learning with a comprehensive software and hardware integration. This approach ensures that the X280 can handle emerging AI challenges with ease, presenting a formidable solution for today's AI-driven applications.
This core focuses on providing robust encryption standards, ensuring data protection and secure communications in various applications. Built with enhanced fault resilience, it aims to ensure data integrity even when faced with logic errors. The AES Core is designed to handle complex industrial and consumer encryption needs efficiently.
AndeSoft SW Stack encompasses a comprehensive set of software building blocks and middleware optimized for AndesCore processors. This rich collection includes operating systems, libraries, drivers, and middleware components, all meticulously designed to enhance software development speed and quality. By providing ready-to-use components, AndeSoft enables developers to focus on crafting their application-specific solutions, significantly reducing time-to-market. Its seamless integration with AndeSight IDE further enhances development efficiency, supporting diverse operating systems and being adaptable to various processor configurations for optimal performance.
The JPEG-LS Encoder delivers high-efficiency lossless image compression tailored for FPGA deployment. Known for its exceptional compression ability in comparison to other standards like JPEG-2000, this encoder operates without the need for external memory resources, offering a streamlined solution with minimal latency. With capabilities to handle image sample depths ranging from 8 to 16 bits, the JPEG-LS encoder stands out with less than one line of encoding delay, ensuring swift and efficient processing. Its low resource requirements make it an ideal solution for applications demanding compact and efficient image compression. JPEG-LS Encoder supports a configurability feature, allowing adjustment of output data word width and accommodating varied image dimensions extending to ultra-high definition scenarios. This adaptability, combined with either pixel and data FIFO inputs/outputs or through an Avalon Streaming interface, provides ample flexibility for integrations into various digital imaging systems.
Helion Technology's AES-XTS solution offers state-of-the-art encryption for data-at-rest in storage systems, adept at mitigating threats such as copy-paste and dictionary attacks. AES-XTS operates by encrypting disk sector data with blocks of 16-bytes under a secret AES key, incorporating a modifier value corresponding to each block's logical disk location. This method ensures that identical plaintext sectors stored at different positions yield different encrypted outputs. Designed to handle high performance requirements, Helion's AES-XTS cores enable custom levels of throughput scaling from 1Gbps up to over 64Gbps, suitable for diverse scenarios like servers and high-speed SSDs. The product range includes single, twin, quad, and giga variants, aligning closely with specific performance and logic resource parameters, optimizing both hardware usage and security efficacy. This flexibility and adherence to the IEEE 1619 standard make Helion's AES-XTS cores valuable for any application demanding secure disk-level encryption. Available for either ASIC or FPGA platforms, these cores are constructed to leverage the unique capabilities of each technology, achieving the best possible performance across different use cases.
Fully autonomous, FIPS 140-3 CAVP compliant PQC subsystem PQPlatform-SubSys is a cryptographic subsystem, designed to provide offloaded cryptographic services with minimal integration effort and full autonomy from an existing security subsystem, as well as configurable side-channel protection. These services include post-quantum signature generation, verification, and secure key establishment. It’s built with optimal performance in mind, as well as crypto agility with its provision of traditional, PQ/T hybrid and fully post-quantum algorithms. PQPlatform-SubSys uses its built-in RISC-V CPU independently from the surrounding system, allowing cryptographic services to be offloaded efficiently from the system processor.
FIPS 140-3 CAVP-compliant, compact lattice-based hardware PQC engine PQPlatform-Lattice is a compact FIPS 140-3 CAVP-compliant, PQC engine that adds post-quantum support for hardware components and embedded devices, using lattice-based cryptographic algorithms such as ML-KEM (FIPS 203) for post-quantum key exchange, and ML-DSA (FIPS 204) – post-quantum digital signature verification. It provides secure acceleration of lattice-based PQC alongside support for traditional cryptography. Its use cases include strong user authentication, protecting hardware keys, and small-footprint, configurable side-channel protection. PQPlatform-Lattice is designed for minimal area as well as maximum compatibility and can be deployed with optional firmware-backed side-channel countermeasures. It is covered by multiple PQShield implementation patents.
The NeuroSense AI Chip is a remarkable innovation for wearable technology, designed to address the key pain points of power consumption and data privacy in mass-market devices. It significantly enhances the accuracy of heart rate measurements and human activity recognition, operating independently of the cloud. The chip processes data at the sensor level, which not only increases precision but also extends battery life, a crucial factor for fitness trackers, smartwatches, and health monitoring devices. With unparalleled power efficiency, the NeuroSense chip maintains high accuracy by implementing analog computation and neural network strategies, translating to more effective biometrics extraction. NeuroSense excels in reducing the typical power burdens of AI-capable wearables. The diminutive size allows for easy integration into small devices without compromising functionality. By bypassing the need for cloud data processing, it ensures faster response times and greater privacy for users. Its capacity to learn from and accurately classify human activity transcends simple monitoring, offering potential expansions into fields like exercise coaching and senior care. Additionally, the NeuroSense chip allows for extended device operation times, which conventional sensor units struggle to deliver. It supports a broader range of applications by making wearables more intelligent and adaptive to various user needs. This positions the NeuroSense as a leading choice for developers seeking to enhance product features while minimizing cost and energy demands.
D2D® Technology, also known as Direct-to-Data, revolutionizes RF communication by bypassing traditional methods for a more integrated solution. By converting RF signals directly to baseband data and vice versa, it optimizes the efficiency and performance of RF conversion processes. This technology excels in simplifying the transmission and reception of signals across numerous wireless applications, including mobile telephony, Wi-Fi, and Internet of Things (IoT). Protected by an extensive suite of global patents, ParkerVision's D2D® facilitates high-performance RF-to-IF conversion, minimizing power consumption and maximizing data throughput. With increasing demands for 4G and forthcoming 5G applications, D2D® stands out for providing robust solutions in managing high data rates and sustaining powerful signal integrity over wide frequency bands. This direct conversion method enables more compact, cost-effective RF environments, crucial for minimizing device size and power use. ParkerVision's D2D® Technology has significantly contributed to the evolution of wireless communication by making RF receivers far more efficient and effective. By enabling devices to process vast amounts of data rapidly and reliably, this innovation continues to shape the functionality and design of modern wireless devices, driving further technological advancements in RF integrated circuits and system-on-chip solutions.
The WiseEye2 AI solution by Himax represents a significant leap forward in AI-enhanced sensing for smart devices. Designed for low-power operation, this solution integrates a specialized CMOS image sensor with the HX6538 microcontroller to deliver high-performance AI capabilities with minimal energy consumption. This makes it ideal for battery-powered devices that require continual operation, facilitating a new generation of always-on AI solutions without the typical drain on battery life. Thanks to its ARM-based Cortex M55 CPU and Ethos U55 NPU, WiseEye2 offers robust processing while maintaining a compact profile. Its multi-layer power management architecture not only maximizes energy efficiency but also supports the latest advancements in AI processing, allowing for faster and more accurate inference. Additionally, its industrial-grade security features ensure that data remains protected, catering particularly well to applications in personal computing devices. By enhancing capabilities such as user presence detection and improving facial recognition functionalities, WiseEye2 helps devices intelligently interact with users over various scenarios, whether in smart home setups, security domains, or personal electronics. This blend of smart functionality with energy conscientiousness reflects Himax's commitment to innovating sustainable technology solutions.
Monolithic Microsystems represents a technological leap in integrated system design, featuring multiple micro-engineered elements within a single chip. This system leverages advanced CMOS technology to unify electronic, photonic, and micromechanical devices, creating a compact and efficient platform suited for a variety of applications. By integrating different functionalities within a single substrate, these Microsystems can enhance performance while reducing the overall system footprint. They are increasingly being used in fields such as telecommunications, medical devices, and consumer electronics, where precision, reliability, and miniaturization are of paramount importance.
Post-quantum Software Development Kit Provides easy-to-use software implementations of both post-quantum and classical cryptographic primitives. It’s designed with prototyping and experimentation in mind, consisting of an integration of PQShield’s PQCryptoLib library with two popular high-level cryptography libraries: OpenSSL and mbedTLS. OpenSSL: a widely-adopted secure-communication library mbedTLS: primarily intended for use in embedded system and IoT deployments
The ONNC Calibrator is engineered to ensure high precision in AI System-on-Chips using post-training quantization (PTQ) techniques. This tool enables architecture-aware quantization, which helps maintain 99.99% precision even with fixed-point architecture, such as INT8. Designed for diverse heterogeneous multicore setups, it supports multiple engines within a single chip architecture and employs rich entropy calculation techniques. A major advantage of the ONNC Calibrator is its efficiency; it significantly reduces the time required for quantization, taking only seconds to process standard computer vision models. Unlike re-training methods, PTQ is non-intrusive, maintains network topology, and adapts based on input distribution to provide quick and precise quantization suitable for modern neural network frameworks such as ONNX and TensorFlow. Furthermore, the Calibrator's internal precision simulator uses hardware control registers to maintain precision, demonstrating less than 1% precision drop in most computer vision models. It adapts flexibly to various hardware through its architecture-aware algorithms, making it a powerful tool for maintaining the high performance of AI systems.
The Securyzr Key Management System is designed to handle complex cryptographic key management centrally, ensuring secure generation, distribution, and storage of keys. This system is integral for maintaining the security of cryptographic protocols which form the backbone of secure communications and digital identity verifications. Featuring flexible and scalable key management strategies, this product is essential for industries with stringent data protection requirements such as banking, telecommunications, and cloud services. It is engineered to seamlessly integrate with a variety of IT infrastructures, offering powerful protective measures against unauthorized access and enhancing the overall security posture of an organization.
Helion Technology delivers efficient hashing solutions through their SHA family of products, including SHA-1 and the more secure SHA-2 family, as well as MD5 for legacy purposes. These hashing cores are implemented to transform arbitrary-length files or messages into unique, fixed-length digests, which act as veritable signatures of the original data. These secure hash algorithms (SHAs) are integral to digital signatures and message authentication applications, underpinning protocols like IPsec and TLS/SSL by ensuring integrity and authenticity. With configurations optimized for high-speed and low-area applications, Helion's hashing solutions prove effective in systems needing cryptographic checks. The cores are partitioned into the FAST and TINY controls, each catering to different throughput and resource trade-offs. FAST delivers performance up to 4Gbps, focusing on speed, while TINY configurations are geared towards minimal resource utilization, providing an ideal solution for energy-efficient, low-data rate needs in both FPGA and ASIC technologies.
The GL3004 fisheye image processor offers comprehensive image processing capabilities, tailored specifically for wide-angle lens applications. It delivers exceptional fisheye correction methods, allowing for versatile dewarping options from spherical panorama views to specific stitching modes. Integrated hardware ensures that images maintain high fidelity, with a focus on accurate color processing and enhanced dynamic range. Supporting inputs up to 3 megapixels, it excels in real-time processing with an integrated ISP that handles a broad spectrum of imaging functions from noise reduction to auto-exposure control. This processor ensures that every captured scene disperses real-life details efficiently, which is critical in surveillance and advanced photography contexts. Designed with multiple interfaces, such as MIPI and BT standards, the GL3004 can fit into diverse applications, offering seamless integration potential. With an onboard Cyclone-8051 CPU, it processes instructions at a high speed, with reliable PLL systems managing clock operations across varied loads, making it a solid solution for creative and technical image requirements.
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