All IPs > Security IP
Security IPs are an integral category within the semiconductor industry focusing on the protection of electronic data and hardware. As technological advancements continue to proliferate across critical sectors like finance, healthcare, and automotive, securing data and hardware has never been more paramount. Security IPs are designed to provide essential security features such as encryption, secure communications, and access control to safeguard sensitive information and devices from unauthorized access and cyber threats.
Within the Security IP category, you will find robust offerings that include both hardware and software-based solutions tailored to various security needs. Content Protection Software enables secure data transmission and protects digital content from piracy and unauthorized distribution. Cryptography Cores and Cryptography Software Libraries offer foundational tools for implementing strong encryption algorithms that are crucial for securing communications and data storage.
Embedded Security Modules are integrated within semiconductor devices to facilitate secure data processing and enhance trust in device operations by preventing code tampering and unauthorized hardware modification. Platform Security solutions encompass a broad range of protective measures designed to secure the entire hardware and software ecosystem, ensuring that devices are safe from potential vulnerabilities at every level.
Additionally, Security Protocol Accelerators and Security Subsystems act as dedicated processing units to efficiently handle complex security algorithms and protocols, enhancing the performance of security operations while reducing the burden on primary CPUs. With an unpredictable security landscape, leveraging a range of specialized Security IPs allows designers and engineers to build robust, secure, and reliable semiconductor solutions that can withstand evolving cyber threats.
BrainChip's Akida Neural Processor IP is a groundbreaking development in neuromorphic processing, designed to mimic the human brain in interpreting sensory inputs. By implementing an event-based architecture, it processes only the critical data at the point of acquisition, achieving unparalleled performance with significantly reduced power consumption. This architecture enables on-chip learning, reducing dependency on cloud processing, thus enhancing privacy and security.\n\nThe Akida Neural Processor IP supports incremental learning and high-speed inference across a vast range of applications, making it highly versatile. It is structured to handle data sparsity effectively, which cuts down on operations substantially, leading to considerable improvements in efficiency and responsiveness. The processor's scalability and compact design allow for wide deployment, from minimal-node setups for ultra-low power operations to more extensive configurations for handling complex tasks.\n\nImportantly, the Akida processor uses a fully customizable AI neural processor that leverages event-based processing and an on-chip mesh network for seamless communication. The technology also features support for hybrid quantized weights and provides robust tools for integration, including fully synthesizable RTL IP packages, hardware-based event processing, and on-chip learning capabilities.
The Akida 2nd Generation is an evolution of BrainChip's innovative neural processor technology. It builds upon its predecessor's strengths by delivering even greater efficiency and a broader range of applications. The processor maintains an event-based architecture that optimizes performance and power consumption, providing rapid response times suitable for edge AI applications that prioritize speed and privacy.\n\nThis next-generation processor enhances accuracy with support for 8-bit quantization, which allows for finer grained processing capabilities and more robust AI model implementations. Furthermore, it offers extensive scalability, supporting configurations from a few nodes for low-power needs to many nodes for handling more complex cognitive tasks. As with the previous version, its architecture is inherently cloud-independent, enabling inference and learning directly on the device.\n\nAkida 2nd Generation continues to push the boundaries of AI processing at the edge by offering enhanced processing capabilities, making it ideal for applications demanding high accuracy and efficiency, such as automotive safety systems, consumer electronics, and industrial monitoring.
Overview: Cybersecurity IPs offer a range of essential security features to protect your digital assets and sensitive information. From True Random Number Generators (TRNG) to advanced encryption algorithms like AES, DES, 3DES, and cryptographic hash functions like SHA, as well as RSA for secure key exchange and digital signatures, the IPs provide a comprehensive suite of tools to safeguard your data. Key Features: True Random Number Generator (TRNG): Generates unpredictable and unbiased random numbers for cryptographic applications. Advanced Encryption Standard (AES): Provides robust encryption with symmetric key algorithms for securing data. Data Encryption Standard (DES) and Triple DES (3DES): Implement legacy encryption algorithms for data protection. Hash Functions: Includes secure cryptographic hash functions like SHA (Secure Hash Algorithm) for data integrity verification. RSA: Enables secure key exchange, encryption, and digital signatures for secure communication. These cybersecurity IPs are designed to meet the stringent security requirements of modern applications, ensuring the confidentiality, integrity, and authenticity of your data.
Overview: The Secure Enclave IPs are Common Criteria (CC) EAL5+PP0084/PP0117 and EAL5+PP0117 certification-ready Secure Enclaves, respectively. They are available as hard macros for seamless integration into SoCs. These Secure Enclave IPs provide the highest level of security for an SoC, incorporating patented design techniques and countermeasures against side-channel and perturbation attacks to ensure robust security while minimizing power consumption. Key Features: Cryptographic Hardware Accelerators: Efficiently support standard cryptography and security operations to increase throughput while adhering to power constraints and security requirements. BootROM and Secondary Boot Loader: Manage the certified life cycle of the Secure Enclave, enforcing and assuring security from manufacturing to deployment. Proprietary IP: Based on proprietary IP that is free of 3rd party rights and royalties. Benefits: The Secure Enclave IPs offer robust security measures, efficient cryptographic support, and secure life cycle management, making them ideal for applications that require the highest levels of security and reliability. Applications: The Secure Enclave IP is versatile and suitable for a wide range of applications, including but not limited to: Secured and Certified iSIM & iUICC EMVco Payment Hardware Cryptocurrency Wallets FIDO2 Web Authentication V2X HSM Protocols Smart Car Access Secured Boot Secure OTA Firmware Updates Secure Debug Any design requiring a Secure Enclave, Secure Element, or Hardware Root of Trust protected against side-channel and perturbation fault attacks. Compliance and Support: The Secure Enclave is compliant with and ready for CC EAL5+ and EMVCo certification. It is delivered with an SDK and pre-certified CryptoLibrary and secure Boot Loader for seamless integration and enhanced security.
Overview: The Secure Boot IP is a turnkey solution that provides a secure boot facility for an SoC. It implements the Post Quantum secure Leighton-Micali Signature (LMS) as specified in NIST SP800-208. The Secure Boot IP operates as a master or slave peripheral to an Application Processor, serving as a secure enclave that securely stores keys to ensure their integrity and the integrity of the firmware authentication process. Features: Post Quantum Secure LMS Signature: Utilizes a robust Post-Quantum secure algorithm for enhanced security. Firmware Updates: Supports up to 32 thousand firmware updates with a minimal signature size of typically less than 5KBytes. SESIP Level 3 Pre-Certification: Pre-certified to SESIP Level 3 for added security assurance. RTL Delivery: Delivered as RTL for ease of integration into SoC designs. Proprietary IP: Based on proprietary IP with no 3rd party rights or royalties. Operation: The Secure Boot IP operates as a master, managing the boot process of the Application Processor to ensure that it only boots from and executes validated and authenticated firmware. The Secure Boot IP also functions as a slave peripheral, where the Application Processor requests validation of the firmware as part of its boot process, eliminating the need for managing keys and simplifying the boot process. Applications: The Secure Boot IP is versatile and suitable for a wide range of applications, including but not limited to: Wearables Smart/Connected Devices Metrology Entertainment Applications Networking Equipment Consumer Appliances Automotive Industrial Control Systems Security Systems Any SoC application that requires executing authenticated firmware in a simple but secure manner.
The AHB-Lite APB4 Bridge from Roa Logic is a versatile interconnect bridge designed to facilitate communication between the AMBA 3 AHB-Lite and AMBA APB bus protocols. As a parameterized soft IP, it offers flexibility in adapting to different system requirements, ensuring smooth data transfer between high-performance and low-performance buses. This bridge is crucial for systems that integrate diverse peripherals requiring seamless interaction across varying bus standards. Its design prioritizes efficiency and performance, minimizing latency and maximizing data throughput. The AHB-Lite APB4 Bridge supports extensive customization options to meet specific design criteria, making it suitable for a wide range of applications across different industries. By serving as a conduit between different bus protocols, it plays a central role in maintaining system cohesiveness and reliability. Roa Logic enhances the bridge's usability through detailed technical documentation and supportive testbenches, easing its integration into existing frameworks. Developers can readily incorporate the bridge into their designs, optimizing inter-bus communication and ensuring that system performance remains uncompromised. This bridge exemplifies Roa Logic's dedication to providing robust, adaptable IP solutions for contemporary digital environments.
The AHB-Lite Multilayer Switch developed by Roa Logic is engineered to provide a high-performance, low-latency interconnect solution for systems using the AHB-Lite bus protocol. This IP is designed to support an unlimited number of bus masters and slaves, ensuring scalability and flexibility in complex system architectures. By enabling efficient data routing, the switch enhances throughput and overall system performance, making it indispensable in data-intensive applications. Capable of handling multiple data paths simultaneously, the multilayer switch ensures that there are no bottlenecks in data flow, facilitating real-time data processing and communication. Its design features are tailored to optimize latency and throughput, effectively addressing the challenges encountered in high-demand environments. Roa Logic provides a comprehensive suite of resources, including thorough documentation and testbench environments, to simplify the integration of this switch into larger system designs. This support ensures that developers can achieve optimal performance with ease, utilizing the switch's capabilities to enhance system interconnectivity and efficiency significantly. The AHB-Lite Multilayer Switch exemplifies the commitment of Roa Logic to provide innovative, responsive solutions that cater to the evolving needs of the semiconductor industry.
The RV12 RISC-V Processor from Roa Logic is a highly versatile CPU designed for embedded applications. It complies with the RV32I and RV64I specifications of the RISC-V instruction set, supporting single-core configurations. The RV12 processor is renowned for its configurability, allowing it to be tailored to specific application requirements. It implements a Harvard architecture, which enables concurrent access to both instruction and data memory, optimizing performance and efficiency. Roa Logic's RV12 processor is part of their broader portfolio of 32/64-bit CPU solutions that leverage the open-source RISC-V instruction set. This architecture is favored for its simplicity and scalability, making it ideal for various embedded systems. The processor is equipped with an optimizing feature set that enhances its processing capabilities, ensuring it meets the rigorous demands of modern applications. Incorporating the RV12 processor into projects is streamlined thanks to its comprehensive support documentation and available test benches. These resources facilitate smooth integration into larger systems, providing developers with a reliable foundation for building advanced embedded systems. Its design is a testament to Roa Logic's commitment to delivering high-performance, adaptable IP solutions to the semiconductor industry.
The AHB-Lite Timer from Roa Logic is a precision timing module designed to comply with the RISC-V Privileged specification. This timer is engineered to manage time-sensitive operations within systems that utilize the AHB-Lite bus protocol, ensuring accurate timing for a variety of applications. By providing robust timer functionalities, the AHB-Lite Timer assists in overseeing operations where precise timing is crucial, such as coordinating tasks within embedded systems or managing periods in control processes. Its compliance with RISC-V standards ensures that it integrates seamlessly with systems based on this widely adopted open standard, enhancing compatibility and performance. Developers can take advantage of Roa Logic's comprehensive support materials, which include detailed documentation and pre-configured test environments, to facilitate the easy integration of the timer into existing designs. This support infrastructure is indicative of Roa Logic's commitment to simplifying the adoption and effective utilization of its sophisticated IP offerings within diverse system architectures.
The Polar ID Biometric Security System by Metalenz revolutionizes smartphone biometric security with its advanced imaging capabilities that capture the full polarization state of light. This system detects unique facial polarization signatures, enabling high-precision face authentication that even sophisticated 3D masks cannot deceive. Unlike traditional systems requiring multiple optical modules, Polar ID achieves secure recognition with a single image, ideal for secure digital payments and more. Operating efficiently across various lighting conditions, from bright daylight to complete darkness, Polar ID ensures robust security without compromising user convenience. By leveraging meta-optic technology, it offers a compact, cost-effective alternative to structured light solutions, suitable for widespread deployment across millions of mobile devices.
Up to 1M KeyEnc/sec with improved power efficiency PQPerform-Lattice is a powerful hardware-based product designed for high throughput, high-performance, and high speed. It adds post-quantum cryptography for applications that typically handle a large number of transactions, such as high-capacity network hardware applications and secure key management HSMs. Optimizable for secure boot, as well as other use-cases, PQPerform-Lattice supports FIPS 204 ML-DSA for quantum-secure digital signature verification, as well as FIPS 203 ML-KEM for quantum key exchange. PQPerform-Lattice supports AXI4, PCIe, and is deployable in multiple instances, making it a powerful solution for existing systems and infrastructure requirements.
The Dynamic Neural Accelerator II (DNA-II) is a highly efficient and versatile IP specifically engineered for optimizing AI workloads at the edge. Its unique architecture allows runtime reconfiguration of interconnects among computing units, which facilitates improved parallel processing and efficiency. DNA-II supports a broad array of networks, including convolutional and transformer networks, making it an ideal choice for numerous edge applications. Its design emphasizes low power consumption while maintaining high computational performance. By utilizing a dynamic data path architecture, DNA-II sets a new benchmark for IP cores aimed at enhancing AI processing capabilities.
aiWare represents aiMotive's advanced hardware intellectual property core for automotive neural network acceleration, pushing boundaries in efficiency and scalability. This neural processing unit (NPU) is tailored to meet the rigorous demands of automotive AI inference, providing robust support for various AI workloads, including CNNs, LSTMs, and RNNs. By achieving up to 256 Effective TOPS and remarkable scalability, aiWare caters to a wide array of applications, from edge processors in sensors to centralized high-performance modules.\n\nThe design of aiWare is particularly focused on enhancing efficiency in neural network operations, achieving up to 98% efficiency across diverse automotive applications. It features an innovative dataflow architecture, ensuring minimal external memory bandwidth usage while maximizing in-chip data processing. This reduces power consumption and enhances performance, making it highly adaptable for deployment in resource-critical environments.\n\nAdditionally, aiWare is embedded with comprehensive tools like the aiWare Studio SDK, which streamlines the neural network optimization and iteration process without requiring extensive NPU code adjustments. This ensures that aiWare can deliver optimal performance while minimizing development timelines by allowing for early performance estimations even before target hardware testing. Its integration into ASIL-B or higher certified solutions underscores aiWare's capability to power the most demanding safety applications in the automotive domain.
The Titanium Ti375 FPGA is a high-density, low-power solution featuring Efinix’s Quantum® compute fabric. This state-of-the-art FPGA is equipped with a range of advanced features including a hardened RISC-V block, SerDes transceiver, and an LPDDR4 DRAM controller. It is designed to meet the demands of applications requiring high computational efficiency and low power consumption, making it ideal for rapid application development and deployment. This FPGA offers exceptional processing capabilities and flexibility, helping to reduce design complexity while optimizing performance for data-intensive applications. Its small package footprint is suitable for highly integrated systems, providing seamless compliance with existing protocols such as MIPI D-PHY. This combination of features makes it suitable for use in edge computing devices, advanced automotive systems, and next-generation IoT applications. Additionally, the Titanium Ti375 allows developers to exploit its high-speed I/O capabilities, facilitating robust peripheral interfacing and data transfer. The device also benefits from bitstream authentication and encryption to secure the intellectual property embedded within. As part of its wide-ranging applicability, it suits industrial environments that require solid reliability and long-term product lifecycles.
The Alcora V-by-One HS Daughter Card is tailored for high-speed digital interfacing, specifically aligning with FPGA development boards via FMC connectors. The card features 8 RX and 8 TX lanes, with the option to combine two FMC cards for a total of 16 lanes. This configuration supports video resolutions up to 4K at 120Hz or 8K at 30Hz, demonstrating its capability to handle large volumes of data efficiently. Designed to meet the demanding requirements of high-resolution and high-frame-rate applications, the Alcora card integrates dual clock generators to optimize signal clarity by synthesizing the transceiver reference clock and minimizing jitter. This characteristic is crucial in maintaining data integrity and ensuring smooth video performance, making the Alcora an optimal choice for flat panel display integration. Featuring flexible connectivity options, the Alcora card is available in both 51-pin and 41-pin header variants. This design ensures that it can provide a comprehensive interface to meet various technical challenges, advancing the capabilities of high-speed digital communications within FPGA systems.
PUFrt is a sophisticated Hardware Root of Trust (HRoT) solution that focuses on generating and storing root keys that never leave the chip, ensuring a secure environment for sensitive operations. This IP incorporates a 1024-bit Physical Unclonable Function (PUF) along with a true random number generator (TRNG) compliant with NIST standards. PUFrt's architecture is fortified with secure storage capabilities that protect key information from potential physical attacks, providing a robust security layer against future threats in the IoT landscape. Its design allows seamless integration across different systems and design architectures, making it versatile for applications ranging from lightweight hardware security keys to full-fledged Security Coprocessors. With built-in anti-tamper features and customization options, PUFrt is a prime choice for those looking to secure their semiconductor supply chain against threats like counterfeiting and reverse engineering. Certified by Riscure, PUFrt sets a high benchmark for reliable security practices in semiconductor design. Its comprehensive security framework makes it indispensable for modern chip designs that necessitate high levels of trust and integrity.
SphinX encryption technology delivers high-performance, low-latency AES-XTS encryption and decryption capabilities, specifically designed to meet the stringent security demands of modern data environments. It supports independent, non-blocking encryption and decryption channels, ensuring that data can be securely processed with minimal delay. This powerful encryption solution is ideal for data centers and enterprises subjected to significant data security and integrity requirements. By ensuring that data is protected from unauthorized access while maintaining operational efficiency, SphinX provides a robust foundation for secure data management. The capabilities of SphinX align with industry standards, making it suitable for a variety of applications that demand high levels of data encryption. Its integration aids businesses in protecting sensitive information without compromising on speed or computing power, facilitating secure yet agile data processing.
Trilinear Technologies' HDCP Encryption-Decryption Engine is a sophisticated solution designed to safeguard digital content as it traverses various transmission channels. This engine is compliant with the HDCP standards 1.4 and 2.3, offering robust protection mechanisms to ensure that digital media investments are secure from unauthorized access and piracy. The engine’s hardware acceleration capabilities represent a crucial advantage, significantly reducing the load on the system processor while maintaining real-time encryption and decryption functions. This not only enhances performance but also extends the operational life of the hardware involved, making it suitable for high-demand media applications across sectors such as broadcast, entertainment, and corporate environments. Trilinear’s HDCP Encryption-Decryption Engine ensures compatibility with a wide array of consumer and professional-grade video equipment, providing seamless protection without interference in media quality or transmission speed. Its flexible integration options allow it to be smoothly incorporated into existing infrastructures, whether in standalone media devices or complex SoC architectures. Supported by comprehensive software resources, the HDCP Encryption-Decryption Engine provides an all-encompassing solution that includes necessary software stacks for managing device authentication and link maintenance. Its ability to safeguard high-definition content effectively makes it an invaluable asset for entities focused on secure content delivery and rights management.
The Intelligence X280 is engineered to provide extensive capabilities for artificial intelligence and machine learning applications, emphasizing a software-first design approach. This high-performance processor supports vector and matrix computations, making it adept at handling the demanding workloads typical in AI-driven environments. With an extensive ALU and integrated VFPU capabilities, the X280 delivers superior data processing power. Capable of supporting complex AI tasks, the X280 processor leverages SiFive's advanced vector architecture to allow for high-speed data manipulation and precision. The core supports extensive vector lengths and offers compatibility with various machine learning frameworks, facilitating seamless deployment in both embedded and edge AI applications. The Intelligence family, represented by the X280, offers solutions that are not only scalable but are customizable to particular workload specifications. With high-bandwidth interfaces for connecting custom engines, this processor is built to evolve alongside AI's progressive requirements, ensuring relevance in rapidly changing technology landscapes.
Helion Technology's AES-XTS solution offers state-of-the-art encryption for data-at-rest in storage systems, adept at mitigating threats such as copy-paste and dictionary attacks. AES-XTS operates by encrypting disk sector data with blocks of 16-bytes under a secret AES key, incorporating a modifier value corresponding to each block's logical disk location. This method ensures that identical plaintext sectors stored at different positions yield different encrypted outputs. Designed to handle high performance requirements, Helion's AES-XTS cores enable custom levels of throughput scaling from 1Gbps up to over 64Gbps, suitable for diverse scenarios like servers and high-speed SSDs. The product range includes single, twin, quad, and giga variants, aligning closely with specific performance and logic resource parameters, optimizing both hardware usage and security efficacy. This flexibility and adherence to the IEEE 1619 standard make Helion's AES-XTS cores valuable for any application demanding secure disk-level encryption. Available for either ASIC or FPGA platforms, these cores are constructed to leverage the unique capabilities of each technology, achieving the best possible performance across different use cases.
The eSi-ADAS Radar IP Suite and Co-processor Engine is at the forefront of automotive and unmanned systems, enhancing radar detection and processing capabilities. It leverages cutting-edge signal processing technologies to provide accurate and rapid situational awareness, crucial for modern vehicles and aerial drones. With its comprehensive offering of radar algorithms, eSi-ADAS supports both traditional automotive radar applications and emerging unmanned aerial vehicle (UAV) platforms. This suite is crafted to meet the complex demands of real-time data processing and simultaneous multi-target tracking in dense environments, key for advanced driver-assistance systems. The co-processor engine within eSi-ADAS is highly efficient, designed to operate alongside existing vehicle systems with minimal additional power consumption. This suite is adaptable, supporting a wide range of vehicle architectures and operational scenarios, from urban driving to cross-country navigation.
Secure OTP is a cutting-edge non-volatile memory solution designed to safeguard key, data, and secret storage with enhanced protection against hardware attacks. It features a combination of physical macros and digital RTL, offering robust anti-tamper and integrated protection mechanisms. This solution is specifically architected for integration in CMOS technologies and is compatible across numerous IC and ASIC applications. By incorporating a 1024-bit PUF for scrambling and I/O shuffling, Secure OTP significantly elevates stored data security, effectively making it tamperproof. As digital security challenges mount, Secure OTP provides a modernized answer, ensuring the safekeeping of critical information across its lifecycle. Its adoption addresses prevalent security gaps in legacy e-fuse solutions and is instrumental in extending robust defense systems within SoC environments, acting as a cornerstone for comprehensive hardware security strategies.
The eSi-Crypto solution provides an advanced encryption and authentication framework, ensuring robust security for digital data. Its sophisticated algorithms cover a wide array of cryptographic needs, from basic encryption to complex data protection mechanisms. This solution is designed to offer high performance with low resource consumption, making it ideal for various embedded systems where security and efficiency are paramount. EnSilica has integrated various cryptographic components, including True Random Number Generators (TRNGs), to support extensive security protocols. These components are critical in applications such as secure communications, financial transactions, and personal data protection, where unauthorized access prevention is crucial. The streamlined architecture of eSi-Crypto ensures it can be efficiently implemented across diverse system architectures, offering scalable security solutions for emerging digital threats. Its flexibility allows customization and integration with other IPs, providing a seamless security shield for both legacy and new systems.
Highly-optimized PQC implementations, capable of running PQC in < 15kb RAM PQCryptoLib-Emebedded is a versatile, CAVP-compliant version of PQCryptoLib, PQShield’s CMVP-certified library of post-quantum cryptographic algorithms. With its design focused on ultra-small area efficiency, PQCryptoLib-Embedded has been specifically designed for embedded systems, microcontrollers and memory-constrained devices. It could be the first step towards a hardware solution for providing PQC integration to devices already in the field.
The Flash Protection Series is a sophisticated suite of security solutions designed to extend the secure boundaries of SoC architectures into flash storage realms. By utilizing PUF technology, this series offers three primary solutions: PUFef for embedded flash, PUFenc for external NAND flash, and PUFxip for external NOR flash. Each solution provides unique protection capabilities such as encryption, real-time decryption, and execution to maintain data integrity and confidentiality. With these protections in place, SoCs achieve a higher level of security, preventing unauthorized access and ensuring that sensitive data remains protected throughout its lifecycle. This series is compatible with a wide range of foundries, making it a flexible choice for designers aiming to implement robust security measures without compromising on performance or compatibility.
FIPS 140-3 CMVP compliant, CAVP PQC cryptographic library designed for PQ/T Hybrid PQCryptoLib is a general-purpose FIPS 140-3 CMVP and CAVP-certified cryptographic library. It’s been designed for a wide variety of applications and provides the latest NIST-standardized post-quantum and classical algorithms in a software environment. With a configurable, secure, and easy-to-use API, PQCryptoLib is optimized for crypto-agility, particularly when it comes to FIPS-compliant hybrid PQ/T solutions, and with crypto-agility in mind, it’s built to protect against the threat of ‘harvest-now-decrypt-later’ attacks. The aim of PQCryptoLib is to help organizations transition smoothly and securely to quantum resistance in a manageable, easy-to-integrate solution.
DolphinWare IPs is a versatile portfolio of intellectual property solutions that enable efficient SoC design. This collection includes various control logic components such as FIFO, arbiter, and arithmetic components like math operators and converters. In addition, the logic components span counters, registers, and multiplexers, providing essential functionalities for diverse industrial applications. The IPs in this lineup are meticulously designed to ensure data integrity, supported by robust verification IPs for AXI4, APB, SD4.0, and more. This comprehensive suite meets the stringent demands of modern electronic designs, facilitating seamless integration into existing design paradigms. Beyond their broad functionality, DolphinWare’s offerings are fundamental to applications requiring specific control logic and data integrity solutions, making them indispensable for enterprises looking to modernize or expand their product offerings while ensuring compliance with industry standards.
Securyzr iSSP is an advanced integrated Security Service Platform that manages the security lifecycle of connected devices from chip to cloud. It provides a seamless solution for provisioning, firmware updates, security monitoring, and device identity management. This platform ensures reliability with zero-touch security services and is built to adapt to various lifecycle stages of embedded systems.
ArrayNav is a groundbreaking GNSS solution utilizing patented adaptive antenna technology, crafted to provide automotive Advanced Driver-Assistance Systems (ADAS) with unprecedented precision and capacity. By employing multiple antennas, ArrayNav substantially enhances sensitivity and coverage through increased antenna gain, mitigates multipath fading with antenna diversity, and offers superior interference and jamming rejection capabilities. This advancement leads to greater accuracy in open environments and markedly better functionality within urban settings, often challenging due to signal interference. It is designed to serve both standalone and cloud-dependent use cases, thereby granting broad application flexibility.
The HOTLink II solution is a fully implemented hardware layer 2 design specifically intended for handling high-speed interface communications. It effectively supports full-rate, half-rate, and quarter-rate operations, as per standards set for such technological interfaces. Tailored for F-18 compatible environments, this IP provides frame interface integration ease, which is critical for successful deployment in high-frequency operational settings. The core's engineering sophistication is evident in its steadfast processing capabilities and adaptability to diverse aviation communication needs. Designed to offer sustainable and efficient data processing, the HOTLink II ensures minimal disruptions, promoting fluid operation within its designated applications. As an industry standard solution, its precision aligns with substantial aerospace demands, guaranteeing optimal performance even under demanding conditions. Organizations deploying this core can expect significant enhancements in data throughput efficiency and streamlined communication processes crucial to operational success in aviation platforms.
The 802.11 LDPC core by Wasiela is engineered for high throughput applications in wireless communication systems. It excels in providing frame-to-frame on-the-fly configuration, allowing developers to balance throughput and error correction performance according to specific needs. This LDPC solution is compliant with relevant throughput and performance specifications, ensuring reliable bit-error-rate and packet-error-rate outcomes that meet industry standards. The core's adaptability in decoding iterations is key to maintaining high efficiency without compromising on quality.
Secure Protocol Engines offer high-performance IP blocks designed to enhance network and security processing capabilities. These engines support critical operations like cryptographic functions, dramatically offloading the central processing units within SoCs. They ensure secure communication channels for embedded systems by seamlessly integrating into existing security frameworks, thereby bolstering the system's defense mechanisms against potential cyber threats.
ParkerVision's Direct-to-Data (D2D) Technology marks a transformative development in RF communication, significantly enhancing the performance of modern smartphones and wireless devices. This innovative technology replaces the century-old super-heterodyne downconverter with a new RF downconverter that operates efficiently within CMOS architectures. D2D allows RF receivers to connect more seamlessly across global bands while processing high data rates essential for today's media and communication needs. D2D RF receivers built on ParkerVision technology minimize power usage while delivering fast data speeds, substantially contributing to the functionality and efficiency of modern smartphones. These receivers are capable of handling a wide spectrum of data rates from streaming video to large data transfers, thanks to their high-performance design capable of managing a range of signal strengths from various distances with cellular towers. This patented technology plays a crucial role in the smartphone revolution, with its incorporation leading to smarter, faster devices. These developments are enabled by a precise downconversion mechanism that transforms high-frequency RF signals into data-efficient formats. The D2D technology reduces the traditional noise and signal loss, making it a cornerstone in the advancement of mobile and IoT device communication strategies.
AndeSoft SW Stack encompasses a comprehensive set of software building blocks and middleware optimized for AndesCore processors. This rich collection includes operating systems, libraries, drivers, and middleware components, all meticulously designed to enhance software development speed and quality. By providing ready-to-use components, AndeSoft enables developers to focus on crafting their application-specific solutions, significantly reducing time-to-market. Its seamless integration with AndeSight IDE further enhances development efficiency, supporting diverse operating systems and being adaptable to various processor configurations for optimal performance.
Fully autonomous, FIPS 140-3 CAVP compliant PQC subsystem PQPlatform-SubSys is a cryptographic subsystem, designed to provide offloaded cryptographic services with minimal integration effort and full autonomy from an existing security subsystem, as well as configurable side-channel protection. These services include post-quantum signature generation, verification, and secure key establishment. It’s built with optimal performance in mind, as well as crypto agility with its provision of traditional, PQ/T hybrid and fully post-quantum algorithms. PQPlatform-SubSys uses its built-in RISC-V CPU independently from the surrounding system, allowing cryptographic services to be offloaded efficiently from the system processor.
The AES Core from Green IP Core provides robust encryption capabilities crucial for maintaining data security across a variety of platforms. It employs advanced encryption standards to safeguard sensitive information, thereby serving as a foundation for secure communication and data storage solutions. This IP is versatile enough to be implemented in both consumer electronics and large-scale enterprise systems where data protection is paramount. Designed with efficiency in mind, this core optimizes hardware resource usage, delivering high-speed encryption while minimizing impact on performance. Its architecture is specifically tailored to offer seamless integration into existing systems, requiring minimal reconfiguration of current operations. This adaptability makes it an ideal choice for companies looking to bolster their security measures without significant infrastructure changes. The AES Core stands out due to its fault-tolerant design, ensuring that it remains operable even under conditions that may induce errors in traditional systems. This reliability factor is key for industries where data integrity and security are of utmost importance, including finance, telecommunications, and government sectors.
FIPS 140-3 CAVP-compliant, compact lattice-based hardware PQC engine PQPlatform-Lattice is a compact FIPS 140-3 CAVP-compliant, PQC engine that adds post-quantum support for hardware components and embedded devices, using lattice-based cryptographic algorithms such as ML-KEM (FIPS 203) for post-quantum key exchange, and ML-DSA (FIPS 204) – post-quantum digital signature verification. It provides secure acceleration of lattice-based PQC alongside support for traditional cryptography. Its use cases include strong user authentication, protecting hardware keys, and small-footprint, configurable side-channel protection. PQPlatform-Lattice is designed for minimal area as well as maximum compatibility and can be deployed with optional firmware-backed side-channel countermeasures. It is covered by multiple PQShield implementation patents.
The Aeonic Integrated Droop Response System introduces a revolutionary approach to managing voltage droop in intricate circuitry. By pairing droop mitigation with detection, it achieves unprecedented adaptability, responding within high-speed clock cycles, thus aiding in significant power savings. Equipped with multi-threshold detection and supported by standard interfaces like APB & JTAG, it facilitates remote and local droop management, providing a wealth of actionable insights for silicon lifecycle analytics. Design architects benefit from these insights, allowing precision-driven power management decisions. This tightly integrated system adopts a standard cell design, making it process portable across varying technological nodes. Its features ensure reliability and adaptability, aiding design teams to efficiently migrate solutions across evolving production landscapes.
The JPEG-LS Encoder delivers high-efficiency lossless image compression tailored for FPGA deployment. Known for its exceptional compression ability in comparison to other standards like JPEG-2000, this encoder operates without the need for external memory resources, offering a streamlined solution with minimal latency. With capabilities to handle image sample depths ranging from 8 to 16 bits, the JPEG-LS encoder stands out with less than one line of encoding delay, ensuring swift and efficient processing. Its low resource requirements make it an ideal solution for applications demanding compact and efficient image compression. JPEG-LS Encoder supports a configurability feature, allowing adjustment of output data word width and accommodating varied image dimensions extending to ultra-high definition scenarios. This adaptability, combined with either pixel and data FIFO inputs/outputs or through an Avalon Streaming interface, provides ample flexibility for integrations into various digital imaging systems.
The Securyzr Key Management System is pivotal in safeguarding cryptographic keys within various systems. By facilitating key lifecycle management, this system ensures that keys remain secure from creation through destruction. It offers an intuitive interface for administrators to oversee and manage keys across their network, providing peace of mind with enhanced access controls and auditing capabilities.
The NeuroSense is a compact AI chip designed specifically for wearable devices, featuring neuromorphic analog signal processing technology. Its main focus lies in resolving common challenges faced by wearable tech, such as high power consumption, and limited battery life. By enabling highly accurate heart rate monitoring and activity recognition, this chip facilitates better fitness tracking without excessively draining battery resources. The NeuroSense's capability of operating independently from cloud connections addresses significant privacy concerns and data latency issues. It excels in delivering enhanced accuracy in heart rate measurements by utilizing a simple photoplethysmogram (PPG) configuration, which involves minimalistic hardware components like two LEDs and one photodiode. Through this setup, it achieves precision in bio-signal extraction far beyond conventional algorithmic methods, particularly when the wearer is in motion. Furthermore, the NeuroSense empowers wearables with advanced features like learning and recognizing user-specific activity patterns. With ultra-low power consumption and a compact size, the NeuroSense enables manufacturers to preserve space within constrained wearable designs while simultaneously enhancing battery life—solving a key concern in the realm of constantly operating smart devices.
The RISC-V CPU IP NS Class is crafted explicitly for applications requiring heightened security and robustness, such as fintech payment systems and IoT security solutions. This processor class is equipped to support secure operations, incorporating features essential for protecting data and ensuring secure communications within devices. This processor integrates security protocols aligned with the RISC-V open standard, offering developers the ability to embed reliable security measures directly at the hardware level. Its architecture provides the foundation for developing systems where data integrity and secure processing are non-negotiable, ensuring that sensitive applications run safely and efficiently. The RISC-V CPU IP NS Class is supported by a strong ecosystem offering tools and resources to facilitate the secure application development process. With its ability to integrate seamlessly with other embedded systems, the NS Class empowers designers to create solutions that prioritize and enhance security in modern digital environments, where threats are constantly evolving.
The ReRAM Memory technology from CrossBar offers a revolutionary approach to data storage, diverging from conventional memory systems. This technology leverages a simple structure that allows it to scale down below 10nm and integrate directly with logic circuits in the same fabrication. This integration results in an optimal blend of low energy usage and high endurance, making it ideal for demanding applications such as data centers and IoT. ReRAM's capability to provide 1/20th the energy consumption, coupled with a 1000x improvement in endurance and dramatic enhancements in read/write performance, makes it a superior alternative to traditional memory technologies. The capacity for on-chip terabytes of storage further augments its appeal for modern computing needs. The innovation extends to ReRAM's ability to stack in 3D and serve various industries, from secure computing to artificial intelligence, providing the necessary performance and security for the emerging digital landscape.
Helion Technology delivers efficient hashing solutions through their SHA family of products, including SHA-1 and the more secure SHA-2 family, as well as MD5 for legacy purposes. These hashing cores are implemented to transform arbitrary-length files or messages into unique, fixed-length digests, which act as veritable signatures of the original data. These secure hash algorithms (SHAs) are integral to digital signatures and message authentication applications, underpinning protocols like IPsec and TLS/SSL by ensuring integrity and authenticity. With configurations optimized for high-speed and low-area applications, Helion's hashing solutions prove effective in systems needing cryptographic checks. The cores are partitioned into the FAST and TINY controls, each catering to different throughput and resource trade-offs. FAST delivers performance up to 4Gbps, focusing on speed, while TINY configurations are geared towards minimal resource utilization, providing an ideal solution for energy-efficient, low-data rate needs in both FPGA and ASIC technologies.
Post-quantum Software Development Kit Provides easy-to-use software implementations of both post-quantum and classical cryptographic primitives. It’s designed with prototyping and experimentation in mind, consisting of an integration of PQShield’s PQCryptoLib library with two popular high-level cryptography libraries: OpenSSL and mbedTLS. OpenSSL: a widely-adopted secure-communication library mbedTLS: primarily intended for use in embedded system and IoT deployments
The FPGA Pre-Trade Risk Check by Algo-Logic Systems enhances financial security by performing comprehensive risk assessments before executing trades. This preemptive analysis is integrated directly into the FPGA infrastructure, facilitating extremely fast identification and analysis of potential risks. Market participants can immediately identify erroneous trades or breaches of risk parameters, ensuring compliance with established guidelines. With the capability to process data at exceptional speeds, this solution ensures that each trade adheres to the pre-defined risk criteria before it's executed in the market. This feature is particularly beneficial for financial institutions and trading firms where rapid and accurate risk assessment is crucial. By preventing unauthorized or high-risk trades from proceeding, the technology helps firms maintain their market integrity and avoid costly errors. Moreover, the integration of risk management processes within the FPGA framework provides an added layer of security, which is vital for maintaining trust and reliability in financial operations. The FPGA Pre-Trade Risk Check solution thus streamlines the intersection of speed, accuracy, and security in the financial trading sector.
The Individual IP Core Modules offered by ResQuant are designed to support a wide array of post-quantum cryptography needs, featuring compatibility with all recognized NIST PQC standards. These include pioneering algorithms such as Dilithium, Kyber, XMSS, and SPHINCS+, guaranteeing breadth in cryptographic applications. These modules offer comprehensive cryptographic functions like advanced encryption standards using AES, hashing with SHA2 and SHA3 families, and generation of true random numbers, posing as a versatile security solution adaptable to a variety of environments. Scheduled for future updates with additional protocols like the FRODO Key Encapsulation Mechanism, these IP cores promise continuous alignment with evolving cryptographic needs. Their structure accommodates substantial flexibility in terms of performance tuning and system integration, enabling easy deployment in diverse application scenarios, from IoT devices to large-scale data centers, making them a staple for entities preparing for quantum computing advancements. These modules ensure security frontiers remain resilient against future computational intricacies.
The L5-Direct GNSS Receiver is a groundbreaking innovation by oneNav, designed to enhance location accuracy by tapping into the L5 frequency band. This technology sets itself apart by directly capturing signals in the L5-band, unlike traditional receivers that rely first on L1 signals before switching to L5. The L5-Direct receiver is adept at handling over 70 satellite signals from major constellations like GPS, Galileo, and BeiDou, thus offering a robust defense against jamming and signal interference—key requirements for urban and defense applications. At the heart of the L5-Direct technology is the Application Specific Array Processor (ASAP), a specialized processor that efficiently acquires L5 signals without sacrificing performance. This processor reduces system complexity and size, an advantage in developing small, cost-effective devices such as wearables and IoT gadgets. The L5-Direct receiver is also fortified by a comprehensive portfolio of patents, ensuring a unique position in the market. This receiver leverages machine learning techniques to enhance multipath rejection, thus maintaining accuracy even in environments with complex signal paths, like urban canyons. Its architecture is designed to achieve significant power savings and rapid location acquisition, making it suitable for devices requiring extended battery life. Overall, the L5-Direct GNSS Receiver represents a significant leap in GNSS technology, overcoming the limitations of older systems and providing enhanced performance with minimal footprint and power requirements.
The AIoT Platform from SEMIFIVE is crafted to create specialized IoT and edge processing devices with efficiency and cutting-edge technology. Leveraging silicon-proven design components on Samsung's 14nm process, it streamlines the development of high-performance, power-efficient applications. This platform is equipped with dual SiFive U54 RISC-V CPUs, LPDDR4 memory, and comprehensive interfaces like MIPI-CSI and USB3.0. Targeted at consumer electronics such as wearables and smart home devices, this platform supports a wide array of IoT applications, including industrial IoT and smart security systems. Its architectural flexibility allows customization of system specifications, enabling designers to address the unique requirements of diverse IoT deployments. The AIoT platform supports applications with rigorous demands for power efficiency and cost-effectiveness, ensuring swift time-to-market and reduced development cycles. With a collaborative ecosystem of package design, board evaluation, and software, it paves the way for innovative IoT solutions that seamlessly integrate advanced technologies into everyday devices.
ResQuant's Cyclone V FPGA with an integrated Post-Quantum Cryptography (PQC) processor is designed to provide a quantum-safe backbone for secure systems. Equipped with a complete set of NIST PQC cryptography suite, this FPGA offers straightforward integration with existing hardware and software architectures, particularly beneficial for validating quantum-secure applications. This FPGA solution provides a practical platform for testing and deploying post-quantum algorithms, making it a preferred choice for organizations looking to explore these next-gen security protocols. The integration of a PQC processor ensures that systems built on this FPGA can withstand potential quantum computing threats, securing data transmission and storage for future technologies. It's suitable for applications needing robust proof-of-concept validation of quantum-safe innovations, supporting an array of configurations for industry-specific applications. Given its comprehensive cryptography suite and integration capabilities, ResQuant's Cyclone V FPGA stands as a vital tool for security innovators paving the way to a quantum-resistant future.
Join the world's most advanced semiconductor IP marketplace!
It's free, and you'll get all the tools you need to discover IP, meet vendors and manage your IP workflow!
Join the world's most advanced AI-powered semiconductor IP marketplace!
It's free, and you'll get all the tools you need to advertise and discover semiconductor IP, keep up-to-date with the latest semiconductor news and more!
Plus we'll send you our free weekly report on the semiconductor industry and the latest IP launches!