All IPs > Security IP
Security IPs are an integral category within the semiconductor industry focusing on the protection of electronic data and hardware. As technological advancements continue to proliferate across critical sectors like finance, healthcare, and automotive, securing data and hardware has never been more paramount. Security IPs are designed to provide essential security features such as encryption, secure communications, and access control to safeguard sensitive information and devices from unauthorized access and cyber threats.
Within the Security IP category, you will find robust offerings that include both hardware and software-based solutions tailored to various security needs. Content Protection Software enables secure data transmission and protects digital content from piracy and unauthorized distribution. Cryptography Cores and Cryptography Software Libraries offer foundational tools for implementing strong encryption algorithms that are crucial for securing communications and data storage.
Embedded Security Modules are integrated within semiconductor devices to facilitate secure data processing and enhance trust in device operations by preventing code tampering and unauthorized hardware modification. Platform Security solutions encompass a broad range of protective measures designed to secure the entire hardware and software ecosystem, ensuring that devices are safe from potential vulnerabilities at every level.
Additionally, Security Protocol Accelerators and Security Subsystems act as dedicated processing units to efficiently handle complex security algorithms and protocols, enhancing the performance of security operations while reducing the burden on primary CPUs. With an unpredictable security landscape, leveraging a range of specialized Security IPs allows designers and engineers to build robust, secure, and reliable semiconductor solutions that can withstand evolving cyber threats.
The Akida Neural Processor IP by BrainChip is a versatile AI solution that melds neural processing capabilities with scalable digital architecture, delivering high performance with minimal power consumption. At its core, this processor is engineered using principles from neuromorphic computing to address the demands of AI workloads with precision and speed. By enabling efficient computations with sparse data, the Akida Neural Processor optimizes sparse data, weights, and activations, making it especially suitable for AI applications that demand real-time processing with low latency. It provides a flexible solution for implementing neural networks with varying complexities and is adaptable to a wide array of use cases from audio processing to visual recognition. The IP core’s configurable framework supports the execution of complex neural models on edge devices, effectively running sophisticated neural algorithms like Convolutional Neural Networks (CNNs) without the need for complementary computing resources. This standalone operation capability reduces dependency on external CPUs, driving down power consumption and liberating devices from constant network connections.
The Akida 2nd Generation processor further advances BrainChip's AI capabilities with enhanced programmability and efficiency for complex neural network operations. Building on the principles of its predecessor, this generation is optimized for 8-, 4-, and 1-bit weights and activations, offering more robust activation functions and support for advanced temporal and spatial neural networks. A standout feature of the Akida 2nd Generation is its enhanced teaching capability, which includes learning directly on the chip. This enables the system to perform one-shot and few-shot learning, significantly boosting its ability to adapt to new tasks without extensive reprogramming. Its architecture supports more sophisticated machine learning models such as Convolutional Neural Networks (CNNs) and Spatio-Temporal Event-Based Neural Networks, optimizing them for energy-efficient application at the edge. The processor's design reduces the necessity for host CPU involvement, thus minimizing communication overhead and conserving energy. This makes it particularly suitable for real-time data processing applications where quick and efficient data handling is crucial. With event-based hardware that accelerates processing, the Akida 2nd Generation is designed for scalability, providing flexible solutions across a wide range of AI-driven tasks.
Overview: Cybersecurity IPs offer a range of essential security features to protect your digital assets and sensitive information. From True Random Number Generators (TRNG) to advanced encryption algorithms like AES, DES, 3DES, and cryptographic hash functions like SHA, as well as RSA for secure key exchange and digital signatures, the IPs provide a comprehensive suite of tools to safeguard your data. Key Features: True Random Number Generator (TRNG): Generates unpredictable and unbiased random numbers for cryptographic applications. Advanced Encryption Standard (AES): Provides robust encryption with symmetric key algorithms for securing data. Data Encryption Standard (DES) and Triple DES (3DES): Implement legacy encryption algorithms for data protection. Hash Functions: Includes secure cryptographic hash functions like SHA (Secure Hash Algorithm) for data integrity verification. RSA: Enables secure key exchange, encryption, and digital signatures for secure communication. These cybersecurity IPs are designed to meet the stringent security requirements of modern applications, ensuring the confidentiality, integrity, and authenticity of your data.
Overview: The Secure Enclave IPs are Common Criteria (CC) EAL5+PP0084/PP0117 and EAL5+PP0117 certification-ready Secure Enclaves, respectively. They are available as hard macros for seamless integration into SoCs. These Secure Enclave IPs provide the highest level of security for an SoC, incorporating patented design techniques and countermeasures against side-channel and perturbation attacks to ensure robust security while minimizing power consumption. Key Features: Cryptographic Hardware Accelerators: Efficiently support standard cryptography and security operations to increase throughput while adhering to power constraints and security requirements. BootROM and Secondary Boot Loader: Manage the certified life cycle of the Secure Enclave, enforcing and assuring security from manufacturing to deployment. Proprietary IP: Based on proprietary IP that is free of 3rd party rights and royalties. Benefits: The Secure Enclave IPs offer robust security measures, efficient cryptographic support, and secure life cycle management, making them ideal for applications that require the highest levels of security and reliability. Applications: The Secure Enclave IP is versatile and suitable for a wide range of applications, including but not limited to: Secured and Certified iSIM & iUICC EMVco Payment Hardware Cryptocurrency Wallets FIDO2 Web Authentication V2X HSM Protocols Smart Car Access Secured Boot Secure OTA Firmware Updates Secure Debug Any design requiring a Secure Enclave, Secure Element, or Hardware Root of Trust protected against side-channel and perturbation fault attacks. Compliance and Support: The Secure Enclave is compliant with and ready for CC EAL5+ and EMVCo certification. It is delivered with an SDK and pre-certified CryptoLibrary and secure Boot Loader for seamless integration and enhanced security.
The AHB-Lite APB4 Bridge is a critical interconnect component that facilitates communication between AMBA 3 AHB-Lite and AMBA APB bus protocols. This soft IP is parametrically designed, allowing for optimized connections between an AHB-Lite bus master and a range of APB peripherals. Its architecture is focused on providing efficient, low-latency data transfer, supporting streamlined communication in complex SoC designs. Implementing this bridge in a system allows developers to seamlessly integrate a wide variety of peripheral devices, leveraging the simplicity and reduced resource demands of the APB protocol. The design is highly configurable, supporting various data widths and clock domains, enabling precise tailoring to fit the specific needs of any system. By using the AHB-Lite APB4 Bridge, designers can ensure comprehensive and efficient integration of peripherals into larger system-on-chip (SoC) designs, enhancing their functionality and performance.
KPIT Technologies offers comprehensive AUTOSAR solutions that are pivotal for the development of modern, adaptive automotive systems. Emphasizing middleware integration and E/E architecture transformation, their solutions simplify the complexities of implementing adaptive AUTOSAR platforms, enabling streamlined application development and expeditious vehicle deployment. With extensive experience in traditional and adaptive AUTOSAR ecosystems, KPIT assists OEMs in navigating the challenges associated with software-defined vehicles. Their expertise facilitates the separation of hardware and software components, which is crucial for the future of vehicle digital transformation. KPIT's middleware development capabilities enhance vehicle systems' robustness and scalability, allowing for seamless integration across various automotive applications and ensuring compliance with industry standards. By fostering strategic partnerships and investing in cutting-edge technology solutions, KPIT ensures that its clients can confidently transition to and maintain advanced AUTOSAR platforms. The company's commitment to innovation and excellence positions it as a trusted partner for automakers striving to stay ahead in the competitive automotive landscape by embracing the shift towards fully software-defined vehicles.
The Akida IP platform is a revolutionary neural processor inspired by the workings of the human brain to achieve unparalleled cognitive capabilities and energy efficiency. This self-contained neural processor utilizes a scalable architecture that can be configured from 1 to 128 nodes, each capable of supporting 128 MAC operations. It allows for the execution of complex neural network operations with minimal power and latency, making it ideal for edge AI applications in vision, audio, and sensor fusion. The Akida IP supports multiple data formats including 4-, 2-, and 1-bit weights and activations, enabling the seamless execution of various neural networks across multiple layers. Its convolutional and fully-connected neural processors can perform multi-layered executions independently of a host CPU, enhancing flexibility in diverse applications. Additionally, its event-based hardware acceleration significantly reduces computation and communication loads, preserving host CPU resources and optimizing overall system efficiency. Silicon-proven, the Akida platform provides a cost-effective and secure solution due to its on-chip learning capabilities, supporting one-shot and few-shot learning methods. By maintaining sensitive data on-chip, the system offers improved security and privacy. Its extensive configurability ensures adaptability for post-silicon applications, making Akida an intelligent and scalable choice for developers. It is especially suited for implementations that require real-time processing and sophisticated AI functionalities at the edge.
The RV12 RISC-V Processor is a highly adaptable single-core CPU that adheres to the RV32I and RV64I specifications of the RISC-V instruction set, aimed at the embedded systems market. This processor supports a variety of standard and custom configurations, making it suitable for diverse application needs. Its inherent flexibility allows it to be implemented efficiently in both FPGA and ASIC environments, ensuring that it meets the performance and resource constraints typical of embedded applications. Designed with an emphasis on configurability, the RV12 Processor can be tailored to include only the necessary components, optimizing both area and power consumption. It comes with comprehensive documentation and verification testbenches, providing a complete solution for developers looking to integrate a RISC-V CPU into their design. Whether for educational purposes or commercial deployment, the RV12 stands out for its robust design and adaptability, making it an ideal choice for modern embedded system solutions.
The AHB-Lite Multilayer Switch is a sophisticated interconnect solution designed to support multiple bus masters and slaves within an AMBA AHB-Lite system. It features high performance and low latency, facilitating efficient communication between various system components by providing a flexible interconnection fabric. This architecture can manage a significant number of simultaneous data transfers, optimizing the throughput in complex SoC environments. This switch fabric empowers designers to construct scalable systems with numerous processors and peripherals without compromising on speed or efficiency. Its configurability allows for tailored setups in terms of bus masters and slaves, supporting high-priority traffic schemes for enhanced system operations. By providing a robust and versatile solution, the AHB-Lite Multilayer Switch plays a crucial role in managing data flow, ensuring seamless operation across diverse embedded applications.
Overview: The Secure Boot IP is a turnkey solution that provides a secure boot facility for an SoC. It implements the Post Quantum secure Leighton-Micali Signature (LMS) as specified in NIST SP800-208. The Secure Boot IP operates as a master or slave peripheral to an Application Processor, serving as a secure enclave that securely stores keys to ensure their integrity and the integrity of the firmware authentication process. Features: Post Quantum Secure LMS Signature: Utilizes a robust Post-Quantum secure algorithm for enhanced security. Firmware Updates: Supports up to 32 thousand firmware updates with a minimal signature size of typically less than 5KBytes. SESIP Level 3 Pre-Certification: Pre-certified to SESIP Level 3 for added security assurance. RTL Delivery: Delivered as RTL for ease of integration into SoC designs. Proprietary IP: Based on proprietary IP with no 3rd party rights or royalties. Operation: The Secure Boot IP operates as a master, managing the boot process of the Application Processor to ensure that it only boots from and executes validated and authenticated firmware. The Secure Boot IP also functions as a slave peripheral, where the Application Processor requests validation of the firmware as part of its boot process, eliminating the need for managing keys and simplifying the boot process. Applications: The Secure Boot IP is versatile and suitable for a wide range of applications, including but not limited to: Wearables Smart/Connected Devices Metrology Entertainment Applications Networking Equipment Consumer Appliances Automotive Industrial Control Systems Security Systems Any SoC application that requires executing authenticated firmware in a simple but secure manner.
The AHB-Lite Timer is a robust timer module compliant with the RISC-V Privileged Specification 1.9.1, designed to provide precise timing and control within a system. This module is an integral part of complex SoC designs where accurate timing functions are essential. Its design offers flexibility and precision, making it ideal for a range of applications that demand reliable timekeeping and event management. The timer supports various counting modes and functions, allowing users to define cycles and generate interrupts based on time-based events. Its versatility and adaptability make it an indispensable component in managing scheduling and timing tasks within embedded systems. By integrating the AHB-Lite Timer, designers can enhance system efficiency and performance, ensuring responsive and accurate operational outcomes.
aiWare is engineered as a high-performance neural processing unit tailored for automotive AI applications, delivering exceptional power efficiency and computational capability across a broad spectrum of neural network tasks. Its design centers around achieving the utmost efficiency in AI inference, providing flexibility and scalability for various levels of autonomous driving, from basic L2 assistance systems to complex L4 self-driving operations. The aiWare architecture exemplifies leading-edge NPU efficiencies, reaching up to 98% across diverse neural network workloads like CNNs and RNNs, making it a premier choice for AI tasks in the automotive sector. It boasts an industry-leading 1024 TOPS capability, making it suitable for multi-sensor and multi-camera setups required by advanced autonomous vehicle systems. The NPU's hardware determinism aids in achieving high ISO 26262 ASIL B certification standards, ensuring it meets the rigorous safety specifications essential in automotive applications. Incorporating an easy-to-integrate RTL design and a comprehensive SDK, aiWare simplifies system integration and accelerates development timelines for automotive manufacturers. Its highly optimized dataflow and minimal external memory traffic significantly enhance system power economy, providing crucial benefits in reducing operational costs for deployed automotive AI solutions. Vibrant with efficiency, aiWare assures OEMs the capabilities needed to handle modern automotive workloads while maintaining minimal system constraints.
Polar ID is a groundbreaking biometric security solution designed for smartphones, providing a secure and convenient face unlock feature. Employing advanced meta-optic technology, Polar ID captures the polarization signature of a human face, offering an additional layer of security that easily identifies human tissue and foils sophisticated 3D mask attempts. This technology enables ultra-secure facial recognition in diverse environments, from daylight to complete darkness, without compromising on the user experience. Unlike traditional facial recognition systems, Polar ID operates using a simple, compact design that eliminates the need for multiple optical modules. Its unique capability to function in any lighting condition, including bright sunlight or total darkness, distinguishes it from conventional systems that struggle under such scenarios. Furthermore, the high resolution and precision of Polar ID ensure reliable performance even when users have their face partially obscured by sunglasses or masks. With its cost-effectiveness and small form factor, Polar ID is set to disrupt the mobile device market by making secure biometric authentication accessible to a broader range of smartphones, not just high-end models. By simplifying the integration of facial recognition technology, Polar ID empowers mobile devices to replace less secure, inconvenient fingerprint sensors, thus broadening the reach and applicability of facial biometrics in consumer electronics.
The SiFive Intelligence X280 is designed to address the burgeoning needs of AI and machine learning at the edge. Emphasizing a software-first methodology, this family of processors is crafted to offer scalable vector and matrix compute capabilities. By integrating broad vector processing features and high-bandwidth interfaces, it can adapt to the ever-evolving landscape of AI workloads, providing both high performance and efficient scalability. Built on the RISC-V foundation, the X280 features comprehensive vector compute engines that cater to modern AI demands, making it a powerful tool for edge computing applications where space and energy efficiency are critical. Its versatility allows it to seamlessly manage diverse AI tasks, from low-latency inferences to complex machine learning models, thanks to its support for RISC-V Vector Extensions (RVV). The X280 family is particularly robust for applications requiring rapid AI deployment and adaptation like IoT devices and smart infrastructure. Through extensive compatibility with machine learning frameworks such as TensorFlow Lite, it ensures ease of deployment, enhanced by its focus on energy-efficient inference solutions and support for legacy systems, making it a comprehensive solution for future AI technologies.
Up to 1M KeyEnc/sec with improved power efficiency PQPerform-Lattice is a powerful hardware-based product designed for high throughput, high-performance, and high speed. It adds post-quantum cryptography for applications that typically handle a large number of transactions, such as high-capacity network hardware applications and secure key management HSMs. Optimizable for secure boot, as well as other use-cases, PQPerform-Lattice supports FIPS 204 ML-DSA for quantum-secure digital signature verification, as well as FIPS 203 ML-KEM for quantum key exchange. PQPerform-Lattice supports AXI4, PCIe, and is deployable in multiple instances, making it a powerful solution for existing systems and infrastructure requirements.
The AES-XTS core is optimized for encryption of storage devices, providing advanced data protection by implementing the AES-XTS mode. XTS-AES is specifically designed for encrypting data storage, such as hard drives and SSDs, ensuring that sensitive information remains secure and inaccessible to unauthorized users. This core delivers high-speed encryption and decryption capabilities, making it ideal for disk encryption applications where performance is a critical factor. It adheres to the IEEE P1619 standard, which outlines the AES consistency in securing data at rest. By employing the AES-XTS core, storage devices can achieve comprehensive protection against data breaches, safeguarding important data across various storage media in personal computers, corporate databases, and portable external devices, ensuring data security and regulatory compliance.
PUFrt stands as a flagship hardware root of trust solution, incorporating PUF technology to create a unique and unclonable UID directly on the chip. This ensures robust security from the ground up, offering features such as TRNG, secure OTP, and an attack-resistant shell. The architecture of PUFrt provides a resilient foundation for semiconductor devices, helping to mitigate reverse engineering and counterfeiting risks. It integrates seamlessly with various systems, offering a trusted base for lightweight hardware security keys and full-function security coprocessors.
This H.264 FPGA Encoder and CODEC Micro Footprint Core is engineered to achieve minimal latency and compact size when deployed in FPGA environments. It is customizable and ITAR compliant, providing robust 1080p60 H.264 Baseline support on a single core. Known for its remarkable speed and small footprint, this core adapts to various configurations, including complete H.264 encoders and I-Frame Only variations, supporting custom pixel depths and unique resolutions. The core's design focuses on reducing latency to a mere 1 millisecond at 1080p30, setting a high industry standard for performance. Flexibility in deployment allows this core to meet bespoke requirements, offering significant value for customer-specific applications. It stands as a versatile solution for applications demanding high-speed video processing while maintaining compliance with industry standards. Supporting a variety of FPGA platforms, the core is especially valuable in environments where space and power constraints are crucial. Its adaptability, combined with A2e's integration capabilities, ensures seamless incorporation into existing systems, bolstering performance and development efficiency.
D2D® Technology, developed by ParkerVision, is a revolutionary approach to RF conversion that transforms how wireless communication operates. This technology eliminates traditional intermediary stages, directly converting RF signals to digital data. The result is a more streamlined and efficient communication process that reduces complexity and power consumption. By bypassing conventional analog-to-digital conversion steps, D2D® achieves higher data accuracy and reliability. Its direct conversion approach not only enhances data processing speeds but also minimizes energy usage, making it an ideal solution for modern wireless devices that demand both performance and efficiency. ParkerVision's D2D® technology continues to influence a broad spectrum of wireless applications. From improving the connectivity in smartphones and wearable devices to optimizing signal processing in telecommunication networks, D2D® is a cornerstone of ParkerVision's technological offerings, illustrating their commitment to advancing communication technology through innovative RF solutions.
CrossBar's ReRAM Memory technology introduces a revolutionary approach to non-volatile memory that transcends the limitations of traditional memory solutions. ReRAM, or Resistive RAM, distinguishes itself through its simple architectural design, enabling manufacturers to scale it down to sizes smaller than 10nm and integrate it seamlessly with existing logic processes in a single foundry. This advancement allows for unprecedented energy efficiency, with ReRAM consuming just 1/20th of the energy compared to traditional flash memory solutions, while also offering dramatically improved endurance and performance metrics. The scalability of ReRAM supports high-density memory applications, including its potential for 3D stacking, which allows terabytes of storage to be integrated on-chip. ReRAM excels in delivering low latency and high-speed operations, making it especially suitable for applications requiring rapid data access and processing, such as in data centers and IoT devices. Its robust performance characteristics make it an ideal solution for modern computing demands, offering both hard macros and architectural licenses depending on customer needs. Another key benefit of ReRAM is enhanced security, essential in applications ranging from automotive to secure computing. By providing low power consumption combined with high data integrity, ReRAM is positioned as a pivotal technology in future-proofing data storage solutions. It has proven to be a secure alternative to flash memory, with superior operational characteristics that address the diverse needs of contemporary electronic and computing environments.
Trilinear Technologies' HDCP Encryption-Decryption Engine is a sophisticated solution designed to safeguard digital content as it traverses various transmission channels. This engine is compliant with the HDCP standards 1.4 and 2.3, offering robust protection mechanisms to ensure that digital media investments are secure from unauthorized access and piracy. The engine’s hardware acceleration capabilities represent a crucial advantage, significantly reducing the load on the system processor while maintaining real-time encryption and decryption functions. This not only enhances performance but also extends the operational life of the hardware involved, making it suitable for high-demand media applications across sectors such as broadcast, entertainment, and corporate environments. Trilinear’s HDCP Encryption-Decryption Engine ensures compatibility with a wide array of consumer and professional-grade video equipment, providing seamless protection without interference in media quality or transmission speed. Its flexible integration options allow it to be smoothly incorporated into existing infrastructures, whether in standalone media devices or complex SoC architectures. Supported by comprehensive software resources, the HDCP Encryption-Decryption Engine provides an all-encompassing solution that includes necessary software stacks for managing device authentication and link maintenance. Its ability to safeguard high-definition content effectively makes it an invaluable asset for entities focused on secure content delivery and rights management.
eSi-Crypto provides advanced features in encryption and authentication, offering an impressive suite of solutions including True Random Number Generators (TRNGs), cryptographic processing, and Public Key Acceleration. Engineered to optimize resource usage without compromising throughput, it is designed to secure devices effectively in various critical applications.
Engineered for high-performance mobile graphics, the IMG DXT GPU provides advanced capabilities such as real-time ray tracing and scalable performance. This GPU's architecture is designed to cater to premium mobile devices, ensuring both graphical fidelity and power efficiency. With its scalable Ray Acceleration Cluster, it offers multiple configurations to tailor performance and cost, making it suitable for flagship mobile platforms seeking premium visual output while maintaining energy efficiency.
Securyzr iSSP is an advanced security lifecycle management solution, designed to offer seamless integration of security features throughout the device lifecycle. It provides a comprehensive platform for managing security tasks such as provisioning, firmware updates, security monitoring, and device identity management. The iSSP is built to facilitate zero-touch security lifecycle services, ensuring robust protection against potential cyber threats from chip to cloud. It stands out with its ability to handle post-quantum cryptography (PQC), making it future-ready and capable of addressing upcoming security challenges in an evolving digital landscape.
FIPS 140-3 CMVP compliant, CAVP PQC cryptographic library designed for PQ/T Hybrid PQCryptoLib is a general-purpose FIPS 140-3 CMVP and CAVP-certified cryptographic library. It’s been designed for a wide variety of applications and provides the latest NIST-standardized post-quantum and classical algorithms in a software environment. With a configurable, secure, and easy-to-use API, PQCryptoLib is optimized for crypto-agility, particularly when it comes to FIPS-compliant hybrid PQ/T solutions, and with crypto-agility in mind, it’s built to protect against the threat of ‘harvest-now-decrypt-later’ attacks. The aim of PQCryptoLib is to help organizations transition smoothly and securely to quantum resistance in a manageable, easy-to-integrate solution.
The Aeonic Integrated Droop Response System addresses droop issues in complex integrated circuits by combining mitigation and detection mechanisms in a seamlessly integrated package. This system supports fine-grained DVFS capability and rapid adaptation, providing significant power savings for SoCs. It offers comprehensive observability tools crucial for modern silicon health management, including multi-threshold detection and rapid response features within just a few clock cycles. This integration promotes energy efficiency by reducing voltage margins and supports various process technologies through a process portable design.
The Cyclone V FPGA with Integrated PQC Processor by ResQuant is a specialized product that comes pre-equipped with a comprehensive NIST PQC cryptography suite. This FPGA is tailored for applications requiring a robust proof-of-concept for quantum-safe implementations. It ensures seamless integration into existing systems, providing a practical platform for testing and deployment in quantum-secure environments. This product is available at a competitive price and represents an ideal starting point for entities looking to explore and adopt quantum-resilient technologies. Its configuration allows for straightforward implementation in diverse hardware infrastructures while offering a reliable option for organizations aiming to stay ahead in the evolving cyber security landscape. By incorporating the latest in cryptographic standards and ensuring vendor independence, the Cyclone V FPGA with Integrated PQC Processor by ResQuant effectively bridges current hardware technologies and future-proof security needs. It supports industry-wide applications, from IoT and ICT to automotive and military sectors, underscoring ResQuant's versatility in hardware security solutions.
DolphinWare IPs is a versatile portfolio of intellectual property solutions that enable efficient SoC design. This collection includes various control logic components such as FIFO, arbiter, and arithmetic components like math operators and converters. In addition, the logic components span counters, registers, and multiplexers, providing essential functionalities for diverse industrial applications. The IPs in this lineup are meticulously designed to ensure data integrity, supported by robust verification IPs for AXI4, APB, SD4.0, and more. This comprehensive suite meets the stringent demands of modern electronic designs, facilitating seamless integration into existing design paradigms. Beyond their broad functionality, DolphinWare’s offerings are fundamental to applications requiring specific control logic and data integrity solutions, making them indispensable for enterprises looking to modernize or expand their product offerings while ensuring compliance with industry standards.
Highly-optimized PQC implementations, capable of running PQC in < 15kb RAM PQCryptoLib-Emebedded is a versatile, CAVP-compliant version of PQCryptoLib, PQShield’s CMVP-certified library of post-quantum cryptographic algorithms. With its design focused on ultra-small area efficiency, PQCryptoLib-Embedded has been specifically designed for embedded systems, microcontrollers and memory-constrained devices. It could be the first step towards a hardware solution for providing PQC integration to devices already in the field.
FIPS 140-3 CAVP-compliant, compact lattice-based hardware PQC engine PQPlatform-Lattice is a compact FIPS 140-3 CAVP-compliant, PQC engine that adds post-quantum support for hardware components and embedded devices, using lattice-based cryptographic algorithms such as ML-KEM (FIPS 203) for post-quantum key exchange, and ML-DSA (FIPS 204) – post-quantum digital signature verification. It provides secure acceleration of lattice-based PQC alongside support for traditional cryptography. Its use cases include strong user authentication, protecting hardware keys, and small-footprint, configurable side-channel protection. PQPlatform-Lattice is designed for minimal area as well as maximum compatibility and can be deployed with optional firmware-backed side-channel countermeasures. It is covered by multiple PQShield implementation patents.
The 802.11 LDPC is a high-throughput solution designed for efficient wireless communication. This product supports frame-to-frame, on-the-fly configurations, offering flexibility in decoding iterations to balance throughput and error correction. It is engineered to conform to necessary performance specifications, ensuring optimal bit-error-rate and packet-error-rate performance in wireless networks. Functionality-wise, the design excels in meeting demanding throughput requirements while maintaining superior error correction capabilities. By allowing flexible configuration of LDPC decoding iterations, the product empowers users to tailor performance based on specific needs. This flexibility is essential for networks requiring dynamic adaptation to changing conditions or varying environmental factors. Technically, the 802.11 LDPC is crafted to integrate seamlessly into existing communication infrastructures, providing robust support for maintaining high data rates even under challenging conditions. Its unique ability to balance performance and energy efficiency makes it a preferred choice for modern wireless applications, strengthening connectivity reliability across multiple devices and environments.
The HOTLink II Core provides a complete layer 2 hardware implementation for high-speed interconnects. It is designed for full-rate, half-rate, and quarter-rate operations, making it versatile for various high-speed communication applications. With its F-18 compatible interface, it offers straightforward integration of frame-level interfaces, supporting high-speed signaling across devices.
Post-quantum Software Development Kit Provides easy-to-use software implementations of both post-quantum and classical cryptographic primitives. It’s designed with prototyping and experimentation in mind, consisting of an integration of PQShield’s PQCryptoLib library with two popular high-level cryptography libraries: OpenSSL and mbedTLS. OpenSSL: a widely-adopted secure-communication library mbedTLS: primarily intended for use in embedded system and IoT deployments
The Alcora V-by-One HS FMC daughter card by Parretto is a high-speed interface solution aimed at enhancing the connectivity of FPGA development boards with high-speed transceivers. By offering 8 RX and 8 TX lanes, the card facilitates high-throughput data transmission, supporting video resolutions such as 4K at 120Hz and 8K at 30Hz. Its dual-variant design, ranging from 41 to 51-pin headers, renders the card adaptable to diverse hardware setups, further broadening its compatibility. Additionally, two clock generators integrated within the card ensure precise synchronization by generating the necessary transceiver reference clocks and reducing jitter. This technology, developed by THine Electronics, finds its primary application in high-resolution video transmission within the flat panel display sector. The card's rich feature set and robust performance make it an ideal choice for industries demanding high-quality video output and seamless integration with existing FCA platforms.
ArrayNav is a groundbreaking GNSS solution utilizing patented adaptive antenna technology, crafted to provide automotive Advanced Driver-Assistance Systems (ADAS) with unprecedented precision and capacity. By employing multiple antennas, ArrayNav substantially enhances sensitivity and coverage through increased antenna gain, mitigates multipath fading with antenna diversity, and offers superior interference and jamming rejection capabilities. This advancement leads to greater accuracy in open environments and markedly better functionality within urban settings, often challenging due to signal interference. It is designed to serve both standalone and cloud-dependent use cases, thereby granting broad application flexibility.
The FPGA Pre-Trade Risk Check by Algo-Logic is designed for traders who demand real-time risk assessments before executing trades. By leveraging FPGA technology, this solution accelerates pre-trade checks by embedding them directly into hardware, reducing the typical delays encountered with software-based checks. This ensures that trades are both high-speed and secure, mitigating financial risks and protecting capital. Ideal for trading firms and exchanges, this solution upholds the integrity of high-frequency trading environments by performing rapid analysis and validation of trading orders.
The L5-Direct GNSS Receiver represents a sophisticated leap in positioning technology, offering a robust solution that directly captures L5-band signals, ensuring high precision in urban canyons and resilience to interference and jamming. This groundbreaking technology operates independently of the legacy L1 signals, utilizing innovative Application Specific Array Processor (ASAP) architecture to optimize signal processing for GNSS applications. The receiver's capabilities include support for a multitude of satellite constellations like GPS, Galileo, QZSS, and BeiDou, providing unmatched versatility and accuracy. Engineered for environments prone to signal disruption, the L5-direct receiver employs machine learning algorithms to effectively mitigate multipath errors, leveraging data from all GNSS signals. The result is a performance that ensures reliable location data, crucial for applications ranging from wearables and IoT devices to defense systems. This technology's design incorporates a single RF chain, reducing the overall size and cost while simplifying antenna integration and system complexity. In addition to its technological prowess, the L5-direct receiver offers scalable integration potential, from standalone ASICs to IP cores adaptable across various silicon processes. Through ongoing R&D and strategic partnerships with leading foundries such as TSMC and GlobalFoundries, oneNav ensures that this receiver not only meets current demands but also evolves with future GNSS innovations, maintaining a competitive edge in global positioning solutions.
The NMOS Control Platform developed by Nextera Video facilitates seamless integration and interoperability of ST 2110 devices across multi-vendor IP networks. This platform democratizes management and control, providing a robust framework compatible with a variety of processors. The NMOS standards are crucial in enabling straightforward discovery, registration, and connection management of media devices, a necessity for those seeking a streamlined IP-enabled production environment. This software-based core specializes in tasks essential to networked media systems, including device discovery (IS-04), connection management (IS-05), and event tally handling (IS-07). Its architecture supports audio channel mapping and secure communications through HTTPS and TLS, simplifying operations and enhancing device security. Its plug-and-play approach vastly reduces the complexity usually associated with integrating multi-manufacturer product systems. Recognized by leading industry bodies like the European Broadcasters Union, NMOS Control Software ensures interoperability and compliance with IP standards, making it a trusted solution for broadcast media facilities upgrading to IP-based setups. It supports operational efficiency by minimizing debugging and interoperability hurdles that are common in IP transition projects.
Fully autonomous, FIPS 140-3 CAVP compliant PQC subsystem PQPlatform-SubSys is a cryptographic subsystem, designed to provide offloaded cryptographic services with minimal integration effort and full autonomy from an existing security subsystem, as well as configurable side-channel protection. These services include post-quantum signature generation, verification, and secure key establishment. It’s built with optimal performance in mind, as well as crypto agility with its provision of traditional, PQ/T hybrid and fully post-quantum algorithms. PQPlatform-SubSys uses its built-in RISC-V CPU independently from the surrounding system, allowing cryptographic services to be offloaded efficiently from the system processor.
SphinX delivers high-performance encryption for data security with its AES-XTS standard encryption and decryption capabilities, providing independent and non-blocking channels for each process. This product offers robust protection against unauthorized data access and manipulation, cementing its position as a reliable security component in critical systems. Supporting independent channels allows SphinX to seamlessly manage multiple streams of data without latency bottlenecks, maintaining both security and operational efficiency. Designed for rigorous environments, it ensures data protection without undermining performance, making it indispensable for financial services, secure communications, and data-intensive industries. SphinX’s architecture is optimized to offer a balance between robust encryption and necessary computation speed, addressing niche market demands for efficient and scalable security solutions. It meets high-security standards whilst maintaining flexibility and resilience, accommodating modifications and enhancements in response to evolving security challenges.
The Individual IP Core Modules by ResQuant are comprehensive components engineered to support diverse post-quantum cryptographic standards, including Dilithium, Kyber, XMSS, SPHINCS+, AES, and the SHA-2 family. These modules offer organizations the flexibility to select specific cryptographic functionalities tailored to their security needs, without the necessity of entire systems or hardware changes. Each module is designed to integrate easily into existing infrastructure, ensuring minimal disruption while enhancing security measures against potential future quantum threats. This approach allows industries to gradually implement PQC standards, ensuring a seamless transition to quantum-resistant cryptographic measures. Tailored for flexibility, the ResQuant Individual IP Core Modules can be used across a wide array of applications, from IoT devices to complex military and IT systems. By offering component-level integration, these modules empower companies to future-proof their offerings incrementally while maintaining robust security practices in their operations.
Offering an efficient solution for lossless image compression, the JPEG-LS Encoder represents Parretto's dedication to high-performance design. This encoder implements the JPEG-LS standard—renowned for its superior performance in lossless compression without the excessive resource demand seen in alternatives like JPEG-2000. With capabilities to handle 8 to 16 bits image depths, it delivers leading compression results while maintaining a low requirement for additional computational resources, such as external memory. The encoder achieves impressive efficiency, performing encoding with less than one line of latency. Its flexible interface options, including pixel and data FIFO input/output and an Avalon Streaming interface, accommodate back-pressure, supporting one pixel per clock cycle. Additionally, configurable options for output data word width and sizes reaching ultra-high-definition ensure versatility in various applications.
SEMIFIVE's AIoT Platform is crafted to meet the evolving needs of the AI and IoT convergence. Aimed at enabling edge computing and connecting smart devices, this platform seamlessly integrates AI processing with IoT capabilities. It is ideal for developing efficient and responsive IoT solutions that require sophisticated AI integration. By utilizing advanced process nodes, the platform ensures that the solutions are not only powerful but also energy-efficient, supporting innovations in smart home technology, connected vehicles, and industrial IoT applications.
CrossBar's ReRAM IP cores offer high-performance, embedded non-volatile memory specifically designed for use in microcontrollers (MCU) and System-on-Chip (SoC) designs. These cores provide industry-leading performance for multi-time programmable (MTP) memory applications, emphasizing enhanced energy efficiency and low latency operations ideal for IoT devices, wearables, tablets, and smartphones. Supporting integration at process nodes beginning from 28nm and below, these IP cores ensure that designers can leverage ReRAM's superior memory characteristics without the need for additional costly integration processes. CrossBar's ReRAM technology not only surpasses current flash performance in terms of data integrity but also provides lower energy code execution and storage solutions. The technology supports from 2M bits (256K Bytes) to 256M bits (32M Bytes) in density, accommodating a vast range of storage needs. Additionally, the ReRAM IP cores are available as either hard macros or as architectural licenses, providing flexibility for integration into various SoC designs. Besides its application in non-volatile memory contexts, CrossBar's ReRAM also enables security-focused solutions using physical unclonable function (PUF) technology, further broadening its practical applications across secure computing domains. This versatility and high-performance delivery make ReRAM an attractive option for next-generation embedded systems, facilitating innovation in how memory interacts with other SoC components.
The SHA hashing core is designed to provide reliable and efficient data verification. It employs Secure Hash Algorithms (SHA) to generate distinct hash values from input data, ensuring data integrity and authentication. With its focus on high-speed operation and low resource usage, this core is ideal for environments requiring secure data handling. Supporting various SHA standards such as SHA-1, SHA-224, SHA-256, SHA-384, and SHA-512, this core caters to a wide range of cryptographic applications. It is instrumental in digital signatures, message authentication codes, and secure boot mechanisms. The implementation is optimized for both hardware and software applications, providing robust security measures essential for financial, governmental, and consumer electronics sectors needing secure data transactions and storage.
Secure Protocol Engines by Secure-IC are high-performance IP blocks designed to offload the intensive computational tasks of network and security processing from primary processors. These engines improve overall system efficiency by handling complex security protocols, ensuring that the main computing resources are available for critical applications. They are architected to provide robust protection against security breaches while ensuring swift data processing, maintaining the integrity, confidentiality, and availability of data across networks.
Featuring G15, this IP is optimized for 2KB correction blocks, suitable for NAND devices with larger page sizes, such as 8KB. The design is aligned with methods seen in the G14X, but it extends its reach with longer codewords for comprehensive coverage of high-density NAND. The design supports a wide array of block sizes and configurational setups, making it highly adaptable to varying design needs. Additional error correction capabilities can be integrated based on client requirements, reinforcing its bespoke delivery.
FIPS 140-3 CAVP-compliant, compact PQC hardware acceleration for subsystems PQPlatform-CoPro combines hash-based and lattice-based post-quantum cryptography that can be added to an existing security subsystem. It can be optimized for minimum area, maintaining high-performance, and is designed to be run by an existing CPU using PQShield-supplied firmware, meaning it involves low integration effort and flexible configurations to support a wide variety of use cases, including quantum-safe secure boot. Solutions are available for hardware acceleration of SHA-3, SHAKE, ML-KEM, ML-DSA, alongside traditional cryptography. In addition, PQPlatform-CoPro can be configured with side-channel protection. PQPlatform-CoPro is covered by multiple PQShield implementation patents.
The RISC-V CPU IP NS Class by Nuclei is specifically aimed at sectors requiring enhanced security and financial technology solutions. Built upon a versatile architecture, it is pivotal for applications in IoT security and payment systems. This processor IP leverages the RISC-V standard to offer customizable configurations, optimized through its Verilog-based development, to enhance readability and effectiveness in debugging, contributing to superior PPA performance. Nuclei’s NS Class equips developers with flexible tools to adapt the processor to varied system requirements, making use of extensive RISC-V extensions and the opportunity for user-defined instructions. The IP’s security features are robust, featuring TEE support and a physical security package, ensuring complete security for sensitive data. Additionally, it complies with functional safety standards such as ASIL-B and ASIL-D, which are crucial in environments requiring stringent safety compliance. In essence, the NS Class stands out for its ability to secure and optimize financial transactions and data protection in IoT applications. Its flexibility in configuration and comprehensive security measures make it a reliable choice for demanding and sensitive technology applications.
The Securyzr Key Management System offers a robust solution integrated into Secure-IC's security ecosystem to manage cryptographic keys effectively and securely. This system ensures that key generation, distribution, and storage processes are carried out in a highly secure manner, facilitating strong encryption and digital signature functions. Its integration into a wide range of devices guarantees secure communication and data handling across various applications, making it a critical component in safeguarding sensitive data.
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