All IPs > Security IP
Security IPs are an integral category within the semiconductor industry focusing on the protection of electronic data and hardware. As technological advancements continue to proliferate across critical sectors like finance, healthcare, and automotive, securing data and hardware has never been more paramount. Security IPs are designed to provide essential security features such as encryption, secure communications, and access control to safeguard sensitive information and devices from unauthorized access and cyber threats.
Within the Security IP category, you will find robust offerings that include both hardware and software-based solutions tailored to various security needs. Content Protection Software enables secure data transmission and protects digital content from piracy and unauthorized distribution. Cryptography Cores and Cryptography Software Libraries offer foundational tools for implementing strong encryption algorithms that are crucial for securing communications and data storage.
Embedded Security Modules are integrated within semiconductor devices to facilitate secure data processing and enhance trust in device operations by preventing code tampering and unauthorized hardware modification. Platform Security solutions encompass a broad range of protective measures designed to secure the entire hardware and software ecosystem, ensuring that devices are safe from potential vulnerabilities at every level.
Additionally, Security Protocol Accelerators and Security Subsystems act as dedicated processing units to efficiently handle complex security algorithms and protocols, enhancing the performance of security operations while reducing the burden on primary CPUs. With an unpredictable security landscape, leveraging a range of specialized Security IPs allows designers and engineers to build robust, secure, and reliable semiconductor solutions that can withstand evolving cyber threats.
Akida Neural Processor IP by BrainChip serves as a pivotal technology asset for enhancing edge AI capabilities. This IP core is specifically designed to process neural network tasks with a focus on extreme efficiency and power management, making it an ideal choice for battery-powered and small-footprint devices. By utilizing neuromorphic principles, the Akida Neural Processor ensures that only the most relevant computations are prioritized, which translates to substantial energy savings while maintaining high processing speeds. This IP's compatibility with diverse data types and its ability to form multi-layer neural networks make it versatile for a wide range of industries including automotive, consumer electronics, and healthcare. Furthermore, its capability for on-device learning, without network dependency, contributes to improved device autonomy and security, making the Akida Neural Processor an integral component for next-gen intelligent systems. Companies adopting this IP can expect enhanced AI functionality with reduced development overheads, enabling quicker time-to-market for innovative AI solutions.
The Akida 2nd Generation continues BrainChip's legacy of low-power, high-efficiency AI processing at the edge. This iteration of the Akida platform introduces expanded support for various data precisions, including 8-, 4-, and 1-bit weights and activations, which enhance computational flexibility and efficiency. Its architecture is significantly optimized for both spatial and temporal data processing, serving applications that demand high precision and rapid response times such as robotics, advanced driver-assistance systems (ADAS), and consumer electronics. The Akida 2nd Generation's event-based processing model greatly reduces unnecessary operations, focusing on real-time event detection and response, which is vital for applications requiring immediate feedback. Furthermore, its sophisticated on-chip learning capabilities allow adaptation to new tasks with minimal data, fostering more robust AI models that can be personalized to specific use cases without extensive retraining. As industries continue to migrate towards AI-powered solutions, the Akida 2nd Generation provides a compelling proposition with its improved performance metrics and lower power consumption profile.
Overview: Cybersecurity IPs offer a range of essential security features to protect your digital assets and sensitive information. From True Random Number Generators (TRNG) to advanced encryption algorithms like AES, DES, 3DES, and cryptographic hash functions like SHA, as well as RSA for secure key exchange and digital signatures, the IPs provide a comprehensive suite of tools to safeguard your data. Key Features:  True Random Number Generator (TRNG): Generates unpredictable and unbiased random numbers for cryptographic applications.  Advanced Encryption Standard (AES): Provides robust encryption with symmetric key algorithms for securing data.  Data Encryption Standard (DES) and Triple DES (3DES): Implement legacy encryption algorithms for data protection.  Hash Functions: Includes secure cryptographic hash functions like SHA (Secure Hash Algorithm) for data integrity verification.  RSA: Enables secure key exchange, encryption, and digital signatures for secure communication. These cybersecurity IPs are designed to meet the stringent security requirements of modern applications, ensuring the confidentiality, integrity, and authenticity of your data.
Akida IP represents BrainChip's groundbreaking approach to neuromorphic AI processing. Inspired by the efficiencies of cognitive processing found in the human brain, Akida IP delivers real-time AI processing capabilities directly at the edge. Unlike traditional data-intensive architectures, it operates with significantly reduced power consumption. Akida IP's design supports multiple data formats and integrates seamlessly with other hardware platforms, making it flexible for a wide range of AI applications. Uniquely, it employs sparsity, focusing computation only on pertinent data, thereby minimizing unnecessary processing and conserving power. The ability to operate independently of cloud-driven data processes not only conserves energy but enhances data privacy and security by ensuring that sensitive data remains on the device. Additionally, Akida IP’s temporal event-based neural networks excel in tracking event patterns over time, providing invaluable benefits in sectors like autonomous vehicles where rapid decision-making is critical. Akida IP's remarkable integration capacity and its scalability from small, embedded systems to larger computing infrastructures make it a versatile choice for developers aiming to incorporate smart AI capabilities into various devices.
Overview: The Secure Enclave IPs are Common Criteria (CC) EAL5+PP0084/PP0117 and EAL5+PP0117 certification-ready Secure Enclaves, respectively. They are available as hard macros for seamless integration into SoCs. These Secure Enclave IPs provide the highest level of security for an SoC, incorporating patented design techniques and countermeasures against side-channel and perturbation attacks to ensure robust security while minimizing power consumption. Key Features:  Cryptographic Hardware Accelerators: Efficiently support standard cryptography and security operations to increase throughput while adhering to power constraints and security requirements.  BootROM and Secondary Boot Loader: Manage the certified life cycle of the Secure Enclave, enforcing and assuring security from manufacturing to deployment.  Proprietary IP: Based on proprietary IP that is free of 3rd party rights and royalties. Benefits: The Secure Enclave IPs offer robust security measures, efficient cryptographic support, and secure life cycle management, making them ideal for applications that require the highest levels of security and reliability. Applications: The Secure Enclave IP is versatile and suitable for a wide range of applications, including but not limited to:  Secured and Certified iSIM & iUICC  EMVco Payment  Hardware Cryptocurrency Wallets  FIDO2 Web Authentication  V2X HSM Protocols  Smart Car Access  Secured Boot  Secure OTA Firmware Updates  Secure Debug  Any design requiring a Secure Enclave, Secure Element, or Hardware Root of Trust protected against side-channel and perturbation fault attacks. Compliance and Support: The Secure Enclave is compliant with and ready for CC EAL5+ and EMVCo certification. It is delivered with an SDK and pre-certified CryptoLibrary and secure Boot Loader for seamless integration and enhanced security.
The AHB-Lite APB4 Bridge is an adaptable soft interconnect bridge linking the AMBA 3 AHB-Lite protocol with the AMBA APB protocol. It facilitates seamless communication between these bus protocols, ensuring data transfers are conducted efficiently within an embedded system. This bridge supports parameterization, allowing engineers to configure it for their unique design needs, thereby improving system flexibility and performance in electronic projects.
The RV12 RISC-V Processor is a versatile single-core microprocessor that adheres to both the RV32I and RV64I RISC-V instruction sets. Designed primarily for the embedded market, this processor features a Harvard architecture that enables simultaneous instruction and data accesses, enhancing performance in computing tasks. As part of the Roa Logic CPU family, this processor is highly configurable, allowing users to adjust its parameters to fit specific application requirements, thus making it an excellent choice for technology developers seeking efficient custom solutions.
Roa Logic's AHB-Lite Multilayer Switch is engineered to provide high-performance, low-latency interconnectivity for AHB-Lite based systems. This switch supports numerous bus masters and slaves, facilitating robust data throughput across the system's architecture. By optimizing data traffic management, it enhances the overall efficiency of electronic devices that require complex data processing capabilities.
The aiWare hardware neural processing unit (NPU) stands out as a state-of-the-art solution for automotive AI applications, bringing unmatched efficiency and performance. Designed specifically for inference tasks associated with automated driving systems, aiWare supports a wide array of AI workloads including CNNs, LSTMs, and RNNs, ensuring optimal operation across numerous applications.\n\naiWare is engineered to achieve industry-leading efficiency rates, boasting up to 98% efficiency on automotive neural networks. It operates across various performance requirements, from cost-sensitive L2 regulatory applications to advanced multi-sensor L3+ systems. The hardware platform is production-proven, already implemented in several products like Nextchip's APACHE series and enjoys strong industry partnerships.\n\nA key feature of aiWare is its scalability, capable of delivering up to 1024 TOPS with its multi-core architecture, and maintaining high efficiency in diverse AI tasks. The design allows for straightforward integration, facilitating early-stage performance evaluations and certifications with its deterministic operations and minimal host CPU intervention.\n\nA dedicated SDK, aiWare Studio, furthers the potential of the NPU by providing a suite of tools focused on neural network optimization, supporting developers in tuning their AI models with fine precision. Optimized for automotive-grade applications, aiWare's technology ensures seamless integration into systems requiring AEC-Q100 Grade 2 compliance, significantly enhancing the capabilities of automated driving applications from L2 through L4.
Overview: The Secure Boot IP is a turnkey solution that provides a secure boot facility for an SoC. It implements the Post Quantum secure Leighton-Micali Signature (LMS) as specified in NIST SP800-208. The Secure Boot IP operates as a master or slave peripheral to an Application Processor, serving as a secure enclave that securely stores keys to ensure their integrity and the integrity of the firmware authentication process. Features:  Post Quantum Secure LMS Signature: Utilizes a robust Post-Quantum secure algorithm for enhanced security.  Firmware Updates: Supports up to 32 thousand firmware updates with a minimal signature size of typically less than 5KBytes.  SESIP Level 3 Pre-Certification: Pre-certified to SESIP Level 3 for added security assurance.  RTL Delivery: Delivered as RTL for ease of integration into SoC designs.  Proprietary IP: Based on proprietary IP with no 3rd party rights or royalties. Operation: The Secure Boot IP operates as a master, managing the boot process of the Application Processor to ensure that it only boots from and executes validated and authenticated firmware. The Secure Boot IP also functions as a slave peripheral, where the Application Processor requests validation of the firmware as part of its boot process, eliminating the need for managing keys and simplifying the boot process. Applications: The Secure Boot IP is versatile and suitable for a wide range of applications, including but not limited to:  Wearables  Smart/Connected Devices  Metrology  Entertainment Applications  Networking Equipment  Consumer Appliances  Automotive  Industrial Control Systems  Security Systems  Any SoC application that requires executing authenticated firmware in a simple but secure manner.
The SiFive Intelligence X280 processor targets applications in machine learning and artificial intelligence, offering a high-performance, scalable architecture for emerging data workloads. As part of the Intelligence family, the X280 prioritizes a software-first methodology in processor design, addressing future ML and AI deployment needs, especially at the edge. This makes it particularly useful for scenarios requiring high computational power close to the data source. Central to its capabilities are scalable vector and matrix compute engines that can adapt to evolving workloads, thus future-proofing investments in AI infrastructure. With high-bandwidth bus interfaces and support for custom engine control, the X280 ensures seamless integration with varied system architectures, enhancing operational efficiency and throughput. By focusing on versatility and scalability, the X280 allows developers to deploy high-performance solutions without the typical constraints of more traditional platforms. It supports wide-ranging AI applications, from edge computing in IoT to advanced machine learning tasks, underpinning its role in modern and future-ready computing solutions.
Roa Logic's AHB-Lite Timer is a timer module that adheres to the RISC-V Privileged 1.9.1 specification, designed for use in RISC-V compliant systems. This module offers reliable timing functions essential for task scheduling and precise time control in embedded applications, delivering dependable performance required in various electronic applications.
ReRAM Memory by CrossBar is designed to push the boundaries of storage technology, offering a high-performance, low-latency memory solution that is both scalable and energy-efficient. This memory technology boasts a radical structure that allows it to function distinctly from traditional memory. It is built to scale under 10nm and integrate seamlessly in 3D stackable architectures, which is ideal for future-proofing against the rising demands of data processing and storage. What sets ReRAM apart is its capability to deliver up to 1000 times the endurance of conventional memory solutions and greatly enhance read and write speeds. This is achieved by its simple yet robust structure, allowing it to be integrated with existing logic circuits without the need for specialized tools. ReRAM is particularly suitable for applications across various domains such as IoT, AI, data centers, and even newer consumer electronics, making it versatile and widely applicable. ReRAM provides a unique advantage in being directly integrated into modern fabrication processes, simplifying both production and deployment for manufacturers. This flexibility ensures that ReRAM can maintain high levels of performance while meeting the industry's stringent efficiency requirements. Moreover, it offers substantial opportunities to advance secure computing through innovative uses in secure keys and encryption functions.
The H.264 FPGA Encoder and CODEC Micro Footprint Cores from A2e Technologies is a highly customizable IP core designed specifically for FPGAs. This core is notable for its small size and high speed, capable of supporting 1080p60 H.264 Baseline video with a single core. Featuring exceptionally low latency, as little as 1ms at 1080p30, it offers a customizable solution for various video resolutions and pixel depths. These capabilities make it a competitive choice for applications requiring high-performance video compression with minimal footprint. Designed to be ITAR compliant and licensable, the H.264 core can be tailored to meet specific requirements, offering flexibility in video applications. This product is especially suitable for industries where space and performance are critical, such as defense and industrial controls. The core can work efficiently across a range of resolutions and color depths, providing the potential for integration into a wide array of devices and systems. The company's expertise ensures that this H.264 core is not only versatile but also comes with the option of a low-cost evaluation license, allowing potential users to explore its capabilities before committing fully. With A2e's strong support and integration services, customers have assurance that even complex design requirements can be met with experienced guidance.
The Polar ID system by Metalenz revolutionizes biometric security through its unique use of meta-optic technology. It captures the polarization signature of a human face, delivering a new level of security that can detect sophisticated 3D masks. Unlike traditional structured light technologies, which rely on complex dot-pattern projectors, Polar ID simplifies the module through a single, low-profile polarization camera that operates in near-infrared, ensuring functionality across varied lighting conditions and environments. Polar ID offers ultra-secure facial authentication capable of operating in both daylight and darkness, accommodating obstacles such as sunglasses and masks. This capability makes it particularly effective for smartphones and other consumer electronics, providing a more reliable and secure alternative to existing fingerprint and visual recognition technologies. By integrating smoothly into the most challenging smartphone designs, Polar ID minimizes the typical hardware footprint, making advanced biometric security accessible at a lower cost. This one-of-a-kind technology not only enhances digital security but also provides seamless user experiences by negating the need for multiple optical components. Its high resolution and accuracy ensure that performance is not compromised, safeguarding user authentication in real-time, even in adverse conditions. By advancing face unlock solutions, Polar ID stands as a future-ready answer to the rising demand for unobtrusive digital security in mainstream devices.
PUFrt stands as a flagship hardware root of trust solution, incorporating PUF technology to create a unique and unclonable UID directly on the chip. This ensures robust security from the ground up, offering features such as TRNG, secure OTP, and an attack-resistant shell. The architecture of PUFrt provides a resilient foundation for semiconductor devices, helping to mitigate reverse engineering and counterfeiting risks. It integrates seamlessly with various systems, offering a trusted base for lightweight hardware security keys and full-function security coprocessors.
Designed for secure disk encryption, Helion's AES-XTS cores leverage the robust AES-XTS algorithm, providing superior security at the sector level. By utilizing tweakable block ciphers, these cores enhance security against threats such as copy-and-paste attacks, while allowing for concurrent processing to boost performance. The AES-XTS core supports data rates exceeding 64Gbps, making it suitable for high-performance storage applications including disk encryption for enterprise servers. It can be configured to operate with dual keys (128-bit and 256-bit) and optionally support features like Ciphertext Stealing, ensuring versatility and robustness in varying storage environments. With specific designs targeting FPGAs and ASICs, Helion's AES-XTS solutions are optimized for the highest efficiency, minimizing logic area usage. These cores are crucial for organizations requiring reliable data encryption for storage media, such as hard drives and solid-state drives, where data protection is paramount.
Up to 1M KeyEnc/sec with improved power efficiency PQPerform-Lattice is a powerful hardware-based product designed for high throughput, high-performance, and high speed. It adds post-quantum cryptography for applications that typically handle a large number of transactions, such as high-capacity network hardware applications and secure key management HSMs. Optimizable for secure boot, as well as other use-cases, PQPerform-Lattice supports FIPS 204 ML-DSA for quantum-secure digital signature verification, as well as FIPS 203 ML-KEM for quantum key exchange. PQPerform-Lattice supports AXI4, PCIe, and is deployable in multiple instances, making it a powerful solution for existing systems and infrastructure requirements.
D2D® Technology, developed by ParkerVision, is a revolutionary approach to RF conversion that transforms how wireless communication operates. This technology eliminates traditional intermediary stages, directly converting RF signals to digital data. The result is a more streamlined and efficient communication process that reduces complexity and power consumption. By bypassing conventional analog-to-digital conversion steps, D2D® achieves higher data accuracy and reliability. Its direct conversion approach not only enhances data processing speeds but also minimizes energy usage, making it an ideal solution for modern wireless devices that demand both performance and efficiency. ParkerVision's D2D® technology continues to influence a broad spectrum of wireless applications. From improving the connectivity in smartphones and wearable devices to optimizing signal processing in telecommunication networks, D2D® is a cornerstone of ParkerVision's technological offerings, illustrating their commitment to advancing communication technology through innovative RF solutions.
Algo-Logic's FPGA Pre-Trade Risk Check is tailored for financial entities needing to assess risk in real-time before trade execution. This product implements risk assessment algorithms on FPGAs, enabling checks to be performed at the speeds necessary to keep pace with high-frequency trading. The integration on FPGA hardware ensures that pre-trade risk checks do not become bottlenecks and contribute to maintaining compliance with regulations while minimizing the latency typically associated with software-based checks.
The eSi-Crypto suite provides a comprehensive range of encryption and authentication functionalities catered for integration in both ASIC and FPGA targets. Designed with efficiency in mind, it offers low resource usage coupled with high throughput. This suite incorporates a high-grade True Random Number Generator (TRNG) compliant with NIST 800-22 standards. Available with standalone or AMBA APB/AHB/AXI bus interfaces, it supports a wide range of cryptographic algorithms such as CRYSTALS Kyber, Dilithium, ECDSA, RSA, AES, and SHA, providing robust security solutions adaptable to varying application needs.
The RISC-V Hardware-Assisted Verification by Bluespec is a high-performance platform designed for swift and precise verification of RISC-V cores. It supports testing at both the core level (ISA) and system level, accommodating RTOS and Linux-based environments. This solution can verify standard ISA extensions, custom ISA extensions, and integrated accelerators, making it a versatile tool for various verification needs. One of the standout features of this platform is its scalability and accessibility via the AWS cloud, which ensures that resources can be tapped into as needed, enabling efficient verification anytime, anywhere. Such scalability is crucial for teams that require the flexibility to test various designs without being confined to local server limitations. With an emphasis on broad compatibility, the RISC-V Hardware-Assisted Verification platform is ideal for those involved in developing RISC-V based systems. It assists developers in ensuring their designs are accurate and reliable before deployment, reducing errors and speeding up time-to-market.
CrossBar's ReRAM IP Cores for Embedded NVM are engineered to optimize the functionality of microcontrollers and System-on-Chip (SoC) designs. These cores are specially tailored for multi-time programmable (MTP) non-volatile memory applications across a range of devices, from IoT gadgets to industrial and automotive systems. By enhancing memory performance while reducing latency and energy consumption, these cores set a new standard for embedded system efficiency. The IP cores support process nodes starting at 28nm and can scale below 10nm, ensuring compatibility with contemporary semiconductor manufacturing processes. They provide customizable memory sizes from 2M bits to 256M bits, allowing for tailored solutions that meet specific application needs. The cores excel in low-energy code execution, making them ideal for devices that prioritize energy efficiency without compromising on performance. In addition to their utility in consumer electronics and smart devices, these ReRAM IP cores are equipped to enhance security functions, integrating secure keys into semiconductors to bolster data protection. Their scalability and versatility make them an excellent choice for developers seeking to integrate high-performance, non-volatile memory components into their silicon architectures.
aiData serves as a comprehensive automated data pipeline tailored specifically for the development of ADAS and autonomous driving technologies. This solution optimizes various stages of MLOps, from data capturing to curation, significantly reducing the traditional manual workload required for assembling high-quality datasets. By leveraging cutting-edge technologies for data collection and annotation, aiData enhances the reliability and speed of deploying AD models, fostering a more efficient flow of data between developers and data scientists.\n\nOne of the standout features of aiData is its versioning system that ensures transparency and traceability throughout the data lifecycle. This system aids in curating datasets tailored for specific use cases via metadata enrichment and SQL querying, supporting seamless data management whether on-premise or cloud. Additionally, the aiData Recorder is engineered to produce high-quality datasets by enabling precise sensor calibration and synchronization, crucial for advanced driving applications.\n\nMoreover, the Auto Annotator component of aiData automates the traditionally labor-intensive process of data annotation, utilizing AI algorithms to produce annotations that meet high accuracy standards. This capability, combined with the aiData Metrics tool, allows for comprehensive validation of datasets, ensuring that they correctly reflect real-world conditions. Collectively, aiData empowers automotive developers to refine neural network algorithms and enhance detection software, accelerating the journey from MLOps to production.
The L5-Direct GNSS Receiver from oneNav, Inc. is a revolutionary product designed to engage directly with L5-band signals, a step away from the reliance on older L1 signals. This GNSS receiver captures signals directly in the L5-band, providing a superior solution that addresses the growing issue of GPS signal jamming, creating significant value for users including defense agencies and OEMs. It boasts unique features such as multi-constellation support, which allows users to access over 70 satellite signals from major constellations like GPS, Galileo, QZSS, and BeiDou. The L5-Direct technology integrates a single RF chain, simplifying design and improving efficiency, making it ideal for applications where space and cost are critical. The technology employs machine learning algorithms to mitigate multipath errors, an innovative approach that elevates accuracy by differentiating between direct and reflected signals in challenging terrains. This level of precision and independence from legacy signals captures the essence of what oneNav stands for. Additionally, the receiver's power efficiency is unmatched, thanks to the Application Specific Array Processor (ASAP), which manages processing speed to conserve energy. Its design is particularly advantageous for wearables, IoT devices, and systems requiring constant location tracking, ensuring a minimal power footprint while delivering consistent, accurate data. The L5-Direct GNSS Receiver is also built to withstand disruptions, with significant resilience to jamming and improved consistency in GPS-challenged environments.
Trilinear Technologies' HDCP Encryption-Decryption Engine is a sophisticated solution designed to safeguard digital content as it traverses various transmission channels. This engine is compliant with the HDCP standards 1.4 and 2.3, offering robust protection mechanisms to ensure that digital media investments are secure from unauthorized access and piracy. The engine’s hardware acceleration capabilities represent a crucial advantage, significantly reducing the load on the system processor while maintaining real-time encryption and decryption functions. This not only enhances performance but also extends the operational life of the hardware involved, making it suitable for high-demand media applications across sectors such as broadcast, entertainment, and corporate environments. Trilinear’s HDCP Encryption-Decryption Engine ensures compatibility with a wide array of consumer and professional-grade video equipment, providing seamless protection without interference in media quality or transmission speed. Its flexible integration options allow it to be smoothly incorporated into existing infrastructures, whether in standalone media devices or complex SoC architectures. Supported by comprehensive software resources, the HDCP Encryption-Decryption Engine provides an all-encompassing solution that includes necessary software stacks for managing device authentication and link maintenance. Its ability to safeguard high-definition content effectively makes it an invaluable asset for entities focused on secure content delivery and rights management.
Helion's SHA Hashing cores are robust solutions for cryptographic integrity verification, supporting SHA-1, SHA-2, and MD5 algorithms. Designed for creating a secure, fixed-length hash from input data, these cores are pivotal in digital signatures and data integrity protocols. SHA Hashing from Helion is renowned for its high-speed performance, offering both FAST and TINY modes. These cores ensure that any alteration in the input data results in a different hash, making them indispensable for data integrity and security measures across various applications. The flexibility of Helion’s SHA Hashing solutions makes them suitable for diverse technological environments, whether in FPGAs or ASICs. The integrity assurance provided by these cores is crucial in fields such as secure communications and data verification, supporting protocols like SSL/TLS and IPsec.
Post-quantum Software Development Kit Provides easy-to-use software implementations of both post-quantum and classical cryptographic primitives. It’s designed with prototyping and experimentation in mind, consisting of an integration of PQShield’s PQCryptoLib library with two popular high-level cryptography libraries: OpenSSL and mbedTLS. OpenSSL: a widely-adopted secure-communication library mbedTLS: primarily intended for use in embedded system and IoT deployments
The Aeonic Integrated Droop Response System addresses droop issues in complex integrated circuits by combining mitigation and detection mechanisms in a seamlessly integrated package. This system supports fine-grained DVFS capability and rapid adaptation, providing significant power savings for SoCs. It offers comprehensive observability tools crucial for modern silicon health management, including multi-threshold detection and rapid response features within just a few clock cycles. This integration promotes energy efficiency by reducing voltage margins and supports various process technologies through a process portable design.
Microdul's Human Body Detector for Ultra-Low-Power is designed to detect proximity and presence with minimal energy consumption. Its efficient power usage extends the operational life of battery-driven devices, making it ideal for wearable technology. The device functions effectively in both dynamic and static modes, facilitating reduced power draw when the device is not actively being worn. This attention to power conservation makes the Human Body Detector a vital component for maintaining energy efficiency in modern electronic applications.
The AON1100 offers a sophisticated AI solution for voice and sensor applications, marked by a remarkable power usage of less than 260μW during processing yet maintaining high levels of accuracy in environments with sub-0dB SNR. It is a leading option for always-on devices, providing effective solutions for contexts requiring constant machine listening ability.\n\nThis AI chip excels in processing real-world acoustic and sensor data efficiently, delivering up to 90% accuracy by employing advanced signal processing techniques. The AON1100's low power requirements make it an excellent choice for battery-operated devices, ensuring sustainable functionality through efficient power consumption over extended operational periods.\n\nThe scalability of the AON1100 allows it to be adapted for various applications, including smart homes and automotive settings. Its integration within broader AI platform strategies enhances intelligent data collection and contextual understanding capabilities, delivering transformative impacts on device interactivity and user experience.
FIPS 140-3 CAVP-compliant, compact lattice-based hardware PQC engine PQPlatform-Lattice is a compact FIPS 140-3 CAVP-compliant, PQC engine that adds post-quantum support for hardware components and embedded devices, using lattice-based cryptographic algorithms such as ML-KEM (FIPS 203) for post-quantum key exchange, and ML-DSA (FIPS 204) – post-quantum digital signature verification. It provides secure acceleration of lattice-based PQC alongside support for traditional cryptography. Its use cases include strong user authentication, protecting hardware keys, and small-footprint, configurable side-channel protection. PQPlatform-Lattice is designed for minimal area as well as maximum compatibility and can be deployed with optional firmware-backed side-channel countermeasures. It is covered by multiple PQShield implementation patents.
AES-GCM cores by Helion stand as a high-performance solution, offering both encryption and authentication within a single, efficient framework. The Galois Counter Mode (GCM) is particularly well-suited for high-speed applications due to its pipeline compatibility and parallel processing capabilities. This makes it ideal for modern networking protocols demanding swift data processing and high security. Helion AES-GCM supports data rates ranging from below 50Mbps to over 40Gbps, ensuring they cater to both low and high bandwidth requirements. Its adaptability across different FPGA and ASIC technologies guarantees optimized performance tailored to client-specific needs, with options for ultra-compact implementations when space and power are of concern. This core is heavily utilized in data transmission where data integrity and privacy must be maintained without the typical throughput sacrifices inherent to traditional encryption methods. Its deployment in MACsec, IPsec, and other security protocols underscore its integral role in maintaining data security across various sectors.
The Cyclone V FPGA with Integrated PQC Processor by ResQuant is a specialized product that comes pre-equipped with a comprehensive NIST PQC cryptography suite. This FPGA is tailored for applications requiring a robust proof-of-concept for quantum-safe implementations. It ensures seamless integration into existing systems, providing a practical platform for testing and deployment in quantum-secure environments. This product is available at a competitive price and represents an ideal starting point for entities looking to explore and adopt quantum-resilient technologies. Its configuration allows for straightforward implementation in diverse hardware infrastructures while offering a reliable option for organizations aiming to stay ahead in the evolving cyber security landscape. By incorporating the latest in cryptographic standards and ensuring vendor independence, the Cyclone V FPGA with Integrated PQC Processor by ResQuant effectively bridges current hardware technologies and future-proof security needs. It supports industry-wide applications, from IoT and ICT to automotive and military sectors, underscoring ResQuant's versatility in hardware security solutions.
The Universal DSP Library is a versatile and comprehensive solution designed to simplify digital signal processing tasks in FPGA applications. It provides a robust framework for handling complex signal processing requirements, enabling developers to integrate advanced DSP functionalities efficiently into their systems. This library is crafted to offer flexibility and adaptability, supporting a wide range of applications in various industries. This DSP library stands out for its ability to handle diverse signal processing operations with ease. By offering pre-built functions and modules, it reduces the complexity traditionally associated with DSP implementation in FPGA designs. Developers can leverage this library to accelerate their development cycles, ensuring quicker time-to-market for their products. Incorporating the Universal DSP Library into an FPGA design allows for enhanced performance and efficiency, as it optimizes the processing power of FPGAs to manage demanding signal processing tasks. Its design enables seamless integration with existing systems, providing scalable solutions that can adapt to future needs. Overall, this library is an invaluable asset for any project involving digital signal processing on FPGA platforms.
The RISC-V CPU IP NS Class is specifically engineered for security-focused applications, including fintech mobile payments and IoT security. This architecture supports a variety of security protocols, making it ideal for systems that require robust data protection and secure transaction handling. It features a background in efficiently managing sensitive information, supporting comprehensive information security solutions with strong cryptographic capabilities. This IP is built with RISC-V's flexible extensions, ensuring files and communication streams maintain confidentiality and integrity in diverse operational scenarios. Robust by design, the NS Class caters to sectors such as IoT, where data protection is paramount, making it a trusted choice for developers seeking to enforce stringent security measures into their solutions. With options for extending functionality and increasing resilience through user-defined instructions, the NS Class remains adaptable for future security requirements.
ArrayNav is a groundbreaking GNSS solution utilizing patented adaptive antenna technology, crafted to provide automotive Advanced Driver-Assistance Systems (ADAS) with unprecedented precision and capacity. By employing multiple antennas, ArrayNav substantially enhances sensitivity and coverage through increased antenna gain, mitigates multipath fading with antenna diversity, and offers superior interference and jamming rejection capabilities. This advancement leads to greater accuracy in open environments and markedly better functionality within urban settings, often challenging due to signal interference. It is designed to serve both standalone and cloud-dependent use cases, thereby granting broad application flexibility.
The Individual IP Core Modules by ResQuant are comprehensive components engineered to support diverse post-quantum cryptographic standards, including Dilithium, Kyber, XMSS, SPHINCS+, AES, and the SHA-2 family. These modules offer organizations the flexibility to select specific cryptographic functionalities tailored to their security needs, without the necessity of entire systems or hardware changes. Each module is designed to integrate easily into existing infrastructure, ensuring minimal disruption while enhancing security measures against potential future quantum threats. This approach allows industries to gradually implement PQC standards, ensuring a seamless transition to quantum-resistant cryptographic measures. Tailored for flexibility, the ResQuant Individual IP Core Modules can be used across a wide array of applications, from IoT devices to complex military and IT systems. By offering component-level integration, these modules empower companies to future-proof their offerings incrementally while maintaining robust security practices in their operations.
QUIC Protocol Core is engineered to handle high-speed data transmission efficiently, making it suitable for environments prone to network congestion and packet loss. By eschewing traditional TCP/IP methods, this core delivers up to 400 times the performance improvement, ensuring data transfers are both secure and swift. The core is particularly adept in FPGA environments, offering low memory footprint and high data processing capabilities. It provides the essential high-level security via integrated TLS 1.3, supporting robust encryption throughout its operation.
The JPEG-LS Encoder core from Parretto is designed to provide superior lossless image compression, compliant with the JPEG-LS standard, known for its efficacy in reducing data without compromising image integrity. Adhering to the ISO/IEC 14495-1 and ITU-T Rec. T.87 specifications, this encoder surpasses JPEG-2000 in many cases due to its minimal resource requirements and negligible latency. It delivers remarkable compression performance for images with sample depths ranging from 8 to 16 bits, and operates with less than one line of encoding latency, eliminating the need for external memory. The core is capable of processing one pixel per clock cycle and offers configurable output data word widths to tailor to specific image processing tasks. This encoder ensures seamless data flow with its pixel and FIFO data interfaces, or alternatively, through an Avalon Streaming interface equipped with back-pressure support. It is suitable for high-resolution image processing up to ultra-high-definition levels, making it a flexible and effective solution for a wide range of imaging applications.
FIPS 140-3 CAVP-compliant, compact PQC hardware acceleration for subsystems PQPlatform-CoPro combines hash-based and lattice-based post-quantum cryptography that can be added to an existing security subsystem. It can be optimized for minimum area, maintaining high-performance, and is designed to be run by an existing CPU using PQShield-supplied firmware, meaning it involves low integration effort and flexible configurations to support a wide variety of use cases, including quantum-safe secure boot. Solutions are available for hardware acceleration of SHA-3, SHAKE, ML-KEM, ML-DSA, alongside traditional cryptography. In addition, PQPlatform-CoPro can be configured with side-channel protection. PQPlatform-CoPro is covered by multiple PQShield implementation patents.
FIPS 140-3 CMVP compliant, CAVP PQC cryptographic library designed for PQ/T Hybrid PQCryptoLib is a general-purpose FIPS 140-3 CMVP and CAVP-certified cryptographic library. It’s been designed for a wide variety of applications and provides the latest NIST-standardized post-quantum and classical algorithms in a software environment. With a configurable, secure, and easy-to-use API, PQCryptoLib is optimized for crypto-agility, particularly when it comes to FIPS-compliant hybrid PQ/T solutions, and with crypto-agility in mind, it’s built to protect against the threat of ‘harvest-now-decrypt-later’ attacks. The aim of PQCryptoLib is to help organizations transition smoothly and securely to quantum resistance in a manageable, easy-to-integrate solution.
DolphinWare IPs is a versatile portfolio of intellectual property solutions that enable efficient SoC design. This collection includes various control logic components such as FIFO, arbiter, and arithmetic components like math operators and converters. In addition, the logic components span counters, registers, and multiplexers, providing essential functionalities for diverse industrial applications. The IPs in this lineup are meticulously designed to ensure data integrity, supported by robust verification IPs for AXI4, APB, SD4.0, and more. This comprehensive suite meets the stringent demands of modern electronic designs, facilitating seamless integration into existing design paradigms. Beyond their broad functionality, DolphinWare’s offerings are fundamental to applications requiring specific control logic and data integrity solutions, making them indispensable for enterprises looking to modernize or expand their product offerings while ensuring compliance with industry standards.
Helion offers comprehensive AES encryption cores, a staple in data security due to its robustness and efficiency. These cores support the AES standard, chosen by NIST for its advanced security features. AES operates as a block cipher with three key size options (128, 192, 256 bits), allowing flexibility in security levels. Ideal for commercial applications, AES ensures data integrity and confidentiality, vital for secure communications and data storage. Helion's AES solutions are distinguished by their scalability and adaptability, making them suitable for various technological implementations. Whether for ASICs or FPGAs, these cores are designed to maximize performance without compromising core area efficiency. With a focus on low power consumption and high data throughput, Helion's AES cores are versatile tools for secure encryption tasks. Moreover, Helion's AES IPs incorporate several modes, including CBC, CFB, OFB, and CTR, to further enhance security for numerous applications ranging from wireless communications to disk encryption. With a commitment to excellence, Helion maintains its standing as a leader in encryption core technology, continually advancing their offerings to meet evolving security demands.
Highly-optimized PQC implementations, capable of running PQC in < 15kb RAM PQCryptoLib-Emebedded is a versatile, CAVP-compliant version of PQCryptoLib, PQShield’s CMVP-certified library of post-quantum cryptographic algorithms. With its design focused on ultra-small area efficiency, PQCryptoLib-Embedded has been specifically designed for embedded systems, microcontrollers and memory-constrained devices. It could be the first step towards a hardware solution for providing PQC integration to devices already in the field.
The FPGA Lock Core is an innovative FPGA solution designed to secure FPGAs and hardware against unauthorized access and counterfeiting, leveraging a Microchip ATSHA204A crypto authentication IC. It reads a unique ID, generates a 256-bit challenge, and uses secure hashing to verify the hardware's authenticity, ensuring hardware integrity in sensitive applications like military and medical fields. This solution allows hardware protection against IP theft by enforcing authentication and disables FPGA functionality if unauthorized access is detected. The core utilizes minimal logic resources and one FPGA pin, communicating through a bidirectional open drain link. The clarity of this system is enhanced by providing the core in VHDL, allowing users to thoroughly understand its functionality, supported by example designs on Cyclone10 and Artix 7 boards, catering to both Intel and Xilinx FPGA platforms. Complementing this security measure is the Key Writer Core, which allows programming of custom secret keys into the ATSHA204A in situ on assembled boards, ensuring a seamless integration with the FPGA Lock system. Available for various FPGA platforms, the Efinix version, distributed with TRS Star, expands its applicability, with webinars and user guides offering in-depth implementation insights.
Designed for seamless integration of the V-by-One HS interface with FPGA development platforms, the Alcora V-by-One HS Daughter Card supports high-speed video data transmission. This card can interface with FPGA boards using 8 RX and 8 TX lanes, allowing for extensive bandwidth utilization. The Alcora card is distinguished by its two available versions, differing by their header pin count: 51-pin and 41-pin. Optimized for high-definition video transmission, it supports resolutions of 4K at 120Hz or 8K at 30Hz by combining two daughter cards for enhanced lane capacity. To maintain signal integrity, Alcora incorporates two clock generators to manage transceiver reference clock synthesis and reduce recovered RX clock jitter. As a high-speed digital video interface solution, it is tailored particularly for display applications that demand rigorous performance and reliability standards.
Secure Protocol Engines are high-performance IP blocks that focus on enhancing network and security processing capabilities in data centers. Designed to support secure communications, these engines provide fast SSL/TLS handshakes, MACsec and IPsec processing, ensuring secure data transmission across networks. They are particularly useful for offloading intensive tasks from central processing units, thereby improving overall system performance and efficiency. These engines cater to data centers and enterprises that demand high throughput and robust security measures.
Suite-Q SW stands as a versatile cryptographic software library offered by PQ Secure that is meticulously engineered to optimize code size, stack usage, and performance across various processing environments. This library is built to be portable, with implementations available in C and assembly languages, catering to a wide array of processor architectures including 8-, 16-, 32-, and 64-bit systems. The software library is designed to seamlessly integrate into diverse development environments, providing developers with modular plug-in modules that facilitate easy hardware offload. Suite-Q SW supports a comprehensive spectrum of cryptographic operations, including both symmetric encryption such as AES and advanced post-quantum schemes, ensuring robust data protection. As part of its feature set, Suite-Q SW offers multiple configurations, allowing developers to balance memory utilization and processing speed according to their specific application needs. This flexibility makes the library suitable for both general-purpose applications and highly specialized embedded systems, ensuring it meets the stringent requirements of modern security demands.
Fully autonomous, FIPS 140-3 CAVP compliant PQC subsystem PQPlatform-SubSys is a cryptographic subsystem, designed to provide offloaded cryptographic services with minimal integration effort and full autonomy from an existing security subsystem, as well as configurable side-channel protection. These services include post-quantum signature generation, verification, and secure key establishment. It’s built with optimal performance in mind, as well as crypto agility with its provision of traditional, PQ/T hybrid and fully post-quantum algorithms. PQPlatform-SubSys uses its built-in RISC-V CPU independently from the surrounding system, allowing cryptographic services to be offloaded efficiently from the system processor.
Join the world's most advanced semiconductor IP marketplace!
It's free, and you'll get all the tools you need to discover IP, meet vendors and manage your IP workflow!
No credit card or payment details required.
Join the world's most advanced AI-powered semiconductor IP marketplace!
It's free, and you'll get all the tools you need to advertise and discover semiconductor IP, keep up-to-date with the latest semiconductor news and more!
Plus we'll send you our free weekly report on the semiconductor industry and the latest IP launches!