All IPs > Security IP
Security IPs are an integral category within the semiconductor industry focusing on the protection of electronic data and hardware. As technological advancements continue to proliferate across critical sectors like finance, healthcare, and automotive, securing data and hardware has never been more paramount. Security IPs are designed to provide essential security features such as encryption, secure communications, and access control to safeguard sensitive information and devices from unauthorized access and cyber threats.
Within the Security IP category, you will find robust offerings that include both hardware and software-based solutions tailored to various security needs. Content Protection Software enables secure data transmission and protects digital content from piracy and unauthorized distribution. Cryptography Cores and Cryptography Software Libraries offer foundational tools for implementing strong encryption algorithms that are crucial for securing communications and data storage.
Embedded Security Modules are integrated within semiconductor devices to facilitate secure data processing and enhance trust in device operations by preventing code tampering and unauthorized hardware modification. Platform Security solutions encompass a broad range of protective measures designed to secure the entire hardware and software ecosystem, ensuring that devices are safe from potential vulnerabilities at every level.
Additionally, Security Protocol Accelerators and Security Subsystems act as dedicated processing units to efficiently handle complex security algorithms and protocols, enhancing the performance of security operations while reducing the burden on primary CPUs. With an unpredictable security landscape, leveraging a range of specialized Security IPs allows designers and engineers to build robust, secure, and reliable semiconductor solutions that can withstand evolving cyber threats.
The Akida 2nd Generation represents a leap forward in the realm of AI processing, enhancing upon its predecessor with greater flexibility and improved efficiency. This advanced neural processor core is tailored for modern applications demanding real-time response and ultra-low power consumption, making it ideal for compact and battery-operated devices. Akida 2nd Generation supports various programming configurations, including 8-, 4-, and 1-bit weights and activations, thus providing developers with the versatility to optimize performance versus power consumption to meet specific application needs. Its architecture is fully digital and silicon-proven, ensuring reliable deployment across diverse hardware setups. With features such as programmable activation functions and support for sophisticated neural network models, Akida 2nd Generation enables a broad spectrum of AI tasks. From object detection in cameras to sophisticated audio sensing, this iteration of the Akida processor is built to handle the most demanding edge applications while sustaining BrainChip's hallmark efficiency in processing power per watt.
The Akida IP is an advanced processor core designed to mimic the efficient processing characteristics of the human brain. Inspired by neuromorphic engineering principles, it delivers real-time AI performance while maintaining a low power profile. The architecture of the Akida IP is sophisticated, allowing seamless integration into existing systems without the need for continuous external computation. Equipped with capabilities for processing vision, audio, and sensor data, the Akida IP stands out by being able to handle complex AI tasks directly on the device. This is done by utilizing a flexible mesh of nodes that efficiently distribute cognitive computing tasks, enabling a scalable approach to machine learning applications. Each node supports hundreds of MAC operations and can be configured to adapt to various computational requirements, making it a versatile choice for AI-centric endeavors. Moreover, the Akida IP is particularly beneficial for edge applications where low latency, high efficiency, and security are paramount. With capabilities for event-based processing and on-chip learning, it enhances response times and reduces data transfer needs, thereby bolstering device autonomy. This solidifies its position as a leading solution for embedding AI into devices across multiple industries.
Overview: Cybersecurity IPs offer a range of essential security features to protect your digital assets and sensitive information. From True Random Number Generators (TRNG) to advanced encryption algorithms like AES, DES, 3DES, and cryptographic hash functions like SHA, as well as RSA for secure key exchange and digital signatures, the IPs provide a comprehensive suite of tools to safeguard your data. Key Features: True Random Number Generator (TRNG): Generates unpredictable and unbiased random numbers for cryptographic applications. Advanced Encryption Standard (AES): Provides robust encryption with symmetric key algorithms for securing data. Data Encryption Standard (DES) and Triple DES (3DES): Implement legacy encryption algorithms for data protection. Hash Functions: Includes secure cryptographic hash functions like SHA (Secure Hash Algorithm) for data integrity verification. RSA: Enables secure key exchange, encryption, and digital signatures for secure communication. These cybersecurity IPs are designed to meet the stringent security requirements of modern applications, ensuring the confidentiality, integrity, and authenticity of your data.
aiWare is a high-performance NPU designed to meet the rigorous demands of automotive AI inference, providing a scalable solution for ADAS and AD applications. This hardware IP core is engineered to handle a wide array of AI workloads, including the most advanced neural network structures like CNNs, LSTMs, and RNNs. By integrating cutting-edge efficiency and scalability, aiWare delivers industry-leading neural processing power tailored to automobile-grade specifications.\n\nThe NPU's architecture emphasizes hardware determinism and offers ISO 26262 ASIL-B certification, ensuring that aiWare meets stringent automotive safety standards. Its efficient design also supports up to 256 effective TOPS per core, and can scale to handle thousands of TOPS through multicore integration, minimizing power consumption effectively. The aiWare's system-level optimizations reduce reliance on external memory by leveraging local memory for data management, boosting performance efficiency across varied input data sizes and complexities.\n\naiWare’s development toolkit, aiWare Studio, is distinguished by its innovative ability to optimize neural network execution without the need for manual intervention by software engineers. This empowers ai engineers to focus on refining NNs for production, significantly accelerating iteration cycles. Coupled with aiMotive's aiDrive software suite, aiWare provides an integrated environment for creating highly efficient automotive AI applications, ensuring seamless integration and rapid deployment across multiple vehicle platforms.
Overview: The Secure Enclave IPs are Common Criteria (CC) EAL5+PP0084/PP0117 and EAL5+PP0117 certification-ready Secure Enclaves, respectively. They are available as hard macros for seamless integration into SoCs. These Secure Enclave IPs provide the highest level of security for an SoC, incorporating patented design techniques and countermeasures against side-channel and perturbation attacks to ensure robust security while minimizing power consumption. Key Features: Cryptographic Hardware Accelerators: Efficiently support standard cryptography and security operations to increase throughput while adhering to power constraints and security requirements. BootROM and Secondary Boot Loader: Manage the certified life cycle of the Secure Enclave, enforcing and assuring security from manufacturing to deployment. Proprietary IP: Based on proprietary IP that is free of 3rd party rights and royalties. Benefits: The Secure Enclave IPs offer robust security measures, efficient cryptographic support, and secure life cycle management, making them ideal for applications that require the highest levels of security and reliability. Applications: The Secure Enclave IP is versatile and suitable for a wide range of applications, including but not limited to: Secured and Certified iSIM & iUICC EMVco Payment Hardware Cryptocurrency Wallets FIDO2 Web Authentication V2X HSM Protocols Smart Car Access Secured Boot Secure OTA Firmware Updates Secure Debug Any design requiring a Secure Enclave, Secure Element, or Hardware Root of Trust protected against side-channel and perturbation fault attacks. Compliance and Support: The Secure Enclave is compliant with and ready for CC EAL5+ and EMVCo certification. It is delivered with an SDK and pre-certified CryptoLibrary and secure Boot Loader for seamless integration and enhanced security.
The Metis AIPU M.2 Accelerator Module by Axelera AI is a compact and powerful solution designed for AI inference at the edge. This module delivers remarkable performance, comparable to that of a PCIe card, all while fitting into the streamlined M.2 form factor. Ideal for demanding AI applications that require substantial computational power, the module enhances processing efficiency while minimizing power usage. With its robust infrastructure, it is geared toward integrating into applications that demand high throughput and low latency, making it a perfect fit for intelligent vision applications and real-time analytics. The AIPU, or Artificial Intelligence Processing Unit, at the core of this module provides industry-leading performance by offloading AI workloads from traditional CPU or GPU setups, allowing for dedicated AI computation that is faster and more energy-efficient. This not only boosts the capabilities of the host systems but also drastically reduces the overall energy consumption. The module supports a wide range of AI applications, from facial recognition and security systems to advanced industrial automation processes. By utilizing Axelera AI’s innovative software solutions, such as the Voyager SDK, the Metis AIPU M.2 Accelerator Module enables seamless integration and full utilization of AI models and applications. The SDK offers enhancements like compatibility with various industry tools and frameworks, thus ensuring a smooth deployment process and quick time-to-market for advanced AI systems. This product represents Axelera AI’s commitment to revolutionizing edge computing with streamlined, effective AI acceleration solutions.
The Talamo SDK from Innatera serves as a comprehensive software development toolkit designed to maximize the capabilities of its Spiking Neural Processor (SNP) lineup. Tailored for developers and engineers, Talamo offers in-depth access to configure and deploy neuromorphic processing solutions effectively. The SDK supports the development of applications that utilize Spiking Neural Networks (SNNs) for diverse sensory processing tasks. Talamo provides a user-friendly interface that simplifies the integration of neural processing capabilities into a wide range of devices and systems. By leveraging the toolkit, developers can customize applications for specific use cases such as real-time audio analysis, touch-free interactions, and biometric data processing. The SDK comes with pre-built models and a model zoo, which helps in rapidly prototyping and deploying sensor-driven solutions. This SDK stands out by offering enhanced tools for developing low-latency, energy-efficient applications. By harnessing the temporal processing strength of SNNs, Talamo allows for the robust development of applications that can operate under strict power and performance constraints, enabling the creation of intelligent systems that can autonomously process data in real-time.
The RV12 RISC-V Processor is a highly configurable, single-core CPU that adheres to RV32I and RV64I standards. It’s engineered for the embedded market, offering a robust structure based on the RISC-V instruction set. The processor's architecture allows simultaneous instruction and data memory accesses, lending itself to a broad range of applications and maintaining high operational efficiency. This flexibility makes it an ideal choice for diverse execution requirements, supporting efficient data processing through an optimized CPU framework. Known for its adaptability, the RV12 processor can support multiple configurations to suit various application demands. It is capable of providing the necessary processing power for embedded systems, boasting a reputation for stability and reliability. This processor becomes integral for designs that require a maintainability of performance without compromising on the configurability aspect, meeting the rigorous needs of modern embedded computing. The processor's support of the open RISC-V architecture ensures its capability to integrate into existing systems seamlessly. It lends itself well to both industrial and academic applications, offering a resource-efficient platform that developers and researchers can easily access and utilize.
The AHB-Lite APB4 Bridge serves as a crucial interconnect that facilitates communication between the AMBA 3 AHB-Lite and AMBA APB bus protocols. As a parameterized soft IP, it offers flexibility and adaptability in managing system interconnections, bridging the gap between high-speed and low-speed peripherals with efficiency. The bridge's architecture is designed to maintain data integrity while transferring information across different protocol tiers. This bridge supports the implementation of a seamless transition for data exchanges, ensuring data packets are transmitted with minimal latency. It is ideal for systems that require stable connectivity across multiple peripheral interfaces, delivering a cohesive platform for system designers to enhance operational uniformity. By enabling efficient bus conversion, it supports broader system architectures, contributing to the overall efficiency of embedded designs. With its open-architecture design, the AHB-Lite APB4 Bridge caters to a wide range of applications, providing necessary adaptability to meet the unique demands of each project. Its robust design ensures that it can accommodate the complex architectures of modern embedded systems, enhancing both performance and reliability.
The WiseEye2 AI Solution by Himax is a highly efficient processor tailored for AI applications, combining an ultra-low power CMOS image sensor with the HX6538 microcontroller. Designed for battery-powered devices requiring continuous operation, it significantly lowers power consumption while boosting performance. This processor leverages the Arm Cortex M55 CPU and Ethos U55 NPU to enhance inference speed and energy efficiency substantially, allowing execution of complex models with precision. Perfectly suited for applications like user-presence detection in laptops, WiseEye2 heightens security through sophisticated facial recognition and adaptive privacy settings. It automatically wakes or locks the device based on user proximity, thereby conserving power and safeguarding sensitive information. WiseEye2’s power management and neural processing units ensure constant device readiness, augmenting AI capabilities ranging from occupancy detection to smart security. This reflects Himax's dedication to providing versatile AI solutions that anticipate and respond to user needs seamlessly. Equipped with sensor fusion and sophisticated security engines, WiseEye2 maintains privacy and operational efficiency, marking a significant step forward in the integration of AI into consumer electronics, especially where energy conservation is pivotal.
CrossBar's ReRAM Memory is designed to redefine data storage with its high-density and energy-efficient characteristics. The memory solution can achieve terabyte-scale storage on-chip, significantly surpassing traditional flash memory solutions in both speed and power consumption. Offered in a 3D cross-point architecture, it is capable of providing high performance with minimal layout overhead. Engineered for next-generation applications, this ReRAM technology boasts a performance edge with 20ns read times and 12µs write capabilities, eliminating the usual erase latency. It is significantly faster than traditional NAND flash with its lightning-fast read and write speeds, making it suitable for real-time processing required by cutting-edge applications such as AI and IoT. Security is a key feature, offering tamper-resistant provisions for cryptographic key storage ensuring robust protection against data breaches. The memory solution leverages advanced technology to deliver energy savings of up to 5x compared to eFlash, and up to 40x when compared to BLE, positioning it as an ideal choice for mobile and low-power applications.
The AHB-Lite Timer module designed by Roa Logic is compliant with the RISC-V Privileged 1.9.1 specification, offering a versatile timing solution for embedded applications. As an integral peripheral, it provides precise timing functionalities, enabling applications to perform scheduled operations accurately. Its parameterized design allows developers to adjust the timer's features to match the needs of their system effectively. This timer module supports a broad scope of timing tasks, ranging from simple delay setups to complex timing sequences, making it ideal for various embedded system requirements. The flexibility in its design ensures straightforward implementation, reducing complexity and enhancing the overall performance of the target application. With RISC-V compliance at its core, the AHB-Lite Timer ensures synchronization and precision in signal delivery, crucial for systems tasked with critical timing operations. Its adaptable architecture and dependable functionality make it an exemplary choice for projects where timing accuracy is required.
The AHB-Lite Multilayer Switch by Roa Logic is a sophisticated interconnect fabric that provides high performance with low latency capabilities. Designed for extensive connectivity, it supports an unlimited number of bus masters and slaves, making it ideal for large-scale system architectures. This switch ensures data is efficiently propagated through various paths, optimizing resource allocation and throughput in complex systems. With a focus on performance, the multilayer switch is crafted to manage data traffic within high-demand environments seamlessly. Its support for multiple layers allows it to efficiently handle concurrent data transactions, facilitating effective communication between different system components. The adaptive structure and controlled latency pathways enable it to fit a multitude of applications, including those requiring rapid data transfer and processing. The AHB-Lite Multilayer Switch is engineered to integrate seamlessly into modern system architectures, enhancing throughput without compromising on signal integrity. Its robust design and flexible configuration options make it indispensable within systems necessitating dynamic connectivity solutions.
Overview: The Secure Boot IP is a turnkey solution that provides a secure boot facility for an SoC. It implements the Post Quantum secure Leighton-Micali Signature (LMS) as specified in NIST SP800-208. The Secure Boot IP operates as a master or slave peripheral to an Application Processor, serving as a secure enclave that securely stores keys to ensure their integrity and the integrity of the firmware authentication process. Features: Post Quantum Secure LMS Signature: Utilizes a robust Post-Quantum secure algorithm for enhanced security. Firmware Updates: Supports up to 32 thousand firmware updates with a minimal signature size of typically less than 5KBytes. SESIP Level 3 Pre-Certification: Pre-certified to SESIP Level 3 for added security assurance. RTL Delivery: Delivered as RTL for ease of integration into SoC designs. Proprietary IP: Based on proprietary IP with no 3rd party rights or royalties. Operation: The Secure Boot IP operates as a master, managing the boot process of the Application Processor to ensure that it only boots from and executes validated and authenticated firmware. The Secure Boot IP also functions as a slave peripheral, where the Application Processor requests validation of the firmware as part of its boot process, eliminating the need for managing keys and simplifying the boot process. Applications: The Secure Boot IP is versatile and suitable for a wide range of applications, including but not limited to: Wearables Smart/Connected Devices Metrology Entertainment Applications Networking Equipment Consumer Appliances Automotive Industrial Control Systems Security Systems Any SoC application that requires executing authenticated firmware in a simple but secure manner.
The ReRAM IP Cores for Embedded Non-Volatile Memory are crafted to seamlessly integrate into microcontrollers (MCUs) and systems on chips (SOCs), addressing the enduring need for efficient and scalable storage. These IP cores leverage CrossBar's signature 3D ReRAM technology to provide unparalleled performance in both speed and density, tailored specifically for embedded systems. Designed to offer superior integration capabilities, this ReRAM technology reduces traditional bottlenecks witnessed with embedded flash memory solutions. It allows for rapid data access and storage, making it a superior choice for applications requiring frequent read/write operations. By offering robust tamper-resistance for secure key storage, these IP cores also add an additional layer of security critical for modern embedded systems. They enable cost-effective scalability and flexibility for manufacturers looking to enhance their products with cutting-edge memory technology.
A2e's H.264 FPGA Encoder and CODEC Micro Footprint Cores provide a customizable solution targeting FPGAs. Known for its small size and rapid execution, the core supports 1080p60 H.264 Baseline with a singular core, making it one of the industry's swiftest and most efficient FPGA offerings. The core is compliant with ITAR, offering options to adjust pixel depths and resolutions according to specific needs. Its high-performance capability includes offering a latency of just 1ms at 1080p30, which is crucial for applications demanding rapid processing speeds. This licensable core is ideal for developers needing robust video compression capabilities in a compact form factor. The H.264 cores can be finely tuned to meet unique project specifications, enabling developers to implement varied pixel resolutions and depths, further enhancing the core's versatility for different application requirements. With a licensable evaluation option available, prospective users can explore the core’s functionalities before opting for full integration. This flexibility makes it suitable for projects demanding customizable compression solutions without the burden of full-scale initial commitment. Furthermore, A2e provides comprehensive integration and custom design services, allowing these cores to be seamlessly absorbed into existing systems or developed into new solutions. This support ensures minimized risk and accelerated project timelines, allowing developers to focus on innovation and efficiency in their video-centric applications.
Secure OTP from PUFsecurity is the next evolution in data protection, utilizing a secure anti-fuse OTP memory for storing keys and sensitive information. It enhances traditional OTP by providing a comprehensive protection mechanism against hardware attacks. The solution features digital and physical macros along with a resilient anti-tamper shell, supporting multiple interfaces for smooth integration into diverse IC applications.
Post-quantum Software Development Kit Provides easy-to-use software implementations of both post-quantum and classical cryptographic primitives. It’s designed with prototyping and experimentation in mind, consisting of an integration of PQShield’s PQCryptoLib library with two popular high-level cryptography libraries: OpenSSL and mbedTLS. OpenSSL: a widely-adopted secure-communication library mbedTLS: primarily intended for use in embedded system and IoT deployments
eSi-ADAS is a radar IP suite designed to enhance the performance and responsiveness of automotive and unmanned vehicle systems. It includes a complete Radar co-processor engine, facilitating rapid situational awareness necessary for safety-critical applications. The scalable nature of this IP makes it adaptable for various automotive and drone-based projects.
The Dynamic Neural Accelerator II (DNA-II) from EdgeCortix is an advanced neural network IP core tailored for high efficiency and parallelism at the edge. Incorporating a run-time reconfigurable interconnect system between compute units, DNA-II effectively manages both convolutional and transformer workloads. This architecture ensures scalable performance beginning with 1K MACs, suitable for a wide range of SoC implementations. EdgeCortix's patented architecture significantly optimizes data paths between DNA engines, enhancing parallelism while reducing on-chip memory usage. As a core component of the SAKURA-II platform, DNA-II supports state-of-the-art generative AI models with industry-leading energy efficiency. DNA-II's design acknowledges the typical inefficiencies in IP cores, improving compute utilization and power consumption metrics substantially. By adopting innovative reconfigurable datapath technologies, EdgeCortix sets a new benchmark for low-power, high-performance edge AI applications.
D2D® Technology, developed by ParkerVision, is a revolutionary approach to RF conversion that transforms how wireless communication operates. This technology eliminates traditional intermediary stages, directly converting RF signals to digital data. The result is a more streamlined and efficient communication process that reduces complexity and power consumption. By bypassing conventional analog-to-digital conversion steps, D2D® achieves higher data accuracy and reliability. Its direct conversion approach not only enhances data processing speeds but also minimizes energy usage, making it an ideal solution for modern wireless devices that demand both performance and efficiency. ParkerVision's D2D® technology continues to influence a broad spectrum of wireless applications. From improving the connectivity in smartphones and wearable devices to optimizing signal processing in telecommunication networks, D2D® is a cornerstone of ParkerVision's technological offerings, illustrating their commitment to advancing communication technology through innovative RF solutions.
The Polar ID is an innovative biometric security system that elevates facial recognition technology through its use of sophisticated meta-optics. By capturing and analyzing the unique polarization signature of a face, Polar ID delivers a new standard in security. This system can detect spoofing attempts that incorporate 3D masks or other similar deceptive tactics, ensuring high security through accurate human authentication. Polar ID minimizes the complexity typically associated with face recognition systems by integrating essential optical functions into a single optic. Its compact design results in cost savings and reduces the space required for optical modules in devices like smartphones. Operating in near-infrared light, Polar ID can consistently deliver secure face unlock capabilities even under challenging lighting conditions, dramatically outperforming traditional systems that may fail in bright or dark environments. The platform does not rely on time-of-flight sensors or structured light projectors, which are costly and complex. Instead, Polar ID leverages the simplicity and efficiency of its single-shot identification process to deliver immediate authentication results. This makes it a potent tool for securing mobile transactions and providing safer user experiences in consumer technology.
Specially engineered for the automotive industry, the NA Class IP by Nuclei complies with the stringent ISO26262 functional safety standards. This processor is crafted to handle complex automotive applications, offering flexibility and rigorous safety protocols necessary for mission-critical transportation technologies. Incorporating a range of functional safety features, the NA Class IP is equipped to ensure not only performance but also reliability and safety in high-stakes vehicular environments.
The L5-Direct GNSS Receiver by oneNav is a revolutionary solution built to leverage the advanced capabilities of L5-band satellite signals. Distinguishing itself by operating solely on the L5 frequency, this product delivers exceptional positioning accuracy and resilience, free from the interference commonly associated with legacy L1 signals. This advanced GNSS receiver is engineered to cater to a variety of professional applications that demand robust performance under challenging conditions, such as dense urban areas.\n\nLeveraging oneNav's proprietary Application Specific Array Processor (ASAP), the system provides best-in-class GPS signal acquisition and processing without compromising sensitivity or fix time. The use of an innovative single RF chain allows for optimal antenna placement, reducing the overall form factor and enabling integration into devices that require stringent size and cost constraints. This makes it an ideal choice for wearable and IoT device applications where space and energy consumptions are pivotal considerations.\n\nAdditionally, the L5-Direct GNSS Receiver incorporates machine learning algorithms to effectively mitigate multipath errors, offering unrivaled accuracy by distinguishing direct from reflected signals. The system is specifically designed to be energy efficient, offering extended operational life critical for applications such as smart wearables and asset tracking devices. Its resilience against GPS jamming and interference ensures it remains a reliable choice for mission-critical operations.
The Securyzr iSSP is an integrated Security Services Platform that provides a comprehensive solution for managing the embedded security of devices throughout their lifecycle. It offers features like secure boot, firmware updates, and security monitoring. By leveraging these lifecycle management services, companies can ensure that device security is maintained continuously from deployment until the end of service. The platform stands out by enabling zero-touch security management, linking secure elements with cloud services effectively.
AES-GCM combines the Advanced Encryption Standard with the Galois/Counter Mode of operation to provide an authenticated encryption solution that ensures both confidentiality and data integrity. Helion's AES-GCM IP cores are optimized for high efficiency and are suitable for use in FPGAs and ASICs across various technical fields. AES-GCM is particularly advantageous for scenarios requiring high-speed data processing with robust security. It achieves this by encrypting data and producing an authentication tag simultaneously, which simplifies the process of securing data streams and verifying data authenticity. This dual function of encryption and integrity check within a single operation enhances performance, making it ideal for secure communication protocols, secure video streaming, and cloud storage solutions. The implementation by Helion is characterized by its adaptability and ease of integration, allowing seamless deployment into existing systems. The IP core supports various key sizes and offers substantial flexibility in operational parameters, ensuring it can be tailored to meet specific security needs while optimizing resource usage and maintaining power efficiency.
FIPS 140-3 CAVP compliant ultra-fast, compact, and power efficient secure hash acceleration PQPlatform-Hash is a power side-channel accelerator, supporting a wide range of Hash-Based Signature Schemes (HBSS). PQPlatform-Hash deploys tried-and-tested HBSS including quantum-safe LMS and XMSS (not hybrid). It provides acceleration of HBSS in embedded devices, especially where high throughput is required, or resource constraints necessitate minimal additional area. For example, PQPlatform-Hash is a solution for secure first-stage boot loading with hash-based signature schemes. HBSS offer different trade-offs of memory/area to lattice-based schemes, and as a result, PQPlatform-Hash is ideally suited for smaller key sizes, larger signature sizes, and processing times for key generation, signature generation and verification.
The SiFive Essential family is designed to deliver high customization for processors across varying applications, from standalone MCUs to deeply embedded systems. This family of processor cores provides a versatile solution, meeting diverse market needs with an optimal combination of power, area, and performance. Within this lineup, users can tailor processors for specific market requirements, ranging from simple MCUs to fully-featured, Linux-capable designs. With features such as high configurability, SiFive Essential processors offer flexible design points, allowing scaling from basic 2-stage pipelines to advanced dual-issue superscalar configurations. This adaptability makes SiFive Essential suitable for a wide variety of use cases in microcontrollers, IoT devices, and control plane processing. Additionally, their innovation is proven by billions of units shipped worldwide, highlighting their reliability and versatility. The Essential cores also provide advanced integration options within SoCs, enabling smooth interface and optimized performance. This includes pre-integrated trace and debug features, ensuring efficient development and deployment in diverse applications.
SHA, or Secure Hash Algorithm, is a fundamental component in the realm of data integrity verification. Helion offers a suite of SHA hashing IP cores designed for efficient data processing and secure validation requirements using ASICs and FPGAs. Helion's SHA solutions encompass various iterations including SHA-1, SHA-256, SHA-384, and SHA-512, ensuring compatibility with a wide range of security protocols. These algorithms transform input data into fixed-length hash values, providing a unique fingerprint for data verification purposes. This capability is crucial in applications such as digital signatures, message integrity, and authentication processes. The design emphasizes high throughput and low latency, facilitating rapid hashing operations for environments demanding high-performance computing. Additionally, the SHA cores are engineered for minimal power consumption, ensuring that they meet modern energy efficiency standards without compromising on security and performance.
The Universal DSP Library is designed to simplify digital signal processing tasks within FPGA systems. This extensive collection of DSP algorithms and functions allows for efficient development and deployment of signal processing applications. Users can leverage this library to handle complex computations swiftly, making it perfect for industries requiring real-time processing power. It streamlines development by offering pre-tested routines that developers can integrate into their systems without extensive customization.
The Human Body Detector developed by Microdul is a state-of-the-art solution designed to minimize power consumption while accurately detecting human presence. This functionality is particularly useful in wearable technology where conserving battery life is paramount. Capable of functioning dynamically and statically, the detector efficiently manages a device's energy by detecting when a wearable is not in use, triggering a low power state. This feature is crucial for prolonging battery life in devices where frequent charging is inconvenient or impractical. Its versatility extends to various applications, including security and smart home systems, where the detector's sensitivity and power management capabilities can substantially enhance system efficiency and user satisfaction. Microdul's human body detector represents the pinnacle of low-power design, making it indispensable for modern electronic innovations.
FIPS 140-3 CAVP-compliant, compact PQC hardware acceleration for subsystems PQPlatform-CoPro combines hash-based and lattice-based post-quantum cryptography that can be added to an existing security subsystem. It can be optimized for minimum area, maintaining high-performance, and is designed to be run by an existing CPU using PQShield-supplied firmware, meaning it involves low integration effort and flexible configurations to support a wide variety of use cases, including quantum-safe secure boot. Solutions are available for hardware acceleration of SHA-3, SHAKE, ML-KEM, ML-DSA, alongside traditional cryptography. In addition, PQPlatform-CoPro can be configured with side-channel protection. PQPlatform-CoPro is covered by multiple PQShield implementation patents.
The Aeonic Integrated Droop Response System sets a new standard in addressing voltage droop issues within integrated circuits through its advanced droop detection and response capabilities. It is uniquely engineered to provide rapid, fine-grained DVFS capabilities, allowing significant reductions in system power requirements. With multi-threshold detection features and support for remote/local droop detection, this system effectively facilitates monitoring and management of critical silicon health metrics. The robust observability and programmability features make it an indispensable asset for adapting to silicon aging and optimizing lifecycle analytics.
The AES-XTS mode offers a robust solution for encrypting data stored on hard drives and other storage devices. Designed specifically to address the security needs of data at rest, Helion's implementation ensures that the data remains confidential and protected against unauthorized access. AES-XTS employs a unique tweaking mechanism that prevents identical plaintext data blocks from producing identical ciphertext data blocks, effectively providing enhanced security for sensitive data storage. This mode is particularly suited for full disk encryption, ensuring that data is secure against physical attempts to extract or manipulate it. Helion's AES-XTS solution is optimized for both performance and power efficiency, making it ideal for integration in environments where data security is paramount without compromising system efficiency. The IP core supports various key lengths to meet specific cryptographic strength requirements, ensuring adaptability across different storage platforms and devices.
Up to 1M KeyEnc/sec with improved power efficiency PQPerform-Lattice is a powerful hardware-based product designed for high throughput, high-performance, and high speed. It adds post-quantum cryptography for applications that typically handle a large number of transactions, such as high-capacity network hardware applications and secure key management HSMs. Optimizable for secure boot, as well as other use-cases, PQPerform-Lattice supports FIPS 204 ML-DSA for quantum-secure digital signature verification, as well as FIPS 203 ML-KEM for quantum key exchange. PQPerform-Lattice supports AXI4, PCIe, and is deployable in multiple instances, making it a powerful solution for existing systems and infrastructure requirements.
eSi-Crypto provides advanced encryption and authentication capabilities crucial for safeguarding modern electronic systems. The IP includes features such as True Random Number Generators (TRNGs), cryptographic processing, and Public Key Acceleration. By optimizing resource usage while ensuring high throughput, this technology aids in protecting device data against cyber threats.
FIPS 140-3 CAVP-compliant, compact lattice-based hardware PQC engine PQPlatform-Lattice is a compact FIPS 140-3 CAVP-compliant, PQC engine that adds post-quantum support for hardware components and embedded devices, using lattice-based cryptographic algorithms such as ML-KEM (FIPS 203) for post-quantum key exchange, and ML-DSA (FIPS 204) – post-quantum digital signature verification. It provides secure acceleration of lattice-based PQC alongside support for traditional cryptography. Its use cases include strong user authentication, protecting hardware keys, and small-footprint, configurable side-channel protection. PQPlatform-Lattice is designed for minimal area as well as maximum compatibility and can be deployed with optional firmware-backed side-channel countermeasures. It is covered by multiple PQShield implementation patents.
The NS Class is Nuclei's crucial offering for applications prioritizing security and fintech solutions. This RISC-V CPU IP securely manages IoT environments with its highly customizable and secure architecture. Equipped to support advanced security protocols and functional safety features, the NS Class is particularly suited for payment systems and other fintech applications, ensuring robust protection and reliable operations. Its design follows the RISC-V standards and is accompanied by customizable configuration options tailored to meet specific security requirements.
The AES Core by Algotronix is a sophisticated solution tailored for securing data using advanced encryption methods. This core supports various encryption modes such as ECB, CBC, CTR, CFB, OFB, CCM, GCM, and XTS, which cater to a wide array of applications requiring different levels and methods of data protection. The flexibility in supported modes allows for tailored implementations in different security-critical environments. This encryption core is known for its deployment among prominent defense electronics organizations, and it has been operational within several NATO member states, testifying to its high-level security assurance and operational readiness in sensitive global contexts. Offered typically in source code form, the AES Core ensures that users can perform thorough security audits and tailor enhancements specific to their security policies and infrastructural needs. This capability positions Algotronix's offering as an optimal choice for organizations prioritizing stringent security postures.
Trilinear Technologies' HDCP Encryption-Decryption Engine is a sophisticated solution designed to safeguard digital content as it traverses various transmission channels. This engine is compliant with the HDCP standards 1.4 and 2.3, offering robust protection mechanisms to ensure that digital media investments are secure from unauthorized access and piracy. The engine’s hardware acceleration capabilities represent a crucial advantage, significantly reducing the load on the system processor while maintaining real-time encryption and decryption functions. This not only enhances performance but also extends the operational life of the hardware involved, making it suitable for high-demand media applications across sectors such as broadcast, entertainment, and corporate environments. Trilinear’s HDCP Encryption-Decryption Engine ensures compatibility with a wide array of consumer and professional-grade video equipment, providing seamless protection without interference in media quality or transmission speed. Its flexible integration options allow it to be smoothly incorporated into existing infrastructures, whether in standalone media devices or complex SoC architectures. Supported by comprehensive software resources, the HDCP Encryption-Decryption Engine provides an all-encompassing solution that includes necessary software stacks for managing device authentication and link maintenance. Its ability to safeguard high-definition content effectively makes it an invaluable asset for entities focused on secure content delivery and rights management.
ArrayNav harnesses adaptive antenna technology to enhance GNSS functionality, optimizing performance in environments with complex multichannel challenges. By leveraging various antennas, ArrayNav achieves enhanced sensitivity and coverage, significantly mitigating issues such as multipath fading. This results in greater positional accuracy even in dense urban environments known for signal interference. This adaptive approach presents an invaluable asset for automotive Advanced Driver Assistance Systems (ADAS), where high precision and rapid response times are critical. The improved antenna diversity offered by ArrayNav not only augments signal strength but also robustly rejects interference and jamming attempts, assuring consistent operation and accuracy. In terms of power efficiency, ArrayNav stands out by combining exceptional accuracy with reduced power needs, offering a flexible solution adaptable for both standalone and cloud-computing modes. This dual capability ensures that system designers have the optimal framework for developing customized solutions catering to specific application requirements. Overall, ArrayNav’s cutting-edge technology fosters improved GNSS operations by delivering enhanced sensitivity and accuracy, thereby meeting the stringent demands of modern automotive and navigation systems.
AES, or Advanced Encryption Standard, is a cryptographic algorithm that stands as a cornerstone in secure data encryption. Helion's AES standard modes provide a range of configurations tailored to ensure data integrity and confidentiality across various applications. These modes are optimally designed for ASICs and FPGAs, promising high performance with low power consumption. The implementation of AES by Helion is distinguished by its flexibility and security, catering to industries that require stringent data protection. The IP core supports multiple AES modes, including ECB, CBC, CFB, OFB, and CTR, each with specific operational characteristics that address different security needs. The efficient design ensures reduced resource usage, which is particularly beneficial for cost-sensitive and resource-constrained environments. Helion's AES cores are compatible with global encryption standards and can be integrated seamlessly into existing frameworks. This adaptability makes them an ideal choice for applications such as secure communications, data storage encryption, and internet security protocols.
The NI Class RISC-V CPU IP caters to communication, video processing, and AI applications, providing a balanced architecture for intensive data handling and processing capabilities. With a focus on high efficiency and flexibility, this processor supports advanced data crunching and networking applications, ensuring that systems run smoothly and efficiently even when managing complex algorithms. The NI Class upholds Nuclei's commitment to providing versatile solutions in the evolving tech landscape.
AndeSoft SW Stack encompasses a comprehensive set of software building blocks and middleware optimized for AndesCore processors. This rich collection includes operating systems, libraries, drivers, and middleware components, all meticulously designed to enhance software development speed and quality. By providing ready-to-use components, AndeSoft enables developers to focus on crafting their application-specific solutions, significantly reducing time-to-market. Its seamless integration with AndeSight IDE further enhances development efficiency, supporting diverse operating systems and being adaptable to various processor configurations for optimal performance.
The JPEG-LS Encoder is an efficient, lossless image encoder designed specifically for FPGA platforms, implementing the ISO/IEC 14495-1 and ITU-T Rec. T.87 standards. This encoder boasts high efficiency and compresses images better than JPEG-2000 in numerous lossless scenarios without the need for auxiliary memory. With a latency of less than one line, it maintains rapid data processing speeds, making it exceptional for real-time applications. Tailored for adaptive image processing, the encoder supports image samples from 8 to 16 bits in various resolutions even reaching ultra high-definition levels. Its configurable design allows for dynamic adjustment of data word widths and image sizes, providing developers with flexibility akin to bespoke designs, optimizing for different operational needs. With its scalable architecture, the JPEG-LS Encoder ensures minimal resource usage while allowing for high throughput, easily integrating into complex systems. Its support for multiple interfaces, including FIFO I/O and Avalon Streaming with back-pressure, makes it versatile enough for various system architectures, augmenting the capabilities of any video or imaging processing platform.
The Origin E1 is a compact yet powerful neural processing unit (NPU) designed for low-power applications in home appliances, smartphones, and security cameras. Specially tailored for always-on functions, the E1 offers unmatched power efficiency by utilizing Expedera's innovative packet-based architecture. This allows it to execute multiple layers in parallel, ensuring the optimal balance of performance and resource utilization. Engineered to operate with minimal to no external memory, the Origin E1 is ideal for cost-effective and area-sensitive designs. The LittleNPU processor within it is fine-tuned for sophisticated neural networks needed in always-sensing applications, maintaining privacy by keeping data on-board. This makes the E1 a robust choice for devices requiring dedicated AI processing without the penalty of high power consumption or large silicon area. In terms of technical specifications, the Origin E1 boasts a performance efficiency of up to 18 TOPS per Watt, with the capability to run various network types such as CNNs, RNNs, and DNNs. Its adaptability allows clients to customize features to meet specific needs, guaranteeing efficient deployments across numerous devices. The E1 leverages a full TVM-based software stack for seamless integration, further endorsing its versatility and effectiveness.
The patented QDID PUF by Crypto Quantique utilizes quantum tunneling current variations to produce a unique identity in standard CMOS processes. This solution leverages oxide thickness variations and trap distributions in the gate oxide to create an unpredictable and unclonable physically unclonable function (PUF). As a hardware root-of-trust, it simplifies secure provisioning and emits high-entropy seeds resistant to side-channel attacks, supporting up to 256-bit security strength. The QDID PUF's robustness is confirmed through extensive testing, including adherence to NIST standards, making it an ideal choice for secure device identity and post-quantum cryptographic applications.
CrossBar's ReRAM IP Cores for High-Density Data Storage are tailored to enhance the memory capacity of various devices beyond current possibilities. These cores are designed with CrossBar's advanced ReRAM architecture which enables stacking technology to achieve ultra-dense data storage solutions. This level of memory sophistication is ideal for applications requiring massive data archiving and real-time data analytics, delivering energy-efficient storage at a fraction of the power needed by traditional HDD or SSD solutions. The ReRAM architecture provides rapid read/write cycles, catering to applications demanding high throughput and low latency. Incorporating CrossBar’s secure storage capability, this core ensures data integrity and security are maintained without sacrificing performance. It is an optimal choice for data-driven sectors striving to manage vast pools of information rapidly and effectively, setting a benchmark for future storage solutions.
The SHA-3 Crypto Engine is designed as a versatile and high-performance hardware accelerator for cryptographic hashing tasks. It supports all SHA-3 hash functions including SHA-3-224, SHA-3-256, SHA-3-384, and SHA-3-512 along with extendable output functions like SHAKE-128 and SHAKE-256. Its design ensures robust security, featuring full protection against timing-based side channel attacks, and includes automatic byte padding for convenience. Operating efficiently in a single clock domain, this engine is extensively verified to maintain data integrity across numerous applications, including blockchain, financial systems, and secure boot engines.
The Individual IP Core Modules by ResQuant are comprehensive components engineered to support diverse post-quantum cryptographic standards, including Dilithium, Kyber, XMSS, SPHINCS+, AES, and the SHA-2 family. These modules offer organizations the flexibility to select specific cryptographic functionalities tailored to their security needs, without the necessity of entire systems or hardware changes. Each module is designed to integrate easily into existing infrastructure, ensuring minimal disruption while enhancing security measures against potential future quantum threats. This approach allows industries to gradually implement PQC standards, ensuring a seamless transition to quantum-resistant cryptographic measures. Tailored for flexibility, the ResQuant Individual IP Core Modules can be used across a wide array of applications, from IoT devices to complex military and IT systems. By offering component-level integration, these modules empower companies to future-proof their offerings incrementally while maintaining robust security practices in their operations.
Join the world's most advanced semiconductor IP marketplace!
It's free, and you'll get all the tools you need to discover IP, meet vendors and manage your IP workflow!
No credit card or payment details required.
Join the world's most advanced AI-powered semiconductor IP marketplace!
It's free, and you'll get all the tools you need to advertise and discover semiconductor IP, keep up-to-date with the latest semiconductor news and more!
Plus we'll send you our free weekly report on the semiconductor industry and the latest IP launches!