All IPs > Processor > Security Processor
Security processors are a pivotal segment of semiconductor IPs, designed to provide robust protection for data and secure transactions within electronic systems. These processors are tailored specifically to handle encryption, decryption, digital signature generation and verification, and other cryptographic functions, ensuring the integrity and confidentiality of data across a variety of platforms. In an age where cybersecurity threats are ever-evolving, the importance of reliable security processors in modern electronic devices cannot be overstated.
This category of semiconductor IP is integral to any device that requires secure communication or data protection. Whether it's in consumer electronics such as smartphones, tablets, and laptops, or in enterprise settings with servers and data centers, security processors are essential for safeguarding sensitive information. Additionally, with the proliferation of the Internet of Things (IoT), security processors are increasingly found in everyday devices, from home automation systems to industrial IoT gadgets, ensuring that they remain robust against unauthorized access and cyberattacks.
In this category, you will find a range of products designed to meet diverse security needs, from standard encryption and secure boot capabilities to more advanced features like trusted execution environments and secure key management. These semiconductor IPs are meticulously engineered to integrate seamlessly within broader processing architectures, offering flexibility and efficiency without compromising on security. Developers and manufacturers can select from a variety of configurations and performance specifications, ensuring that the security processor IPs can be optimally aligned with their specific application requirements.
As the digital landscape continues to expand, incorporating security processors becomes a crucial aspect of electronics design. They offer not only protection but also contribute to building trust among users and stakeholders by ensuring that devices and systems can function securely and efficiently. Selecting the right security processor semiconductor IP is essential for ensuring that modern electronics can withstand the challenges of the digital age, safeguarding everything from personal data to critical enterprise resources.
AndesCore Processors offer a robust lineup of high-performance CPUs tailored for diverse market segments. Employing the AndeStar V5 instruction set architecture, these cores uniformly support the RISC-V technology. The processor family is classified into different series, including the Compact, 25-Series, 27-Series, 40-Series, and 60-Series, each featuring unique architectural advances. For instance, the Compact Series specializes in delivering compact, power-efficient processing, while the 60-Series is optimized for high-performance out-of-order execution. Additionally, AndesCore processors extend customization through Andes Custom Extension, which allows users to define specific instructions to accelerate application-specific tasks, offering a significant edge in design flexibility and processing efficiency.
The Hanguang 800 AI Accelerator by T-Head is an advanced semiconductor technology designed to accelerate AI computations and machine learning tasks. This accelerator is specifically optimized for high-performance inference, offering substantial improvements in processing times for deep learning applications. Its architecture is developed to leverage parallel computing capabilities, making it highly suitable for tasks that require fast and efficient data handling. This AI accelerator supports a broad spectrum of machine learning frameworks, ensuring compatibility with various AI algorithms. It is equipped with specialized processing units and a high-throughput memory interface, allowing it to handle large datasets with minimal latency. The Hanguang 800 is particularly effective in environments where rapid inferencing and real-time data processing are essential, such as in smart cities and autonomous driving. With its robust design and multi-faceted processing abilities, the Hanguang 800 Accelerator empowers industries to enhance their AI and machine learning deployments. Its capability to deliver swift computation and inference results ensures it is a valuable asset for companies looking to stay at the forefront of technological advancement in AI applications.
The Intelligence X280 is engineered to provide extensive capabilities for artificial intelligence and machine learning applications, emphasizing a software-first design approach. This high-performance processor supports vector and matrix computations, making it adept at handling the demanding workloads typical in AI-driven environments. With an extensive ALU and integrated VFPU capabilities, the X280 delivers superior data processing power. Capable of supporting complex AI tasks, the X280 processor leverages SiFive's advanced vector architecture to allow for high-speed data manipulation and precision. The core supports extensive vector lengths and offers compatibility with various machine learning frameworks, facilitating seamless deployment in both embedded and edge AI applications. The Intelligence family, represented by the X280, offers solutions that are not only scalable but are customizable to particular workload specifications. With high-bandwidth interfaces for connecting custom engines, this processor is built to evolve alongside AI's progressive requirements, ensuring relevance in rapidly changing technology landscapes.
The eSi-ADAS Radar IP Suite and Co-processor Engine is at the forefront of automotive and unmanned systems, enhancing radar detection and processing capabilities. It leverages cutting-edge signal processing technologies to provide accurate and rapid situational awareness, crucial for modern vehicles and aerial drones. With its comprehensive offering of radar algorithms, eSi-ADAS supports both traditional automotive radar applications and emerging unmanned aerial vehicle (UAV) platforms. This suite is crafted to meet the complex demands of real-time data processing and simultaneous multi-target tracking in dense environments, key for advanced driver-assistance systems. The co-processor engine within eSi-ADAS is highly efficient, designed to operate alongside existing vehicle systems with minimal additional power consumption. This suite is adaptable, supporting a wide range of vehicle architectures and operational scenarios, from urban driving to cross-country navigation.
The Securyzr Key Management System is pivotal in safeguarding cryptographic keys within various systems. By facilitating key lifecycle management, this system ensures that keys remain secure from creation through destruction. It offers an intuitive interface for administrators to oversee and manage keys across their network, providing peace of mind with enhanced access controls and auditing capabilities.
The RISC-V CPU IP NS Class is crafted explicitly for applications requiring heightened security and robustness, such as fintech payment systems and IoT security solutions. This processor class is equipped to support secure operations, incorporating features essential for protecting data and ensuring secure communications within devices. This processor integrates security protocols aligned with the RISC-V open standard, offering developers the ability to embed reliable security measures directly at the hardware level. Its architecture provides the foundation for developing systems where data integrity and secure processing are non-negotiable, ensuring that sensitive applications run safely and efficiently. The RISC-V CPU IP NS Class is supported by a strong ecosystem offering tools and resources to facilitate the secure application development process. With its ability to integrate seamlessly with other embedded systems, the NS Class empowers designers to create solutions that prioritize and enhance security in modern digital environments, where threats are constantly evolving.
The ReRAM Memory technology from CrossBar offers a revolutionary approach to data storage, diverging from conventional memory systems. This technology leverages a simple structure that allows it to scale down below 10nm and integrate directly with logic circuits in the same fabrication. This integration results in an optimal blend of low energy usage and high endurance, making it ideal for demanding applications such as data centers and IoT. ReRAM's capability to provide 1/20th the energy consumption, coupled with a 1000x improvement in endurance and dramatic enhancements in read/write performance, makes it a superior alternative to traditional memory technologies. The capacity for on-chip terabytes of storage further augments its appeal for modern computing needs. The innovation extends to ReRAM's ability to stack in 3D and serve various industries, from secure computing to artificial intelligence, providing the necessary performance and security for the emerging digital landscape.
The Individual IP Core Modules offered by ResQuant are designed to support a wide array of post-quantum cryptography needs, featuring compatibility with all recognized NIST PQC standards. These include pioneering algorithms such as Dilithium, Kyber, XMSS, and SPHINCS+, guaranteeing breadth in cryptographic applications. These modules offer comprehensive cryptographic functions like advanced encryption standards using AES, hashing with SHA2 and SHA3 families, and generation of true random numbers, posing as a versatile security solution adaptable to a variety of environments. Scheduled for future updates with additional protocols like the FRODO Key Encapsulation Mechanism, these IP cores promise continuous alignment with evolving cryptographic needs. Their structure accommodates substantial flexibility in terms of performance tuning and system integration, enabling easy deployment in diverse application scenarios, from IoT devices to large-scale data centers, making them a staple for entities preparing for quantum computing advancements. These modules ensure security frontiers remain resilient against future computational intricacies.
The Chimera Software Development Kit (SDK) by Quadric empowers developers with a robust platform to create and deploy complex AI and machine learning applications efficiently. It offers tools for developing, simulating, profiling, and deploying software, perfectly adaptable for Quadric’s Chimera GPNPU. The SDK simplifies coding by allowing integration of machine learning graph code with traditional C++ code into a singular, streamlined programming flow. This SDK includes the Chimera LLVM C++ compiler which utilizes state-of-the-art compiler infrastructure tailored to Chimera's specific instruction sets, driving efficiency and optimization. The SDK is compatible with Docker environments, enabling seamless on-premises or cloud-based deployment. This flexibility supports the versatile development needs of corporates working with private proprietary models while streamlining the toolchain for increased productivity. Its Graph Compiler transcodes machine learning inference models from popular frameworks like TensorFlow and PyTorch into optimized C++ using the Chimera Compute Library. This feature ensures that even the most complex AI models are efficiently deployed, lowering computational overheads and maximizing processing potential. Hence, the Chimera SDK serves as an invaluable tool for engineers aiming to expedite the deployment of cutting-edge ML algorithms both effectively and swiftly.
The PUFcc is an advanced Crypto Coprocessor that amalgamates high-level cryptographic capabilities with a robust Hardware Root of Trust foundation. This IP module is thoroughly equipped with a full suite of cryptographic algorithms certified by NIST CAVP and compliant with OSCCA standards, tailored to fulfill complex and diverse IoT security needs. The coprocessor enhances security measures across multiple layers by integrating seamless key management and secure boot functionalities within its core operations, thus expanding security boundaries to external flash and other system components. Designed for ease of integration, PUFcc simplifies the process with built-in interfaces for swift memory access and data processing, bolstering system architecture with programmable flexibility to adopt evolving security protocols.
The Cryptographic Core offers a comprehensive suite of classical cryptographic solutions. This product leverages well-established algorithms like AES for symmetric encryption and ECC for asymmetric encryption. Its design caters to both high and low-end applications, ensuring compatibility across various devices. This core is crucial for maintaining confidentiality and integrity in systems where traditional cryptography still reigns supreme. With the increasing vulnerability posed by advancing technology, including potential quantum threats, this Cryptographic Core provides secure encryption and decryption processes. Utilizing advanced algorithms such as RSA and variants of elliptic curve cryptography (ECC), it supports the secure exchange of information. Despite looming quantum computing challenges, many elements of classical cryptography remain effective and secure. The Cryptographic Core stands as a reliable option while industries transition towards more robust quantum-safe systems. It offers flexibility and adaptability, accommodating specific security needs through customization and configuration for various performance levels.
The QDID PUF provides a unique identity based directly on quantum effects observed in standard CMOS processes. These identities are inherently secure due to the randomness that originates from variations in device oxide thickness and defect distribution. By leveraging such inherent unpredictability, QDID PUFs form a robust basis for hardware root-of-trust. This IP simplifies secure provisioning by avoiding traditional factory-based key injections, thereby reducing reliance on external secure manufacturing processes. QDID PUFs also ensure that identities are not stored in memory, instead being generated dynamically. This characteristic defends against side-channel attacks exploiting memory vulnerabilities. Additionally, the high entropy of the quantum effects they harness offers robust resistance to machine learning-based entropy source attacks, generating customizable security seeds up to 256 bits. Boosting its security, the QDID PUF integrates strategic countermeasures against side-channel attacks and has been certified to comply with stringent standards like PSA Level 2 and CC EAL4+. It supports wide-ranging environmental conditions and boasts extensive process node compatibility with major fabrication technologies. Typically used for key generation and device authentication, it represents the vanguard of cryptographic consistency for post-quantum applications.
The Customizable Cryptography Accelerator by ResQuant is designed to cater to diverse client needs, offering a broad range of configurable options. It integrates seamlessly with the complete set of NIST post-quantum cryptography standards, including algorithms like Dilithium, Kyber, and XMSS. This flexibility extends further by allowing customers to incorporate their own algorithms. This cryptography accelerator is straightforward to tailor in terms of performance and size, helping cater to varied application requirements. Its design incorporates defenses against various side-channel attacks, although some features like resistance to Differential Power Analysis (DPA), timing attacks, and Simple Power Analysis (SCA) are in development. The adaptability of the accelerator is enhanced with AXI 4 compatibility, ensuring it can be easily integrated into complex system-on-chip designs. Customers can expect a future-proof, versatile cryptographic solution that addresses both existing and emerging cybersecurity challenges. This product represents a significant advancement for organizations transitioning to quantum-safe security solutions.
The Prodigy Universal Processor from Tachyum is a groundbreaking innovation designed to revolutionize data center performance. It remarkably integrates the power of CPUs, GPGPUs, and TPUs into a single homogeneous architecture. This processor architecture supports not only general computing tasks but also excels in high-performance computing, AI, and deep machine learning applications. The Prodigy is engineered to reduce power consumption drastically while significantly boosting server utilization and space efficiency, a much-needed advantage for modern data centers. One of its most praised attributes is its unrivaled performance per watt, being able to deliver up to 18 times higher performance and six times better energy efficiency compared to its peers. The processor's design overcomes the technological bottlenecks that have traditionally hindered data center efficiency, such as excessive power usage and low server utilization rates. Its streamlined architecture simplifies programming, offering a coherent multiprocessor model that easily integrates into existing data center infrastructures. Moreover, Tachyum's Universal Processor breaks free from the constraints imposed by Moore's Law, setting new standards in computational power and energy utilization. Its innovative approach allows seamless execution of traditional and high-demand AI tasks without necessitating significant overhauls in the software environment. As such, this processor is poised to be a key player in emerging technologies, driving future developments in AI and helping propel forward-thinking organizational strategies across the globe.
The RISC-V CPU IP NI Class is tailored for AI, ADAS communications, and advanced video processing applications. Developed for performance-intensive environments, this processor is equipped to handle complex computational tasks required for sophisticated AI operations and real-time data processing in advanced driver-assistance systems (ADAS). With its focus on AI and video applications, the NI Class supports a wide range of functionalities that promote efficient processing and integration into systems that demand high computational capabilities. The flexibility of the RISC-V architecture allows developers to implement custom solutions that meet specific application criteria, ensuring efficient deployment across varied markets. The RISC-V CPU IP NI Class is supported by a dynamic ecosystem providing extensive development tools and libraries to maximize its potential in applications. This ecosystem facilitates rapid prototyping and deployment, allowing designers to stay ahead in evolving industries such as multimedia processing and automotive technology, where performance and adaptability are keys to success.
PUFhsm is an advanced Hardware Security Module (HSM) developed specifically for automotive and other high-security applications. It serves as an 'Embedded Security Enclave', freeing the main CPU from handling secure tasks while ensuring comprehensive protection through EVITA-Full compliance. With capabilities such as secure boot, updates, provisioning, and lifecycle management, PUFhsm stands as a robust solution for fulfilling stringent security requirements. The module integrates cryptographic engines and a dedicated CPU, and offers extensive features for managing cryptographic keys and securing communications. By adopting PUFhsm, designers can enhance security architectures, minimizing tampering risks and improving the overall reliability of systems in mission-critical environments.
The EMSA5-FS is a 32-bit RISC-V embedded processor core optimized for functional safety applications, adhering to the ISO 26262 ASIL-D guidelines. It features a single-issue, in-order, 5-stage pipeline design. The core accommodates optional configurations such as the L0 instruction cache. Enhanced with fail-safe features like Dual Modular Redundancy (DMR) and Error Correcting Code (ECC), it's designed to deliver reliable performance in safety-critical environments. The EMSA5-FS excels in both ASIC and FPGA deployments, with the flexibility to operate at frequencies surpassing 1GHz in advanced node technologies. Its deliverables include a comprehensive Safety Manual and Failure Modes, Effects and Diagnostics Analysis (FMEDA) document, ensuring thorough functional safety compliance.
The Evo Gen 5 PCIe Card is crafted for the next generation of AI inferencing, focusing on advancing the capabilities of deep learning models. Designed to provide high performance inferences, this PCIe card leverages Gen 5 technology to deliver faster data throughput and improved energy efficiency. The Evo Gen 5's capabilities are well-suited for demanding computational tasks found in modern AI applications, offering an elevated level of integration and performance. Engineered to optimize AI frameworks, the Evo Gen 5 PCIe Card ensures a seamless blend with existing hardware setups, reducing downtime and promoting operational continuity. Its robust architecture allows it to handle the intricate requirements of large-scale neural network models with ease, making it an indispensable tool for sectors relying heavily on AI inference. With its state-of-the-art design, the Evo Gen 5 PCIe Card supports diverse workloads, ensuring high adaptability across various AI landscapes. Businesses focused on AI innovation will find this card instrumental in maintaining a competitive edge, thanks to its blend of speed, reliability, and efficiency.
Suite-Q SW consists of a versatile cryptographic software library designed for optimizing code size, stack usage, and performance across various embedded processors and microcontrollers. Available in portable C code and high-speed assembly, Suite-Q SW can be tailored to fit the specific needs of diverse development environments. This library provides extensive support for symmetric and asymmetric cryptographic functions, catering to systems ranging from high-end processors to memory-constrained embedded devices. By facilitating efficient cryptographic computations, Suite-Q SW ensures minimal impact on system performance while maximizing data security. Its adaptability is marked by simple integration modules that work seamlessly with hardware accelerators, enabling enhanced cryptography for both standard and custom specifications. This reliability makes Suite-Q SW an indispensable tool for ensuring secure communication channels while maintaining an optimal balance between speed and resource utilization.
For applications requiring ISO26262 functional safety standards, the RISC-V CPU IP NA Class caters to the automotive industry's safety-critical demands. This processor is tailored to support the development of automotive systems that demand rigorous safety protocols and are utilized in high-assurance environments, where failures are not an option. By adhering to functional safety standards like ASIL-B and ASIL-D, the NA Class processors lay the groundwork for developing safe automotive solutions. Its architecture is crafted to manage safety requirements effectively, enabling automotive manufacturers to integrate reliable safety mechanisms directly into their products, ensuring compliance with industry standards. The RISC-V CPU IP NA Class is integrated into an ecosystem that includes support for development tools necessary to leverage the processor's capabilities fully. From simulation environments to safety-focused development kits, these resources help streamline the process of creating and validating automotive solutions, ultimately ensuring that vehicles equipped with NA Class processors operate safely under all conditions.
Suite-Q HW represents a sophisticated system-on-chip (SoC) design that integrates essential cryptographic operations crucial for modern data security protocols. Targeting both high-end servers and low-end embedded systems, Suite-Q HW employs a unified hardware architecture to ensure efficient execution of cryptographic tasks. This hardware solution supports a diverse range of cryptographic algorithms, including both classical and post-quantum options. It incorporates advanced public key cryptographic operations such as ECDSA and various isogeny, lattice, and code-based strategies awaiting broader standardization. The suite’s flexibility allows it to adapt to different operational demands and integrate with existing infrastructure seamlessly. Suite-Q HW's cornerstone is its high degree of configurability, offering customizable performance based on targeted applications. This versatility ensures optimal resource allocation, making it a preferred choice for systems requiring stringent security measures without compromising on computational efficiency. With optional features for defending against differential power analysis (DPA) attacks, the SoC further enhances its defense mechanisms, ensuring robust protection against sophisticated threats.
The Time-to-Digital Converter (TDC) Core is a state-of-the-art module intended for high-accuracy time measurement applications, offering time resolutions as fine as 5 picoseconds. This remarkable precision makes it indispensable in fields requiring exact timing solutions. Integrated with CP-Line technology, each component of the TDC core facilitates unparalleled accuracy in time-stamping and time interval measurements. Whether used for scientific research, communication timing, or precision instrumentation, this Core is engineered to deliver exceptional performance. The TDC core offers an innovative platform for systems that need precise timing, such as synchronization of events and phases. These capabilities extend its use in sectors like telecommunications, where inline data transfer accuracy is vital, and scientific sectors demanding high-resolution temporal measurements.
DRV32IMZicsr – Scalable RISC-V Power. Tailored for Your Project. Ready for the Future. The DRV32IMZicsr is a high-performance, 32-bit RISC-V processor core, equipped with M (Multiply/Divide), Zicsr (Control and Status Registers), and External Debug support. Built as part of DCD’s latest DRVX Core Family, it delivers the full flexibility, openness, and innovation that RISC-V promises—without locking you into proprietary architectures. ✅ Why RISC-V? RISC-V is a rapidly growing open standard for modern computing—backed by a global ecosystem of developers and vendors. It brings: * Freedom from licensing fees and vendor lock-in * Scalability from embedded to high-performance systems * Customizability with standard and custom instruction sets * Strong toolchain & ecosystem support 🚀 DRV32IMZicsr Highlights: * Five-stage pipeline and Harvard architecture for optimized performance * Configurable memory architecture: size and address allocation tailored to your needs Performance metrics: * **Up to 1.15 DMIPS/MHz** * **Up to 2.36 CoreMark/MHz** * Minimal footprint starting from just 14k gates * Flexible interfaces: Choose from AXI, AHB, or native bus options 🛡️ Designed for Safety & Integration: * Developed as an ISO 26262 Safety Element out of Context (SEooC) * Fully technology-agnostic, compatible with all FPGA and ASIC platforms * Seamless integration with DCD’s rich portfolio of IPs: DMA, SPI, UART, PWM, CAN, and more 🔍 Advanced Feature Set: * 32 general-purpose registers * Support for arithmetic, logic, load/store, conditional and unconditional control flow * M extension enables efficient integer multiplication/division * Zicsr extension provides robust interrupt and exception handling, performance counters, and timers * External Debug via JTAG: compliant with RISC-V Debug Specification 0.13.2 and 1.0.0, compatible with all mainstream tools 🧪 Developer-Ready: * Delivered with a fully automated testbench * Includes a comprehensive validation test suite for smooth integration into your SoC flow Whether you're building for automotive, IoT, consumer electronics, or embedded systems, the DRV32IMZicsr offers a future-ready RISC-V solution—highly configurable, performance-optimized, and backed by DCD’s 25 years of experience. Interested? Let’s build the next generation together. 📩 Contact us at info@dcd.pl
**DRV64IMZicsr – 64-bit RISC-V Performance. Designed for Demanding Innovation.** The DRV64IMZicsr is a powerful and versatile 64-bit RISC-V CPU core, built to meet the performance and safety needs of next-generation embedded systems. Featuring the M (Multiply/Divide), Zicsr (Control and Status Registers), and External Debug extensions, this core is engineered to scale—from edge computing to mission-critical applications. As part of the DRVX Core Family, the DRV64IMZicsr embodies DCD’s philosophy of combining open-standard freedom with customizable IP excellence—making it a smart and future-proof alternative to legacy architectures. ✅ Why Choose RISC-V? * No license fees – open-source instruction set means reduced TCO * Unmatched flexibility – tailor the architecture to your specific needs * A global, thriving ecosystem – support from toolchains, OSes, and hardware vendors * Security & longevity – open and verifiable architecture ensures trust and sustainability 🚀 DRV64IMZicsr – Core Advantages: * 64-bit RISC-V ISA with M, Zicsr, and Debug support * Five-stage pipeline, Harvard architecture, and efficient branch prediction * Configurable memory size and allocation for program and data spaces Performance optimized: * **Up to 2.38 CoreMark/MHz** * **Up to 1.17 DMIPS/MHz** * Compact footprint starting from just 17.6k gates * Interface options: AXI, AHB, or native * Compatible with Classical CAN, CAN FD, and CAN XL through additional IPs 🛡️ Safety, Compatibility & Flexibility Built In: * Developed as an ISO 26262 Safety Element out of Context (SEooC) * Technology-agnostic – works seamlessly across all FPGA and ASIC vendors * Expandable with DCD’s IP portfolio: DMA, SPI, UART, I²C, CAN, PWM, and more 🔍 Robust Feature Set for Real Applications: * Full 64-bit processing – ideal for performance-intensive, memory-heavy tasks * M extension enables high-speed multiplication/division via dedicated hardware unit * Zicsr extension gives full access to Control and Status Registers, enabling: * Interrupts and exception handling (per RISC-V Privileged Spec) * Performance counters and timers * JTAG-compatible debug interface – compliant with RISC-V Debug Spec (0.13.2 & 1.0.0) 🧪 Ready for Development & Integration: * Comes with a fully automated testbench * Includes a comprehensive suite of validation tests for smooth SoC integration * Supported by industry-standard tools, ensuring a hassle-free dev experience Whether you’re designing for automotive safety, industrial control, IoT gateways, or AI-enabled edge devices, the DRV64IMZicsr gives you the performance, flexibility, and future-readiness of RISC-V—without compromise. 💡 Build smarter, safer systems—on your terms. 📩 Contact us today at info@dcd.pl to start your next RISC-V-powered project.
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