All IPs > Processor > Coprocessor
In the realm of modern computing, coprocessor semiconductor IPs play a crucial role in augmenting system capabilities. A coprocessor is a supplementary processor that executes specific tasks more efficiently than the primary central processing unit (CPU). These coprocessors are specialized semiconductor IPs utilized in devices requiring enhanced computational power for particular functions such as graphics rendering, encryption, mathematical calculations, and artificial intelligence (AI) processing.
Coprocessors are integral in sectors where high performance and efficiency are paramount. For instance, in the gaming industry, a graphics processing unit (GPU) acts as a coprocessor to handle the high demand for rendering visuals, thus alleviating the burden from the CPU. Similarly, AI accelerators in smartphones and servers offload intensive AI computation tasks to speed up processing while conserving power.
You will find various coprocessor semiconductor IP products geared toward enhancing computational specialization. These include digital signal processors (DSPs) for processing real-time audio and video signals and hardware encryption coprocessors for securing data transactions. With the rise in machine learning applications, tensor processing units (TPUs) have become invaluable, offering massively parallel computing to efficiently manage AI workloads.
By incorporating these coprocessor semiconductor IPs into a system design, manufacturers can achieve remarkable improvements in speed, power efficiency, and processing power. This enables the development of cutting-edge technology products across a range of fields from personal electronics to autonomous vehicles, ensuring optimal performance in specialized computing tasks.
BrainChip's Akida Neural Processor IP is a groundbreaking development in neuromorphic processing, designed to mimic the human brain in interpreting sensory inputs. By implementing an event-based architecture, it processes only the critical data at the point of acquisition, achieving unparalleled performance with significantly reduced power consumption. This architecture enables on-chip learning, reducing dependency on cloud processing, thus enhancing privacy and security.\n\nThe Akida Neural Processor IP supports incremental learning and high-speed inference across a vast range of applications, making it highly versatile. It is structured to handle data sparsity effectively, which cuts down on operations substantially, leading to considerable improvements in efficiency and responsiveness. The processor's scalability and compact design allow for wide deployment, from minimal-node setups for ultra-low power operations to more extensive configurations for handling complex tasks.\n\nImportantly, the Akida processor uses a fully customizable AI neural processor that leverages event-based processing and an on-chip mesh network for seamless communication. The technology also features support for hybrid quantized weights and provides robust tools for integration, including fully synthesizable RTL IP packages, hardware-based event processing, and on-chip learning capabilities.
MetaTF is BrainChip's proprietary software development framework built to streamline the creation, training, and deployment of neural networks on their Akida neuromorphic processor. This tool is designed specifically for working with edge AI, complementing the hardware capabilities of Akida by providing a rich environment for model development and conversion.\n\nThe framework supports the conversion of traditional TensorFlow and Keras models into spiking neural networks optimized for BrainChip's unique event-based processing. This conversion allows developers to harness the energy efficiency and performance benefits of the Akida architecture without needing to overhaul existing machine learning frameworks.\n\nMetaTF facilitates the adaptation of models to the Akida system through its model zoo, which includes various pre-configured network models, and offers comprehensive tools for simulation and testing. This environment makes it an indispensable resource for businesses aiming to deploy sophisticated AI applications at the edge, minimizing development time while maximizing performance and efficiency.
RaiderChip's GenAI v1 is a pioneering hardware-based generative AI accelerator, designed to perform local inference at the Edge. This technology integrates optimally with on-premises servers and embedded devices, offering substantial benefits in privacy, performance, and energy efficiency over traditional hybrid AI solutions. The design of the GenAI v1 NPU streamlines the process of executing large language models by embedding them directly onto the hardware, eliminating the need for external components like CPUs or internet connections. With its ability to support complex models such as the Llama 3.2 with 4-bit quantization on LPDDR4 memory, the GenAI v1 achieves unprecedented efficiency in AI token processing, coupled with energy savings and reduced latency. What sets GenAI v1 apart is its scalability and cost-effectiveness, significantly outperforming competitive solutions such as Intel Gaudi 2, Nvidia's cloud GPUs, and Google's cloud TPUs in terms of memory efficiency. This solution maximizes the number of tokens generated per unit of memory bandwidth, thus addressing one of the primary limitations in generative AI workflow. Furthermore, the adept memory usage of GenAI v1 reduces the dependency on costly memory types like HBM, opening the door to more affordable alternatives without diminishing processing capabilities. With a target-agnostic approach, RaiderChip ensures the GenAI v1 can be adapted to various FPGAs and ASICs, offering configuration flexibility that allows users to balance performance with hardware costs. Its compatibility with a wide range of transformers-based models, including proprietary modifications, ensures GenAI v1's robust placement across sectors requiring high-speed processing, like finance, medical diagnostics, and autonomous systems. RaiderChip's innovation with GenAI v1 focuses on supporting both vanilla and quantized AI models, ensuring high computation speeds necessary for real-time applications without compromising accuracy. This capability underpins their strategic vision of enabling versatile and sustainable AI solutions across industries. By prioritizing integration ease and operational independence, RaiderChip provides a tangible edge in applying generative AI effectively and widely.
Designed for entry-level server-class applications, the SCR9 is a 64-bit RISC-V processor core that comes equipped with cutting-edge features, such as an out-of-order superscalar pipeline, making it apt for processing-intensive environments. It supports both single and double-precision floating-point operations adhering to IEEE standards, which ensure precise computation results. This processor core is tailored for high-performance computing needs, with a focus on AI and ML, as well as conventional data processing tasks. It integrates an advanced interrupt system featuring APLIC configurations, enabling responsive operations even under heavy workloads. SCR9 supports up to 16 cores in a multi-cluster arrangement, each utilizing coherent multi-level caches to maintain rapid data processing and management. The comprehensive development package for SCR9 includes ready-to-deploy toolchains and simulators that expedite software development, particularly within Linux environments. The core is well-suited for deployment in entry-level server markets and data-intensive applications, with robust support for virtualization and heterogeneous architectures.
Altek Corporation's 3D Imaging Chip is designed to enhance three-dimensional sensing capabilities across various applications. By incorporating advanced image processing algorithms, it delivers superior depth perception and spatial awareness, making it well-suited for industries that require high precision and accuracy. This chip is particularly beneficial in robotics, automation, and surveillance, where accurate distance measurement and object tracking are critical.<br/><br/>The chip's innovative design allows for seamless integration with existing systems, optimizing performance without compromising on speed or quality. Its ability to deliver real-time processing enables dynamic interactions, providing improved user experiences in augmented and virtual reality environments. Moreover, the chip's energy-efficient construction ensures prolonged operation without excessive power consumption, making it an ideal choice for portable devices.<br/><br/>Altek's commitment to pushing the boundaries of imaging technology is evident in this 3D Imaging Chip. It combines hardware resilience with software intricacy, creating a robust solution that supports a multitude of applications, from industrial automation to healthcare equipment, enhancing operational efficiency through sophisticated visual data analysis.
xcore.ai is a powerful platform tailored for the intelligent IoT market, offering unmatched flexibility and performance. It boasts a unique multi-threaded micro-architecture that provides low-latency and deterministic performance, perfect for smart applications. Each xcore.ai contains 16 logical cores distributed across two multi-threaded processor tiles, each equipped with 512kB of SRAM and capable of both integer and floating-point operations. The integrated interprocessor communication allows high-speed data exchange, ensuring ultimate scalability across multiple xcore.ai SoCs within a unified development environment.
The GenAI v1-Q from RaiderChip brings forth a specialized focus on quantized AI operations, reducing memory requirements significantly while maintaining impressive precision and speed. This innovative accelerator is engineered to execute large language models in real-time, utilizing advanced quantization techniques such as Q4_K and Q5_K, thereby enhancing AI inference efficiency especially in memory-constrained environments. By offering a 276% boost in processing speed alongside a 75% reduction in memory footprint, GenAI v1-Q empowers developers to integrate advanced AI capabilities into smaller, less powerful devices without sacrificing operational quality. This makes it particularly advantageous for applications demanding swift response times and low latency, including real-time translation, autonomous navigation, and responsive customer interactions. The GenAI v1-Q diverges from conventional AI solutions by functioning independently, free from external network or cloud auxiliaries. Its design harmonizes superior computational performance with scalability, allowing seamless adaptation across variegated hardware platforms including FPGAs and ASIC implementations. This flexibility is crucial for tailoring performance parameters like model scale, inference velocity, and power consumption to meet exacting user specifications effectively. RaiderChip's GenAI v1-Q addresses crucial AI industry needs with its ability to manage multiple transformer-based models and confidential data securely on-premises. This opens doors for its application in sensitive areas such as defense, healthcare, and financial services, where confidentiality and rapid processing are paramount. With GenAI v1-Q, RaiderChip underscores its commitment to advancing AI solutions that are both environmentally sustainable and economically viable.
The Veyron V1 CPU is designed to meet the demanding needs of data center workloads. Optimized for robust performance and efficiency, it handles a variety of tasks with precision. Utilizing RISC-V open architecture, the Veyron V1 is easily integrated into custom high-performance solutions. It aims to support the next-generation data center architectures, promising seamless scalability for various applications. The CPU is crafted to compete effectively against ARM and x86 data center CPUs, providing the same class-leading performance with added flexibility for bespoke integrations.
The DisplayPort Transmitter from Trilinear Technologies is a sophisticated solution designed for high-performance digital video streaming applications. It is compliant with the latest VESA DisplayPort standards, ensuring compatibility and seamless integration with a wide range of display devices. This transmitter core supports high-resolution video outputs and is equipped with advanced features like adaptive sync and panel refresh options, making it ideal for consumer electronics, automotive displays, and professional AV systems. This IP core provides reliable performance with minimal power consumption, addressing the needs of modern digital ecosystems where energy efficiency is paramount. It includes customizable settings for audio and video synchronization, ensuring optimal output quality and user experience across different devices and configurations. By reducing load on the system processor, the DisplayPort Transmitter guarantees a seamless streaming experience even in high-demand environments. In terms of integration, Trilinear's DisplayPort Transmitter is supported with comprehensive software stacks allowing for easy customization and deployment. This ensures rapid product development cycles and aids developers in managing complex video data streams effectively. The transmitter is particularly optimized for use in embedded systems and consumer devices, offering robust performance capabilities that stand up to rigorous real-time application demands. With a focus on compliance and testing, the DisplayPort Transmitter is pre-tested and proven to work seamlessly with a variety of hardware platforms including FPGA and ASIC technologies. This robustness in design and functionality underlines Trilinear's reputation for delivering reliable, high-quality semiconductor IP solutions that cater to diverse industrial applications.
The Spiking Neural Processor T1 is a microcontroller tailored for ultra-low-power applications demanding high-performance pattern recognition at the sensor edge. It features an advanced neuromorphic architecture that leverages spiking neural network engines combined with RISC-V core capabilities. This architecture allows for sub-milliwatt power dissipation and sub-millisecond latency, enabling the processor to conduct real-time analysis and identification of embedded patterns in sensor data while operating in always-on scenarios. Additionally, the T1 provides diverse interfaces, making it adaptable for use with various sensor types.
DolphinWare IPs is a versatile portfolio of intellectual property solutions that enable efficient SoC design. This collection includes various control logic components such as FIFO, arbiter, and arithmetic components like math operators and converters. In addition, the logic components span counters, registers, and multiplexers, providing essential functionalities for diverse industrial applications. The IPs in this lineup are meticulously designed to ensure data integrity, supported by robust verification IPs for AXI4, APB, SD4.0, and more. This comprehensive suite meets the stringent demands of modern electronic designs, facilitating seamless integration into existing design paradigms. Beyond their broad functionality, DolphinWare’s offerings are fundamental to applications requiring specific control logic and data integrity solutions, making them indispensable for enterprises looking to modernize or expand their product offerings while ensuring compliance with industry standards.
Trilinear Technologies has developed a cutting-edge DisplayPort Receiver that enhances digital connectivity, offering robust video reception capabilities necessary for today's high-definition video systems. Compliant with VESA standards, the receiver supports the latest DisplayPort specifications, effortlessly handling high-bandwidth video data necessary for applications such as ultra-high-definition televisions, professional video wall setups, and complex automotive display systems. The DisplayPort Receiver is designed with advanced features that facilitate seamless video data acquisition and processing, including multi-stream transport capabilities for handling multiple video streams concurrently. This is particularly useful in professional display settings where multiple input sources are needed. The core also incorporates adaptive sync features, which help reduce screen tearing and ensure smooth video playback, enhancing user experience significantly. An important facet of the DisplayPort Receiver is its low latency and high-efficiency operations, crucial for systems requiring real-time data processing. Trilinear's receiver core ensures that video data is processed with minimal delay, maintaining the integrity and fidelity of the original visual content. This makes it a preferred choice for high-performance applications in sectors like gaming, broadcasting, and high-definition video conferencing. To facilitate integration and ease of use, the DisplayPort Receiver is supported by a comprehensive suite of development tools and software packages. This makes the deployment process straightforward, allowing developers to integrate the receiver into both FPGA and ASIC environments with minimal adjustments. Its scalability and flexibility mean it can meet the demands of a wide range of applications, solidifying Trilinear Technologies' position as a leader in the field of semiconductor IP solutions.
The RISC-V Hardware-Assisted Verification by Bluespec is designed to expedite the verification process for RISC-V cores. This platform supports both ISA and system-level testing, adding robust features such as verifying standard and custom ISA extensions along with accelerators. Moreover, it offers scalable access through the AWS cloud, making verification available anytime and anywhere. This tool aligns with the needs of modern developers, ensuring thorough testing within a flexible and accessible framework.
Dyumnin Semiconductors' RISCV SoC is a robust solution built around a 64-bit quad-core server-class RISC-V CPU, designed to meet advanced computing demands. This chip is modular, allowing for the inclusion of various subsystems tailored to specific applications. It integrates a sophisticated AI/ML subsystem that features an AI accelerator tightly coupled with a TensorFlow unit, streamlining AI operations and enhancing their efficiency. The SoC supports a multimedia subsystem equipped with IP for HDMI, Display Port, and MIPI, as well as camera and graphic accelerators for comprehensive multimedia processing capabilities. Additionally, the memory subsystem includes interfaces for DDR, MMC, ONFI, NorFlash, and SD/SDIO, ensuring compatibility with a wide range of memory technologies available in the market. This versatility makes it a suitable choice for devices requiring robust data storage and retrieval capabilities. To address automotive and communication needs, the chip's automotive subsystem provides connectivity through CAN, CAN-FD, and SafeSPI IPs, while the communication subsystem supports popular protocols like PCIe, Ethernet, USB, SPI, I2C, and UART. The configurable nature of this SoC allows for the adaptation of its capabilities to meet specific end-user requirements, making it a highly flexible tool for diverse applications.
The PACE Photonic Arithmetic Computing Engine from Lightelligence represents a paradigm shift in computing technologies. By utilizing photonic processes, this product significantly boosts computing speeds while maintaining energy efficiency. PACE is designed to leverage the inherent capabilities of photonics to perform high-speed arithmetic calculations, which are essential for complex data processing tasks. It's an ideal solution for industries demanding rapid and intensive computational power without the typical energy overhead.<br> <br> This advanced engine is central to the development of next-generation computing environments, where performance metrics exceed traditional expectations. By converting light signals into computing potential, PACE ensures that intensive processes such as AI computations, data analyses, and real-time processing are handled more efficiently. This product is tailored for enterprises seeking to minimize latency and enhance throughput across various applications.<br> <br> PACE not only meets the requirements of current computational demands but also sets the stage for future innovations in the field. It's a promising tool for developers and researchers aiming to explore the unexplored realms of digital capabilities, fostering an era of optical computing that's faster and more efficient than ever before. This makes PACE an indispensable component in both current and upcoming technological advancements.
The RV32EC_P2 core is a streamlined 2-stage pipeline RISC-V processor core aimed at small, low-power embedded applications. This processor core is designed to run only trusted firmware and can be implemented in both ASIC and FPGA-based design flows. It is compliant with RISC-V User-Level ISA V2.2, incorporating standard compressed instructions to minimize code size and optional integer multiplication and division instructions for flexibility. With a simple machine-mode privileged architecture, it supports direct physical memory addressing, along with an external interrupt controller for expanded interrupt handling. The core also integrates tightly-coupled memory interfaces and a low-power idle state option, making it highly adaptable for various low-energy applications.
SystemBIST is a revolutionary plug-and-play device designed to facilitate flexible FPGA configuration and embedded JTAG testing. As part of Intellitech's TEST-IP family, this tool is vendor-independent, capable of configuring all IEEE 1532 or IEEE 1149.1 compliant FPGAs and CPLDs in-system. SystemBIST employs patented architecture enabling design engineers to create high-quality, self-testable, and reconfigurable field-ready products, negating the need for custom firmware or software-driven built-in tests. Through its interface, SystemBIST allows for the reprogramming of system CPLDs, EEPROMs, and FLASH in the field, reusing manufacturing test patterns and scripts. This dramatically reduces the cost and complexity traditionally associated with board-level BIST systems. The ability to store tests and FPGA configurations compressed in FLASH memory, permits PCBs to be tested conveniently whenever power is available, enhancing the operational flexibility. Not only does this solution offer comprehensive testing capabilities, but it also includes troubleshooting and security features like anti-tamper FPGA security options, preventing unauthorized bitstream overwriting. SystemBIST, while reducing overall system costs, provides significant benefits such as deterministic built-in self-test, eliminating the need for costly ATE systems, and providing seamless test and configuration updates across a product’s lifecycle, making it an invaluable tool for modern PCB testing demands.
iCEVision facilitates rapid prototyping and evaluation of connectivity features using the Lattice iCE40 UltraPlus FPGA. Designers can take advantage of exposed I/Os for quick implementation and validation of solutions, while enjoying compatibility with common camera interfaces such as ArduCam CSI and PMOD. This flexibility is complemented by software tools such as the Lattice Diamond Programmer and iCEcube2, which allow designers to reprogram the onboard SPI Flash and develop custom solutions. The platform comes preloaded with a bootloader and an RGB demo application, making it quick and easy for users to begin experimenting with their projects. Its design includes features like a 50mmx50mm form factor, LED applications, and multiple connectivity options, ensuring broad usability across various rapid prototyping scenarios. With its user-friendly setup and comprehensive toolkit, iCEVision is perfect for developers who need a streamlined path from initial design to functional prototype, especially in environments where connectivity and sensor integration are key.
The Maverick-2 Intelligent Compute Accelerator is an advanced computing architecture that revolutionizes the handling of high-performance tasks through intelligent software-defined hardware. It optimizes workloads in real time, ensuring that computational resources are used efficiently to accelerate applications in high-performance computing (HPC) and artificial intelligence (AI). Designed to support demanding workloads, Maverick-2 improves developer productivity and reduces the time-to-solution significantly by bypassing the traditional need for extensive application porting. This cutting-edge system uses an adaptable architecture that dynamically adjusts to application demands, freeing developers to focus on scientific or computational breakthroughs without being encumbered by technical complexities. With support for a wide array of programming languages and frameworks, including C/C++, FORTRAN, and OpenMP, Maverick-2 provides a flexible platform that reduces the need for code rewriting or vendor-specific tools. Operating on TSMC's advanced 5nm process technology, the Maverick-2 boasts significant power efficiencies and scalability, with deployments in single or dual configurations to suit various computational needs. It combines HBM3E memory and high-bandwidth interfaces to ensure high throughput and low-latency data access, crucial for many contemporary scientific and industrial applications. Moreover, the intelligent architecture adapts over time, future-proofing investments by evolving alongside new computing needs and technologies.
The Origami Programmer is a sophisticated configuration tool for Menta’s eFPGA architecture. This software stands out for delivering an easy-to-use interface, which simplifies the complex tasks of synthesis, place-and-route, and static timing analysis. Designed to optimize RTL specifically for the Menta eFPGA, Origami Programmer enables designers to bypass the need for additional FPGA configuration tools. Within its intuitive environment, users can benefit from a range of functionalities, such as an embedded Verific parser for synthesizing designs written in VHDL, Verilog, or SystemVerilog. The tool provides comprehensive analysis capabilities, including complete path and setup/hold reports, ensuring thorough insights into the design's performance metrics. Aimed at improving the design process efficiency, Origami Programmer supports various technology nodes and libraries, permitting performance estimations and resources optimization directly. This seamless integration and the ability to adapt configurations efficiently make Origami Programmer an indispensable asset in eFPGA design and implementation.
FortiPKA-RISC-V is a high-speed public key accelerator that enhances the efficiency of cryptographic tasks by offloading complex operations from the main CPU. It is particularly effective for tasks involving large integer arithmetic typical in asymmetric cryptography. The design eliminates the need for data transformations linked to Montgomery domain conversion, boosting performance significantly. The RISC-V core allows flexible integration using interfaces such as AMBA AXI4, APB, and others. It supports a wide range of cryptographic algorithms including RSA, ECDSA, and SM2, maintaining resilience against side-channel attacks through robust technological methodologies. This solution proves ideal for embedded systems in IoT, automotive, and payment systems, offering high configurability to align with specific performance and area requirements.
The Cobalt GNSS Receiver is a state-of-the-art ultra-low-power GNSS receiver that significantly enhances IoT system-on-chip designs. It provides a compact yet powerful solution for integrating navigation capabilities into mobile and compact IoT devices. By sharing resources between GNSS and other modem functions, Cobalt offers cost and size efficiency to extend the market potential of products. Cobalt excels in mass-market applications, particularly those constrained by size and cost, such as logistics, agriculture, and animal tracking. It employs a software-defined approach, making it versatile across different satellite constellations including Galileo and GPS, and is designed to be supported with cloud assistance for enhanced positioning accuracy and energy optimization. Developed in collaboration with CEVA DSP and supported by the European Space Agency, this GNSS receiver delivers improved resistance to multi-path interference and an increased modulation rate for optimal accuracy. The inclusion of integrated resources ensures a seamless continuation of GNSS-enabled services, reducing power demands in comparison to conventional receivers.
The RV32IC_P5 processor core is tailored for medium-scale embedded applications that require enhanced performance. Featuring a 5-stage pipeline, this RISC-V processor supports a wider range of applications due to its ability to handle both trusted firmware and user-level applications. Enhanced with machine-mode and user-mode privileged architecture, it is compliant with RISC-V Privileged Architecture Version 1.10. The core offers optional support for branch prediction and data cache memories, delivering high-speed processing capabilities. With its sophisticated design, it is suitable for ASIC and FPGA-based implementations, supporting various execution contexts through an array of configurable options such as interrupt management and memory protection.
The Neural Network Accelerator by Gyrus AI is designed for high-performance and energy-efficient computation in edge computing environments. With a core focus on maximizing throughput and minimizing latency, this accelerator implements advanced graph processing techniques. It achieves impressive performance metrics, delivering up to 30 Tera Operations Per Second per Watt (TOPS/W), alongside significantly lower power requirements, thanks to its optimized memory usage configurations. This minimizes the die area and power consumption while supporting various neural network models efficiently. Leveraging this technology, companies can enhance computational speed and reduce energy expenditure in their AI applications, making it particularly suitable for enterprises aiming to deploy AI at scale on the edge. Gyrus AI's solution also includes complementary software tools that facilitate seamless integration and operation of neural networks, ensuring they run smoothly on the hardware without extensive manual intervention. The Neural Network Accelerator thus stands out as a critical component for businesses looking to leverage AI-powered tools and applications on reduced hardware footprints, emphasizing not just performance, but also operational economy and sustainability. Supported by state-of-the-art software applications and designed for easy adaptability across various hardware architectures, this solution empowers enterprises to transition smoothly to AI-driven operations, enhancing both computing efficiency and strategic business outcomes.
eSi-Floating Point cores offer a complete suite for executing IEEE 754-2008 compliant floating-point arithmetic operations, integral for projects requiring mathematical precision and effective data handling in sophisticated computing environments. These operations include addition, subtraction, multiplication, division, and more, applicable for single, double, and half-precision contexts. Cores within this suite are engineered to accommodate denormalized numbers, infinities, NaNs, and support rounding strategies alongside exception flags indicating calculation precision or errors. This solidifies their functionally robust design adaptable to diverse floating-point processor requirements. Fully pipelined to ensure one output per cycle, the distribution of these IP cores includes technology-independent formats (Verilog HDL), ensuring compatibility across ASIC and FPGA deployments. This versatility makes them an essential asset for computational applications across industries demanding high precision and consistent performance.
Advanced Silicon's Specialty Microcontrollers set a new standard in high-performance computing with their integration of cutting-edge RISC-V architectures and advanced coprocessing capabilities. These MCUs are tailored for demanding applications requiring precise and rapid data processing, including image processing and complex algorithm execution. The specialty microcontrollers boast sophisticated features like embedded algorithms that cater to modern interactive touchscreen and machine learning applications. They perfectly complement Advanced Silicon's touch components, providing high levels of user interface innovation, system reliability, and operational efficiency. Whether for small-scale or expansive digital touch interfaces, these MCUs offer the processing power and integration needed to meet the demands of interactive technology solutions. Advanced Silicon continues to enhance these MCUs’ feature sets, keeping them at the forefront of technological capabilities in computing and interfacing systems.
Designed to excel in AI-powered recommendation systems, the RecAccel N3000 PCIe Card offers significant advancements in processing speed and reliability. By focusing on enhancing recommendation accuracy and throughput, this PCIe card aligns itself as a valuable asset for data-intensive environments. Its design accommodates the high-speed demands necessary for cutting-edge recommendation models, ensuring efficient data handling and real-time application performance. The RecAccel N3000 PCIe Card is anchored by a robust hardware configuration that facilitates low-latency data processing, granting organizations the ability to harness the full potential of AI-driven insights. Adaptable and versatile, it enables seamless integration with various AI frameworks, supporting a broad spectrum of applications across industries. Through its focus on minimizing energy consumption while maximizing computational output, the RecAccel N3000 PCIe Card stands as a leader in power efficiency. This makes it a wise investment for enterprises looking to enhance their recommendation capabilities without incurring excessive energy costs.
Menta’s Adaptive Digital Signal Processor (DSP) is tailored for managing and optimizing signal processing tasks within embedded systems. This IP is ideal for applications demanding high processing performance without compromising energy consumption or space. Utilizing Menta’s standard-cell approach, this DSP ensures ease of integration across various process nodes with high efficiency. Integrated with customizable algorithms and interfaces, Menta’s DSP provides engineers the flexibility to implement specific processing tasks tailored to their applications. This adaptability is crucial for areas like real-time data analysis and machine learning, where rapid response and prediction accuracy are essential. By leveraging the advantages of Menta’s eFPGA base, such processors offer exemplary processing speed, reduced latency, and energy-efficient operation. These attributes significantly contribute to optimizing applications across sectors including automotive, telecommunications, and portable electronics, making Menta’s DSP a standout choice for developers seeking performance and innovation.
This IP from Gyrus AI empowers enterprises with data-driven insights for smarter decision-making processes. It integrates machine learning algorithms to analyze large datasets, enabling transparent and explainable AI model deployment. By developing complimentary explainability models alongside complex deep-learning frameworks, Gyrus AI ensures that decision-making paths are well-accounted for, significantly enhancing enterprise data analytics capabilities. The AI in BI solution covers aspects such as inventory management, anomaly detection, and forecasting, with models allowing for data augmentation and dynamic analysis. These features are tailored to optimize business operations across various domains, transforming raw data inputs into actionable intelligence through sophisticated analytics and processing methodologies. Further, the tool leverages statistical and NLP techniques to enhance customer interaction, process optimization, and equipment usage analysis, enabling businesses to streamline operations and improve customer engagement and service delivery. It acts as a bridge that mitigates the complexity of AI deployments, ensuring its seamless integration into existing business processes. Overall, Gyrus AI's Business Intelligence offering is designed for enterprises keen on driving innovation and operational efficiency, fostering a landscape where intelligent systems aid in strategic data-driven decision-making.
The Miscellaneous FEC and DSP IP Cores from Creonic encompass a comprehensive range of digital signal processing and forward error correction solutions tailored for various communication challenges. These cores are pivotal for enhancing signal integrity and performance across diverse communication frameworks. A standout feature within this collection is the Fast Fourier Transform (FFT/IFFT) core, which is crucial in converting signals between time and frequency domains, a key process in modern communication systems. Meanwhile, the DVB-GSE encapsulates data, optimizing payload organization for effective data transfer in broadcasting and network systems. Additional offerings include exemplary channel simulations, such as the Doppler Channel Core, which is essential for accurately predicting signal behavior in dynamic environments. These cores are crafted to provide maximum efficiency and can be seamlessly adapted for specific application requirements, ensuring high performance and resilience across a range of technological landscapes.
The RecAccel AI Platform is an all-encompassing solution engineered to boost computing accuracy in AI applications. This platform integrates advanced algorithms with high-performance AI engines, ensuring precision and efficiency in executing complex tasks. By reducing computational errors and enhancing inference precision, the RecAccel AI Platform becomes essential for businesses requiring reliable AI outcomes. This platform distinguishes itself with its adaptability, supporting a variety of industry-specific AI models, and ensuring that businesses can customize its use to meet their individual needs. From powering large-scale machine learning tasks to facilitating real-time decision-making processes, the RecAccel AI Platform enables seamless transitions across diverse operational environments. Deploying the RecAccel AI Platform guarantees substantial gains in productivity, thanks to its innovative architecture and integration with cutting-edge AI technologies. Companies can rely on its comprehensive framework to maintain operational excellence, delivering on the promise of AI-enhanced decision-making with consistent accuracy.
Application Specific Instruction-set Processors (ASIPs) from Wasiela provide highly specialized, programmable hardware accelerators designed to excel in specific application domains. By offering an instruction set tailored to particular tasks, ASIPs achieve optimal performance and efficiency in processing. These processors are pivotal in demanding fields where low power and high configurability are paramount. They stand as versatile solutions in Wasiela's portfolio, adaptable for a broad range of digital systems needing customized computing power.
The PanAccelerator is Panmnesia's AI accelerator featuring an innovative CXL-enabled design that facilitates rapid scaling of AI services. It offers hardware acceleration through flexible memory resources composability, enabled by CXL technology. The accelerator's design allows for quick adaptation to evolving compute requirements by efficiently disaggregating compute and memory resources. Equipped with a robust compute unit optimized for parallel vector and tensor operations, PanAccelerator ensures the cost-effective deployment of large-scale AI services without sacrificing performance.
DRV32IMZicsr – Scalable RISC-V Power. Tailored for Your Project. Ready for the Future. The DRV32IMZicsr is a high-performance, 32-bit RISC-V processor core, equipped with M (Multiply/Divide), Zicsr (Control and Status Registers), and External Debug support. Built as part of DCD’s latest DRVX Core Family, it delivers the full flexibility, openness, and innovation that RISC-V promises—without locking you into proprietary architectures. ✅ Why RISC-V? RISC-V is a rapidly growing open standard for modern computing—backed by a global ecosystem of developers and vendors. It brings: * Freedom from licensing fees and vendor lock-in * Scalability from embedded to high-performance systems * Customizability with standard and custom instruction sets * Strong toolchain & ecosystem support 🚀 DRV32IMZicsr Highlights: * Five-stage pipeline and Harvard architecture for optimized performance * Configurable memory architecture: size and address allocation tailored to your needs Performance metrics: * **Up to 1.15 DMIPS/MHz** * **Up to 2.36 CoreMark/MHz** * Minimal footprint starting from just 14k gates * Flexible interfaces: Choose from AXI, AHB, or native bus options 🛡️ Designed for Safety & Integration: * Developed as an ISO 26262 Safety Element out of Context (SEooC) * Fully technology-agnostic, compatible with all FPGA and ASIC platforms * Seamless integration with DCD’s rich portfolio of IPs: DMA, SPI, UART, PWM, CAN, and more 🔍 Advanced Feature Set: * 32 general-purpose registers * Support for arithmetic, logic, load/store, conditional and unconditional control flow * M extension enables efficient integer multiplication/division * Zicsr extension provides robust interrupt and exception handling, performance counters, and timers * External Debug via JTAG: compliant with RISC-V Debug Specification 0.13.2 and 1.0.0, compatible with all mainstream tools 🧪 Developer-Ready: * Delivered with a fully automated testbench * Includes a comprehensive validation test suite for smooth integration into your SoC flow Whether you're building for automotive, IoT, consumer electronics, or embedded systems, the DRV32IMZicsr offers a future-ready RISC-V solution—highly configurable, performance-optimized, and backed by DCD’s 25 years of experience. Interested? Let’s build the next generation together. 📩 Contact us at info@dcd.pl
The Complex DSP Engine provided by IPCoreWorx incorporates advanced digital signal processing with a robust architecture designed to optimize performance. It is delivered as a netlist or synthesizable RTL source code in VHDL, complete with a comprehensive verification test bench and vectors also in VHDL. The package includes detailed integration documentation and user guides to ensure that developers can effectively implement the engine into their systems. This DSP Engine is particularly adept at handling complex computational tasks, offering significant enhancements in processing speed and efficiency.
**DRV64IMZicsr – 64-bit RISC-V Performance. Designed for Demanding Innovation.** The DRV64IMZicsr is a powerful and versatile 64-bit RISC-V CPU core, built to meet the performance and safety needs of next-generation embedded systems. Featuring the M (Multiply/Divide), Zicsr (Control and Status Registers), and External Debug extensions, this core is engineered to scale—from edge computing to mission-critical applications. As part of the DRVX Core Family, the DRV64IMZicsr embodies DCD’s philosophy of combining open-standard freedom with customizable IP excellence—making it a smart and future-proof alternative to legacy architectures. ✅ Why Choose RISC-V? * No license fees – open-source instruction set means reduced TCO * Unmatched flexibility – tailor the architecture to your specific needs * A global, thriving ecosystem – support from toolchains, OSes, and hardware vendors * Security & longevity – open and verifiable architecture ensures trust and sustainability 🚀 DRV64IMZicsr – Core Advantages: * 64-bit RISC-V ISA with M, Zicsr, and Debug support * Five-stage pipeline, Harvard architecture, and efficient branch prediction * Configurable memory size and allocation for program and data spaces Performance optimized: * **Up to 2.38 CoreMark/MHz** * **Up to 1.17 DMIPS/MHz** * Compact footprint starting from just 17.6k gates * Interface options: AXI, AHB, or native * Compatible with Classical CAN, CAN FD, and CAN XL through additional IPs 🛡️ Safety, Compatibility & Flexibility Built In: * Developed as an ISO 26262 Safety Element out of Context (SEooC) * Technology-agnostic – works seamlessly across all FPGA and ASIC vendors * Expandable with DCD’s IP portfolio: DMA, SPI, UART, I²C, CAN, PWM, and more 🔍 Robust Feature Set for Real Applications: * Full 64-bit processing – ideal for performance-intensive, memory-heavy tasks * M extension enables high-speed multiplication/division via dedicated hardware unit * Zicsr extension gives full access to Control and Status Registers, enabling: * Interrupts and exception handling (per RISC-V Privileged Spec) * Performance counters and timers * JTAG-compatible debug interface – compliant with RISC-V Debug Spec (0.13.2 & 1.0.0) 🧪 Ready for Development & Integration: * Comes with a fully automated testbench * Includes a comprehensive suite of validation tests for smooth SoC integration * Supported by industry-standard tools, ensuring a hassle-free dev experience Whether you’re designing for automotive safety, industrial control, IoT gateways, or AI-enabled edge devices, the DRV64IMZicsr gives you the performance, flexibility, and future-readiness of RISC-V—without compromise. 💡 Build smarter, safer systems—on your terms. 📩 Contact us today at info@dcd.pl to start your next RISC-V-powered project.
The Low Power Security Engine stands as a testament to highly efficient design, aimed at securing IoT networks within resource-limited environments. At its core, it supports ECDHE and ECDSA protocols, functioning as a robust HW acceleration engine capable of facilitating cryptographic operations such as ECC, SHA, AES, and TRNG.\n\nFocusing on power conservation without compromising security, the engine is structured to resist timing and side-channel attacks, which are crucial for maintaining data integrity in sensitive use cases. It is instrumental within smart sensor networks and secure RFID systems, providing ironclad protection without the usual high power demands associated with comprehensive data security solutions.\n\nThanks to its compact and complete nature, the Security Engine can be embedded effortlessly into larger systems-on-chip, making it a seamless addition to existing IoT architectures. Its AMBA Standard Interface compatibility furthers its integration capabilities across multiple platforms, ensuring versatile deployment options. As IoT devices become more complex, having a security engine that is low-power yet high-performance is indispensable, positioning this IP as a cornerstone of secure IoT ecosystems.
The D68HC11F is a synthesizable SOFT Microcontroller IP Core, fully compatible with the Motorola 68HC11F1 industry standard. It can be used as a direct replacement for the 68HC11F1 Microcontrollers. Major peripheral functions are integrated on-chip, including an asynchronous serial communications interface (SCI) and a synchronous serial peripheral interface (SPI). The main 16-bit, free-running timer system includes input capture and output-compare lines, and a real-time interrupt function. An 8-bit pulse accumulator subsystem counts external events or measures external periods. Self-monitoring on-chip circuitry protects the D68HC11F against system errors. The Computer Operating Properly (COP) watchdog system and illegal opcode detection circuit provide extra security features. Two power-saving modes, WAIT and STOP, make the IP core especially attractive for automotive and battery-driven applications. Additionally, the D68HC11F can be equipped with an ADC Controller, offering compatibility with external ADCs. Its customizable nature means it's delivered in configurations tailored to need, avoiding unnecessary features and silicon waste. The D68HC11F also includes a fully automated test bench and comprehensive tests for easy SoC design validation. It supports DCD’s DoCD™, a real-time hardware debugger, for non-intrusive debugging of complete SoCs. This IP Core is technology agnostic, ensuring 100% compatibility with all FPGA and ASIC vendors.
The D68000-CPU32 soft core is binary-compatible with the industry standard 68000's CPU32 version of the 32-bit microcontroller. The D68000-CPU32 has a 16-bit data bus and a 24-bit address data bus, and it is code compatible with the 68000's CPU32 (version of MC68020). The D68000-CPU32 includes an improved instruction set, allowing for higher performance than the standard 68000 core, and a built-in DoCD-BDM debugger interface. It is delivered with a fully automated test bench and a set of tests enabling easy package validation during different stages of the SoC design flow. The D68000-CPU32 is technology-agnostic, ensuring compatibility with all FPGA and ASIC vendors.
The DP8051 is an ultra-high performance, speed-optimized softcore, of a single-chip 8-bit embedded controller, intended to operate with fast (typically on-chip) and slow (off-chip) memories. The core was designed with a special concern about the performance to power-consumption ratio. This ratio is extended by the PMU – an advanced power management unit. The DP8051 softcore is 100% binary-compatible with the industry standard 8051 8-bit microcontrollers. There are two configurations of the DP8051: Harvard, where internal data and program buses are separated and von Neumann, with a common program and external data bus. The DP8051 has a Pipelined RISC architecture and executes 120-300 million instructions per second. Dhrystone 2.1 benchmark program runs from 11.46 to 15.55 times faster than the original 80C51 at the same frequency. The same C compiler was used for benchmarking of the core vs 80C51, with the same settings. This performance can also be exploited to great advantage in low-power applications, where the core can be clocked over ten times slower than the original implementation, without performance depletion. The DP8051 is delivered with a fully automated test bench and a complete set of tests, allowing easy package validation, at each stage of the SoC design flow. Each of DCD’s 8051 Cores has built-in support for the Hardware Debug System called DoCD™. It is a real-time hardware debugger, which provides debugging capability of the whole System-on-Chip (SoC). Unlike other on-chip debuggers, the DoCD™ provides non-intrusive debugging of a running application. It can halt, run, step into or skip an instruction, and read/write any contents of the microcontroller, including all registers, internal and external program memories, and all SFRs, including user-defined peripherals. ALL DCD’S IP CORES ARE TECHNOLOGY AGNOSTIC, ENSURING 100% COMPATIBILITY WITH ALL FPGA AND ASIC VENDORS.
The RSA Encryption Core by IP Cores, Inc. provides essential cryptographic performance, supporting public-key cryptographic operations critical for secure communications. Utilizing finite field exponentiation logic, this core targets RSA cryptographic necessities where long-life battery operation is prioritized, such as in trusted communication systems and digital rights management applications. With baseline processes integrating RSA computational needs, this core outlines a trusted solution towards designing robust security networks, ensuring mission critical encryption and decryption within modern hardware setups.
This high-performance FPGA and ASIC networking product by CetraC is tailored for distributed architectures embedded in critical systems across various industries. The core innovation relies on a fully hardware-based technology, circumventing traditional computational methods that usually necessitate software intervention. Recognized for its ultra-low latency and determinism, this product features a 10Gb backbone facilitated by finite state machines. Its efficiency is highlighted by low heat dissipation and cyber resilience. Designed from insights gained within the aircraft manufacturing sector, this product boasts unparalleled safety features, facilitating easier certification for airworthiness up to D0254 DAL A levels. Its frugal design leads to significant weight savings and reduces energy consumption, as the hardware executes tasks traditionally managed by computing systems. Additionally, enhanced cybersecurity is inherent, with built-in data segregation, ensuring no remote modifications can be made to the device's behavior. This networking product offers additional capabilities including data encryption using AES-256 GCM or other algorithms, protocol conversion supporting over 15 protocols, and effective data aggregation to optimize decision-making processes. Such attributes render it invaluable for industries needing reliable and secure data handling, such as automotive and naval sectors. Its hardware-centric design ensures that it remains impervious to hacking, immune to viruses or malicious software, providing a robust solution for critical system networking needs.
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