All IPs > Processor > Coprocessor
In the realm of modern computing, coprocessor semiconductor IPs play a crucial role in augmenting system capabilities. A coprocessor is a supplementary processor that executes specific tasks more efficiently than the primary central processing unit (CPU). These coprocessors are specialized semiconductor IPs utilized in devices requiring enhanced computational power for particular functions such as graphics rendering, encryption, mathematical calculations, and artificial intelligence (AI) processing.
Coprocessors are integral in sectors where high performance and efficiency are paramount. For instance, in the gaming industry, a graphics processing unit (GPU) acts as a coprocessor to handle the high demand for rendering visuals, thus alleviating the burden from the CPU. Similarly, AI accelerators in smartphones and servers offload intensive AI computation tasks to speed up processing while conserving power.
You will find various coprocessor semiconductor IP products geared toward enhancing computational specialization. These include digital signal processors (DSPs) for processing real-time audio and video signals and hardware encryption coprocessors for securing data transactions. With the rise in machine learning applications, tensor processing units (TPUs) have become invaluable, offering massively parallel computing to efficiently manage AI workloads.
By incorporating these coprocessor semiconductor IPs into a system design, manufacturers can achieve remarkable improvements in speed, power efficiency, and processing power. This enables the development of cutting-edge technology products across a range of fields from personal electronics to autonomous vehicles, ensuring optimal performance in specialized computing tasks.
The Akida IP is an advanced processor core designed to mimic the efficient processing characteristics of the human brain. Inspired by neuromorphic engineering principles, it delivers real-time AI performance while maintaining a low power profile. The architecture of the Akida IP is sophisticated, allowing seamless integration into existing systems without the need for continuous external computation. Equipped with capabilities for processing vision, audio, and sensor data, the Akida IP stands out by being able to handle complex AI tasks directly on the device. This is done by utilizing a flexible mesh of nodes that efficiently distribute cognitive computing tasks, enabling a scalable approach to machine learning applications. Each node supports hundreds of MAC operations and can be configured to adapt to various computational requirements, making it a versatile choice for AI-centric endeavors. Moreover, the Akida IP is particularly beneficial for edge applications where low latency, high efficiency, and security are paramount. With capabilities for event-based processing and on-chip learning, it enhances response times and reduces data transfer needs, thereby bolstering device autonomy. This solidifies its position as a leading solution for embedding AI into devices across multiple industries.
Chimera GPNPU is engineered to revolutionize AI/ML computational capabilities on single-core architectures. It efficiently handles matrix, vector, and scalar code, unifying AI inference and traditional C++ processing under one roof. By alleviating the need for partitioning AI workloads between different processors, it streamlines software development and drastically speeds up AI model adaptation and integration. Ideal for SoC designs, the Chimera GPNPU champions an architecture that is both versatile and powerful, handling complex parallel workloads with a single unified binary. This configuration not only boosts software developer productivity but also ensures an enduring flexibility capable of accommodating novel AI model architectures on the horizon. The architectural fabric of the Chimera GPNPU seamlessly blends the high matrix performance of NPUs with C++ programmability found in traditional processors. This core is delivered in a synthesizable RTL form, with scalability options ranging from a single-core to multi-cluster designs to meet various performance benchmarks. As a testament to its adaptability, the Chimera GPNPU can run any AI/ML graph from numerous high-demand application areas such as automotive, mobile, and home digital appliances. Developers seeking optimization in inference performance will find the Chimera GPNPU a pivotal tool in maintaining cutting-edge product offerings. With its focus on simplifying hardware design, optimizing power consumption, and enhancing programmer ease, this processor ensures a sustainable and efficient path for future AI/ML developments.
xcore.ai is XMOS Semiconductor's innovative programmable chip designed for advanced AI, DSP, and I/O applications. It enables developers to create highly efficient systems without the complexity typical of multi-chip solutions, offering capabilities that integrate AI inference, DSP tasks, and I/O control seamlessly. The chip architecture boasts parallel processing and ultra-low latency, making it ideal for demanding tasks in robotics, automotive systems, and smart consumer devices. It provides the toolset to deploy complex algorithms efficiently while maintaining robust real-time performance. With xcore.ai, system designers can leverage a flexible platform that supports the rapid prototyping and development of intelligent applications. Its performance allows for seamless execution of tasks such as voice recognition and processing, industrial automation, and sensor data integration. The adaptable nature of xcore.ai makes it a versatile solution for managing various inputs and outputs simultaneously, while maintaining high levels of precision and reliability. In automotive and industrial applications, xcore.ai supports real-time control and monitoring tasks, contributing to smarter, safer systems. For consumer electronics, it enhances user experience by enabling responsive voice interfaces and high-definition audio processing. The chip's architecture reduces the need for exterior components, thus simplifying design and reducing overall costs, paving the way for innovative solutions where technology meets efficiency and scalability.
RaiderChip's GenAI v1 is a pioneering hardware-based generative AI accelerator, designed to perform local inference at the Edge. This technology integrates optimally with on-premises servers and embedded devices, offering substantial benefits in privacy, performance, and energy efficiency over traditional hybrid AI solutions. The design of the GenAI v1 NPU streamlines the process of executing large language models by embedding them directly onto the hardware, eliminating the need for external components like CPUs or internet connections. With its ability to support complex models such as the Llama 3.2 with 4-bit quantization on LPDDR4 memory, the GenAI v1 achieves unprecedented efficiency in AI token processing, coupled with energy savings and reduced latency. What sets GenAI v1 apart is its scalability and cost-effectiveness, significantly outperforming competitive solutions such as Intel Gaudi 2, Nvidia's cloud GPUs, and Google's cloud TPUs in terms of memory efficiency. This solution maximizes the number of tokens generated per unit of memory bandwidth, thus addressing one of the primary limitations in generative AI workflow. Furthermore, the adept memory usage of GenAI v1 reduces the dependency on costly memory types like HBM, opening the door to more affordable alternatives without diminishing processing capabilities. With a target-agnostic approach, RaiderChip ensures the GenAI v1 can be adapted to various FPGAs and ASICs, offering configuration flexibility that allows users to balance performance with hardware costs. Its compatibility with a wide range of transformers-based models, including proprietary modifications, ensures GenAI v1's robust placement across sectors requiring high-speed processing, like finance, medical diagnostics, and autonomous systems. RaiderChip's innovation with GenAI v1 focuses on supporting both vanilla and quantized AI models, ensuring high computation speeds necessary for real-time applications without compromising accuracy. This capability underpins their strategic vision of enabling versatile and sustainable AI solutions across industries. By prioritizing integration ease and operational independence, RaiderChip provides a tangible edge in applying generative AI effectively and widely.
The GenAI v1-Q from RaiderChip brings forth a specialized focus on quantized AI operations, reducing memory requirements significantly while maintaining impressive precision and speed. This innovative accelerator is engineered to execute large language models in real-time, utilizing advanced quantization techniques such as Q4_K and Q5_K, thereby enhancing AI inference efficiency especially in memory-constrained environments. By offering a 276% boost in processing speed alongside a 75% reduction in memory footprint, GenAI v1-Q empowers developers to integrate advanced AI capabilities into smaller, less powerful devices without sacrificing operational quality. This makes it particularly advantageous for applications demanding swift response times and low latency, including real-time translation, autonomous navigation, and responsive customer interactions. The GenAI v1-Q diverges from conventional AI solutions by functioning independently, free from external network or cloud auxiliaries. Its design harmonizes superior computational performance with scalability, allowing seamless adaptation across variegated hardware platforms including FPGAs and ASIC implementations. This flexibility is crucial for tailoring performance parameters like model scale, inference velocity, and power consumption to meet exacting user specifications effectively. RaiderChip's GenAI v1-Q addresses crucial AI industry needs with its ability to manage multiple transformer-based models and confidential data securely on-premises. This opens doors for its application in sensitive areas such as defense, healthcare, and financial services, where confidentiality and rapid processing are paramount. With GenAI v1-Q, RaiderChip underscores its commitment to advancing AI solutions that are both environmentally sustainable and economically viable.
The Maverick-2 Intelligent Compute Accelerator represents the pinnacle of Next Silicon's innovative approach to computational resources. This state-of-the-art accelerator leverages the Intelligent Compute Architecture for software-defined adaptability, enabling it to autonomously tailor its real-time operations across various HPC and AI workloads. By optimizing performance using insights gained through real-time telemetry, Maverick-2 ensures superior computational efficiency and reduced power consumption, making it an ideal choice for demanding computational environments.\n\nMaverick-2 brings transformative performance enhancements to large-scale scientific research and data-heavy industries by dispensing with the need for codebase modifications or specialized software stacks. It supports a wide range of familiar development tools and frameworks, such as C/C++, FORTRAN, and Kokkos, simplifying the integration process for developers and reducing time-to-discovery significantly.\n\nEngineered with advanced features like high bandwidth memory (HBM3E) and built on TSMC's 5nm process technology, this accelerator provides not only unmatched adaptability but also an energy-efficient, eco-friendly computing solution. Whether embedded in single-die PCIe cards or dual-die OCP Accelerator Modules, the Maverick-2 is positioned as a future-proof solution capable of evolving with technological advancements in AI and HPC.
KPIT Technologies provides comprehensive vehicle engineering and design solutions that blend aesthetic appeal with functional efficiency. These solutions are designed to assist automakers throughout the vehicle development process, from initial concept to finished product, ensuring designs are both innovative and practical. Focusing on high precision and quality, KPIT’s engineering solutions encompass a wide range of services such as design validation, prototyping, and simulation-driven design optimizations. They utilize advanced simulation tools to refine vehicle dynamics, structural integrity, and ergonomic designs, ensuring a balance between cost-effectiveness and cutting-edge innovation. KPIT’s design approach emphasizes sustainable and intelligent engineering, enabling automakers to create vehicles that not only look good but also perform exceptionally well under various conditions. By offering tailored design and engineering solutions, KPIT enhances the ability of automotive companies to bring state-of-the-art vehicles to market swiftly and efficiently.
Altek's 3D Imaging Chip is a breakthrough in the field of vision technology. Designed with an emphasis on depth perception, it enhances the accuracy of 3D scene capturing, making it ideal for applications requiring precise distance gauging such as autonomous vehicles and drones. The chip integrates seamlessly within complex systems, boasting superior recognition accuracy that ensures reliable and robust performance. Building upon years of expertise in 3D imaging, this chip supports multiple 3D modes, offering flexible solutions for devices from surveillance robots to delivery mechanisms. It facilitates medium-to-long-range detection needs thanks to its refined depth sensing capabilities. Altek's approach ensures a comprehensive package from modular design to chip production, creating a cohesive system that marries both hardware and software effectively. Deployed within various market segments, it delivers adaptable image solutions with dynamic design agility. Its imaging prowess is further enhanced by state-of-the-art algorithms that refine image quality and facilitate facial detection and recognition, thereby expanding its utility across diverse domains.
The Spiking Neural Processor T1 is an ultra-low power processor developed specifically for enhancing sensor capabilities at the edge. By leveraging advanced Spiking Neural Networks (SNNs), the T1 efficiently deciphers patterns in sensor data with minimal latency and power usage. This processor is especially beneficial in real-time applications, such as audio recognition, where it can discern speech from audio inputs with sub-millisecond latency and within a strict power budget, typically under 1mW. Its mixed-signal neuromorphic architecture ensures that pattern recognition functions can be continually executed without draining resources. In terms of processing capabilities, the T1 resembles a dedicated engine for sensor tasks, offering functionalities like signal conditioning, filtering, and classification independent of the main application processor. This means tasks traditionally handled by general-purpose processors can now be offloaded to the T1, conserving energy and enhancing performance in always-on scenarios. Such functionality is crucial for pervasive sensing tasks across a range of industries. With an architecture that balances power and performance impeccably, the T1 is prepared for diverse applications spanning from audio interfaces to the rapid deployment of radar-based touch-free interactions. Moreover, it supports presence detection systems, activity recognition in wearables, and on-device ECG processing, showcasing its versatility across various technological landscapes.
Targeted at high-end applications, the SCR9 processor core boasts a 12-stage dual-issue out-of-order pipeline, adding vector processing units (VPUs) to manage intensive computational tasks. It offers hypervisor support, making it suitable for diverse enterprise-grade applications. Configured for up to 16 cores, it exhibits excellent memory management and cache coherency required for state-of-the-art computing platforms such as HPC, AI, and machine learning environments. This core embodies efficiency and performance, catering to industries that leverage high-throughput data processing.
The RISCV SoC - Quad Core Server Class is engineered for high-performance applications requiring robust processing capabilities. Designed around the RISC-V architecture, this SoC integrates four cores to offer substantial computing power. It's ideal for server-class operations, providing both performance efficiency and scalability. The RISCV architecture allows for open-source compatibility and flexible customization, making it an excellent choice for users who demand both power and adaptability. This SoC is engineered to handle demanding workloads efficiently, making it suitable for various server applications.
The 2D FFT IP extends the power of the traditional FFT by enabling two-dimensional transforms, essential for image and signal processing where data is structured in matrices. With an impressive balance of speed and resource utilization, the 2D FFT handles massive data efficiently using internal or external memory interfaces to fit broad application demands. Its adaptability for FPGA and ASIC applications makes it an ideal candidate for high-performance computing tasks needing complex data manipulation.
The iCan PicoPop® is a highly compact System on Module (SOM) based on the Zynq UltraScale+ MPSoC from Xilinx, suited for high-performance embedded applications in aerospace. Known for its advanced signal processing capabilities, it is particularly effective in video processing contexts, offering efficient data handling and throughput. Its compact size and performance make it ideal for integration into sophisticated systems where space and performance are critical.
Trilinear Technologies has developed a cutting-edge DisplayPort Receiver that enhances digital connectivity, offering robust video reception capabilities necessary for today's high-definition video systems. Compliant with VESA standards, the receiver supports the latest DisplayPort specifications, effortlessly handling high-bandwidth video data necessary for applications such as ultra-high-definition televisions, professional video wall setups, and complex automotive display systems. The DisplayPort Receiver is designed with advanced features that facilitate seamless video data acquisition and processing, including multi-stream transport capabilities for handling multiple video streams concurrently. This is particularly useful in professional display settings where multiple input sources are needed. The core also incorporates adaptive sync features, which help reduce screen tearing and ensure smooth video playback, enhancing user experience significantly. An important facet of the DisplayPort Receiver is its low latency and high-efficiency operations, crucial for systems requiring real-time data processing. Trilinear's receiver core ensures that video data is processed with minimal delay, maintaining the integrity and fidelity of the original visual content. This makes it a preferred choice for high-performance applications in sectors like gaming, broadcasting, and high-definition video conferencing. To facilitate integration and ease of use, the DisplayPort Receiver is supported by a comprehensive suite of development tools and software packages. This makes the deployment process straightforward, allowing developers to integrate the receiver into both FPGA and ASIC environments with minimal adjustments. Its scalability and flexibility mean it can meet the demands of a wide range of applications, solidifying Trilinear Technologies' position as a leader in the field of semiconductor IP solutions.
The DisplayPort Transmitter from Trilinear Technologies is a sophisticated solution designed for high-performance digital video streaming applications. It is compliant with the latest VESA DisplayPort standards, ensuring compatibility and seamless integration with a wide range of display devices. This transmitter core supports high-resolution video outputs and is equipped with advanced features like adaptive sync and panel refresh options, making it ideal for consumer electronics, automotive displays, and professional AV systems. This IP core provides reliable performance with minimal power consumption, addressing the needs of modern digital ecosystems where energy efficiency is paramount. It includes customizable settings for audio and video synchronization, ensuring optimal output quality and user experience across different devices and configurations. By reducing load on the system processor, the DisplayPort Transmitter guarantees a seamless streaming experience even in high-demand environments. In terms of integration, Trilinear's DisplayPort Transmitter is supported with comprehensive software stacks allowing for easy customization and deployment. This ensures rapid product development cycles and aids developers in managing complex video data streams effectively. The transmitter is particularly optimized for use in embedded systems and consumer devices, offering robust performance capabilities that stand up to rigorous real-time application demands. With a focus on compliance and testing, the DisplayPort Transmitter is pre-tested and proven to work seamlessly with a variety of hardware platforms including FPGA and ASIC technologies. This robustness in design and functionality underlines Trilinear's reputation for delivering reliable, high-quality semiconductor IP solutions that cater to diverse industrial applications.
The Veyron V1 is a high-performance RISC-V CPU designed to meet the rigorous demands of modern data centers and compute-intensive applications. This processor is tailored for cloud environments requiring extensive compute capabilities, offering substantial power efficiency while optimizing processing workloads. It provides comprehensive architectural support for virtualization and efficient task management with its robust feature set. Incorporating advanced RISC-V standards, the Veyron V1 ensures compatibility and scalability across a wide range of industries, from enterprise servers to high-performance embedded systems. Its architecture is engineered to offer seamless integration, providing an excellent foundation for robust, scalable computing designs. Equipped with state-of-the-art processing cores and enhanced vector acceleration, the Veyron V1 delivers unmatched throughput and performance management, making it suitable for use in diverse computing environments.
The RFicient chip is a cutting-edge technology designed to optimize power usage in IoT applications. This ultra-low-power receiver is ideal for environments requiring long-term battery operation, such as remote sensors in industrial IoT setups. With its efficient energy harvesting capabilities, the RFicient chip is pivotal in advancing sustainable technology solutions, reducing power consumption within the Internet of Things (IoT) framework.
The Origin E1 is a compact yet powerful neural processing unit (NPU) designed for low-power applications in home appliances, smartphones, and security cameras. Specially tailored for always-on functions, the E1 offers unmatched power efficiency by utilizing Expedera's innovative packet-based architecture. This allows it to execute multiple layers in parallel, ensuring the optimal balance of performance and resource utilization. Engineered to operate with minimal to no external memory, the Origin E1 is ideal for cost-effective and area-sensitive designs. The LittleNPU processor within it is fine-tuned for sophisticated neural networks needed in always-sensing applications, maintaining privacy by keeping data on-board. This makes the E1 a robust choice for devices requiring dedicated AI processing without the penalty of high power consumption or large silicon area. In terms of technical specifications, the Origin E1 boasts a performance efficiency of up to 18 TOPS per Watt, with the capability to run various network types such as CNNs, RNNs, and DNNs. Its adaptability allows clients to customize features to meet specific needs, guaranteeing efficient deployments across numerous devices. The E1 leverages a full TVM-based software stack for seamless integration, further endorsing its versatility and effectiveness.
The Neural Network Accelerator from Gyrus AI is designed to enhance edge computing capabilities through native graph processing. This innovative solution offers up to 30 TOPs/W, making it highly efficient by achieving 10-30 times lower clock-cycles than conventional processors. Its design supports low memory usage configurations, significantly reducing power consumption and enabling up to 20 times lower energy requirements. Designed for seamless integration, it supports diverse neural network models with superior utilization of over 80%, leading to enhanced performance and reduced die area by 10 to 8 times smaller than traditional designs.
DolphinWare IPs is a versatile portfolio of intellectual property solutions that enable efficient SoC design. This collection includes various control logic components such as FIFO, arbiter, and arithmetic components like math operators and converters. In addition, the logic components span counters, registers, and multiplexers, providing essential functionalities for diverse industrial applications. The IPs in this lineup are meticulously designed to ensure data integrity, supported by robust verification IPs for AXI4, APB, SD4.0, and more. This comprehensive suite meets the stringent demands of modern electronic designs, facilitating seamless integration into existing design paradigms. Beyond their broad functionality, DolphinWare’s offerings are fundamental to applications requiring specific control logic and data integrity solutions, making them indispensable for enterprises looking to modernize or expand their product offerings while ensuring compliance with industry standards.
The TSP1 Neural Network Accelerator by Applied Brain Research is a groundbreaking AI chip engineered to enhance processing power and efficiency for time series data. Utilizing state-of-the-art neural network capabilities, it facilitates natural voice interfaces and advanced bio-signal classification within compact battery-powered devices. The TSP1 ensures fully self-contained processing across multiple network setups, handling diverse voice and sensor signal applications with low power consumption. This chip is revolutionary in its ability to perform high-efficiency neural network operations while sustaining ultra-low energy usage. The integrated DC-DC supply supports a range of power options, ensuring adaptability across various applications like wearables and smart home technologies. Moreover, its architecture offers robust AI inference with minimal latency, making it a prime choice for those aiming to incorporate efficient AI processing into edge devices. Technically, the TSP1 supports up to four stereo audio inputs and features secure on-chip storage, empowering devices to execute complex AI functions with great fidelity. Its compact packaging options make it suitable for a host of applications, ensuring seamless integration in environments where space and power efficiency are critical. This AI chip stands out in the market for its ability to offer comprehensive AI capabilities while remaining highly efficient and low-cost, promising transformative impacts across multiple sectors.
The TimbreAI T3 is meticulously designed to cater to ultra-low-power AI applications, notably in audio devices like headsets. Providing optimal noise reduction capabilities, the T3 performs efficient AI inference while utilizing minimal power, making it ideal for power-constrained environments. This AI engine achieves superior audio processing through 3.2 billion operations per second, while consuming less than 300 microWatts of power. The TimbreAI T3 supports full deployment across leading silicon processes, delivering seamless integration as soft IP to enhance audio experiences without extensive power requirements. With its focus on minimal footprint and maximized efficiency, the TimbreAI T3 allows developers to deploy neural networks without altering trained models, ensuring high accuracy and performance in tiny devices. Its flexibility and proven field deployment further solidify its credentials as a leading solution for the mobile audio market.
Engineered to excel in large language model (LLM) applications, the Viper Series Gen AI PCIe Card integrates cutting-edge AI hardware design with an intuitive deployment model. This card is explicitly developed to tackle the enormous computational demands posed by LLM workloads, efficiently offloading these to its optimized hardware framework. The Viper Series emphasizes robust performance while integrating with existing systems to deliver seamless AI solution flexibility. It features reliable operability across various environments by optimizing resource management to ensure high availability and performance. As AI models continue to expand in complexity and volume, the Viper Series offers a scalable platform that addresses the ever-growing needs of AI developers and enterprises. Whether it's for enterprise-level deployments or research applications, the Viper Series PCIe Card stands as a testament to Neuchips' innovative spirit in the AI hardware domain. It not only enables high-accuracy inferencing but also ensures process efficiency, making it ideal for businesses aiming to integrate scalable AI solutions.
The Pipelined FFT IP stands out with its continuous-stream processing capacity, suitable for applications needing uninterrupted data flow and low memory use. By using a single butterfly per rank architecture, it balances between speed and resource efficiency. This design makes it highly appropriate for applications with steady incoming data streams that require real-time processing, ensuring consistent output without the need for extensive buffers or memory.
The Avispado core by Semidynamics is a highly efficient, in-order RISC-V processor optimized for energy-conscious applications, such as AI edge computing and IoT devices. Its 64-bit architecture supports in-order execution and is particularly notable for its energy efficiency, making it suitable for power-sensitive environments. Avispado is designed to manage two instruction widths, which enhances its flexibility and scalability for embedded systems and AI workload implementations. Avispado features the integration of Semidynamics’ Gazzillion Misses™ technology, ensuring high-bandwidth access by efficiently managing up to 64 simultaneous memory requests. This high data throughput capability makes it ideal for edge AI applications where rapid data processing is essential. Additionally, Avispado is vector-ready, supporting RISC-V’s Vector Specification 1.0, which facilitates AI acceleration in applications such as machine learning and embedded computing. This core is also built to support multiprocessing, allowing scalability to multicore implementations. With compatibility for Linux environments, Avispado expands its usability scope into more traditional computing environments that leverage open-source platforms for development and deployment. Its branch predictor and various customizable options make it a versatile choice for integrators seeking a robust solution within a highly adaptable processor design.
Atrevido is a powerful out-of-order RISC-V core from Semidynamics, designed to support high-performance processing requirements in AI and HPC domains. This 64-bit processor features an advanced out-of-order execution system that is configurable for 2, 3, or 4-wide instruction handling, ensuring peak computing efficiency. Its architecture incorporates both vector and tensor processing capabilities, providing zero-latency integration which is critical for AI inferencing and high-speed data processing. One of Atrevido's standout features is the integration of Semidynamics’ proprietary Gazzillion Misses™ technology, which enhances data throughput by overcoming memory bottlenecks, allowing up to 128 concurrent memory requests. This makes the processor ideally suited for demanding tasks such as machine learning inferencing, sparse data management, and complex analytics. Atrevido’s multiprocessor readiness, with support for both AXI and CHI interfaces, further enhances its adaptability to high-bandwidth infrastructure requirements. The processor supports a wide range of extensions, making it adaptable to various use-cases including bit manipulation and cryptographic operations. This makes Atrevido particularly attractive for users needing a robust and configurable core that can be tailored to meet specific performance and energy efficiency needs. Its architectural flexibility and high processing power make Atrevido a quintessential element for building next-gen AI-driven solutions.
Targeting high-performance demands, the Origin E8 is built for sectors requiring robust AI capabilities, such as data centers and autonomous driving. It accommodates demanding applications for real-time processing tasks, offering up to 128 TOPS in a single core configuration. The E8 expedites complex AI workloads with its advanced packet-based architecture that enhances efficiency through concurrent multi-layer execution. The scalable design of the Origin E8 enables its use in diverse contexts, managing multiple AI networks simultaneously with minimal latency. Expedera's solution addresses the architectural needs of sectors where performance, area, and power efficiency are paramount, providing competitive advantages through optimal configuration. Including a comprehensive suite of development tools like a compiler, scheduler, and quantizer, the Origin E8 facilitates straightforward integration and adaptation to various AI models, thereby ensuring it can meet a broad range of application scenarios.
The MERA Compiler and Software Framework by EdgeCortix is designed to streamline AI model deployment across various platforms, simplifying the transition of pre-trained models to functional applications. By offering a robust set of tools for model calibration and quantization, MERA ensures that models run optimally on the Dynamic Neural Accelerator (DNA) architecture. MERA's integration capabilities extend across leading processors such as AMD, Intel, Arm, and RISC-V, providing flexibility and ease of use. It supports a range of machine learning frameworks like TensorFlow Lite and ONNX, making it easier for developers to adapt to this platform. The framework is especially suited for edge AI tasks where quick adaptation and efficiency are necessary. Apart from model portability, MERA stands out with its ease of integration, supporting popular neural network models, including those from Hugging Face. Its open-source front end ensures community involvement and adaptability, encouraging industry-wide collaboration and innovation in AI deployment strategies.
The UltraLong FFT IP is designed for applications requiring extended FFT calculation lengths and re-targets towards both FPGA and ASIC platforms. With a focus on high performance, this IP core provides medium throughput and medium logic resource requirements, using external memory to expand data handling capacity. Ideal for applications involving large data sets, the UltraLong FFT IP core boasts robust capabilities, effectively managing bandwidth-intensive tasks.
The Raptor N3000 AI Accelerator is a pioneering solution devised for enhancing AI capability via specialized inferencing technology. Crafted to address the growing demands of intensive AI applications, this accelerator offers unparalleled processing power and efficiency, crucial for managing large AI models such as those seen in LLMs. By shouldering the computational load, the Raptor N3000 allows other system components to operate unhindered, significantly enhancing overall performance. With its meticulously engineered architecture, the Raptor N3000 delivers robust processing speeds and power efficiency, which are essential for deploying AI at scale. Whether used in enterprise or sophisticated research settings, this accelerator offers flexibility and adaptability, streamlining the process for developers. The Raptor N3000 embodies Neuchips' commitment to cutting-edge design and sustainability. Through its energy-efficient model, this accelerator not only supports advanced AI applications but also promotes eco-conscious tech solutions, aligning with global needs for green technology advancements.
The Origin E2 NPU is engineered for power-sensitive devices requiring on-device AI processing. Suitable for smartphones and edge nodes, it supports various AI models and balances performance with low power consumption. By utilizing Expedera's packet-based architecture, the E2 achieves high efficiency and effective resource utilization, facilitating parallel execution across multiple layers to enhance computational throughput. The E2 is highly adaptable, supporting a broad performance range from 1 to 20 TOPS, making it well-suited for running neural networks like RNN, LSTM, CNN, and DNN without the need for hardware-specific modifications. This ensures seamless integration for customers looking to leverage their existing trained models. Equipped with a full TVM-based software stack, the Origin E2 simplifies network deployment while offering excellent customization capabilities to meet specific application requirements. Its design emphasizes field-proven reliability with its inclusion in over 10 million consumer devices globally.
Specialty Microcontrollers from Advanced Silicon are architected on the contemporary RISC-V platforms, integrating sophisticated coprocessing units for advanced image processing tasks. These microcontrollers are crucial for applications demanding high-performance algorithm execution, notably in touch screen and interactive display technologies. Leveraging the CoolTouch® technology, the microcontrollers provide enhanced touch interface solutions with built-in machine learning for gesture recognition and command interaction. The systems are developed to excel in varied environments, maintaining reliability under challenging conditions such as EMI interference or with tactile accessories like gloves.
Designed for edge inference applications, the Origin E6 NPU offers a state-of-the-art solution supporting both traditional and generative AI models. With performance scaling from 16 to 32 TOPS, the E6 is tailored to meet the sophisticated demands of next-gen smartphones, AR/VR devices, and automotive applications. Expedera's packet-based architecture facilitates parallel operations, ensuring efficient resource use and reducing latency. The E6 is highly customizable, supporting a wide range of AI models and enabling seamless deployments across diverse hardware environments without the need for extensive hardware-specific tuning. Expedera offers the Origin E6 with a complete software stack that promotes ease of integration and supports advanced features like multiple job APIs and quantization options. By achieving up to 90% processor utilization, the E6 maximizes performance while minimizing dark silicon waste, positioning it as a leading choice for AI chip architects seeking power efficiency and scalability in their designs.
The Mixed Radix FFT core is engineered to handle various non-radix-2 FFT lengths using combinations of radix-2, 3, 5, and 7. This flexibility allows the core to optimize performance for a breadth of applications, accommodating diverse computational requirements. Featuring medium throughput and logic usage, the core efficiently manages resources while delivering tailored FFT solutions for non-standard computational loads. Designed for both FPGA and ASIC platforms, it delivers robust performance in heterogeneous computing environments.
iCEVision provides an adaptable platform for evaluating connectivity features within the iCE40 UltraPlus FPGA. By enabling rapid prototyping, iCEVision allows users to quickly develop, test, and confirm the design of user-defined functions, thereby reducing development time. The platform includes compatibility with prevalent camera interfaces such as ArduCam CSI and PMOD, ensuring ease of connection and expandability. With onboard features like programmable SPI Flash, SRAM, and multiple connectivity options, iCEVision is optimized for effortless connectivity and simple programming. The platform includes intuitive software tools like the Lattice Diamond Programmer and iCEcube2 for writing and refining custom code, simplifying the user experience and facilitating seamless integration. Ideal for applications requiring high flexibility and rapid deployment, iCEVision's robust processing capabilities are complemented by a compact 50mm x 50mm size, making it a versatile choice for various development needs. Pre-loaded applications and a user-friendly programming interface further contribute to its desirability as a core development kit for embedded system design.
Parallel FFT IP offers a streamlined approach to executing FFT operations, employing multiple parallel processing streams to significantly enhance throughput. Featuring a low logic and memory footprint, this IP core is tailored for deployment on high-performance FPGA systems. By utilizing a series of highly efficient parallel algorithms, it dramatically accelerates FFT processing in both small and large configurations, supporting real-time signal analysis and complex data computations efficiently.
The RV32EC_P2 processor core by IQonIC Works is a compact RISC-V processor designed for low-power embedded applications. It features a two-stage pipeline architecture ideal for running trusted firmware and offers a base RV32E instruction set. To enhance efficiency, the core supports RVC compressed instructions for reduced code sizes and optionally includes integer multiplication and division functionalities through the 'M' standard extension. Additionally, it accommodates custom instruction set extensions for tasks such as DSP operations, making it versatile for numerous applications. Designed for ASIC and FPGA implementations, the core provides interfaces like AHB-Lite or APB for memory and I/O operations, ensuring comprehensive system integration. Key features include a simple privileged architecture for machine-mode operations and clock gating for reduced power consumption during idle states. Furthermore, the core supports vectorized interrupts, enabling fast responses to system signals. The RV32EC_P2 is backed by a full suite of development and simulation tools, including synthesis scripts and firmware development environments based on the GNU tool chain. The Virtual Lab (VLAB) system-level tools offer enhanced support for developing and testing applications in a virtual context, ensuring a seamless development experience from conception to deployment.
The Low Power Security Engine is a compact yet complete solution designed to safeguard resource-constrained embedded devices by providing low-power, high-efficiency security services. It supports ECDHE (Elliptic-curve Diffie-Hellman) and ECDSA (Elliptic Curve Digital Signature Algorithm), enabling robust cryptographic operations and secure data handling. This security engine is engineered to resist timing and side channel attacks, which are critical for maintaining data integrity and confidentiality. Optimized for power and area, it suits embedded systems requiring enhanced security features without compromising on resource usage. Applications extend from smart sensors and embedded SIMs to secure RFID systems, underscoring its versatility in IoT applications. Its AMBA standard interface ensures smooth integration into various platforms, making it a reliable addition to secure IoT deployments.
The Load Unload FFT IP focuses on efficient data handling during Fast Fourier Transform operations. This IP core is adept at balancing high-speed data processing with minimal logic usage, ensuring swift and reliable data transfers during FFT calculations. It is optimized for FPGA and ASIC targets, making it a versatile choice for demanding signal processing applications that require a seamless flow of data.
IQonIC Works' RV32IC_P5 processor core is a high-performance RISC-V solution designed for medium-scale embedded systems requiring advanced processing capabilities and efficient multitasking. Its five-stage pipeline architecture supports complex operations with high-speed processing, catering to applications involving both trusted firmware and user code execution. The core is capable of handling a variety of tasks efficiently due to features like cache memories and privileged machine- and user-modes. This core offers a comprehensive RISC-V RV32I base instruction set and includes optional standard extensions for integer operations (M), user-mode execution (N), and critical section handling (A). It's designed to optimize branch prediction and interrupt response times with configurable buffers and vectorized handling capabilities, which are critical for high-performance applications. Supporting both ASIC and FPGA design flows, the RV32IC_P5 core integrates tightly with memory and I/O interfaces, using AHB-Lite buses for extensive connectivity. The accompanying development environment includes the GNU tool chain and ASTC's VLAB for prototyping and firmware testing, ensuring developers have robust tools for seamless application development and deployment.
CetraC.io's High-Performance FPGA & ASIC Networking Product is designed to offer unparalleled performance in distributed network architectures. Built on the foundation of hardware acceleration, it simplifies network design by embedding complex networking functionalities directly into ASICs and FPGAs. These products are optimized for high-bandwidth operations and ensure consistent network reliability. Utilizing advanced finite state machine technology, CetraC.io provides a solution that dramatically enhances data throughput and minimizes latency in data transmissions. With an ability to handle multiple data streams concurrently, networks using these products can efficiently process and manage large volumes of data, crucial for real-time operations in sectors like aerospace and defense. This networking product supports a broad array of protocols, ensuring seamless integration within existing systems while maintaining security and data integrity. Designed with high efficiency in mind, it reduces the overhead typically associated with software-based networking solutions, leading to improvements in energy consumption and overall system performance. CetraC.io's networking product is ideal for applications requiring robust data processing, such as those found in mission-critical environments. Its inherent support for future-ready networking standards positions it well within industries demanding cutting-edge technology with scalable features for expanding network demands.
**DRV64IMZicsr – 64-bit RISC-V Performance. Designed for Demanding Innovation.** The DRV64IMZicsr is a powerful and versatile 64-bit RISC-V CPU core, built to meet the performance and safety needs of next-generation embedded systems. Featuring the M (Multiply/Divide), Zicsr (Control and Status Registers), and External Debug extensions, this core is engineered to scale—from edge computing to mission-critical applications. As part of the DRVX Core Family, the DRV64IMZicsr embodies DCD’s philosophy of combining open-standard freedom with customizable IP excellence—making it a smart and future-proof alternative to legacy architectures. ✅ Why Choose RISC-V? * No license fees – open-source instruction set means reduced TCO * Unmatched flexibility – tailor the architecture to your specific needs * A global, thriving ecosystem – support from toolchains, OSes, and hardware vendors * Security & longevity – open and verifiable architecture ensures trust and sustainability 🚀 DRV64IMZicsr – Core Advantages: * 64-bit RISC-V ISA with M, Zicsr, and Debug support * Five-stage pipeline, Harvard architecture, and efficient branch prediction * Configurable memory size and allocation for program and data spaces Performance optimized: * **Up to 2.38 CoreMark/MHz** * **Up to 1.17 DMIPS/MHz** * Compact footprint starting from just 17.6k gates * Interface options: AXI, AHB, or native * Compatible with Classical CAN, CAN FD, and CAN XL through additional IPs 🛡️ Safety, Compatibility & Flexibility Built In: * Developed as an ISO 26262 Safety Element out of Context (SEooC) * Technology-agnostic – works seamlessly across all FPGA and ASIC vendors * Expandable with DCD’s IP portfolio: DMA, SPI, UART, I²C, CAN, PWM, and more 🔍 Robust Feature Set for Real Applications: * Full 64-bit processing – ideal for performance-intensive, memory-heavy tasks * M extension enables high-speed multiplication/division via dedicated hardware unit * Zicsr extension gives full access to Control and Status Registers, enabling: * Interrupts and exception handling (per RISC-V Privileged Spec) * Performance counters and timers * JTAG-compatible debug interface – compliant with RISC-V Debug Spec (0.13.2 & 1.0.0) 🧪 Ready for Development & Integration: * Comes with a fully automated testbench * Includes a comprehensive suite of validation tests for smooth SoC integration * Supported by industry-standard tools, ensuring a hassle-free dev experience Whether you’re designing for automotive safety, industrial control, IoT gateways, or AI-enabled edge devices, the DRV64IMZicsr gives you the performance, flexibility, and future-readiness of RISC-V—without compromise. 💡 Build smarter, safer systems—on your terms. 📩 Contact us today at info@dcd.pl to start your next RISC-V-powered project.
Silhouse is an advanced machine vision toolkit designed to accelerate the deployment of AI-driven visual recognition systems. It is particularly tailored for industrial and robotics applications where rapid processing and accuracy are required. The toolkit simplifies the integration of machine vision capabilities in assembly lines, quality control, and automated inspection systems. Equipped with high-performance algorithms and hardware-agnostic interfaces, Silhouse reduces the complexity inherent in setting up vision systems. It allows users to configure and deploy vision applications without in-depth programming knowledge, making advanced visual analytics accessible to a wider range of users. In an era where automation and process efficiency demand swift technological integration, Silhouse provides a competitive edge. It supports adaptable and scalable solutions tailored to individual user needs, facilitating seamless integration into existing infrastructure across various industries.
DRV32IMZicsr – Scalable RISC-V Power. Tailored for Your Project. Ready for the Future. The DRV32IMZicsr is a high-performance, 32-bit RISC-V processor core, equipped with M (Multiply/Divide), Zicsr (Control and Status Registers), and External Debug support. Built as part of DCD’s latest DRVX Core Family, it delivers the full flexibility, openness, and innovation that RISC-V promises—without locking you into proprietary architectures. ✅ Why RISC-V? RISC-V is a rapidly growing open standard for modern computing—backed by a global ecosystem of developers and vendors. It brings: * Freedom from licensing fees and vendor lock-in * Scalability from embedded to high-performance systems * Customizability with standard and custom instruction sets * Strong toolchain & ecosystem support 🚀 DRV32IMZicsr Highlights: * Five-stage pipeline and Harvard architecture for optimized performance * Configurable memory architecture: size and address allocation tailored to your needs Performance metrics: * **Up to 1.15 DMIPS/MHz** * **Up to 2.36 CoreMark/MHz** * Minimal footprint starting from just 14k gates * Flexible interfaces: Choose from AXI, AHB, or native bus options 🛡️ Designed for Safety & Integration: * Developed as an ISO 26262 Safety Element out of Context (SEooC) * Fully technology-agnostic, compatible with all FPGA and ASIC platforms * Seamless integration with DCD’s rich portfolio of IPs: DMA, SPI, UART, PWM, CAN, and more 🔍 Advanced Feature Set: * 32 general-purpose registers * Support for arithmetic, logic, load/store, conditional and unconditional control flow * M extension enables efficient integer multiplication/division * Zicsr extension provides robust interrupt and exception handling, performance counters, and timers * External Debug via JTAG: compliant with RISC-V Debug Specification 0.13.2 and 1.0.0, compatible with all mainstream tools 🧪 Developer-Ready: * Delivered with a fully automated testbench * Includes a comprehensive validation test suite for smooth integration into your SoC flow Whether you're building for automotive, IoT, consumer electronics, or embedded systems, the DRV32IMZicsr offers a future-ready RISC-V solution—highly configurable, performance-optimized, and backed by DCD’s 25 years of experience. Interested? Let’s build the next generation together. 📩 Contact us at info@dcd.pl
The D68000-CPU32 soft core is binary-compatible with the industry standard 68000's CPU32 version of the 32-bit microcontroller. The D68000-CPU32 has a 16-bit data bus and a 24-bit address data bus, and it is code compatible with the 68000's CPU32 (version of MC68020). The D68000-CPU32 includes an improved instruction set, allowing for higher performance than the standard 68000 core, and a built-in DoCD-BDM debugger interface. It is delivered with a fully automated test bench and a set of tests enabling easy package validation during different stages of the SoC design flow. The D68000-CPU32 is technology-agnostic, ensuring compatibility with all FPGA and ASIC vendors.
The D68HC11F is a synthesizable SOFT Microcontroller IP Core, fully compatible with the Motorola 68HC11F1 industry standard. It can be used as a direct replacement for the 68HC11F1 Microcontrollers. Major peripheral functions are integrated on-chip, including an asynchronous serial communications interface (SCI) and a synchronous serial peripheral interface (SPI). The main 16-bit, free-running timer system includes input capture and output-compare lines, and a real-time interrupt function. An 8-bit pulse accumulator subsystem counts external events or measures external periods. Self-monitoring on-chip circuitry protects the D68HC11F against system errors. The Computer Operating Properly (COP) watchdog system and illegal opcode detection circuit provide extra security features. Two power-saving modes, WAIT and STOP, make the IP core especially attractive for automotive and battery-driven applications. Additionally, the D68HC11F can be equipped with an ADC Controller, offering compatibility with external ADCs. Its customizable nature means it's delivered in configurations tailored to need, avoiding unnecessary features and silicon waste. The D68HC11F also includes a fully automated test bench and comprehensive tests for easy SoC design validation. It supports DCD’s DoCD™, a real-time hardware debugger, for non-intrusive debugging of complete SoCs. This IP Core is technology agnostic, ensuring 100% compatibility with all FPGA and ASIC vendors.
The DP8051 is an ultra-high performance, speed-optimized softcore, of a single-chip 8-bit embedded controller, intended to operate with fast (typically on-chip) and slow (off-chip) memories. The core was designed with a special concern about the performance to power-consumption ratio. This ratio is extended by the PMU – an advanced power management unit. The DP8051 softcore is 100% binary-compatible with the industry standard 8051 8-bit microcontrollers. There are two configurations of the DP8051: Harvard, where internal data and program buses are separated and von Neumann, with a common program and external data bus. The DP8051 has a Pipelined RISC architecture and executes 120-300 million instructions per second. Dhrystone 2.1 benchmark program runs from 11.46 to 15.55 times faster than the original 80C51 at the same frequency. The same C compiler was used for benchmarking of the core vs 80C51, with the same settings. This performance can also be exploited to great advantage in low-power applications, where the core can be clocked over ten times slower than the original implementation, without performance depletion. The DP8051 is delivered with a fully automated test bench and a complete set of tests, allowing easy package validation, at each stage of the SoC design flow. Each of DCD’s 8051 Cores has built-in support for the Hardware Debug System called DoCD™. It is a real-time hardware debugger, which provides debugging capability of the whole System-on-Chip (SoC). Unlike other on-chip debuggers, the DoCD™ provides non-intrusive debugging of a running application. It can halt, run, step into or skip an instruction, and read/write any contents of the microcontroller, including all registers, internal and external program memories, and all SFRs, including user-defined peripherals. ALL DCD’S IP CORES ARE TECHNOLOGY AGNOSTIC, ENSURING 100% COMPATIBILITY WITH ALL FPGA AND ASIC VENDORS.
The I3C Host/Device Dual Role Controller IP by Arasan offers flexibility and efficiency in managing both master and slave configurations in device communication. Compliant with the latest I3C specifications, this IP facilitates data exchanges in smart devices with reduced complexity and power consumption. It is particularly effective in applications requiring systematic inter-device communication, such as IoT and mobile systems, where balanced performance and low power draw are priorities.
Gyrus AI's ML/AI Frameworks provide the essential structures needed for developing and deploying machine learning and AI solutions across industries. This suite offers comprehensive support for various stages of AI implementation, from model training to deployment, ensuring that businesses can efficiently integrate AI capabilities into their operations. Designed to work across platforms, their frameworks support seamless execution and scaling of AI components, promoting agile innovation and improving technology efficiencies in business processes.
Silvaco's IP includes a selection of 32/16/8-bit embedded processors designed to meet the demands of tier-1 semiconductor companies. The range includes ColdFire V1 to V4 processors, featuring high performance and low-power operation, ideal for embedded systems requiring reliable data processing capabilities.
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