All IPs > Processor > Coprocessor
In the realm of modern computing, coprocessor semiconductor IPs play a crucial role in augmenting system capabilities. A coprocessor is a supplementary processor that executes specific tasks more efficiently than the primary central processing unit (CPU). These coprocessors are specialized semiconductor IPs utilized in devices requiring enhanced computational power for particular functions such as graphics rendering, encryption, mathematical calculations, and artificial intelligence (AI) processing.
Coprocessors are integral in sectors where high performance and efficiency are paramount. For instance, in the gaming industry, a graphics processing unit (GPU) acts as a coprocessor to handle the high demand for rendering visuals, thus alleviating the burden from the CPU. Similarly, AI accelerators in smartphones and servers offload intensive AI computation tasks to speed up processing while conserving power.
You will find various coprocessor semiconductor IP products geared toward enhancing computational specialization. These include digital signal processors (DSPs) for processing real-time audio and video signals and hardware encryption coprocessors for securing data transactions. With the rise in machine learning applications, tensor processing units (TPUs) have become invaluable, offering massively parallel computing to efficiently manage AI workloads.
By incorporating these coprocessor semiconductor IPs into a system design, manufacturers can achieve remarkable improvements in speed, power efficiency, and processing power. This enables the development of cutting-edge technology products across a range of fields from personal electronics to autonomous vehicles, ensuring optimal performance in specialized computing tasks.
The Akida Neural Processor IP by BrainChip is a versatile AI solution that melds neural processing capabilities with scalable digital architecture, delivering high performance with minimal power consumption. At its core, this processor is engineered using principles from neuromorphic computing to address the demands of AI workloads with precision and speed. By enabling efficient computations with sparse data, the Akida Neural Processor optimizes sparse data, weights, and activations, making it especially suitable for AI applications that demand real-time processing with low latency. It provides a flexible solution for implementing neural networks with varying complexities and is adaptable to a wide array of use cases from audio processing to visual recognition. The IP core’s configurable framework supports the execution of complex neural models on edge devices, effectively running sophisticated neural algorithms like Convolutional Neural Networks (CNNs) without the need for complementary computing resources. This standalone operation capability reduces dependency on external CPUs, driving down power consumption and liberating devices from constant network connections.
xcore.ai stands as a cutting-edge processor that brings sophisticated intelligence, connectivity, and computation capabilities to a broad range of smart products. Designed to deliver optimal performance for applications in consumer electronics, industrial control, and automotive markets, it efficiently handles complex processing tasks with low power consumption and rapid execution speeds. This processor facilitates seamless integration of AI capabilities, enhancing voice processing, audio interfacing, and real-time analytics functions. It supports various interfacing options to accommodate different peripheral and sensor connections, thus providing flexibility in design and deployment across multiple platforms. Moreover, the xcore.ai ensures robust performance in environments requiring precise control and high data throughput. Its compatibility with a wide array of software tools and libraries enables developers to swiftly create and iterate applications, reducing the time-to-market and optimizing the design workflows.
RaiderChip's GenAI v1 is a pioneering hardware-based generative AI accelerator, designed to perform local inference at the Edge. This technology integrates optimally with on-premises servers and embedded devices, offering substantial benefits in privacy, performance, and energy efficiency over traditional hybrid AI solutions. The design of the GenAI v1 NPU streamlines the process of executing large language models by embedding them directly onto the hardware, eliminating the need for external components like CPUs or internet connections. With its ability to support complex models such as the Llama 3.2 with 4-bit quantization on LPDDR4 memory, the GenAI v1 achieves unprecedented efficiency in AI token processing, coupled with energy savings and reduced latency. What sets GenAI v1 apart is its scalability and cost-effectiveness, significantly outperforming competitive solutions such as Intel Gaudi 2, Nvidia's cloud GPUs, and Google's cloud TPUs in terms of memory efficiency. This solution maximizes the number of tokens generated per unit of memory bandwidth, thus addressing one of the primary limitations in generative AI workflow. Furthermore, the adept memory usage of GenAI v1 reduces the dependency on costly memory types like HBM, opening the door to more affordable alternatives without diminishing processing capabilities. With a target-agnostic approach, RaiderChip ensures the GenAI v1 can be adapted to various FPGAs and ASICs, offering configuration flexibility that allows users to balance performance with hardware costs. Its compatibility with a wide range of transformers-based models, including proprietary modifications, ensures GenAI v1's robust placement across sectors requiring high-speed processing, like finance, medical diagnostics, and autonomous systems. RaiderChip's innovation with GenAI v1 focuses on supporting both vanilla and quantized AI models, ensuring high computation speeds necessary for real-time applications without compromising accuracy. This capability underpins their strategic vision of enabling versatile and sustainable AI solutions across industries. By prioritizing integration ease and operational independence, RaiderChip provides a tangible edge in applying generative AI effectively and widely.
The Akida IP platform is a revolutionary neural processor inspired by the workings of the human brain to achieve unparalleled cognitive capabilities and energy efficiency. This self-contained neural processor utilizes a scalable architecture that can be configured from 1 to 128 nodes, each capable of supporting 128 MAC operations. It allows for the execution of complex neural network operations with minimal power and latency, making it ideal for edge AI applications in vision, audio, and sensor fusion. The Akida IP supports multiple data formats including 4-, 2-, and 1-bit weights and activations, enabling the seamless execution of various neural networks across multiple layers. Its convolutional and fully-connected neural processors can perform multi-layered executions independently of a host CPU, enhancing flexibility in diverse applications. Additionally, its event-based hardware acceleration significantly reduces computation and communication loads, preserving host CPU resources and optimizing overall system efficiency. Silicon-proven, the Akida platform provides a cost-effective and secure solution due to its on-chip learning capabilities, supporting one-shot and few-shot learning methods. By maintaining sensitive data on-chip, the system offers improved security and privacy. Its extensive configurability ensures adaptability for post-silicon applications, making Akida an intelligent and scalable choice for developers. It is especially suited for implementations that require real-time processing and sophisticated AI functionalities at the edge.
The 3D Imaging Chip is designed to enhance the capabilities of devices requiring advanced 3D sensing and imaging technology. With an emphasis on precision, this chip supports a myriad of applications ranging from security and surveillance systems to autonomous machinery. It integrates seamlessly not only into varied machine vision systems but also into devices used in different fields that rely on accurate depth perception. This 3D imaging solution underscores Altek's commitment to producing high-performance technology that aids in intricate environment analysis and decision-making processes. This chip employs cutting-edge algorithms to improve the depth perception capabilities of devices, ensuring that it can operate effectively in diverse environments from short to long range. By integrating seamlessly into complex systems, this product strengthens overall functionality, making it an indispensable component in robotics and automated systems. Its robust capacity to handle various environmental conditions also highlights its versatility in usage across different industries. Moreover, this imaging technology is meticulously crafted to reduce energy consumption while maintaining high processing speeds, which are critical in time-sensitive and energy-conscious applications. The sophistication of this chip lies in its ability to combine high-resolution data capture with fast data processing, providing users with the assurance of accuracy and efficiency in real-time operational settings. This positions it as a pivotal development for industries looking to adopt smarter and more efficient technological solutions.
Poised to deliver exceptional performance in advanced applications, the SCR9 processor core epitomizes modern processing standards with its 12-stage dual-issue out-of-order pipeline and hypervisor support. Its inclusion of a vector processing unit (VPU) positions it as essential for high-performance computing tasks that require extensive parallel data processing. Suitable for high-demand environments such as enterprise data systems, AI workloads, and computationally intensive mobile applications, the SCR9 core is tailored to address high-throughput demands while maintaining reliability and accuracy. With support for symmetric multiprocessing (SMP) of up to 16 cores, this core stands as a configurable powerhouse, enabling developers to maximize processing efficiency and throughput. The SCR9's capabilities are bolstered by Syntacore’s dedication to supporting developers with comprehensive tools and documentation, ensuring efficient design and implementation. Through its blend of sophisticated features and support infrastructure, the SCR9 processor core paves the way for advancing technological innovation across numerous fields, establishing itself as a robust solution in the rapidly evolving landscape of high-performance computing.
The GenAI v1-Q from RaiderChip brings forth a specialized focus on quantized AI operations, reducing memory requirements significantly while maintaining impressive precision and speed. This innovative accelerator is engineered to execute large language models in real-time, utilizing advanced quantization techniques such as Q4_K and Q5_K, thereby enhancing AI inference efficiency especially in memory-constrained environments. By offering a 276% boost in processing speed alongside a 75% reduction in memory footprint, GenAI v1-Q empowers developers to integrate advanced AI capabilities into smaller, less powerful devices without sacrificing operational quality. This makes it particularly advantageous for applications demanding swift response times and low latency, including real-time translation, autonomous navigation, and responsive customer interactions. The GenAI v1-Q diverges from conventional AI solutions by functioning independently, free from external network or cloud auxiliaries. Its design harmonizes superior computational performance with scalability, allowing seamless adaptation across variegated hardware platforms including FPGAs and ASIC implementations. This flexibility is crucial for tailoring performance parameters like model scale, inference velocity, and power consumption to meet exacting user specifications effectively. RaiderChip's GenAI v1-Q addresses crucial AI industry needs with its ability to manage multiple transformer-based models and confidential data securely on-premises. This opens doors for its application in sensitive areas such as defense, healthcare, and financial services, where confidentiality and rapid processing are paramount. With GenAI v1-Q, RaiderChip underscores its commitment to advancing AI solutions that are both environmentally sustainable and economically viable.
The Spiking Neural Processor T1 represents a significant leap in neuromorphic microcontroller technology, blending ultra-low power consumption with advanced spiking neural network capabilities. This microcontroller stands as a complete solution for processing sensor data with unprecedented efficiency and speed, bringing intelligence directly to the sensor. Incorporating a nimble RISC-V processor core alongside its spiking neural network engine, the T1 is engineered for seamless integration into next-generation AI applications. Within a tightly constrained power envelope, it excels at signal processing tasks that are crucial for battery-operated, latency-sensitive devices. The T1's architecture allows for fast, sub-1mW pattern recognition, enabling real-time sensory data processing akin to the human brain's capabilities. This microcontroller facilitates complex event-driven processing with remarkable efficiency, reducing the burden on application processors by offloading sensor data processing tasks. It is an enabler of groundbreaking developments in wearables, ambient intelligence, and smart devices, particularly in scenarios where power and response time are critical constraints. With flexible interface support, including QSPI, I2C, UART, and more, the T1 is designed for easy integration into existing systems. Its compact package size further enhances its suitability for embedded applications, while its comprehensive Evaluation Kit (EVK) supports developers in accelerating application development. The EVK provides extensive performance profiling tools, enabling the exploration of the T1's multifaceted processing capabilities. Overall, the T1 stands at the forefront of bringing brain-inspired intelligence to the edge, setting a new standard for smart sensor technology.
The Veyron V1 is a high-performance RISC-V CPU aimed at data centers and similar applications that require robust computing power. It integrates with various chiplet and IP cores, making it a versatile choice for companies looking to create customized solutions. The Veyron V1 is designed to offer competitive performance against x86 and ARM counterparts, providing a seamless transition between different node process technologies. This CPU benefits from Ventana's innovation in RISC-V technology, where efforts are placed on providing an extensible architecture that facilitates domain-specific acceleration. With capabilities stretching from hyperscale computing to edge applications, the Veyron V1 supports extensive instruction sets for high-throughput operations. It also boasts leading-edge chiplet interfaces, opening up numerous opportunities for rapid productization and cost-effective deployment. Ventana's emphasis on open standards ensures that the Veyron V1 remains an adaptable choice for businesses aiming at bespoke solutions. Its compatibility with system IP and its provision in multiple platform formats—including chiplets—enable businesses to leverage the latest technological advancements in RISC-V. Additionally, the ecosystem surrounding the Veyron series ensures support for both modern software frameworks and cross-platform integration.
The DisplayPort Transmitter from Trilinear Technologies is a sophisticated solution designed for high-performance digital video streaming applications. It is compliant with the latest VESA DisplayPort standards, ensuring compatibility and seamless integration with a wide range of display devices. This transmitter core supports high-resolution video outputs and is equipped with advanced features like adaptive sync and panel refresh options, making it ideal for consumer electronics, automotive displays, and professional AV systems. This IP core provides reliable performance with minimal power consumption, addressing the needs of modern digital ecosystems where energy efficiency is paramount. It includes customizable settings for audio and video synchronization, ensuring optimal output quality and user experience across different devices and configurations. By reducing load on the system processor, the DisplayPort Transmitter guarantees a seamless streaming experience even in high-demand environments. In terms of integration, Trilinear's DisplayPort Transmitter is supported with comprehensive software stacks allowing for easy customization and deployment. This ensures rapid product development cycles and aids developers in managing complex video data streams effectively. The transmitter is particularly optimized for use in embedded systems and consumer devices, offering robust performance capabilities that stand up to rigorous real-time application demands. With a focus on compliance and testing, the DisplayPort Transmitter is pre-tested and proven to work seamlessly with a variety of hardware platforms including FPGA and ASIC technologies. This robustness in design and functionality underlines Trilinear's reputation for delivering reliable, high-quality semiconductor IP solutions that cater to diverse industrial applications.
The RISC-V Hardware-Assisted Verification by Bluespec is designed to expedite the verification process for RISC-V cores. This platform supports both ISA and system-level testing, adding robust features such as verifying standard and custom ISA extensions along with accelerators. Moreover, it offers scalable access through the AWS cloud, making verification available anytime and anywhere. This tool aligns with the needs of modern developers, ensuring thorough testing within a flexible and accessible framework.
Dyumnin's RISCV SoC is a versatile platform centered around a 64-bit quad-core server-class RISCV CPU, offering extensive subsystems, including AI/ML, automotive, multimedia, memory, cryptographic, and communication systems. This test chip can be reviewed in an FPGA format, ensuring adaptability and extensive testing possibilities. The AI/ML subsystem is particularly noteworthy due to its custom CPU configuration paired with a tensor flow unit, accelerating AI operations significantly. This adaptability lends itself to innovations in artificial intelligence, setting it apart in the competitive landscape of processors. Additionally, the automotive subsystem caters robustly to the needs of the automotive sector with CAN, CAN-FD, and SafeSPI IPs, all designed to enhance systems connectivity within vehicles. Moreover, the multimedia subsystem boasts a complete range of IPs to support HDMI, Display Port, MIPI, and more, facilitating rich audio and visual experiences across devices.
Trilinear Technologies has developed a cutting-edge DisplayPort Receiver that enhances digital connectivity, offering robust video reception capabilities necessary for today's high-definition video systems. Compliant with VESA standards, the receiver supports the latest DisplayPort specifications, effortlessly handling high-bandwidth video data necessary for applications such as ultra-high-definition televisions, professional video wall setups, and complex automotive display systems. The DisplayPort Receiver is designed with advanced features that facilitate seamless video data acquisition and processing, including multi-stream transport capabilities for handling multiple video streams concurrently. This is particularly useful in professional display settings where multiple input sources are needed. The core also incorporates adaptive sync features, which help reduce screen tearing and ensure smooth video playback, enhancing user experience significantly. An important facet of the DisplayPort Receiver is its low latency and high-efficiency operations, crucial for systems requiring real-time data processing. Trilinear's receiver core ensures that video data is processed with minimal delay, maintaining the integrity and fidelity of the original visual content. This makes it a preferred choice for high-performance applications in sectors like gaming, broadcasting, and high-definition video conferencing. To facilitate integration and ease of use, the DisplayPort Receiver is supported by a comprehensive suite of development tools and software packages. This makes the deployment process straightforward, allowing developers to integrate the receiver into both FPGA and ASIC environments with minimal adjustments. Its scalability and flexibility mean it can meet the demands of a wide range of applications, solidifying Trilinear Technologies' position as a leader in the field of semiconductor IP solutions.
Enclustra's Universal Drive Controller is a versatile IP core designed for controlling a range of motors directly from FPGAs. This robust solution allows simultaneous position and velocity control of up to eight different DC, BLDC, or stepper motors, offering high flexibility for a variety of industrial and robotic applications. The drive controller provides precise and independent motor management features through its customizable architecture, ensuring optimized performance tailored to specific motion control requirements. This capability reduces the need for additional external components, streamlining integration and reducing system complexity. In addition to its primary control features, the Universal Drive Controller supports various communication interfaces, enabling seamless integration into existing systems. This IP core is essential for developers focusing on high-performance motor control systems, thanks to its scalable and adaptable approach to motor management.
DolphinWare IPs is a versatile portfolio of intellectual property solutions that enable efficient SoC design. This collection includes various control logic components such as FIFO, arbiter, and arithmetic components like math operators and converters. In addition, the logic components span counters, registers, and multiplexers, providing essential functionalities for diverse industrial applications. The IPs in this lineup are meticulously designed to ensure data integrity, supported by robust verification IPs for AXI4, APB, SD4.0, and more. This comprehensive suite meets the stringent demands of modern electronic designs, facilitating seamless integration into existing design paradigms. Beyond their broad functionality, DolphinWare’s offerings are fundamental to applications requiring specific control logic and data integrity solutions, making them indispensable for enterprises looking to modernize or expand their product offerings while ensuring compliance with industry standards.
Designed to cater to the needs of edge computing, the Neural Network Accelerator by Gyrus AI is a powerhouse of performance and efficiency. With a focus on graph processing capabilities, this product excels in implementing neural networks by providing native graph processing. The accelerator attains impressive speeds, achieving 30 TOPS/W, while offering efficient computational power with significantly reduced clock cycles, ranging between 10 to 30 times less compared to traditional models. The design ensures that power consumption is kept at a minimum, being 10-20 times lower due to its low memory usage configuration. Beyond its power efficiency, this accelerator is designed to maximize space with a smaller die area, ensuring an 8-10 times reduction in size while maintaining high utilization rates of over 80% for various model structures. Such design optimizations make it an ideal choice for applications requiring a compact, high-performance solution capable of delivering fast computations without compromising on energy efficiency. The Neural Network Accelerator is a testament to Gyrus AI's commitment to enabling smarter edge computing solutions. Additionally, Gyrus AI has paired this technology with software tools that facilitate the execution of neural networks on the IP, simplifying integration and use in various applications. This seamless integration is part of their broader strategy to augment human intelligence, providing solutions that enhance and expand the capabilities of AI-driven technologies across industries.
SystemBIST offers a versatile plug-and-play solution for FPGA configuration and JTAG testing with its unique patented architecture. This product is ideal for creating high-quality, self-testable, and in-the-field reconfigurable equipment, ensuring reliable integration and testing in any IEEE 1532 or 1149.1 compliant devices. SystemBIST efficiently utilizes existing system flash memory to store vital configuration and test data, which can be applied at power-up, enabling cost-effective setup without the need for multiple configuration PROMs. Additionally, SystemBIST enhances PCB testing efficacy by embedding deterministic Built-In Self-Test (BIST) capabilities, using manufacturing-based JTAG/IEEE 1149.1 test patterns to conduct efficient system tests. This platform simplifies the adoption of robust security measures, including 128-bit security identifiers, helping prevent unauthorized cloning and tampering of FPGAs. By doing so, it seamlessly supports the intricate demands of modern electronics and embedded systems. The platform not only reduces the cost associated with in-system configuration but also advances the embedded test methodology by enabling debugging without removing and replacing programmable components. It offers a scalable and reusable test infrastructure, applicable across different product generations and varying applications, thereby extending the operational life and value of the technology involved.
The Maverick-2 Intelligent Compute Accelerator represents a significant leap in compute technology, designed to deliver exceptional performance and adaptability for complex workloads. Building on the foundation of its predecessor, Maverick-2 integrates advanced software-defined architecture that dynamically adjusts its configuration to optimize for different computational tasks in real-time. \n\nThis product is ideal for high-performance computing and AI applications, offering unparalleled efficiency and flexibility. Its intelligent architecture is capable of responding to dynamic workload conditions, ensuring that computational resources are used optimally. Maverick-2 seamlessly integrates with existing systems, providing developers with a robust toolset that simplifies porting and enhances application compatibility across different programming environments. \n\nMaverick-2 stands out with its sustainable design, emphasizing power efficiency and reduced operational costs. Its next-generation technology supports a wide range of applications, ensuring that organizations can meet both their immediate and future technological needs. With this accelerator, Next Silicon Ltd. reinforces its position as a leader in adapting cutting-edge technology to support long-term innovation and efficiency in high-performance computing spaces.
iCEVision facilitates rapid prototyping and evaluation of connectivity features using the Lattice iCE40 UltraPlus FPGA. Designers can take advantage of exposed I/Os for quick implementation and validation of solutions, while enjoying compatibility with common camera interfaces such as ArduCam CSI and PMOD. This flexibility is complemented by software tools such as the Lattice Diamond Programmer and iCEcube2, which allow designers to reprogram the onboard SPI Flash and develop custom solutions. The platform comes preloaded with a bootloader and an RGB demo application, making it quick and easy for users to begin experimenting with their projects. Its design includes features like a 50mmx50mm form factor, LED applications, and multiple connectivity options, ensuring broad usability across various rapid prototyping scenarios. With its user-friendly setup and comprehensive toolkit, iCEVision is perfect for developers who need a streamlined path from initial design to functional prototype, especially in environments where connectivity and sensor integration are key.
The TimbreAI T3 is tailored for audio-focused devices, providing ultra-low power AI capabilities for applications like noise reduction in headsets. Offering performance up to 3.2 billion operations per second while maintaining minimal power draw of under 300μW, it is a prime choice for consumer audio solutions with strict area and power consumption needs. Its architecture ensures seamless integration and rapid deployment without external memory requirements, thereby achieving high performance while saving system power and chip area.
Cobalt is a cutting-edge GNSS receiver that is expertly designed to offer ultra-low-power functionality, specifically tailored to IoT Systems-on-Chip. It is engineered to extend the market potential of IoT devices by integrating essential GNSS capabilities into modem SoCs. This not only conserves energy but also ensures that devices maintain compact sizes, essential for applications sensitive to size constraints and energy efficiency. Cobalt features a software-defined receiver capable of supporting major constellations such as Galileo, GPS, and Beidou, ensuring a broad reach and reliable performance in varied environments. Its standalone and cloud-assisted positioning functions optimize power usage, allowing for enhanced sensitivity and finer accuracy even in challenging conditions. Developed in collaboration with CEVA DSP and backed by the European Space Program Agency, Cobalt incorporates advanced processing techniques that improve resistance to multi-path interference and enhance modulation rates. This ensures that IoT devices utilizing Cobalt are equipped with state-of-the-art geolocation services, vital for sectors like logistics, agriculture, and mobility solutions.
Designed as a public key algorithm coprocessor, the FortiPKA-RISC-V stands out for its ability to streamline operations typically bogged down by Montgomery domain transformations. This component is tailored for high performance in embedded systems, ensuring enhanced data security through its advanced modular multiplication and robust protection against SCA and FIA. Particularly suited for secure System on Chip (SoC) integration, FortiPKA-RISC-V offers significant performance improvements without increasing area constraints.
The Avispado core is a highly efficient, 64-bit in-order RISC-V processor from Semidynamics, engineered for energy-conscious applications such as AI edge computing and embedded systems. Its in-order architecture ensures predictable execution with lower power consumption, making it suitable for applications where energy efficiency is paramount. Equipped with the RISC-V Vector Specification 1.0, Avispado supports advanced AI acceleration. This feature allows the core to handle complex machine learning tasks and edge AI applications with ease. Its design facilitates high bandwidth data movement, leveraging Gazzillion Misses™ technology to process up to 64 simultaneous memory requests efficiently. The Avispado core is built for versatility, supporting multiprocessing environments with cache-coherent implementations. The core’s interface can be tailored to specific requirements, using either AXI or CHI depending on the application, making it an excellent fit for embedded computing and IoT devices that require enhanced processing capabilities without sacrificing power efficiency.
The CVC Verilog Simulator by Tachyon Design Automation is a robust tool designed to adhere to the IEEE 1364 2005 Verilog HDL standard. It offers both compiled and interpreted simulation modes, allowing users to choose between quick elaboration and high-speed execution. Benefiting from its native x86_64 machine instruction execution, the simulator ensures optimum performance and capability to handle extensive gate and RTL designs. Available in both open-source and commercial versions, CVC enables users to download and evaluate its powerful features without financial commitment, while enterprises can opt for additional support with the Enterprise version. With its advanced simulation capabilities, CVC supports a variety of features including toggle coverage, full PLI support, and efficient dump formats like VCD/EVCD/FST. These features, combined with parallel processing options, make it a go-to simulator for complex electronic hardware modeling. The tool’s architecture allows for the efficient simulation of very large gate and RTL designs, leveraging 64-bit simulation speeds. Additionally, its compatibility with Linux X86 systems ensures broad accessibility and usability within various design environments. CVC’s advanced features set, including novel x-propagation algorithms and machine code optimization, positions it as a market leader in the domain of HDL simulation.
Specialty Microcontrollers from Advanced Silicon harness the capabilities of the latest RISC-V architectures for advanced processing tasks. These microcontrollers are particularly suited to applications involving image processing, thanks to built-in coprocessing units that enhance their algorithm execution efficiency. They serve as ideal platforms for sophisticated touch screen interfaces, offering a balance of high performance, reliability, and low power consumption. The integrated features allow for the enhancement of complex user interfaces and their interaction with other system components to improve overall system functionality and user experience.
The IEEE Floating Point Multiplier/Adder core is designed to efficiently execute floating point arithmetic operations, staple computations within complex digital signal processing tasks. By adhering to IEEE standards, this core guarantees precision and consistency in mathematical operations, vital for scientific and engineering applications. This IP core efficiently handles both multiplication and addition processes, allowing for enhanced computational throughput in environments such as signal processing, computer graphics, and machine learning algorithms. Its design ensures minimal latency and optimal resource utilization, making it highly suitable for integration into high-performance digital systems. Engineers and developers benefit from the core’s precision and speed, which are critical for simulations and real-time processing requirements. Whether in enhancing image processing capabilities or improving algorithmic efficiency, this IP contributes significantly to the reduction of processing load times and increases overall system performance.
Gyrus AI's offering in Business Intelligence harnesses cutting-edge AI technologies to transform the landscape of enterprise analytics. This solution interfaces seamlessly with business data layers to provide actionable insights, enhancing decision-making processes across organizational levels. By integrating with existing AI and ML frameworks, it draws on vast amounts of data, processing it to reveal patterns and predictive insights that drive strategic business outcomes. The AI in Business Intelligence solution is designed to handle large datasets efficiently, utilizing machine learning models to automate the data processing and analysis pipeline. With its capacity to quickly generate detailed visual and textual summaries, businesses can achieve enhanced visibility over operations and market trends, aiding in more informed and timely decision-making. This capability empowers organizations to stay agile and responsive in today's fast-paced economic environment. Its AI-powered analytics is implemented using intuitive dashboards and reporting tools that are user-friendly, allowing multiple stakeholders to glean insights without the need for deep technical expertise. This democratization of data intelligence significantly increases the utility and accessibility of business analytics, providing a competitive edge through data-driven strategy formulation and execution.
Semidynamics offers the Atrevido core, a cutting-edge 64-bit RISC-V processor designed for high-performance computing environments. The core supports out-of-order execution, enhancing processing efficiency by allowing multiple instructions to be executed simultaneously. This flexibility enables the Atrevido processor to excel in demanding AI and HPC applications, providing an efficient solution for tasks such as inference, key-value stores, and sparse data processing. An integral feature of the Atrevido core is its support for vector and tensor capabilities. These units are seamlessly integrated within the core to provide scalable AI acceleration without incurring latency penalties. This makes the Atrevido core an optimal choice for industries looking to incorporate AI workloads seamlessly into their computing systems. The Atrevido core also benefits from the Gazzillion Misses™ technology, which improves memory access performance by handling a high number of simultaneous memory requests, reducing bottlenecks. Compatibility with AXI and CHI interfaces further enhances its utility in multiprocessor configurations, making it a robust, versatile option for advanced computing needs.
Panmnesia's PanAccelerator is a high-performance solution crafted to boost the processing power of AI systems. It is tailored for leading-edge machine learning workloads that require high-bandwidth memory expansion and rapid GPU interconnection. This accelerator supports efficient power usage and offers expansive scalability, making it ideal for large-scale AI training environments.
Low Power Futures offers a formidable solution in the Low Power Security Engine, tailored to enhance the security measures of resource-constrained embedded devices. This advanced IP features a compact design that combines power efficiency with robust security capabilities, including support for ECDHE and ECDSA protocols. Its integrated acceleration engine offers protection against timing and side-channel attacks while enabling efficient cryptographic operations. Designed for seamless prototyping and real-world application, this security engine makes an impressive addition to any smart IoT device looking to emphasize security without compromising on performance.
DRV32IMZicsr – Scalable RISC-V Power. Tailored for Your Project. Ready for the Future. The DRV32IMZicsr is a high-performance, 32-bit RISC-V processor core, equipped with M (Multiply/Divide), Zicsr (Control and Status Registers), and External Debug support. Built as part of DCD’s latest DRVX Core Family, it delivers the full flexibility, openness, and innovation that RISC-V promises—without locking you into proprietary architectures. ✅ Why RISC-V? RISC-V is a rapidly growing open standard for modern computing—backed by a global ecosystem of developers and vendors. It brings: * Freedom from licensing fees and vendor lock-in * Scalability from embedded to high-performance systems * Customizability with standard and custom instruction sets * Strong toolchain & ecosystem support 🚀 DRV32IMZicsr Highlights: * Five-stage pipeline and Harvard architecture for optimized performance * Configurable memory architecture: size and address allocation tailored to your needs Performance metrics: * **Up to 1.15 DMIPS/MHz** * **Up to 2.36 CoreMark/MHz** * Minimal footprint starting from just 14k gates * Flexible interfaces: Choose from AXI, AHB, or native bus options 🛡️ Designed for Safety & Integration: * Developed as an ISO 26262 Safety Element out of Context (SEooC) * Fully technology-agnostic, compatible with all FPGA and ASIC platforms * Seamless integration with DCD’s rich portfolio of IPs: DMA, SPI, UART, PWM, CAN, and more 🔍 Advanced Feature Set: * 32 general-purpose registers * Support for arithmetic, logic, load/store, conditional and unconditional control flow * M extension enables efficient integer multiplication/division * Zicsr extension provides robust interrupt and exception handling, performance counters, and timers * External Debug via JTAG: compliant with RISC-V Debug Specification 0.13.2 and 1.0.0, compatible with all mainstream tools 🧪 Developer-Ready: * Delivered with a fully automated testbench * Includes a comprehensive validation test suite for smooth integration into your SoC flow Whether you're building for automotive, IoT, consumer electronics, or embedded systems, the DRV32IMZicsr offers a future-ready RISC-V solution—highly configurable, performance-optimized, and backed by DCD’s 25 years of experience. Interested? Let’s build the next generation together. 📩 Contact us at info@dcd.pl
**DRV64IMZicsr – 64-bit RISC-V Performance. Designed for Demanding Innovation.** The DRV64IMZicsr is a powerful and versatile 64-bit RISC-V CPU core, built to meet the performance and safety needs of next-generation embedded systems. Featuring the M (Multiply/Divide), Zicsr (Control and Status Registers), and External Debug extensions, this core is engineered to scale—from edge computing to mission-critical applications. As part of the DRVX Core Family, the DRV64IMZicsr embodies DCD’s philosophy of combining open-standard freedom with customizable IP excellence—making it a smart and future-proof alternative to legacy architectures. ✅ Why Choose RISC-V? * No license fees – open-source instruction set means reduced TCO * Unmatched flexibility – tailor the architecture to your specific needs * A global, thriving ecosystem – support from toolchains, OSes, and hardware vendors * Security & longevity – open and verifiable architecture ensures trust and sustainability 🚀 DRV64IMZicsr – Core Advantages: * 64-bit RISC-V ISA with M, Zicsr, and Debug support * Five-stage pipeline, Harvard architecture, and efficient branch prediction * Configurable memory size and allocation for program and data spaces Performance optimized: * **Up to 2.38 CoreMark/MHz** * **Up to 1.17 DMIPS/MHz** * Compact footprint starting from just 17.6k gates * Interface options: AXI, AHB, or native * Compatible with Classical CAN, CAN FD, and CAN XL through additional IPs 🛡️ Safety, Compatibility & Flexibility Built In: * Developed as an ISO 26262 Safety Element out of Context (SEooC) * Technology-agnostic – works seamlessly across all FPGA and ASIC vendors * Expandable with DCD’s IP portfolio: DMA, SPI, UART, I²C, CAN, PWM, and more 🔍 Robust Feature Set for Real Applications: * Full 64-bit processing – ideal for performance-intensive, memory-heavy tasks * M extension enables high-speed multiplication/division via dedicated hardware unit * Zicsr extension gives full access to Control and Status Registers, enabling: * Interrupts and exception handling (per RISC-V Privileged Spec) * Performance counters and timers * JTAG-compatible debug interface – compliant with RISC-V Debug Spec (0.13.2 & 1.0.0) 🧪 Ready for Development & Integration: * Comes with a fully automated testbench * Includes a comprehensive suite of validation tests for smooth SoC integration * Supported by industry-standard tools, ensuring a hassle-free dev experience Whether you’re designing for automotive safety, industrial control, IoT gateways, or AI-enabled edge devices, the DRV64IMZicsr gives you the performance, flexibility, and future-readiness of RISC-V—without compromise. 💡 Build smarter, safer systems—on your terms. 📩 Contact us today at info@dcd.pl to start your next RISC-V-powered project.
This networking solution from CetraC endows high-performance capabilities into FPGA and ASIC products, tailored for distributed architectural systems. It is crafted specifically for industries that demand high-speed data transmissions and excellent reliability across their networking infrastructures. The product supports numerous protocols such as TSN, CAN FD, and ARINC429, making it versatile for integration into various high-tech systems needing comprehensive data management and communication structures. The solution also features robust security measures including AES256 encryption to protect data integrity while facilitating seamless protocol conversions to enhance interoperability between various network segments.
The BA22-AP Basic Application Processor, providing 1.79 DMIPS/MHz, operates efficiently at higher frequencies, offering flexibility for diverse applications. Constructed for efficiency, it maintains a gate count of 35,000, making it suitable for various tasks. It is crafted for developers needing reliable performance while enabling custom instructions for specialized needs.
The BA22-CE Cache Enabled Processor is crafted for applications requiring high code density and low power usage. Achieving 1.79 DMIPS/MHz, this processor reaches higher frequencies of up to 450 MHz in 65 nm technology while maintaining a modest gate count under 20,000 and operating power as low as 0.05 W/MHz on 90 nm processes.
The BA25 Advanced Application Processor stands out with independent functional units supporting out-of-order execution. Delivering 1.51 DMIPS/MHz at speeds up to 800 MHz on a 65 nm process, it boasts the highest code density among its category. This processor is designed for high-performance applications that require robust processing capabilities alongside flexible architectural features.
The D68HC11F is a synthesizable SOFT Microcontroller IP Core, fully compatible with the Motorola 68HC11F1 industry standard. It can be used as a direct replacement for the 68HC11F1 Microcontrollers. Major peripheral functions are integrated on-chip, including an asynchronous serial communications interface (SCI) and a synchronous serial peripheral interface (SPI). The main 16-bit, free-running timer system includes input capture and output-compare lines, and a real-time interrupt function. An 8-bit pulse accumulator subsystem counts external events or measures external periods. Self-monitoring on-chip circuitry protects the D68HC11F against system errors. The Computer Operating Properly (COP) watchdog system and illegal opcode detection circuit provide extra security features. Two power-saving modes, WAIT and STOP, make the IP core especially attractive for automotive and battery-driven applications. Additionally, the D68HC11F can be equipped with an ADC Controller, offering compatibility with external ADCs. Its customizable nature means it's delivered in configurations tailored to need, avoiding unnecessary features and silicon waste. The D68HC11F also includes a fully automated test bench and comprehensive tests for easy SoC design validation. It supports DCD’s DoCD™, a real-time hardware debugger, for non-intrusive debugging of complete SoCs. This IP Core is technology agnostic, ensuring 100% compatibility with all FPGA and ASIC vendors.
The D68000-CPU32 soft core is binary-compatible with the industry standard 68000's CPU32 version of the 32-bit microcontroller. The D68000-CPU32 has a 16-bit data bus and a 24-bit address data bus, and it is code compatible with the 68000's CPU32 (version of MC68020). The D68000-CPU32 includes an improved instruction set, allowing for higher performance than the standard 68000 core, and a built-in DoCD-BDM debugger interface. It is delivered with a fully automated test bench and a set of tests enabling easy package validation during different stages of the SoC design flow. The D68000-CPU32 is technology-agnostic, ensuring compatibility with all FPGA and ASIC vendors.
The DP8051 is an ultra-high performance, speed-optimized softcore, of a single-chip 8-bit embedded controller, intended to operate with fast (typically on-chip) and slow (off-chip) memories. The core was designed with a special concern about the performance to power-consumption ratio. This ratio is extended by the PMU – an advanced power management unit. The DP8051 softcore is 100% binary-compatible with the industry standard 8051 8-bit microcontrollers. There are two configurations of the DP8051: Harvard, where internal data and program buses are separated and von Neumann, with a common program and external data bus. The DP8051 has a Pipelined RISC architecture and executes 120-300 million instructions per second. Dhrystone 2.1 benchmark program runs from 11.46 to 15.55 times faster than the original 80C51 at the same frequency. The same C compiler was used for benchmarking of the core vs 80C51, with the same settings. This performance can also be exploited to great advantage in low-power applications, where the core can be clocked over ten times slower than the original implementation, without performance depletion. The DP8051 is delivered with a fully automated test bench and a complete set of tests, allowing easy package validation, at each stage of the SoC design flow. Each of DCD’s 8051 Cores has built-in support for the Hardware Debug System called DoCD™. It is a real-time hardware debugger, which provides debugging capability of the whole System-on-Chip (SoC). Unlike other on-chip debuggers, the DoCD™ provides non-intrusive debugging of a running application. It can halt, run, step into or skip an instruction, and read/write any contents of the microcontroller, including all registers, internal and external program memories, and all SFRs, including user-defined peripherals. ALL DCD’S IP CORES ARE TECHNOLOGY AGNOSTIC, ENSURING 100% COMPATIBILITY WITH ALL FPGA AND ASIC VENDORS.
Optimized for deeply embedded systems, the BA22-DE Processor offers exceptional code density with 1.79 DMIPS/MHz. Designed with efficiency in mind, it contains around 15,000 gates and requires as little as 0.05 mW/MHz on a 90 nm process, outperforming competitors like ARM's Thumb-2 in code density.
The BA20 PipelineZero Embedded Processor is engineered to be the most energy-efficient 32-bit processor available. At a remarkable 2.17 DMIPS/MHz, it operates with ultra-low power consumption of 2uW/MHz, making it ideal for energy-constrained applications. Occupying just 0.01mm^2, this processor's compact design does not compromise on performance.
The Cortex-X Custom CPU from Arm is engineered to exceed standard performance levels, meeting specific market demands for next-generation devices. By integrating this high-powered CPU into your design, you benefit from a performance-first approach that achieves the largest year-on-year performance uplift in the Cortex-X series history. The architecture allows customization, collaborating closely with Arm to tailor the product for specific market needs, providing a significant advantage over traditional offerings. This CPU supports a robust ecosystem compatible with Arm Cortex-A CPUs, ensuring design flexibility and scalability through DynamIQ technology. It's built to power premium devices such as flagship smartphones and laptops, delivering 36% improvements in single-thread performance compared to the latest Android flagship models. Designed on the Armv9.2 architecture, it incorporates cutting-edge security features alongside exceptional computational prowess. The Cortex-X Custom CPU is optimized for a broad range of advanced applications, including AI processing, gaming, and multitasking. Its industry-leading design focuses on achieving maximum market-specific customization and performance optimization, presenting a compelling option for developers aiming for the pinnacle of next-gen device capabilities.
Join the world's most advanced semiconductor IP marketplace!
It's free, and you'll get all the tools you need to discover IP, meet vendors and manage your IP workflow!
Join the world's most advanced AI-powered semiconductor IP marketplace!
It's free, and you'll get all the tools you need to advertise and discover semiconductor IP, keep up-to-date with the latest semiconductor news and more!
Plus we'll send you our free weekly report on the semiconductor industry and the latest IP launches!