All IPs > Processor > Coprocessor
In the realm of modern computing, coprocessor semiconductor IPs play a crucial role in augmenting system capabilities. A coprocessor is a supplementary processor that executes specific tasks more efficiently than the primary central processing unit (CPU). These coprocessors are specialized semiconductor IPs utilized in devices requiring enhanced computational power for particular functions such as graphics rendering, encryption, mathematical calculations, and artificial intelligence (AI) processing.
Coprocessors are integral in sectors where high performance and efficiency are paramount. For instance, in the gaming industry, a graphics processing unit (GPU) acts as a coprocessor to handle the high demand for rendering visuals, thus alleviating the burden from the CPU. Similarly, AI accelerators in smartphones and servers offload intensive AI computation tasks to speed up processing while conserving power.
You will find various coprocessor semiconductor IP products geared toward enhancing computational specialization. These include digital signal processors (DSPs) for processing real-time audio and video signals and hardware encryption coprocessors for securing data transactions. With the rise in machine learning applications, tensor processing units (TPUs) have become invaluable, offering massively parallel computing to efficiently manage AI workloads.
By incorporating these coprocessor semiconductor IPs into a system design, manufacturers can achieve remarkable improvements in speed, power efficiency, and processing power. This enables the development of cutting-edge technology products across a range of fields from personal electronics to autonomous vehicles, ensuring optimal performance in specialized computing tasks.
Akida Neural Processor IP by BrainChip serves as a pivotal technology asset for enhancing edge AI capabilities. This IP core is specifically designed to process neural network tasks with a focus on extreme efficiency and power management, making it an ideal choice for battery-powered and small-footprint devices. By utilizing neuromorphic principles, the Akida Neural Processor ensures that only the most relevant computations are prioritized, which translates to substantial energy savings while maintaining high processing speeds. This IP's compatibility with diverse data types and its ability to form multi-layer neural networks make it versatile for a wide range of industries including automotive, consumer electronics, and healthcare. Furthermore, its capability for on-device learning, without network dependency, contributes to improved device autonomy and security, making the Akida Neural Processor an integral component for next-gen intelligent systems. Companies adopting this IP can expect enhanced AI functionality with reduced development overheads, enabling quicker time-to-market for innovative AI solutions.
MetaTF is BrainChip's toolkit aimed at optimizing and deploying machine learning models onto their proprietary Akida neuromorphic platform. This sophisticated toolset allows developers to convert existing models into sparse neural networks suited for Akida's efficient processing capabilities. MetaTF supports a seamless workflow from model conversion to deployment, simplifying the transition for developers aiming to leverage Akida's low-power, high-performance processing. The toolkit ensures that machine learning applications are optimized for edge deployment without compromising on speed or accuracy. This tool fosters an environment where AI models can be customized to meet specific application demands, delivering personalized and highly-innovative AI solutions. MetaTF's role is crucial in enabling developers to efficiently integrate complex neural networks into real-world devices, aiding in applications like smart city infrastructure, IoT devices, and industrial automation. By using MetaTF, companies can dramatically enhance the adaptability and responsiveness of their AI applications while maintaining stringent power efficiency standards.
Akida IP represents BrainChip's groundbreaking approach to neuromorphic AI processing. Inspired by the efficiencies of cognitive processing found in the human brain, Akida IP delivers real-time AI processing capabilities directly at the edge. Unlike traditional data-intensive architectures, it operates with significantly reduced power consumption. Akida IP's design supports multiple data formats and integrates seamlessly with other hardware platforms, making it flexible for a wide range of AI applications. Uniquely, it employs sparsity, focusing computation only on pertinent data, thereby minimizing unnecessary processing and conserving power. The ability to operate independently of cloud-driven data processes not only conserves energy but enhances data privacy and security by ensuring that sensitive data remains on the device. Additionally, Akida IP’s temporal event-based neural networks excel in tracking event patterns over time, providing invaluable benefits in sectors like autonomous vehicles where rapid decision-making is critical. Akida IP's remarkable integration capacity and its scalability from small, embedded systems to larger computing infrastructures make it a versatile choice for developers aiming to incorporate smart AI capabilities into various devices.
xcore.ai is a versatile and powerful processing platform designed for AIoT applications, delivering a balance of high performance and low power consumption. Crafted to bring AI processing capabilities to the edge, it integrates embedded AI, DSP, and advanced I/O functionalities, enabling quick and effective solutions for a variety of use cases. What sets xcore.ai apart is its cycle-accurate programmability and low-latency control, which improve the responsiveness and precision of the applications in which it is deployed. Tailored for smart environments, xcore.ai ensures robust and flexible computing power, suitable for consumer, industrial, and automotive markets. xcore.ai supports a wide range of functionalities, including voice and audio processing, making it ideal for developing smart interfaces such as voice-controlled devices. It also provides a framework for implementing complex algorithms and third-party applications, positioning it as a scalable solution for the growing demands of the connected world.
RaiderChip's GenAI v1 is a pioneering hardware-based generative AI accelerator, designed to perform local inference at the Edge. This technology integrates optimally with on-premises servers and embedded devices, offering substantial benefits in privacy, performance, and energy efficiency over traditional hybrid AI solutions. The design of the GenAI v1 NPU streamlines the process of executing large language models by embedding them directly onto the hardware, eliminating the need for external components like CPUs or internet connections. With its ability to support complex models such as the Llama 3.2 with 4-bit quantization on LPDDR4 memory, the GenAI v1 achieves unprecedented efficiency in AI token processing, coupled with energy savings and reduced latency. What sets GenAI v1 apart is its scalability and cost-effectiveness, significantly outperforming competitive solutions such as Intel Gaudi 2, Nvidia's cloud GPUs, and Google's cloud TPUs in terms of memory efficiency. This solution maximizes the number of tokens generated per unit of memory bandwidth, thus addressing one of the primary limitations in generative AI workflow. Furthermore, the adept memory usage of GenAI v1 reduces the dependency on costly memory types like HBM, opening the door to more affordable alternatives without diminishing processing capabilities. With a target-agnostic approach, RaiderChip ensures the GenAI v1 can be adapted to various FPGAs and ASICs, offering configuration flexibility that allows users to balance performance with hardware costs. Its compatibility with a wide range of transformers-based models, including proprietary modifications, ensures GenAI v1's robust placement across sectors requiring high-speed processing, like finance, medical diagnostics, and autonomous systems. RaiderChip's innovation with GenAI v1 focuses on supporting both vanilla and quantized AI models, ensuring high computation speeds necessary for real-time applications without compromising accuracy. This capability underpins their strategic vision of enabling versatile and sustainable AI solutions across industries. By prioritizing integration ease and operational independence, RaiderChip provides a tangible edge in applying generative AI effectively and widely.
The GenAI v1-Q from RaiderChip brings forth a specialized focus on quantized AI operations, reducing memory requirements significantly while maintaining impressive precision and speed. This innovative accelerator is engineered to execute large language models in real-time, utilizing advanced quantization techniques such as Q4_K and Q5_K, thereby enhancing AI inference efficiency especially in memory-constrained environments. By offering a 276% boost in processing speed alongside a 75% reduction in memory footprint, GenAI v1-Q empowers developers to integrate advanced AI capabilities into smaller, less powerful devices without sacrificing operational quality. This makes it particularly advantageous for applications demanding swift response times and low latency, including real-time translation, autonomous navigation, and responsive customer interactions. The GenAI v1-Q diverges from conventional AI solutions by functioning independently, free from external network or cloud auxiliaries. Its design harmonizes superior computational performance with scalability, allowing seamless adaptation across variegated hardware platforms including FPGAs and ASIC implementations. This flexibility is crucial for tailoring performance parameters like model scale, inference velocity, and power consumption to meet exacting user specifications effectively. RaiderChip's GenAI v1-Q addresses crucial AI industry needs with its ability to manage multiple transformer-based models and confidential data securely on-premises. This opens doors for its application in sensitive areas such as defense, healthcare, and financial services, where confidentiality and rapid processing are paramount. With GenAI v1-Q, RaiderChip underscores its commitment to advancing AI solutions that are both environmentally sustainable and economically viable.
The 3D Imaging Chip by Altek Corporation is engineered to deliver exceptional depth sensing and precision in imaging applications. Built with advanced 3D sensing capabilities, it is designed for deployment in various environments that require detailed spatial awareness and object recognition. This chip is particularly beneficial for industries such as robotics and drones, where depth precision and object avoidance are critical. In addition to depth accuracy, this imaging chip offers robust integration with IoT platforms, promoting seamless interaction within smart ecosystems. It is equipped with features that support real-time data processing, allowing for immediate visualization and analysis of depth information. This enables enhanced AI-driven functionalities, ensuring that machines can interact with their environment more effectively. Altek's 3D Imaging Chip is distinguished by its low power consumption and adaptive design, which can be tailored to meet specific requirements of different tech sectors. It supports high-resolution data capture and efficient signal processing, providing clear and detailed visuals that enhance machine learning algorithms. Furthermore, its compatibility with a wide range of software tools makes it a versatile choice for developers looking to integrate advanced 3D imaging into their products.
The Spiking Neural Processor T1 is a neuromorphic microcontroller engineered for always-on sensor applications. It utilizes a spiking neural network engine alongside a RISC-V processor core, creating an ultra-efficient single-chip solution for real-time data processing. With its optimized power consumption, it enables next-generation artificial intelligence and signal processing in small, battery-operated devices. The T1 delivers advanced applications capabilities within a minimal power envelope, making it suitable for use in devices where power and latency are critical factors. The T1 includes a compact, multi-core RISC-V CPU paired with substantial on-chip SRAM, enabling fast and responsive processing of sensor data. By employing the remarkable abilities of spiking neural networks for pattern recognition, it ensures superior power performance on signal-processing tasks. The versatile processor can execute both SNNs and conventional processing tasks, supported by various standard interfaces, thus offering maximum flexibility to developers looking to implement AI features across different devices. Developers can quickly prototype and deploy solutions using the T1's development kit, which includes software for easy integration into existing systems and tools for accurate performance profiling. The development kit supports a variety of sensor interfaces, streamlining the creation of sophisticated sensor applications without the need for extensive power or size trade-offs.
Syntacore's SCR9 processor core is a state-of-the-art, high-performance design targeted at applications requiring extensive data processing across multiple domains. It features a robust 12-stage dual-issue out-of-order pipeline and is Linux-capable. Additionally, the core supports up to 16 cores, offering superior processing power and versatility. This processor includes advanced features such as a VPU (Vector Processing Unit) and hypervisor support, allowing it to manage complex computational tasks efficiently. The SCR9 is particularly well-suited for deployments in enterprise, AI, and telecommunication sectors, reinforcing its status as a key component in next-generation computing solutions.
The Veyron V1 CPU from Ventana Micro Systems is an industry-leading processor designed to deliver unparalleled performance for data-intensive applications. This RISC-V based CPU is crafted to meet the needs of modern data centers and enterprises, offering a sophisticated balance of power efficiency and computational capabilities. The Veyron V1 is engineered to handle complex workloads with its advanced architecture that competes favorably against current industry standards. Incorporating the latest innovations in chiplet technology, the Veyron V1 boasts exceptional scalability, allowing it to seamlessly integrate into diverse computing environments. Whether employed in a high-performance cloud server or an enterprise data center, this CPU is optimized to provide a consistent, robust performance across various applications. Its architecture supports scalable, modular designs, making it suitable for custom SoC implementations, thereby enabling faster time-to-market for new products. The Veyron V1’s compatibility with RISC-V open standards ensures versatility and adaptability, providing enterprises the freedom to innovate without the constraints of proprietary technologies. It includes support for essential system IP and interfaces, facilitating easy integration across different technology platforms. With a focus on extensible instruction sets, the Veyron V1 allows customized performance optimizations tailored to specific user needs, making it an essential tool in the arsenal of modern computing solutions.
The DisplayPort Transmitter from Trilinear Technologies is a sophisticated solution designed for high-performance digital video streaming applications. It is compliant with the latest VESA DisplayPort standards, ensuring compatibility and seamless integration with a wide range of display devices. This transmitter core supports high-resolution video outputs and is equipped with advanced features like adaptive sync and panel refresh options, making it ideal for consumer electronics, automotive displays, and professional AV systems. This IP core provides reliable performance with minimal power consumption, addressing the needs of modern digital ecosystems where energy efficiency is paramount. It includes customizable settings for audio and video synchronization, ensuring optimal output quality and user experience across different devices and configurations. By reducing load on the system processor, the DisplayPort Transmitter guarantees a seamless streaming experience even in high-demand environments. In terms of integration, Trilinear's DisplayPort Transmitter is supported with comprehensive software stacks allowing for easy customization and deployment. This ensures rapid product development cycles and aids developers in managing complex video data streams effectively. The transmitter is particularly optimized for use in embedded systems and consumer devices, offering robust performance capabilities that stand up to rigorous real-time application demands. With a focus on compliance and testing, the DisplayPort Transmitter is pre-tested and proven to work seamlessly with a variety of hardware platforms including FPGA and ASIC technologies. This robustness in design and functionality underlines Trilinear's reputation for delivering reliable, high-quality semiconductor IP solutions that cater to diverse industrial applications.
Dyumnin's RISCV SoC is a versatile platform centered around a 64-bit quad-core server-class RISCV CPU, offering extensive subsystems, including AI/ML, automotive, multimedia, memory, cryptographic, and communication systems. This test chip can be reviewed in an FPGA format, ensuring adaptability and extensive testing possibilities. The AI/ML subsystem is particularly noteworthy due to its custom CPU configuration paired with a tensor flow unit, accelerating AI operations significantly. This adaptability lends itself to innovations in artificial intelligence, setting it apart in the competitive landscape of processors. Additionally, the automotive subsystem caters robustly to the needs of the automotive sector with CAN, CAN-FD, and SafeSPI IPs, all designed to enhance systems connectivity within vehicles. Moreover, the multimedia subsystem boasts a complete range of IPs to support HDMI, Display Port, MIPI, and more, facilitating rich audio and visual experiences across devices.
The RISC-V Hardware-Assisted Verification by Bluespec is a high-performance platform designed for swift and precise verification of RISC-V cores. It supports testing at both the core level (ISA) and system level, accommodating RTOS and Linux-based environments. This solution can verify standard ISA extensions, custom ISA extensions, and integrated accelerators, making it a versatile tool for various verification needs. One of the standout features of this platform is its scalability and accessibility via the AWS cloud, which ensures that resources can be tapped into as needed, enabling efficient verification anytime, anywhere. Such scalability is crucial for teams that require the flexibility to test various designs without being confined to local server limitations. With an emphasis on broad compatibility, the RISC-V Hardware-Assisted Verification platform is ideal for those involved in developing RISC-V based systems. It assists developers in ensuring their designs are accurate and reliable before deployment, reducing errors and speeding up time-to-market.
The iCan PicoPop® is a miniaturized system on module (SOM) based on the Xilinx Zynq UltraScale+ Multi-Processor System-on-Chip (MPSoC). This advanced module is designed to handle sophisticated signal processing tasks, making it particularly suited for aeronautic embedded systems that require high-performance video processing capabilities. The module leverages the powerful architecture of the Zynq MPSoC, providing a robust platform for developing cutting-edge avionics and defense solutions. With its compact form factor, the iCan PicoPop® SOM offers unparalleled flexibility and performance, allowing it to seamlessly integrate into various system architectures. The high level of integration offered by the Zynq UltraScale+ MPSoC aids in simplifying the design process while reducing system latency and power consumption, providing a highly efficient solution for demanding applications. Additionally, the iCan PicoPop® supports advanced functionalities through its integration of programmable logic, multi-core processing, and high-speed connectivity options, making it ideal for developing next-generation applications in video processing and other complex avionics functions. Its modular design also allows for easy customization, enabling developers to tailor the system to meet specific performance and functionality needs, ensuring optimal adaptability for intricate aerospace environments. Overall, the iCan PicoPop® demonstrates a remarkable blend of high-performance computing capabilities and adaptable configurations, making it a valuable asset in the development of high-tech avionics solutions designed to withstand rigorous operational demands in aviation and defense.
The Maverick-2 Intelligent Compute Accelerator (ICA) is a groundbreaking innovation by Next Silicon Ltd. This architecture introduces a novel software-defined approach that adapts in real-time to optimize computational tasks, breaking the traditional constraints of CPUs and GPUs. By dynamically learning and accelerating critical code segments, Maverick-2 ensures enhanced efficiency and performance efficiency for high-performance computing (HPC), artificial intelligence (AI), and vector databases. Designers have developed the Maverick-2 to support a wide range of common programming languages, including C/C++, FORTRAN, OpenMP, and Kokkos, facilitating an effortless porting process. This robust toolchain reduces time-intensive application porting, allowing for a significant cut in development time while maximizing scientific output and insights. Developers can enjoy seamless integration into their existing workflows without needing new proprietary software stacks. A standout feature of this intelligent architecture is its ability to adjust hardware configurations on-the-fly, optimizing power efficiency and overall performance. With an emphasis on sustainable innovation, the Maverick-2 offers a performance-per-watt advantage that exceeds traditional GPU and high-end CPU solutions by over fourfold, making it a cost-effective and environmentally friendly choice for modern data centers and research facilities.
Trilinear Technologies has developed a cutting-edge DisplayPort Receiver that enhances digital connectivity, offering robust video reception capabilities necessary for today's high-definition video systems. Compliant with VESA standards, the receiver supports the latest DisplayPort specifications, effortlessly handling high-bandwidth video data necessary for applications such as ultra-high-definition televisions, professional video wall setups, and complex automotive display systems. The DisplayPort Receiver is designed with advanced features that facilitate seamless video data acquisition and processing, including multi-stream transport capabilities for handling multiple video streams concurrently. This is particularly useful in professional display settings where multiple input sources are needed. The core also incorporates adaptive sync features, which help reduce screen tearing and ensure smooth video playback, enhancing user experience significantly. An important facet of the DisplayPort Receiver is its low latency and high-efficiency operations, crucial for systems requiring real-time data processing. Trilinear's receiver core ensures that video data is processed with minimal delay, maintaining the integrity and fidelity of the original visual content. This makes it a preferred choice for high-performance applications in sectors like gaming, broadcasting, and high-definition video conferencing. To facilitate integration and ease of use, the DisplayPort Receiver is supported by a comprehensive suite of development tools and software packages. This makes the deployment process straightforward, allowing developers to integrate the receiver into both FPGA and ASIC environments with minimal adjustments. Its scalability and flexibility mean it can meet the demands of a wide range of applications, solidifying Trilinear Technologies' position as a leader in the field of semiconductor IP solutions.
The Universal Drive Controller is an advanced solution tailored for motion control applications across a range of motor types, including DC, BLDC, and stepper motors. It offers a comprehensive set of features that allows for independent position and velocity control of multiple motors directly from FPGA platforms. This flexibility makes it ideal for various industrial and commercial applications where precise motor control is paramount. With a focus on enhancing efficiency and performance, this controller simplifies the integration of motor control systems by providing a unified framework. It streamlines the management of complex control loops and ensures that each motor operates under optimal conditions. This results in improved operational stability and precision in movement, which is crucial for applications requiring high levels of accuracy. The design of the Universal Drive Controller is optimized for easy integration and configuration, supporting seamless implementation within existing setups. It promises to cut down development times and reduce complexities associated with traditional motor controller solutions. By utilizing FPGA technology, it offers a scalable and future-proof solution that can accommodate emerging requirements in motor control engineering.
DolphinWare IPs is a versatile portfolio of intellectual property solutions that enable efficient SoC design. This collection includes various control logic components such as FIFO, arbiter, and arithmetic components like math operators and converters. In addition, the logic components span counters, registers, and multiplexers, providing essential functionalities for diverse industrial applications. The IPs in this lineup are meticulously designed to ensure data integrity, supported by robust verification IPs for AXI4, APB, SD4.0, and more. This comprehensive suite meets the stringent demands of modern electronic designs, facilitating seamless integration into existing design paradigms. Beyond their broad functionality, DolphinWare’s offerings are fundamental to applications requiring specific control logic and data integrity solutions, making them indispensable for enterprises looking to modernize or expand their product offerings while ensuring compliance with industry standards.
Gyrus AI's Neural Network Accelerator is specifically crafted to enhance edge computing with its groundbreaking graph processing capabilities. This innovative solution achieves unparalleled efficiency with a performance of 30 trillion operations per second per Watt (TOPS/W). Such efficiency significantly enhances the speed of machine learning operations, minimizing the clock cycles required for tasks, which translates to a 10-30x reduction in clock-cycle count. As a low-power usage configuration, the Neural Network Accelerator ensures reduced energy consumption without compromising computational performance. Designed to offer seamless integration, this accelerator maximizes die area utilization over 80%, ensuring the efficient implementation of diverse model architectures. Its uniqueness lies in its software tools that complement the IP, facilitating the operation of neural networks on the IP with seamless ease. The Neural Network Accelerator is tailored to provide high performance without the trade-offs typically associated with increased power consumption, making it ideal for a variety of edge computing applications. The product serves as a critical enabler for enterprises seeking to implement sophisticated AI solutions at the edge, ensuring that their wide-ranging applications are both efficient and high-functioning. As edge devices increasingly drive innovation across industries, Gyrus AI's solution stands out for its dexterity in supporting complex model structures while conserving power, thereby catering to the modern demands of AI-driven operations.
SystemBIST is a sophisticated, plug-and-play configuration module designed to streamline FPGA configuration and embedded JTAG testing within PCBs. Built on patented architectures, it simplifies the creation of high-quality, self-testable products that can be reconfigured in the field. This vendor-independent device supports extensive compatibility, enabling the configuration of any IEEE 1532 or IEEE 1149.1 compliant FPGA and CPLD in-system. SystemBIST notably improves the efficiency of embedded test processes by repurposing manufacturing JTAG/IEEE 1149.1 based test patterns into the PCB design, providing significant savings on production costs. The SystemBIST architecture not only re-uses existing test scripts but also compresses them into onboard FLASH memory, allowing for fast and reliable PCB testing anywhere. This capability is crucial for modern electronics, where flexibility and security, such as mitigating risks from trojan bitstreams and cloning, are vital considerations. Intellitech's device incorporates AES encryption for secure configurations, ensuring product integrity and protecting against unauthorized cloning. SystemBIST's failsafe update feature allows field updates without erasing the entire FLASH, safeguarding original FPGA designs. With its robust testing and configuration capabilities, SystemBIST paves the way for efficient debugging and maintenance, offering a unified methodology for in-system configuration and test across the entire product lifecycle. It serves as both a debugging tool and an updater, adding value by facilitating anytime and anywhere PCB testing.
The Origin E1 is a neural engine meticulously optimized for always-on applications found in devices like home appliances and smartphones. It excels in scenarios requiring approximately 1 TOPS performance, ideal for cost and area-sensitive applications like security cameras and always-sensing applications. This processor manages to combine power efficiency with high-level performance, ensuring continuous operation on minimal energy.
Avispado is an in-order 64-bit RISC-V core, optimized for high-efficiency and low-power operation, making it an exemplary choice for edge AI and embedded applications. This core excels in environments where energy efficiency is paramount, leveraging its in-order execution pathway while remaining power conscious. Avispado is fitted with RISC-V Vector Specification 1.0, enabling advanced acceleration for AI workloads. Adaptable to multi-core setups, Avispado facilitates multiprocessing and offers compatibility with Linux, ensuring a seamless integration into diverse computational environments. The high bandwidth access enabled by Gazzillion Misses™ technology supports efficient handling of multiple memory requests, thereby enhancing performance. Customization options for Avispado include varied cache sizes and the integration of a branch predictor, ensuring a tailored performance that meets unique computing requirements. Whether applied in IoT contexts, machine learning tasks, or edge computing scenarios, Avispado’s reliable and flexible architecture stands out for its integration and scalability.
The TimbreAI T3 is an ultra-low-power AI engine tailored for audio noise reduction in devices like wireless headsets. Its streamlined architecture is crafted specifically for minimizing power while maintaining high fidelity audio processing. The engine operates at less than 300μW, making it the ideal choice for battery-sensitive applications.
Cobalt is an ultra-low-power GNSS receiver designed specifically for chipset integration to expand the market capabilities of IoT System-on-Chip (SoC) products. This GNSS receiver stands out for its ability to drastically reduce energy consumption while maintaining high performance in geolocation tasks. This makes Cobalt an ideal choice for IoT applications where battery life is critical, such as in wearable technology and remote asset tracking devices. By integrating Cobalt into chipsets, developers can enhance their products with robust and reliable GNSS functionalities without eliminating critical power resources, thus maintaining extended operational periods for their IoT devices. Cobalt's design caters to evolving needs in IoT infrastructures by supporting efficient satellite communication, essential for precise and reliable real-time location tracking. Its inclusion in SoC designs fosters the development of sophisticated IoT products capable of delivering real-time, accurate geolocation data, accelerating the integration of smart technologies across various sectors.
The FortiPKA-RISC-V is a unique public key accelerator that incorporates modular multiplication resistant to both side-channel and fault injection threats. It serves as an efficient coprocessor for RISC-V architectures, enabling secure and quick cryptographic operations while offering a streamlined performance across low-power device applications.
iCEVision facilitates rapid prototyping and evaluation of connectivity features using the Lattice iCE40 UltraPlus FPGA. Designers can take advantage of exposed I/Os for quick implementation and validation of solutions, while enjoying compatibility with common camera interfaces such as ArduCam CSI and PMOD. This flexibility is complemented by software tools such as the Lattice Diamond Programmer and iCEcube2, which allow designers to reprogram the onboard SPI Flash and develop custom solutions. The platform comes preloaded with a bootloader and an RGB demo application, making it quick and easy for users to begin experimenting with their projects. Its design includes features like a 50mmx50mm form factor, LED applications, and multiple connectivity options, ensuring broad usability across various rapid prototyping scenarios. With its user-friendly setup and comprehensive toolkit, iCEVision is perfect for developers who need a streamlined path from initial design to functional prototype, especially in environments where connectivity and sensor integration are key.
The N5186A MXG Vector Signal Generator is a versatile and sophisticated solution designed for generating signals across a comprehensive range of frequencies. Ideal for a wide array of testing scenarios, this signal generator can emulate complex signal environments, which is essential for evaluating device performance under realistic conditions. Its robust design not only enhances reliability but also ensures high precision in measurements, crucial for applications in advanced research and development. This vector signal generator caters to high-performance requirements, offering exceptional performance with its wide bandwidth and flexibility. These attributes make it a preferred choice for professionals involved in designing and testing next-generation wireless communication systems. Its user-friendly interface allows for easy setup and operation, making it suitable even for users who may not have extensive experience in signal generation. Equipped with the latest technology, the N5186A MXG ensures accurate and repeatable results, critically supporting the validation of new protocols and devices. By leveraging this tool, engineers can accelerate the development cycle, reducing the time-to-market for innovative products, and ensuring they comply with industry standards and customer expectations.
Designed for environments requiring extensive processing power, the Origin E8 is suitable for high-demand applications such as data centers and autonomous vehicles. This NPU supports major AI models effectively while minimizing latency and maximizing throughput. Capable of handling up to 128 TOPS, it ensures robust performance with efficient resource management.
Specialty Microcontrollers from Advanced Silicon harness the capabilities of the latest RISC-V architectures for advanced processing tasks. These microcontrollers are particularly suited to applications involving image processing, thanks to built-in coprocessing units that enhance their algorithm execution efficiency. They serve as ideal platforms for sophisticated touch screen interfaces, offering a balance of high performance, reliability, and low power consumption. The integrated features allow for the enhancement of complex user interfaces and their interaction with other system components to improve overall system functionality and user experience.
Origin E2 is devised for applications demanding power and area efficiency, essential for smartphones and other devices. With a focus on maintaining a balance between performance and resource use, it supports a wide range of neural networks and achieves sustainable power efficiencies up to 18 TOPS/W. This makes it a versatile choice for both consumer and industrial use cases.
The RV32EC_P2 Processor Core is a streamlined, 2-stage pipeline RISC-V processor core developed to meet the requirements of compact, power-efficient embedded applications running exclusively on trusted firmware. Engineered for use in both ASIC and FPGA design flows, it supports the RISC-V RV32E base instruction set and is compliant with RISC-V User-Level ISA Version 2.2. Its design includes RVC compressed instructions to minimize code size, along with optional integer multiplication and division instructions ("M" standard extension). A key feature of the RV32EC_P2 Processor Core is its provision for custom, application-specific instruction set extensions, making it particularly suited for digital signal processing tasks. It employs a straightforward machine-mode privileged architecture, ensuring compliance with the RISC-V Privileged Architecture Version 1.10, and offers 20 extended interrupts, along with support for external controllers to handle additional interrupts. Designed to deliver fast interrupt responses, this processor core includes vectored interrupts and clock gating to aid low-power idling, ensuring energy efficiency. It supports tightly-coupled memory interfaces applicable to both ASIC ROM and SRAM or FPGA block memories. Its functionality is enhanced by AHB-Lite or APB interfaces for expanded memory access, and it comes equipped with GNU toolchain and Eclipse support for efficient firmware development.
Atrevido is a versatile 64-bit out-of-order execution RISC-V processor core known for its high performance in demanding AI and HPC applications. The core is capable of handling a wide range of tasks with a design that supports 2/3/4-wide execution paths, ensuring optimal throughput. Included within Atrevido's capabilities are integrated vector and tensor units, which deliver comprehensive acceleration for AI and machine learning tasks without latency penalties. Equipped with Gazzillion Misses™ technology, Atrevido efficiently manages memory bottlenecks, supporting up to 128 simultaneous memory requests. This enhancement is critical for handling large datasets typical in AI and high-performance computing. Designed for Linux environments, it supports multiprocessing with extensive interfaces such as AXI and CHI for high-bandwidth requirements. With customizable elements including vector specifications and cache configurations, Atrevido is engineered for precision and flexibility. Whether you are developing key-value stores, engaging in AI inference, or conducting complex data analysis, Atrevido's robust architecture is designed to provide highly efficient and rapid computational capabilities.
The Origin E6 targets next-generation edge devices requiring sophisticated AI capabilities. It delivers outstanding performance by accommodating a variety of modern AI models, including video, audio, and text-based networks. By optimizing workloads and achieving up to 90% processor utilization, it reduces power consumption and enhances user experience in mobile, automotive, and consumer electronics.
The RecAccel N3000 PCIe is fundamentally designed to revolutionize AI-based recommendation systems. This card is optimized to handle the intensive computations involved in processing large-scale recommendation models, offering speed and accuracy in decision-making processes. With its advanced technology, the RecAccel N3000 PCIe ensures that recommendation engines are capable of delivering results with enhanced precision and at a faster rate, significantly improving user experience and service delivery. Designed with efficiency in mind, the RecAccel N3000 PCIe is a powerful component that helps businesses maximize their operational efficacy. Its integration into data systems supports faster and more reliable recommendation outputs. The card is designed to be highly resilient, adaptable to a variety of workloads, and offers compelling benefits for industries relying heavily on recommendation algorithms to drive user engagement and business growth. This product exemplifies Neuchips’ dedication to providing solutions that align with the contemporary demands of AI-based applications. The RecAccel N3000 PCIe not only supports existing systems but is built to foster adaptation to new developments in AI technology. Its blend of performance, power efficiency, and scalability makes it a standout solution for enterprises aiming to future-proof their recommendation infrastructures.
The RV32IC_P5 Processor Core is a high-performance, 5-stage pipeline RISC-V processor designed to support medium-scale embedded systems that demand elevated performance levels. It features capabilities like caching and support for both trusted firmware and general user applications. Using the RISC-V RV32I base instruction set, this core complies with the RISC-V User-Level ISA V 2.2 and introduces several optional standard extensions. The processor includes "A" standard extensions, which aid in critical section handling in uniprocessor systems, and support for RVC standard compressed instructions to optimize code size. Developed with both machine-mode and user-mode privileged architectures, it ensures direct physical memory access while supporting potential application-specific DSP operations through customizable instruction set extensions. It is equipped with a robust interrupt handling mechanism, including vectoring of interrupts and exceptions delegated to user mode, allowing for expedited response times. Its power efficiency is maintained by a wait-for-interrupt instruction that enables clock gating during low-power idle states, and it interfaces through AHB-Lite paths for extended memory and memory-mapped I/O access.
Panmnesia's PanAccelerator is a high-performance solution crafted to boost the processing power of AI systems. It is tailored for leading-edge machine learning workloads that require high-bandwidth memory expansion and rapid GPU interconnection. This accelerator supports efficient power usage and offers expansive scalability, making it ideal for large-scale AI training environments.
The Low Power Security Engine is designed by Low Power Futures to provide robust security for IoT devices while maintaining minimal power usage. Focusing on compact and comprehensive security capabilities, it supports elliptic-curve based cryptographic algorithms, including ECDHE (Elliptic-Curve Diffie-Hellman) and ECDSA (Elliptic Curve Digital Signature Algorithm). The design is perfect for ensuring secure operations in constrained environments like RFID systems and embedded SIM cards, offering side-channel and timing attack resistance, thus securing sensitive data in demanding applications like IIoT and connected infrastructure.
This networking solution from CetraC endows high-performance capabilities into FPGA and ASIC products, tailored for distributed architectural systems. It is crafted specifically for industries that demand high-speed data transmissions and excellent reliability across their networking infrastructures. The product supports numerous protocols such as TSN, CAN FD, and ARINC429, making it versatile for integration into various high-tech systems needing comprehensive data management and communication structures. The solution also features robust security measures including AES256 encryption to protect data integrity while facilitating seamless protocol conversions to enhance interoperability between various network segments.
**DRV64IMZicsr – 64-bit RISC-V Performance. Designed for Demanding Innovation.** The DRV64IMZicsr is a powerful and versatile 64-bit RISC-V CPU core, built to meet the performance and safety needs of next-generation embedded systems. Featuring the M (Multiply/Divide), Zicsr (Control and Status Registers), and External Debug extensions, this core is engineered to scale—from edge computing to mission-critical applications. As part of the DRVX Core Family, the DRV64IMZicsr embodies DCD’s philosophy of combining open-standard freedom with customizable IP excellence—making it a smart and future-proof alternative to legacy architectures. ✅ Why Choose RISC-V? * No license fees – open-source instruction set means reduced TCO * Unmatched flexibility – tailor the architecture to your specific needs * A global, thriving ecosystem – support from toolchains, OSes, and hardware vendors * Security & longevity – open and verifiable architecture ensures trust and sustainability 🚀 DRV64IMZicsr – Core Advantages: * 64-bit RISC-V ISA with M, Zicsr, and Debug support * Five-stage pipeline, Harvard architecture, and efficient branch prediction * Configurable memory size and allocation for program and data spaces Performance optimized: * **Up to 2.38 CoreMark/MHz** * **Up to 1.17 DMIPS/MHz** * Compact footprint starting from just 17.6k gates * Interface options: AXI, AHB, or native * Compatible with Classical CAN, CAN FD, and CAN XL through additional IPs 🛡️ Safety, Compatibility & Flexibility Built In: * Developed as an ISO 26262 Safety Element out of Context (SEooC) * Technology-agnostic – works seamlessly across all FPGA and ASIC vendors * Expandable with DCD’s IP portfolio: DMA, SPI, UART, I²C, CAN, PWM, and more 🔍 Robust Feature Set for Real Applications: * Full 64-bit processing – ideal for performance-intensive, memory-heavy tasks * M extension enables high-speed multiplication/division via dedicated hardware unit * Zicsr extension gives full access to Control and Status Registers, enabling: * Interrupts and exception handling (per RISC-V Privileged Spec) * Performance counters and timers * JTAG-compatible debug interface – compliant with RISC-V Debug Spec (0.13.2 & 1.0.0) 🧪 Ready for Development & Integration: * Comes with a fully automated testbench * Includes a comprehensive suite of validation tests for smooth SoC integration * Supported by industry-standard tools, ensuring a hassle-free dev experience Whether you’re designing for automotive safety, industrial control, IoT gateways, or AI-enabled edge devices, the DRV64IMZicsr gives you the performance, flexibility, and future-readiness of RISC-V—without compromise. 💡 Build smarter, safer systems—on your terms. 📩 Contact us today at info@dcd.pl to start your next RISC-V-powered project.
DRV32IMZicsr – Scalable RISC-V Power. Tailored for Your Project. Ready for the Future. The DRV32IMZicsr is a high-performance, 32-bit RISC-V processor core, equipped with M (Multiply/Divide), Zicsr (Control and Status Registers), and External Debug support. Built as part of DCD’s latest DRVX Core Family, it delivers the full flexibility, openness, and innovation that RISC-V promises—without locking you into proprietary architectures. ✅ Why RISC-V? RISC-V is a rapidly growing open standard for modern computing—backed by a global ecosystem of developers and vendors. It brings: * Freedom from licensing fees and vendor lock-in * Scalability from embedded to high-performance systems * Customizability with standard and custom instruction sets * Strong toolchain & ecosystem support 🚀 DRV32IMZicsr Highlights: * Five-stage pipeline and Harvard architecture for optimized performance * Configurable memory architecture: size and address allocation tailored to your needs Performance metrics: * **Up to 1.15 DMIPS/MHz** * **Up to 2.36 CoreMark/MHz** * Minimal footprint starting from just 14k gates * Flexible interfaces: Choose from AXI, AHB, or native bus options 🛡️ Designed for Safety & Integration: * Developed as an ISO 26262 Safety Element out of Context (SEooC) * Fully technology-agnostic, compatible with all FPGA and ASIC platforms * Seamless integration with DCD’s rich portfolio of IPs: DMA, SPI, UART, PWM, CAN, and more 🔍 Advanced Feature Set: * 32 general-purpose registers * Support for arithmetic, logic, load/store, conditional and unconditional control flow * M extension enables efficient integer multiplication/division * Zicsr extension provides robust interrupt and exception handling, performance counters, and timers * External Debug via JTAG: compliant with RISC-V Debug Specification 0.13.2 and 1.0.0, compatible with all mainstream tools 🧪 Developer-Ready: * Delivered with a fully automated testbench * Includes a comprehensive validation test suite for smooth integration into your SoC flow Whether you're building for automotive, IoT, consumer electronics, or embedded systems, the DRV32IMZicsr offers a future-ready RISC-V solution—highly configurable, performance-optimized, and backed by DCD’s 25 years of experience. Interested? Let’s build the next generation together. 📩 Contact us at info@dcd.pl
The D68000-CPU32 soft core is binary-compatible with the industry standard 68000's CPU32 version of the 32-bit microcontroller. The D68000-CPU32 has a 16-bit data bus and a 24-bit address data bus, and it is code compatible with the 68000's CPU32 (version of MC68020). The D68000-CPU32 includes an improved instruction set, allowing for higher performance than the standard 68000 core, and a built-in DoCD-BDM debugger interface. It is delivered with a fully automated test bench and a set of tests enabling easy package validation during different stages of the SoC design flow. The D68000-CPU32 is technology-agnostic, ensuring compatibility with all FPGA and ASIC vendors.
The D68HC11F is a synthesizable SOFT Microcontroller IP Core, fully compatible with the Motorola 68HC11F1 industry standard. It can be used as a direct replacement for the 68HC11F1 Microcontrollers. Major peripheral functions are integrated on-chip, including an asynchronous serial communications interface (SCI) and a synchronous serial peripheral interface (SPI). The main 16-bit, free-running timer system includes input capture and output-compare lines, and a real-time interrupt function. An 8-bit pulse accumulator subsystem counts external events or measures external periods. Self-monitoring on-chip circuitry protects the D68HC11F against system errors. The Computer Operating Properly (COP) watchdog system and illegal opcode detection circuit provide extra security features. Two power-saving modes, WAIT and STOP, make the IP core especially attractive for automotive and battery-driven applications. Additionally, the D68HC11F can be equipped with an ADC Controller, offering compatibility with external ADCs. Its customizable nature means it's delivered in configurations tailored to need, avoiding unnecessary features and silicon waste. The D68HC11F also includes a fully automated test bench and comprehensive tests for easy SoC design validation. It supports DCD’s DoCD™, a real-time hardware debugger, for non-intrusive debugging of complete SoCs. This IP Core is technology agnostic, ensuring 100% compatibility with all FPGA and ASIC vendors.
The DP8051 is an ultra-high performance, speed-optimized softcore, of a single-chip 8-bit embedded controller, intended to operate with fast (typically on-chip) and slow (off-chip) memories. The core was designed with a special concern about the performance to power-consumption ratio. This ratio is extended by the PMU – an advanced power management unit. The DP8051 softcore is 100% binary-compatible with the industry standard 8051 8-bit microcontrollers. There are two configurations of the DP8051: Harvard, where internal data and program buses are separated and von Neumann, with a common program and external data bus. The DP8051 has a Pipelined RISC architecture and executes 120-300 million instructions per second. Dhrystone 2.1 benchmark program runs from 11.46 to 15.55 times faster than the original 80C51 at the same frequency. The same C compiler was used for benchmarking of the core vs 80C51, with the same settings. This performance can also be exploited to great advantage in low-power applications, where the core can be clocked over ten times slower than the original implementation, without performance depletion. The DP8051 is delivered with a fully automated test bench and a complete set of tests, allowing easy package validation, at each stage of the SoC design flow. Each of DCD’s 8051 Cores has built-in support for the Hardware Debug System called DoCD™. It is a real-time hardware debugger, which provides debugging capability of the whole System-on-Chip (SoC). Unlike other on-chip debuggers, the DoCD™ provides non-intrusive debugging of a running application. It can halt, run, step into or skip an instruction, and read/write any contents of the microcontroller, including all registers, internal and external program memories, and all SFRs, including user-defined peripherals. ALL DCD’S IP CORES ARE TECHNOLOGY AGNOSTIC, ENSURING 100% COMPATIBILITY WITH ALL FPGA AND ASIC VENDORS.
The Cortex-X custom CPU is part of Arm's strategy to deliver high-performance, tailored processors that meet the demands of next-generation applications. Designed under the Cortex-X Custom Program, this CPU allows for customization beyond the traditional Arm roadmap, enabling partners to deliver ultimate performance tailored to specific use cases. Its performance-first design is evident in its year-on-year performance improvements, making it a cornerstone in devices that require peak CPU capabilities. With compatibility to Arm's Cortex-A CPUs and scalability provided by DynamIQ support, the Cortex-X Custom CPU can be integrated into systems requiring flexible and robust computing solutions. The CPU's architecture supports advanced features to enhance device efficiency and user experience, especially in high-demand environments like mobile gaming and VR/AR applications. The Cortex-X Custom CPU integrates seamlessly into existing and new infrastructures, facilitating targeted market needs with tangible improvements in computational power. Thanks to its ability to achieve notable single-thread performance enhancements, it is a popular choice for flagship smartphones and other high-performance consumer electronics.
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