All IPs > Processor > Coprocessor
In the realm of modern computing, coprocessor semiconductor IPs play a crucial role in augmenting system capabilities. A coprocessor is a supplementary processor that executes specific tasks more efficiently than the primary central processing unit (CPU). These coprocessors are specialized semiconductor IPs utilized in devices requiring enhanced computational power for particular functions such as graphics rendering, encryption, mathematical calculations, and artificial intelligence (AI) processing.
Coprocessors are integral in sectors where high performance and efficiency are paramount. For instance, in the gaming industry, a graphics processing unit (GPU) acts as a coprocessor to handle the high demand for rendering visuals, thus alleviating the burden from the CPU. Similarly, AI accelerators in smartphones and servers offload intensive AI computation tasks to speed up processing while conserving power.
You will find various coprocessor semiconductor IP products geared toward enhancing computational specialization. These include digital signal processors (DSPs) for processing real-time audio and video signals and hardware encryption coprocessors for securing data transactions. With the rise in machine learning applications, tensor processing units (TPUs) have become invaluable, offering massively parallel computing to efficiently manage AI workloads.
By incorporating these coprocessor semiconductor IPs into a system design, manufacturers can achieve remarkable improvements in speed, power efficiency, and processing power. This enables the development of cutting-edge technology products across a range of fields from personal electronics to autonomous vehicles, ensuring optimal performance in specialized computing tasks.
Akida Neural Processor IP is a groundbreaking component offering a self-contained AI processing solution capable of locally executing AI/ML workloads without reliance on external systems. This IP's configurability allows it to be tailored to various applications, emphasizing space-efficient and power-conscious designs. Supporting both convolutional and fully-connected layers, along with multiple quantization formats, it addresses the data movement challenge inherent in AI, significantly curtailing power usage while maintaining high throughput rates. Akida is designed for deployment scalability, supporting as little as two nodes up to extensive networks where complex models can thrive.
MetaTF is BrainChip's machine learning framework for developing systems on the Akida neural processor. Designed to aid in creating, training, and testing neural networks, MetaTF integrates seamlessly with TensorFlow models. Its key feature is the ability to convert CNN models to Spiking Neural Networks (SNN), facilitating low-latency, low-power operations suited for edge environments. By utilizing Python scripting and tools, MetaTF simplifies model conversion and optimization, delivering automatic CNN to SNN transitions without needing to learn new frameworks. MetaTF also includes various development tools, encompassing runtime simulation and robust testing environments.
RaiderChip's GenAI v1 is a pioneering hardware-based generative AI accelerator, designed to perform local inference at the Edge. This technology integrates optimally with on-premises servers and embedded devices, offering substantial benefits in privacy, performance, and energy efficiency over traditional hybrid AI solutions. The design of the GenAI v1 NPU streamlines the process of executing large language models by embedding them directly onto the hardware, eliminating the need for external components like CPUs or internet connections. With its ability to support complex models such as the Llama 3.2 with 4-bit quantization on LPDDR4 memory, the GenAI v1 achieves unprecedented efficiency in AI token processing, coupled with energy savings and reduced latency. What sets GenAI v1 apart is its scalability and cost-effectiveness, significantly outperforming competitive solutions such as Intel Gaudi 2, Nvidia's cloud GPUs, and Google's cloud TPUs in terms of memory efficiency. This solution maximizes the number of tokens generated per unit of memory bandwidth, thus addressing one of the primary limitations in generative AI workflow. Furthermore, the adept memory usage of GenAI v1 reduces the dependency on costly memory types like HBM, opening the door to more affordable alternatives without diminishing processing capabilities. With a target-agnostic approach, RaiderChip ensures the GenAI v1 can be adapted to various FPGAs and ASICs, offering configuration flexibility that allows users to balance performance with hardware costs. Its compatibility with a wide range of transformers-based models, including proprietary modifications, ensures GenAI v1's robust placement across sectors requiring high-speed processing, like finance, medical diagnostics, and autonomous systems. RaiderChip's innovation with GenAI v1 focuses on supporting both vanilla and quantized AI models, ensuring high computation speeds necessary for real-time applications without compromising accuracy. This capability underpins their strategic vision of enabling versatile and sustainable AI solutions across industries. By prioritizing integration ease and operational independence, RaiderChip provides a tangible edge in applying generative AI effectively and widely.
Designed for entry-level server-class applications, the SCR9 is a 64-bit RISC-V processor core that comes equipped with cutting-edge features, such as an out-of-order superscalar pipeline, making it apt for processing-intensive environments. It supports both single and double-precision floating-point operations adhering to IEEE standards, which ensure precise computation results. This processor core is tailored for high-performance computing needs, with a focus on AI and ML, as well as conventional data processing tasks. It integrates an advanced interrupt system featuring APLIC configurations, enabling responsive operations even under heavy workloads. SCR9 supports up to 16 cores in a multi-cluster arrangement, each utilizing coherent multi-level caches to maintain rapid data processing and management. The comprehensive development package for SCR9 includes ready-to-deploy toolchains and simulators that expedite software development, particularly within Linux environments. The core is well-suited for deployment in entry-level server markets and data-intensive applications, with robust support for virtualization and heterogeneous architectures.
BrainChip's Akida IP is an innovative neuromorphic processor that emulates the human brain's functionalities to analyze essential sensor inputs at the acquisition point. By maintaining AI/ML processes on-chip, Akida IP minimizes cloud dependency, reducing latency and enhancing data privacy. The scalable architecture supports up to 256 nodes interconnected over a mesh network, each node equipped with configurable Neural Network Layer Engines (NPEs). This event-based processor leverages data sparsity to decrease operational requirements significantly, which in turn improves performance and energy efficiency. With robust customization and the ability to perform on-chip learning, Akida IP adeptly supports a wide range of edge AI applications while maintaining a small silicon footprint.
The xcore.ai platform from XMOS is engineered to revolutionize the scope of intelligent IoT by offering a powerful yet cost-efficient solution that combines high-performance AI processing with flexible I/O and DSP capabilities. At its heart, xcore.ai boasts a multi-threaded architecture with 16 logical cores divided across two processor tiles, each equipped with substantial SRAM and a vector processing unit. This setup ensures seamless execution of integer and floating-point operations while facilitating high-speed communication between multiple xcore.ai systems, allowing for scalable deployments in varied applications. One of the standout features of xcore.ai is its software-defined I/O, enabling deterministic processing and precise timing accuracy, which is crucial for time-sensitive applications. It integrates embedded PHYs for various interfaces such as MIPI, USB, and LPDDR, enhancing its adaptability in meeting custom application needs. The device's clock frequency can be adjusted to optimize power consumption, affirming its cost-effectiveness for IoT solutions demanding high efficiency. The platform's DSP and AI performances are equally impressive. The 32-bit floating-point pipeline can deliver up to 1600 MFLOPS with additional block floating point capabilities, accommodating complex arithmetic computations and FFT operations essential for audio and vision processing. Its AI performance reaches peaks of 51.2 GMACC/s for 8-bit operations, maintaining substantial throughput even under intensive AI workloads, making xcore.ai an ideal candidate for AI-enhanced IoT device creation.
The Veyron V1 CPU is designed to meet the demanding needs of data center workloads. Optimized for robust performance and efficiency, it handles a variety of tasks with precision. Utilizing RISC-V open architecture, the Veyron V1 is easily integrated into custom high-performance solutions. It aims to support the next-generation data center architectures, promising seamless scalability for various applications. The CPU is crafted to compete effectively against ARM and x86 data center CPUs, providing the same class-leading performance with added flexibility for bespoke integrations.
The 3D Imaging Chip developed by Altek Corporation exemplifies innovation in depth sensing technology. Delving into this field for many years, Altek provides a cutting-edge module equipped for varied needs, from surveillance devices to transport robotics. This technology enhances the accuracy of recognition capabilities, paving the way for holistic hardware and software solutions from modules to chips. Altek's 3D imaging solutions are optimal for scenarios where precise distance measurement and object identification are requisite, demonstrating robustness across medium to long-range applications. As these systems mature, they continually improve the precision of spatial recognition, positioning Altek at the forefront of depth sensing innovation.
The DisplayPort Transmitter is a highly advanced solution designed to seamlessly transmit high-definition audio and video data between devices. It adheres to the latest VESA standards, ensuring it can handle DisplayPort 1.4 and 2.1 specifications with ease. The transmitter is engineered to support a plethora of audio interfaces including I2S, SPDIF, and DMA, making it highly adaptable to a wide range of consumer and professional audio-visual equipment. With features focused on AV sync and timing recovery, it ensures smooth and uninterrupted data flow even in the most demanding applications. This transmitter is particularly beneficial for those wishing to integrate top-of-the-line audio and video synchronization within their projects, offering customizable sound settings that can accommodate unique user requirements. It's robust enough to be used across industry sectors, from high-end consumer electronics like gaming consoles and home theater systems to professional equipment used in broadcast and video wall displays. Moreover, the DisplayPort Transmitter's architecture facilitates seamless integration into existing FPGA and ASIC systems without a hitch in performance. Comprehensive compliance testing ensures that it is compatible with a wide base of devices and technologies, making it a dependable choice for developers looking to provide comprehensive DisplayPort solutions. Whether it's enhancing consumer electronics or powering complex industry-specific systems, the DisplayPort Transmitter is built to deliver exemplary performance.
The GenAI v1-Q from RaiderChip brings forth a specialized focus on quantized AI operations, reducing memory requirements significantly while maintaining impressive precision and speed. This innovative accelerator is engineered to execute large language models in real-time, utilizing advanced quantization techniques such as Q4_K and Q5_K, thereby enhancing AI inference efficiency especially in memory-constrained environments. By offering a 276% boost in processing speed alongside a 75% reduction in memory footprint, GenAI v1-Q empowers developers to integrate advanced AI capabilities into smaller, less powerful devices without sacrificing operational quality. This makes it particularly advantageous for applications demanding swift response times and low latency, including real-time translation, autonomous navigation, and responsive customer interactions. The GenAI v1-Q diverges from conventional AI solutions by functioning independently, free from external network or cloud auxiliaries. Its design harmonizes superior computational performance with scalability, allowing seamless adaptation across variegated hardware platforms including FPGAs and ASIC implementations. This flexibility is crucial for tailoring performance parameters like model scale, inference velocity, and power consumption to meet exacting user specifications effectively. RaiderChip's GenAI v1-Q addresses crucial AI industry needs with its ability to manage multiple transformer-based models and confidential data securely on-premises. This opens doors for its application in sensitive areas such as defense, healthcare, and financial services, where confidentiality and rapid processing are paramount. With GenAI v1-Q, RaiderChip underscores its commitment to advancing AI solutions that are both environmentally sustainable and economically viable.
DolphinWare IPs is a versatile portfolio of intellectual property solutions that enable efficient SoC design. This collection includes various control logic components such as FIFO, arbiter, and arithmetic components like math operators and converters. In addition, the logic components span counters, registers, and multiplexers, providing essential functionalities for diverse industrial applications. The IPs in this lineup are meticulously designed to ensure data integrity, supported by robust verification IPs for AXI4, APB, SD4.0, and more. This comprehensive suite meets the stringent demands of modern electronic designs, facilitating seamless integration into existing design paradigms. Beyond their broad functionality, DolphinWare’s offerings are fundamental to applications requiring specific control logic and data integrity solutions, making them indispensable for enterprises looking to modernize or expand their product offerings while ensuring compliance with industry standards.
The RISC-V Hardware-Assisted Verification by Bluespec is designed to expedite the verification process for RISC-V cores. This platform supports both ISA and system-level testing, adding robust features such as verifying standard and custom ISA extensions along with accelerators. Moreover, it offers scalable access through the AWS cloud, making verification available anytime and anywhere. This tool aligns with the needs of modern developers, ensuring thorough testing within a flexible and accessible framework.
The DisplayPort Receiver is an essential component for receiving and interpreting high-quality audio and video data streams from a DisplayPort source. Compatible with the latest VESA DisplayPort standards, this receiver is built to handle both screen and audio signals with precision and minimal latency. It integrates sophisticated timing recovery features and boasts compliance with I2S and SPDIF audio protocols, ensuring that it remains versatile across different devices and applications. This receiver is designed to serve industries such as consumer electronics and professional video production, where reliability in signal reception and minimal downtime are crucial. Its capability to work seamlessly with multiple interfaces makes it a versatile asset for developers aiming to build robust multimedia systems, whether it be digital televisions, gaming devices, or large-scale video walls. Equipped to sync efficiently with various compilers on architectures like x86 and ARM, it guarantees that integration is both smooth and effective, validating its potential as a component for high-performance SoCs and FPGAs. The DisplayPort Receiver stands out with its real-time performance capabilities and ensures that the final output maintains high fidelity, catering to sectors that require uncompromised audio-visual quality.
The Spiking Neural Processor T1 is an innovative ultra-low power microcontroller designed for always-on sensing applications, bringing intelligence directly to the sensor edge. This processor utilizes the processing power of spiking neural networks, combined with a nimble RISC-V processor core, to form a singular chip solution. Its design supports next-generation AI and signal processing capabilities, all while operating within a very narrow power envelope, crucial for battery-powered and latency-sensitive devices. This microcontroller's architecture supports advanced on-chip signal processing capabilities that include both Spiking Neural Networks (SNNs) and Deep Neural Networks (DNNs). These processing capabilities enable rapid pattern recognition and data processing similar to how the human brain functions. Notably, it operates efficiently under sub-milliwatt power consumption and offers fast response times, making it an ideal choice for devices such as wearables and other portable electronics that require continuous operation without significant energy draw. The T1 is also equipped with diverse interface options, such as QSPI, I2C, UART, JTAG, GPIO, and a front-end ADC, contained within a compact 2.16mm x 3mm, 35-pin WLCSP package. The device boosts applications by enabling them to execute with incredible efficiency and minimal power, allowing for direct connection and interaction with multiple sensor types, including audio and image sensors, radar, and inertial units for comprehensive data analysis and interaction.
PACE, or Photonic Arithmetic Computing Engine, represents a significant leap forward in computing by using optical components to perform mathematical operations. This breakthrough allows for speed and efficiency improvements that are hard to replicate with traditional electronic designs. The PACE engine is engineered to accelerate the execution of complex algorithms, essential for high-performance applications such as artificial intelligence and large-scale data processing. With its ability to process computations at the speed of light, it opens new avenues for ultra-fast data analysis, making it a pivotal tool for industries relying on rapid data processing and intelligence. Emphasizing low energy consumption, PACE leverages the inherent energy efficiency of photonic processes, minimizing the power requirements compared to electronic counterparts. This feature is crucial for sustainability, reducing the overall energy footprint of data centers and large computing facilities. The engine's design is not only focused on speed but also on operational stability, ensuring consistent performance under intensive computational loads. Integration with existing systems is seamless, as PACE is compatible with current technological infrastructures. This compatibility ensures that businesses can adopt this advanced technology with minimal disruption, enhancing their computational capabilities without the need for extensive overhauls. The photonic nature of the PACE engine ensures future scalability, aligning with the evolving demands of data-driven industries.
The RV32EC_P2 Processor Core is a compact, high-efficiency RISC-V processor designed for low-power, small-scale embedded applications. Featuring a 2-stage pipeline architecture, it efficiently executes trusted firmware. It supports the RISC-V RV32E base instruction set, complemented by compression and optional integer multiplication instructions, greatly optimizing code size and runtime efficiency. This processor accommodates both ASIC and FPGA workflows, offering tightly-coupled memory interfaces for robust design flexibility. With a simple machine-mode architecture, the RV32EC_P2 ensures swift data access. It boasts extended compatibility with AHB-Lite and APB interfaces, allowing seamless interaction with memory and I/O peripherals. Designed for enhanced power management, it features an interrupt system and clock-gating abilities, effectively minimizing idle power consumption. Developers can benefit from its comprehensive toolchain support, ensuring smooth firmware and virtual prototype development through platforms such as the ASTC VLAB. Further distinguished by its vectored interrupt system and support for application-specific instruction sets, the RV32EC_P2 is adaptable to various embedded applications. Enhancements include wait-for-interrupt commands for reduced power usage during inactivity and multiple timer interfaces. This versatility, along with integrated GNU and Eclipse tools, makes the RV32EC_P2 a prime choice for efficient, low-power technology integrations.
The ONNC Calibrator is engineered to ensure high precision in AI System-on-Chips using post-training quantization (PTQ) techniques. This tool enables architecture-aware quantization, which helps maintain 99.99% precision even with fixed-point architecture, such as INT8. Designed for diverse heterogeneous multicore setups, it supports multiple engines within a single chip architecture and employs rich entropy calculation techniques. A major advantage of the ONNC Calibrator is its efficiency; it significantly reduces the time required for quantization, taking only seconds to process standard computer vision models. Unlike re-training methods, PTQ is non-intrusive, maintains network topology, and adapts based on input distribution to provide quick and precise quantization suitable for modern neural network frameworks such as ONNX and TensorFlow. Furthermore, the Calibrator's internal precision simulator uses hardware control registers to maintain precision, demonstrating less than 1% precision drop in most computer vision models. It adapts flexibly to various hardware through its architecture-aware algorithms, making it a powerful tool for maintaining the high performance of AI systems.
iCEVision facilitates rapid prototyping and evaluation of connectivity features using the Lattice iCE40 UltraPlus FPGA. Designers can take advantage of exposed I/Os for quick implementation and validation of solutions, while enjoying compatibility with common camera interfaces such as ArduCam CSI and PMOD. This flexibility is complemented by software tools such as the Lattice Diamond Programmer and iCEcube2, which allow designers to reprogram the onboard SPI Flash and develop custom solutions. The platform comes preloaded with a bootloader and an RGB demo application, making it quick and easy for users to begin experimenting with their projects. Its design includes features like a 50mmx50mm form factor, LED applications, and multiple connectivity options, ensuring broad usability across various rapid prototyping scenarios. With its user-friendly setup and comprehensive toolkit, iCEVision is perfect for developers who need a streamlined path from initial design to functional prototype, especially in environments where connectivity and sensor integration are key.
The RV32IC_P5 Processor Core from IQonIC Works is designed for medium-scale embedded applications requiring higher performance and enhanced processing capabilities. This 5-stage pipeline processor supports the RISC-V RV32I base instruction set, alongside standard extension instructions such as 'A' for atomic operations, boosting system efficiency. Its ability to run a mix of trusted firmware and user applications allows for diverse operational integration. Supporting both ASIC and FPGA design flows, the RV32IC_P5 incorporates advanced memory interfaces, offering optional instruction and write-back data caches for improved performance and adaptability. It features a tightly-coupled scratchpad memory architecture, ensuring efficient data handling and reduced latency. The processor's architecture also incorporates AHB-Lite interfaces and optional physical memory protections for robust security management. With a vectored interrupt system and support for platform-specific instruction extensions, the RV32IC_P5 provides tailored options for DSP operations. Its toolchain support includes GNU and Eclipse environments, affording developers a streamlined path from concept to execution. The RV32IC_P5 demonstrates a firm focus on power efficiency and enhanced processing capabilities, making it ideal for complex applications demanding reliable processing power and flexibility.
Cobalt is Ubiscale's specialized GNSS receiver, designed for ultra-low-power consumption, making it ideal for integration into IoT systems on chip. This advanced GNSS receiver broadens the market potential of IoT devices by enabling cost-effective and power-efficient GNSS functionalities. It's particularly well-suited for systems constrained by size and power where GNSS is necessary. Engineered with embedded processing and optional cloud assistance, Cobalt optimizes power usage and maintains exceptional positioning sensitivity. It supports constellations such as Galileo/GPS/Beidou and provides robust standalone as well as cloud-assisted positioning capabilities, which cater to diverse application requirements. Cobalt is developed in partnership with CEVA DSP and benefits from the European Space Program's support, illustrating its integration into high-standard European technology initiatives. Its design allows for optimal use in massive-market applications like logistics and mobility, ensuring high precision despite challenging environmental conditions. The Cobalt GNSS Receiver allows for shared resources with modem functionalities and operates efficiently in the same frequency bands as older GPS modules, enhancing its utility without requiring additional infrastructure complexities.
The Origami Programmer is a sophisticated configuration tool for Menta’s eFPGA architecture. This software stands out for delivering an easy-to-use interface, which simplifies the complex tasks of synthesis, place-and-route, and static timing analysis. Designed to optimize RTL specifically for the Menta eFPGA, Origami Programmer enables designers to bypass the need for additional FPGA configuration tools. Within its intuitive environment, users can benefit from a range of functionalities, such as an embedded Verific parser for synthesizing designs written in VHDL, Verilog, or SystemVerilog. The tool provides comprehensive analysis capabilities, including complete path and setup/hold reports, ensuring thorough insights into the design's performance metrics. Aimed at improving the design process efficiency, Origami Programmer supports various technology nodes and libraries, permitting performance estimations and resources optimization directly. This seamless integration and the ability to adapt configurations efficiently make Origami Programmer an indispensable asset in eFPGA design and implementation.
Crafted to support IEEE 754-2008 standards, the eSi-Floating Point libraries are capable of half, single, and double-precision operations. Performing efficiently across diverse arithmetic operations, these cores feature capabilities like rounding, exception handling, and support for non-standard numbers like infinities and NaNs. The pipelined structure of these cores allows the production of a result every clock cycle, balancing frequency against operational latency. This precision and versatility make them crucial for high-demand applications such as DSP and computing tasks, offering flexibility that spans ASIC and FPGA implementations.
Advanced Silicon's specialty microcontrollers are tailored to offer cutting-edge solutions for complex image processing tasks. These microcontrollers are built using the latest RISC-V architectures, integrated with advanced coprocessing capabilities, enabling them to handle intricate algorithms efficiently. With a focus on delivering high-speed processing for touchscreen interface management, these microcontrollers are indispensable in modern large-format display systems. They incorporate sophisticated machine learning algorithms within the touch firmware, empowering them to interpret varied user gestures and inputs with high accuracy, supporting interactive touch interfaces across diverse operational environments. The specialization extends to integrating seamlessly with proprietary technologies like Advanced Silicon’s Tactors™ for enhanced touch functionality on glass surfaces, addressing demanding user interface challenges with improved reliability, performance, and user experience.
The Maverick-2 Intelligent Compute Accelerator represents a revolutionary advancement in the realm of high-performance computing. It leverages an innovative intelligent compute architecture to dynamically adjust its configuration, enhancing efficiency for diverse workloads such as HPC and AI tasks. This adaptive technology offers unmatched scalability and performance, crucial for computational tasks requiring real-time data processing and optimization. The architecture redefines traditional computing paradigms by integrating software-defined hardware with real-time adaptability, ensuring the system can fluidly cater to the evolving demands of myriad computational fields. This capability renders extensive application porting unnecessary, facilitating a seamless development process and rapid deployment of applications without the typical burdens. With native support for popular programming languages, including C/C++, FORTRAN, and tools like OpenMP and Kokkos, Maverick-2 offers straightforward integration and development, saving valuable time and resources in code migration. Its versatility extends to supporting cutting-edge AI frameworks and GPU languages like CUDA, making it a robust solution for complex data-driven environments.
Menta’s Adaptive Digital Signal Processor (DSP) is tailored for managing and optimizing signal processing tasks within embedded systems. This IP is ideal for applications demanding high processing performance without compromising energy consumption or space. Utilizing Menta’s standard-cell approach, this DSP ensures ease of integration across various process nodes with high efficiency. Integrated with customizable algorithms and interfaces, Menta’s DSP provides engineers the flexibility to implement specific processing tasks tailored to their applications. This adaptability is crucial for areas like real-time data analysis and machine learning, where rapid response and prediction accuracy are essential. By leveraging the advantages of Menta’s eFPGA base, such processors offer exemplary processing speed, reduced latency, and energy-efficient operation. These attributes significantly contribute to optimizing applications across sectors including automotive, telecommunications, and portable electronics, making Menta’s DSP a standout choice for developers seeking performance and innovation.
The Neural Network Accelerator offered by Gyrus AI is a high-performance solution designed to enhance computational efficiency for edge-based AI applications. Utilizing native graph processing capabilities, this accelerator is optimized for implementing neural networks, significantly boosting inference speeds while maintaining low power consumption. Its architectural design allows for 30 TOPS/W, making it ideal for applications where energy efficiency is as critical as performance. Gyrus AI's Neural Network Accelerator significantly reduces the overheads involved in neural network computations by running operations at 10 to 30 times fewer clock cycles. This reduction leads to faster processing times and, consequently, more efficient data handling across various AI models. Furthermore, the low memory footprint ensures that the device runs on a low-power configuration, enabling extended use in edge computing scenarios without the need for excessive energy resources. The flexibility of this accelerator extends to its adaptability, supporting a broad spectrum of model types with over 80% utilization of the die area. This capability not only maximizes the hardware efficiency but also ensures consistent performance across diverse neural network structures and use cases. Gyrus AI's Neural Network Accelerator is devoid of the typical compromise between power and performance, achieving optimal results for various edge computing applications.
Specially designed for accelerating AI recommendation systems, the RecAccel N3000 PCIe card offers exceptional performance in handling data-intensive AI workloads. It stands out due to its advanced architecture, which allows for high efficiency and fast processing speeds in recommendation tasks. The PCIe card is optimized to interact with existing infrastructures, providing a straightforward solution for enterprises looking to enhance their AI capabilities without significant investments in new hardware. This product excels in performance metrics, offering up to a million DLRM inferences per Joule, which makes it highly power-efficient and cost-effective. Moreover, the RecAccel N3000 PCIe ensures compatibility with prevailing AI frameworks, thus allowing users to upgrade their systems seamlessly. This compatibility, combined with power efficiency and high performance, makes it a preferred choice for businesses that require reliable AI recommendations capabilities.
The RecAccel AI Platform is a cutting-edge computing solution tailored for high-accuracy AI applications. Engineered for environments that desperately require precision and speed, this platform stands out with its ability to handle complex AI tasks with remarkable efficiency. Its architecture is calibrated to support seamless integration, ensuring that enterprises can adopt AI solutions without facing significant system overhauls. This platform is equipped to maintain crucial accuracy levels across intensive workloads, making it indispensable in fields where precision cannot be compromised. By harnessing significant computational power with energy-saving capabilities, the RecAccel AI Platform helps businesses minimize costs while maximizing performance. This blend of power efficiency and high-performance computing positions the RecAccel AI Platform as a desirable choice for organizations aiming to harness the full potential of AI technology.
Wasiela’s Application Specific Instruction Set Processors (ASIPs) provide tailored solutions for specific applications, offering an architecture that is highly customizable and power-efficient. These specialized processors are designed to meet the needs of diverse applications, providing a flexible and programmable hardware acceleration option. The ASIPs are particularly suited for environments where standard processors may not meet the stringent power and performance requirements needed in today's fast-evolving tech landscape. With an instruction set tailored uniquely for each application, these processors allow for significant improvements in both processing efficiency and energy consumption. Each ASIP is equipped to handle complex tasks specific to the desired application, making them an integral part of modern systems that require both customization and scalability. Wasiela’s ASIPs stand out as indispensable tools for developers aiming to maximize system performance while minimizing associated costs and energy usage.
The VE1210 Sonar IC is part of VivEng's specialized family developed for air sonar systems, enabling precise short-range distance measurements and proximity sensing applications. Its advanced design drives an ultrasonic piezoelectric transmitter to emit sound waves and utilize the reflected echoes for object detection. Providing analog output through a flexible 3-wire interface and programmable gain in EEPROM, the VE1210 caters to various industrial and automotive applications, offering robust performance even in challenging environments.
The VE1214 Sonar IC stands as a key component in VivEng’s air sonar system solutions, specifically tailored for proximity sensing and short-range distance measurements. Featuring a 2-wire interface with pulse-width encoded digital output, this IC facilitates dynamic gain adjustments crucial for detecting weaker echoes. Adaptable across diverse sectors such as automotive and security, it ensures high precision and reliability in varying conditions.
The I3C Host/Device Dual Role Controller IP provides the flexibility to operate as either a host or a device within an I3C network. Designed to support the latest MIPI I3C specifications, this IP allows devices to dynamically switch roles based on the system configuration and needs. Its enhanced communication protocol ensures efficient data transfers, lower power consumption, and support for a wide range of peripheral devices. The controller is highly suitable for applications in mobile, IoT, and automotive industries, providing designers with a versatile tool to address the growing demand for advanced I3C solutions.
VivEng’s VE1212 Sonar IC, optimized for air sonar applications, enhances distance measurement and proximity sensing with its efficient ultrasonic wave emission mechanism. Equipped with a 3-wire interface and programmable EEPROM for gain adjustments, it provides synchronized analog output. This IC is well-suited for applications spanning industrial, automotive, and robotics sectors, offering customized gain configurations for improved detection accuracy.
Truechip’s NoC Mesh Silicon IP is engineered to enhance system-on-chip (SoC) communication by implementing a mesh network architecture. This IP facilitates efficient data management and transfer across multiple network nodes, supporting extensive scalability for complex SoC designs. By adopting a mesh topology, it offers robust interconnectivity between processors, memory, and peripherals, ensuring optimal performance even as system complexity increases. The mesh architecture provides high bandwidth and low-latency communication pathways, ideal for applications requiring strenuous data traffic management. It efficiently balances loads across nodes, enabling seamless data flow without congestion, thereby optimizing overall network throughput. The mesh network supports various protocol interfaces, enabling versatile integration with diverse SOC components. Equipped with advanced debugging and monitoring tools, Truechip's NoC Mesh Silicon IP ensures reliability and predictability in system operations. Its configurability allows engineers to customize routes and manage power efficiency dynamically, adapting to performance needs and ensuring energy saving. This IP is indispensable for demanding applications that require high levels of reliability, scalability, and performance in their interconnect solutions.
The NoC Crossbar Silicon IP by Truechip offers a robust solution for enhancing the communication fabric of a system on chip (SoC) through a crossbar architecture. This IP is designed to support a variety of connected master and slave nodes, ensuring efficient data routing across the network. It effortlessly handles multiple data streams and different protocol requirements at each port, thanks to its flexible configuration options. The crossbar IP features programmable registers, which help dynamically adjust operation to meet varying data loads and processing requirements. Integration into SOC environments is streamlined through a highly customizable framework that accommodates diverse communication standards and protocols. This makes it particularly suited for scenarios requiring intricate data path management and intricate synchronization between different system components. Advanced features such as port prioritization and physical address conversion enhance network communication efficiency, supporting high-speed data transfer while maintaining data integrity. The inclusion of comprehensive debug features and scenarios allows thorough testing and validation to ensure seamless operation under different conditions and workloads. Overall, Truechip's NoC Crossbar IP boosts system performance with its optimized routing and communication capabilities within SoC environments.
The NoC Coherent Crossbar Silicon IP from Truechip provides a sophisticated solution for interconnectivity within a System on Chip (SoC) through a coherent crossbar architecture. Designed for efficiency and flexibility, this IP supports coherent communication pathways by maintaining data consistency across various processing units, an essential feature for multi-core systems. Incorporating advanced coherence management functionalities, the crossbar IP ensures that data operations remain consistent across the different nodes, reducing latency and improving throughput. This is crucial for systems that perform complex computations and require stringent data synchronization and communication between processors. The crossbar design streamlines integration in SoCs while offering robust support for different protocol standards. Truechip's solution is equipped with debugging and monitoring features, aiding in the rapid identification and correction of system issues. The ability to prioritize ports and seamlessly convert physical addresses enhances processing performance by optimizing data traffic flow. With a focus on ensuring data integrity and lowering operational costs, this IP is tailored for high-performance multi-core systems demanding tight data coherence and reliability.
The Complex DSP Engine provided by IPCoreWorx incorporates advanced digital signal processing with a robust architecture designed to optimize performance. It is delivered as a netlist or synthesizable RTL source code in VHDL, complete with a comprehensive verification test bench and vectors also in VHDL. The package includes detailed integration documentation and user guides to ensure that developers can effectively implement the engine into their systems. This DSP Engine is particularly adept at handling complex computational tasks, offering significant enhancements in processing speed and efficiency.
DRV32IMZicsr – Scalable RISC-V Power. Tailored for Your Project. Ready for the Future. The DRV32IMZicsr is a high-performance, 32-bit RISC-V processor core, equipped with M (Multiply/Divide), Zicsr (Control and Status Registers), and External Debug support. Built as part of DCD’s latest DRVX Core Family, it delivers the full flexibility, openness, and innovation that RISC-V promises—without locking you into proprietary architectures. ✅ Why RISC-V? RISC-V is a rapidly growing open standard for modern computing—backed by a global ecosystem of developers and vendors. It brings: * Freedom from licensing fees and vendor lock-in * Scalability from embedded to high-performance systems * Customizability with standard and custom instruction sets * Strong toolchain & ecosystem support 🚀 DRV32IMZicsr Highlights: * Five-stage pipeline and Harvard architecture for optimized performance * Configurable memory architecture: size and address allocation tailored to your needs Performance metrics: * **Up to 1.15 DMIPS/MHz** * **Up to 2.36 CoreMark/MHz** * Minimal footprint starting from just 14k gates * Flexible interfaces: Choose from AXI, AHB, or native bus options 🛡️ Designed for Safety & Integration: * Developed as an ISO 26262 Safety Element out of Context (SEooC) * Fully technology-agnostic, compatible with all FPGA and ASIC platforms * Seamless integration with DCD’s rich portfolio of IPs: DMA, SPI, UART, PWM, CAN, and more 🔍 Advanced Feature Set: * 32 general-purpose registers * Support for arithmetic, logic, load/store, conditional and unconditional control flow * M extension enables efficient integer multiplication/division * Zicsr extension provides robust interrupt and exception handling, performance counters, and timers * External Debug via JTAG: compliant with RISC-V Debug Specification 0.13.2 and 1.0.0, compatible with all mainstream tools 🧪 Developer-Ready: * Delivered with a fully automated testbench * Includes a comprehensive validation test suite for smooth integration into your SoC flow Whether you're building for automotive, IoT, consumer electronics, or embedded systems, the DRV32IMZicsr offers a future-ready RISC-V solution—highly configurable, performance-optimized, and backed by DCD’s 25 years of experience. Interested? Let’s build the next generation together. 📩 Contact us at info@dcd.pl
**DRV64IMZicsr – 64-bit RISC-V Performance. Designed for Demanding Innovation.** The DRV64IMZicsr is a powerful and versatile 64-bit RISC-V CPU core, built to meet the performance and safety needs of next-generation embedded systems. Featuring the M (Multiply/Divide), Zicsr (Control and Status Registers), and External Debug extensions, this core is engineered to scale—from edge computing to mission-critical applications. As part of the DRVX Core Family, the DRV64IMZicsr embodies DCD’s philosophy of combining open-standard freedom with customizable IP excellence—making it a smart and future-proof alternative to legacy architectures. ✅ Why Choose RISC-V? * No license fees – open-source instruction set means reduced TCO * Unmatched flexibility – tailor the architecture to your specific needs * A global, thriving ecosystem – support from toolchains, OSes, and hardware vendors * Security & longevity – open and verifiable architecture ensures trust and sustainability 🚀 DRV64IMZicsr – Core Advantages: * 64-bit RISC-V ISA with M, Zicsr, and Debug support * Five-stage pipeline, Harvard architecture, and efficient branch prediction * Configurable memory size and allocation for program and data spaces Performance optimized: * **Up to 2.38 CoreMark/MHz** * **Up to 1.17 DMIPS/MHz** * Compact footprint starting from just 17.6k gates * Interface options: AXI, AHB, or native * Compatible with Classical CAN, CAN FD, and CAN XL through additional IPs 🛡️ Safety, Compatibility & Flexibility Built In: * Developed as an ISO 26262 Safety Element out of Context (SEooC) * Technology-agnostic – works seamlessly across all FPGA and ASIC vendors * Expandable with DCD’s IP portfolio: DMA, SPI, UART, I²C, CAN, PWM, and more 🔍 Robust Feature Set for Real Applications: * Full 64-bit processing – ideal for performance-intensive, memory-heavy tasks * M extension enables high-speed multiplication/division via dedicated hardware unit * Zicsr extension gives full access to Control and Status Registers, enabling: * Interrupts and exception handling (per RISC-V Privileged Spec) * Performance counters and timers * JTAG-compatible debug interface – compliant with RISC-V Debug Spec (0.13.2 & 1.0.0) 🧪 Ready for Development & Integration: * Comes with a fully automated testbench * Includes a comprehensive suite of validation tests for smooth SoC integration * Supported by industry-standard tools, ensuring a hassle-free dev experience Whether you’re designing for automotive safety, industrial control, IoT gateways, or AI-enabled edge devices, the DRV64IMZicsr gives you the performance, flexibility, and future-readiness of RISC-V—without compromise. 💡 Build smarter, safer systems—on your terms. 📩 Contact us today at info@dcd.pl to start your next RISC-V-powered project.
The D68000-CPU32 soft core is binary-compatible with the industry standard 68000's CPU32 version of the 32-bit microcontroller. The D68000-CPU32 has a 16-bit data bus and a 24-bit address data bus, and it is code compatible with the 68000's CPU32 (version of MC68020). The D68000-CPU32 includes an improved instruction set, allowing for higher performance than the standard 68000 core, and a built-in DoCD-BDM debugger interface. It is delivered with a fully automated test bench and a set of tests enabling easy package validation during different stages of the SoC design flow. The D68000-CPU32 is technology-agnostic, ensuring compatibility with all FPGA and ASIC vendors.
The DP8051 is an ultra-high performance, speed-optimized softcore, of a single-chip 8-bit embedded controller, intended to operate with fast (typically on-chip) and slow (off-chip) memories. The core was designed with a special concern about the performance to power-consumption ratio. This ratio is extended by the PMU – an advanced power management unit. The DP8051 softcore is 100% binary-compatible with the industry standard 8051 8-bit microcontrollers. There are two configurations of the DP8051: Harvard, where internal data and program buses are separated and von Neumann, with a common program and external data bus. The DP8051 has a Pipelined RISC architecture and executes 120-300 million instructions per second. Dhrystone 2.1 benchmark program runs from 11.46 to 15.55 times faster than the original 80C51 at the same frequency. The same C compiler was used for benchmarking of the core vs 80C51, with the same settings. This performance can also be exploited to great advantage in low-power applications, where the core can be clocked over ten times slower than the original implementation, without performance depletion. The DP8051 is delivered with a fully automated test bench and a complete set of tests, allowing easy package validation, at each stage of the SoC design flow. Each of DCD’s 8051 Cores has built-in support for the Hardware Debug System called DoCD™. It is a real-time hardware debugger, which provides debugging capability of the whole System-on-Chip (SoC). Unlike other on-chip debuggers, the DoCD™ provides non-intrusive debugging of a running application. It can halt, run, step into or skip an instruction, and read/write any contents of the microcontroller, including all registers, internal and external program memories, and all SFRs, including user-defined peripherals. ALL DCD’S IP CORES ARE TECHNOLOGY AGNOSTIC, ENSURING 100% COMPATIBILITY WITH ALL FPGA AND ASIC VENDORS.
The D68HC11F is a synthesizable SOFT Microcontroller IP Core, fully compatible with the Motorola 68HC11F1 industry standard. It can be used as a direct replacement for the 68HC11F1 Microcontrollers. Major peripheral functions are integrated on-chip, including an asynchronous serial communications interface (SCI) and a synchronous serial peripheral interface (SPI). The main 16-bit, free-running timer system includes input capture and output-compare lines, and a real-time interrupt function. An 8-bit pulse accumulator subsystem counts external events or measures external periods. Self-monitoring on-chip circuitry protects the D68HC11F against system errors. The Computer Operating Properly (COP) watchdog system and illegal opcode detection circuit provide extra security features. Two power-saving modes, WAIT and STOP, make the IP core especially attractive for automotive and battery-driven applications. Additionally, the D68HC11F can be equipped with an ADC Controller, offering compatibility with external ADCs. Its customizable nature means it's delivered in configurations tailored to need, avoiding unnecessary features and silicon waste. The D68HC11F also includes a fully automated test bench and comprehensive tests for easy SoC design validation. It supports DCD’s DoCD™, a real-time hardware debugger, for non-intrusive debugging of complete SoCs. This IP Core is technology agnostic, ensuring 100% compatibility with all FPGA and ASIC vendors.
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