All IPs > Processor > Coprocessor
In the realm of modern computing, coprocessor semiconductor IPs play a crucial role in augmenting system capabilities. A coprocessor is a supplementary processor that executes specific tasks more efficiently than the primary central processing unit (CPU). These coprocessors are specialized semiconductor IPs utilized in devices requiring enhanced computational power for particular functions such as graphics rendering, encryption, mathematical calculations, and artificial intelligence (AI) processing.
Coprocessors are integral in sectors where high performance and efficiency are paramount. For instance, in the gaming industry, a graphics processing unit (GPU) acts as a coprocessor to handle the high demand for rendering visuals, thus alleviating the burden from the CPU. Similarly, AI accelerators in smartphones and servers offload intensive AI computation tasks to speed up processing while conserving power.
You will find various coprocessor semiconductor IP products geared toward enhancing computational specialization. These include digital signal processors (DSPs) for processing real-time audio and video signals and hardware encryption coprocessors for securing data transactions. With the rise in machine learning applications, tensor processing units (TPUs) have become invaluable, offering massively parallel computing to efficiently manage AI workloads.
By incorporating these coprocessor semiconductor IPs into a system design, manufacturers can achieve remarkable improvements in speed, power efficiency, and processing power. This enables the development of cutting-edge technology products across a range of fields from personal electronics to autonomous vehicles, ensuring optimal performance in specialized computing tasks.
Akida's Neural Processor IP represents a leap in AI architecture design, tailored to provide exceptional energy efficiency and processing speed for an array of edge computing tasks. At its core, the processor mimics the synaptic activity of the human brain, efficiently executing tasks that demand high-speed computation and minimal power usage. This processor is equipped with configurable neural nodes capable of supporting innovative AI frameworks such as convolutional and fully-connected neural network processes. Each node accommodates a range of MAC operations, enhancing scalability from basic to complex deployment requirements. This scalability enables the development of lightweight AI solutions suited for consumer electronics as well as robust systems for industrial use. Onboard features like event-based processing and low-latency data communication significantly decrease the strain on host processors, enabling faster and more autonomous system responses. Akida's versatile functionality and ability to learn on the fly make it a cornerstone for next-generation technology solutions that aim to blend cognitive computing with practical, real-world applications.
The Akida IP is a groundbreaking neural processor designed to emulate the cognitive functions of the human brain within a compact and energy-efficient architecture. This processor is specifically built for edge computing applications, providing real-time AI processing for vision, audio, and sensor fusion tasks. The scalable neural fabric, ranging from 1 to 128 nodes, features on-chip learning capabilities, allowing devices to adapt and learn from new data with minimal external inputs, enhancing privacy and security by keeping data processing localized. Akida's unique design supports 4-, 2-, and 1-bit weight and activation operations, maximizing computational efficiency while minimizing power consumption. This flexibility in configuration, combined with a fully digital neuromorphic implementation, ensures a cost-effective and predictable design process. Akida is also equipped with event-based acceleration, drastically reducing the demands on the host CPU by facilitating efficient data handling and processing directly within the sensor network. Additionally, Akida's on-chip learning supports incremental learning techniques like one-shot and few-shot learning, making it ideal for applications that require quick adaptation to new data. These features collectively support a broad spectrum of intelligent computing tasks, including object detection and signal processing, all performed at the edge, thus eliminating the need for constant cloud connectivity.
MetaTF is BrainChip's premier development tool platform designed to complement its neuromorphic technology solutions. This platform is a comprehensive toolkit that empowers developers to convert and optimize standard machine learning models into formats compatible with BrainChip's Akida technology. One of its key advantages is its ability to adjust models into sparse formats, enhancing processing speed and reducing power consumption. The MetaTF framework provides an intuitive interface for integrating BrainChip’s specialized AI capabilities into existing workflows. It supports streamlined adaptation of models to ensure they are optimized for the unique characteristics of neuromorphic processing. Developers can utilize MetaTF to rapidly iterate and refine AI models, making the deployment process smoother and more efficient. By providing direct access to pre-trained models and tuning mechanisms, MetaTF allows developers to capitalize on the benefits of event-based neural processing with minimal configuration effort. This platform is crucial for advancing the application of machine learning across diverse fields such as IoT devices, healthcare technology, and smart infrastructure.
xcore.ai by XMOS is a groundbreaking solution designed to bring intelligent functionality to the forefront of semiconductor applications. It enables powerful real-time execution of AI, DSP, and control functionalities, all on a single, programmable chip. The flexibility of its architecture allows developers to integrate various computational tasks efficiently, making it a fitting choice for projects ranging from smart audio devices to automated industrial systems. With xcore.ai, XMOS provides the technology foundation necessary for swift deployment and scalable application across different sectors, delivering high performance in demanding environments.
RaiderChip's GenAI v1 is a pioneering hardware-based generative AI accelerator, designed to perform local inference at the Edge. This technology integrates optimally with on-premises servers and embedded devices, offering substantial benefits in privacy, performance, and energy efficiency over traditional hybrid AI solutions. The design of the GenAI v1 NPU streamlines the process of executing large language models by embedding them directly onto the hardware, eliminating the need for external components like CPUs or internet connections. With its ability to support complex models such as the Llama 3.2 with 4-bit quantization on LPDDR4 memory, the GenAI v1 achieves unprecedented efficiency in AI token processing, coupled with energy savings and reduced latency. What sets GenAI v1 apart is its scalability and cost-effectiveness, significantly outperforming competitive solutions such as Intel Gaudi 2, Nvidia's cloud GPUs, and Google's cloud TPUs in terms of memory efficiency. This solution maximizes the number of tokens generated per unit of memory bandwidth, thus addressing one of the primary limitations in generative AI workflow. Furthermore, the adept memory usage of GenAI v1 reduces the dependency on costly memory types like HBM, opening the door to more affordable alternatives without diminishing processing capabilities. With a target-agnostic approach, RaiderChip ensures the GenAI v1 can be adapted to various FPGAs and ASICs, offering configuration flexibility that allows users to balance performance with hardware costs. Its compatibility with a wide range of transformers-based models, including proprietary modifications, ensures GenAI v1's robust placement across sectors requiring high-speed processing, like finance, medical diagnostics, and autonomous systems. RaiderChip's innovation with GenAI v1 focuses on supporting both vanilla and quantized AI models, ensuring high computation speeds necessary for real-time applications without compromising accuracy. This capability underpins their strategic vision of enabling versatile and sustainable AI solutions across industries. By prioritizing integration ease and operational independence, RaiderChip provides a tangible edge in applying generative AI effectively and widely.
The GenAI v1-Q from RaiderChip brings forth a specialized focus on quantized AI operations, reducing memory requirements significantly while maintaining impressive precision and speed. This innovative accelerator is engineered to execute large language models in real-time, utilizing advanced quantization techniques such as Q4_K and Q5_K, thereby enhancing AI inference efficiency especially in memory-constrained environments. By offering a 276% boost in processing speed alongside a 75% reduction in memory footprint, GenAI v1-Q empowers developers to integrate advanced AI capabilities into smaller, less powerful devices without sacrificing operational quality. This makes it particularly advantageous for applications demanding swift response times and low latency, including real-time translation, autonomous navigation, and responsive customer interactions. The GenAI v1-Q diverges from conventional AI solutions by functioning independently, free from external network or cloud auxiliaries. Its design harmonizes superior computational performance with scalability, allowing seamless adaptation across variegated hardware platforms including FPGAs and ASIC implementations. This flexibility is crucial for tailoring performance parameters like model scale, inference velocity, and power consumption to meet exacting user specifications effectively. RaiderChip's GenAI v1-Q addresses crucial AI industry needs with its ability to manage multiple transformer-based models and confidential data securely on-premises. This opens doors for its application in sensitive areas such as defense, healthcare, and financial services, where confidentiality and rapid processing are paramount. With GenAI v1-Q, RaiderChip underscores its commitment to advancing AI solutions that are both environmentally sustainable and economically viable.
Altek's 3D Imaging Chip is a breakthrough in the field of vision technology. Designed with an emphasis on depth perception, it enhances the accuracy of 3D scene capturing, making it ideal for applications requiring precise distance gauging such as autonomous vehicles and drones. The chip integrates seamlessly within complex systems, boasting superior recognition accuracy that ensures reliable and robust performance. Building upon years of expertise in 3D imaging, this chip supports multiple 3D modes, offering flexible solutions for devices from surveillance robots to delivery mechanisms. It facilitates medium-to-long-range detection needs thanks to its refined depth sensing capabilities. Altek's approach ensures a comprehensive package from modular design to chip production, creating a cohesive system that marries both hardware and software effectively. Deployed within various market segments, it delivers adaptable image solutions with dynamic design agility. Its imaging prowess is further enhanced by state-of-the-art algorithms that refine image quality and facilitate facial detection and recognition, thereby expanding its utility across diverse domains.
The Maverick-2 Intelligent Compute Accelerator revolutionizes computing with its Intelligent Compute Architecture (ICA), delivering unparalleled performance and efficiency for HPC and AI applications. This innovative product leverages real-time adaptability, enabling it to optimize hardware configurations dynamically to match the specific demands of various software workloads. Its standout feature is the elimination of domain-specific languages, offering a universal solution for scientific and technical computing. Equipped with a robust developer toolchain that supports popular languages like C, C++, FORTRAN, and OpenMP, the Maverick-2 seamlessly integrates into existing workflows. This minimizes the need for code rewrites while maximizing developer productivity. By providing extensive support for emerging technologies such as CUDA and HIP/ROCm, Maverick-2 ensures that it remains a viable and potent solution for current and future computing challenges. Built on TSMC's advanced 5nm process, the accelerator incorporates HBM3E memory and high-bandwidth PCIe Gen 5 interfaces, supporting demanding computations with remarkable efficiency. The Maverick-2 achieves a significant power performance advantage, making it ideal for data centers and research facilities aiming for greater sustainability without sacrificing computational power.
The Spiking Neural Processor T1 is an advanced microcontroller engineered for highly efficient always-on sensing tasks. Integrating a low-power spiking neural network engine with a RISC-V processor core, the T1 provides a compact solution for rapid sensor data processing. Its design supports next-generation AI applications and signal processing while maintaining a minimal power footprint. The processor excels in scenarios requiring both high power efficiency and fast response. By employing a tightly-looped spiking neural network algorithm, the T1 can execute complex pattern recognition and signal processing tasks directly on-device. This autonomy enables battery-powered devices to operate intelligently and independently of cloud-based services, ideal for portable or remote applications. A notable feature includes its low-power operation, making it suitable for use in portable devices like wearables and IoT-enabled gadgets. Embedded with a RISC-V CPU and 384KB of SRAM, the T1 can interface with a variety of sensors through diverse connectivity options, enhancing its versatility in different environments.
The 2D FFT core is designed to efficiently handle two-dimensional FFT processing, ideal for applications in image and video processing where data is inherently two-dimensional. This core is engineered to integrate both internal and external memory configurations, which optimize data handling for complex multimedia processing tasks, ensuring a high level of performance is maintained throughout. Utilizing sophisticated algorithms, the 2D FFT core processes data through two FFT engines. This dual approach maximizes throughput, typically limiting bottlenecks to memory bandwidth constraints rather than computational delays. This efficiency is critical for applications handling large volumes of multimedia data where real-time processing is a requisite. The capacity of the 2D FFT core to adapt to varying processing environments marks its versatility in the digital processing landscape. By ensuring robust data processing capabilities, it addresses the challenges of dynamic data movement, providing the reliability necessary for multimedia systems. Its strategic design supports the execution of intensive computational tasks while maintaining the operational flow integral to real-time applications.
Syntacore’s SCR9 processor core stands out as a powerful force in handling high-performance computing tasks with its dual-issue out-of-order 12-stage pipeline. This core is engineered for environments that demand peak computational ability and robust pipeline execution, crucial for data-intense tasks such as AI and ML, enterprise applications, and network processing. The architecture is tailored to support extensive multicore and heterogeneous configurations, providing valuable tools for developers aiming to maximize workload efficiency and processing speed. The inclusion of a vector processing unit (VPU) underscores its capability to handle large datasets and complex calculations, while maintaining system integrity and coherence through its comprehensive cache management. With support for hypervisor functionalities and scalable Linux environments, the SCR9 continues to be a key strategic element in expanding the horizons of RISC-V-based applications. Syntacore’s extensive library of development resources further enriches the usability of this core, ensuring that its implementation remains smooth and effective across diverse technological landscapes.
The RISCV SoC developed by Dyumnin Semiconductors is engineered with a 64-bit quad-core server-class RISCV CPU, aiming to bridge various application needs with an integrated, holistic system design. Each subsystem of this SoC, from AI/ML capabilities to automotive and multimedia functionalities, is constructed to deliver optimal performance and streamlined operations. Designed as a reference model, this SoC enables quick adaptation and deployment, significantly reducing the time-to-market for clients. The AI Accelerator subsystem enhances AI operations with its collaboration of a custom central processing unit, intertwined with a specialized tensor flow unit. In the multimedia domain, the SoC boasts integration capabilities for HDMI, Display Port, MIPI, and other advanced graphic and audio technologies, ensuring versatile application across various multimedia requirements. Memory handling is another strength of this SoC, with support for protocols ranging from DDR and MMC to more advanced interfaces like ONFI and SD/SDIO, ensuring seamless connectivity with a wide array of memory modules. Moreover, the communication subsystem encompasses a broad spectrum of connectivity protocols, including PCIe, Ethernet, USB, and SPI, crafting an all-rounded solution for modern communication challenges. The automotive subsystem, offering CAN and CAN-FD protocols, further extends its utility into automotive connectivity.
The iCan PicoPop® is a highly compact System on Module (SOM) based on the Zynq UltraScale+ MPSoC from Xilinx, suited for high-performance embedded applications in aerospace. Known for its advanced signal processing capabilities, it is particularly effective in video processing contexts, offering efficient data handling and throughput. Its compact size and performance make it ideal for integration into sophisticated systems where space and performance are critical.
The DisplayPort Transmitter from Trilinear Technologies is a sophisticated solution designed for high-performance digital video streaming applications. It is compliant with the latest VESA DisplayPort standards, ensuring compatibility and seamless integration with a wide range of display devices. This transmitter core supports high-resolution video outputs and is equipped with advanced features like adaptive sync and panel refresh options, making it ideal for consumer electronics, automotive displays, and professional AV systems. This IP core provides reliable performance with minimal power consumption, addressing the needs of modern digital ecosystems where energy efficiency is paramount. It includes customizable settings for audio and video synchronization, ensuring optimal output quality and user experience across different devices and configurations. By reducing load on the system processor, the DisplayPort Transmitter guarantees a seamless streaming experience even in high-demand environments. In terms of integration, Trilinear's DisplayPort Transmitter is supported with comprehensive software stacks allowing for easy customization and deployment. This ensures rapid product development cycles and aids developers in managing complex video data streams effectively. The transmitter is particularly optimized for use in embedded systems and consumer devices, offering robust performance capabilities that stand up to rigorous real-time application demands. With a focus on compliance and testing, the DisplayPort Transmitter is pre-tested and proven to work seamlessly with a variety of hardware platforms including FPGA and ASIC technologies. This robustness in design and functionality underlines Trilinear's reputation for delivering reliable, high-quality semiconductor IP solutions that cater to diverse industrial applications.
The Veyron V1 is a high-performance RISC-V CPU designed to meet the rigorous demands of modern data centers and compute-intensive applications. This processor is tailored for cloud environments requiring extensive compute capabilities, offering substantial power efficiency while optimizing processing workloads. It provides comprehensive architectural support for virtualization and efficient task management with its robust feature set. Incorporating advanced RISC-V standards, the Veyron V1 ensures compatibility and scalability across a wide range of industries, from enterprise servers to high-performance embedded systems. Its architecture is engineered to offer seamless integration, providing an excellent foundation for robust, scalable computing designs. Equipped with state-of-the-art processing cores and enhanced vector acceleration, the Veyron V1 delivers unmatched throughput and performance management, making it suitable for use in diverse computing environments.
The RFicient chip is designed to revolutionize the Internet of Things with its ultra-low power consumption. It enables devices to operate more sustainably by drastically reducing energy requirements. This is particularly important for devices in remote locations, where battery life is a critical concern. By leveraging energy harvesting and efficient power management, the RFicient chip significantly extends the operational life of IoT devices, making it ideal for widespread applications across industrial sectors.
Trilinear Technologies has developed a cutting-edge DisplayPort Receiver that enhances digital connectivity, offering robust video reception capabilities necessary for today's high-definition video systems. Compliant with VESA standards, the receiver supports the latest DisplayPort specifications, effortlessly handling high-bandwidth video data necessary for applications such as ultra-high-definition televisions, professional video wall setups, and complex automotive display systems. The DisplayPort Receiver is designed with advanced features that facilitate seamless video data acquisition and processing, including multi-stream transport capabilities for handling multiple video streams concurrently. This is particularly useful in professional display settings where multiple input sources are needed. The core also incorporates adaptive sync features, which help reduce screen tearing and ensure smooth video playback, enhancing user experience significantly. An important facet of the DisplayPort Receiver is its low latency and high-efficiency operations, crucial for systems requiring real-time data processing. Trilinear's receiver core ensures that video data is processed with minimal delay, maintaining the integrity and fidelity of the original visual content. This makes it a preferred choice for high-performance applications in sectors like gaming, broadcasting, and high-definition video conferencing. To facilitate integration and ease of use, the DisplayPort Receiver is supported by a comprehensive suite of development tools and software packages. This makes the deployment process straightforward, allowing developers to integrate the receiver into both FPGA and ASIC environments with minimal adjustments. Its scalability and flexibility mean it can meet the demands of a wide range of applications, solidifying Trilinear Technologies' position as a leader in the field of semiconductor IP solutions.
The Origin E1 is a streamlined neural processing unit designed specifically for always-on applications in personal electronics and smart devices such as smartphones and security systems. This processor focuses on delivering highly efficient AI performance, achieving around 18 TOPS per watt. With its low power requirements, the E1 is ideally suited for tasks demanding continuous data sampling, such as camera operations in smart surveillance systems where it runs on less than 20mW of power. Its packet-based architecture ensures efficient resource utilization, maintaining high performance with lower power and area consumption. The E1's adaptability is enhanced through customizable options, allowing it to meet specific PPA requirements effectively, making it the go-to choice for applications seeking to improve user privacy and experience by minimizing external memory use.
The Neural Network Accelerator from Gyrus AI is a state-of-the-art processing solution tailored for executing neural networks efficiently. Leverage this IP to achieve high-performance computing with streamlined power consumption. It features a noteworthy capability of operating at 30 TOPS/W, drastically reducing clock cycles by 10-30x compared to traditional processors. This advancement supports various neural network structures, ensuring high operational efficiency while minimizing energy demands.\n\nThe architecture of the Neural Network Accelerator is optimized for low memory usage, resulting in significantly lower power needs, which in turn reduces operational costs. Its design focuses on achieving optimal die area usage, ensuring over 80% utilization for different model structures, which supports compact and effective chip designs. This enhances the scalability and flexibility required for varied applications in edge computing.\n\nAccompanied by advanced software tools, this IP supports seamless integration into existing systems, facilitating the straightforward execution of neural networks. The tools offer robust support, helping run complex models with ease, boosting both performance and resource efficiency. This makes it ideal for companies looking to enhance their AI processing capabilities on edge devices. Its cutting-edge technology enables enterprises to maintain competitive advantages in AI-driven markets.
DolphinWare IPs is a versatile portfolio of intellectual property solutions that enable efficient SoC design. This collection includes various control logic components such as FIFO, arbiter, and arithmetic components like math operators and converters. In addition, the logic components span counters, registers, and multiplexers, providing essential functionalities for diverse industrial applications. The IPs in this lineup are meticulously designed to ensure data integrity, supported by robust verification IPs for AXI4, APB, SD4.0, and more. This comprehensive suite meets the stringent demands of modern electronic designs, facilitating seamless integration into existing design paradigms. Beyond their broad functionality, DolphinWare’s offerings are fundamental to applications requiring specific control logic and data integrity solutions, making them indispensable for enterprises looking to modernize or expand their product offerings while ensuring compliance with industry standards.
The Pipelined FFT core delivers streamlined continuous data processing capabilities with an architecture designed for pipelined execution of FFT computations. This core is perfectly suited for use in environments where data is fed continuously and needs to be processed with minimal delays. Its design minimizes memory footprint while ensuring high-speed data throughput, making it invaluable for real-time signal processing applications. By structurally arranging computations into a pipeline, the core facilitates a seamless flow of operations, allowing for one-step-after-another processing of data. The efficiency of the pipelining process reduces the system's overall latency, ensuring that data is processed as quickly as it arrives. This functionality is especially beneficial in time-sensitive applications where downtime can impact system performance. The compact design of the Pipelined FFT core integrates well into systems requiring consistent data flow and reduced resource allocation. It offers effective management of continuous data streams, supporting critical applications in areas such as real-time monitoring and control systems. By ensuring rapid data turnover, this core enhances system efficiency and contributes significantly to achieving strategic processing objectives.
Avispado is a 64-bit in-order RISC-V core designed by Semidynamics, focused on offering efficiency for AI edge applications and embedded systems. Its in-order execution model ensures optimal power consumption, making it a prudent choice for energy-constrained environments such as IoT and mobile devices. Equipped with Gazzillion Misses™ technology, Avispado effectively manages memory requests for efficient data handling, crucial for processing real-time data streams in embedded setups. This core supports the RISC-V Vector Specification 1.0, making it an excellent fit for machine learning tasks that require vector processing capabilities. Avispado also features customizable components like branch predictors and configurable instruction/data caches, which can be tailored to fit specific application needs. Its multiprocessor ready design is scalable for systems demanding cache coherence and reliable data access, supporting a wide range of AI and computation-heavy applications.
The UltraLong FFT core is specifically optimized for Xilinx FPGAs, designed to handle extensive data processing tasks with efficiency. With an architecture that accommodates large-scale FFT applications, this core is engineered to maximize throughput while minimizing memory usage. Ideal for creating high-speed data processing pipelines, the UltraLong FFT core supports advanced signal processing with unparalleled speed and accuracy, providing a reliable solution for real-time applications that demand robust performance. This FFT core integrates seamlessly with external memory systems, utilizing dual FFT engines to achieve maximum data throughput, which is typically constrained only by the bandwidth of the memory. The two FFT engines operate in tandem, allowing for rapid data computation, making it perfect for high-end computation needs. Additionally, the design's flexibility allows for easy adaptation to various signal processing demands, ensuring it meets the specific requirements of different applications. The UltraLong FFT core's design is this finely tuned integration capability, which leverages external memory and custom control logic, effectively streamlining data handling challenges. This makes it highly suited for industries requiring precise control over data transformation and real-time data processing. Whether employed in digital communication or image processing, this core offers the computational prowess necessary to maintain efficiency across complex datasets.
TimbreAI T3 addresses audio processing needs by embedding AI in sound-based applications, particularly suitable for power-constrained devices like wireless headsets. It's engineered for exceptional power efficiency, requiring less than 300 µW to operate while maintaining a performance capacity of 3.2 GOPS. This AI inference engine simplifies deployment by never necessitating changes to existing trained models, thus preserving accuracy and efficiency. The TimbreAI T3's architecture ensures that it handles noise reduction seamlessly, offering core audio neural network support. This capability is complemented by its flexible software stack, further reinforcing its strength as a low-power, high-functionality solution for state-of-the-art audio applications.
The Atrevido core from Semidynamics is a 64-bit out-of-order RISC-V processor, engineered for high performance in artificial intelligence and high-performance computing (HPC) environments. Offering extensive customization, it supports 2/3/4-wide design configurations, making it well-suited for handling intricate AI workloads that require significant processing bandwidth. Atrevido is capable of executing multiple operations simultaneously thanks to its Gazzillion Misses™ technology, which can manage up to 128 memory requests concurrently, reducing processing bottlenecks. This core is optimized for applications requiring high data throughput and is compatible with AXI and CHI interfaces, facilitating integration into advanced multiprocessor systems. Additionally, Atrevido comes vector and tensor ready, enabling it to support complex AI tasks, including key-value stores and machine learning. It includes advanced features such as vector extensions and memory interface enhancements, which improve performance in systems that demand robust computational power and flexibility.
Engineered for top-tier AI applications, the Origin E8 excels in delivering high-caliber neural processing for industries spanning from automotive solutions to complex data center implementations. The E8's design supports singular core performance up to 128 TOPS, while its adaptive architecture allows easy multi-core scalability to exceed PetaOps. This architecture eradicates common performance bottlenecks associated with tiling, delivering robust throughput without unnecessary power or area compromises. With an impressive suite of features, the E8 facilitates remarkable computational capacity, ensuring that even the most intricate AI networks function smoothly. This high-performance capability, combined with its relatively low power usage, positions the E8 as a leader in AI processing technologies where high efficiency and reliability are imperative.
The Viper Series Gen AI PCIe Card is crafted to deliver peak performance for AI inference tasks, setting a new standard in accelerator technology. Tailored for cutting-edge AI applications, it combines robust processing capabilities with energy efficiency, making it an excellent choice for enterprises aiming to improve their data processing frameworks. Its design emphasizes speed and reliability, crucial for operations demanding high throughput and low latency. The Viper Series Card integrates effortlessly into existing IT infrastructures, offering scalability and flexibility that cater to various market needs. Organizations leveraging this card can expect enhanced efficiency in their AI-driven projects. Furthermore, the card is engineered to support extensive AI models, facilitating seamless operations across different platforms and environments. The Viper Series not only enhances the performance of AI implementations but also reduces operational costs, giving businesses a competitive edge in deploying large-scale AI projects.
The Raptor N3000 AI Accelerator is engineered to redefine the capabilities of AI applications with its specialized architecture. Designed specifically for demanding inference workloads, it ensures rapid processing speeds and enhanced energy efficiency. This tool is ideal for enterprises seeking to leverage AI for data-intensive tasks without overwhelming existing IT infrastructure. Built on advanced ASIC technology, the Raptor N3000 supports a range of machine learning frameworks and models, making it a versatile asset for businesses. Its integration into existing systems is straightforward, providing a scalable solution that aligns with growth in AI demands. By accelerating inferencing tasks, it helps reduce latency and improve the overall speed of AI-driven processes. Furthermore, the Raptor N3000 is crafted to minimize power consumption, an essential feature in today’s eco-conscious environment. Its efficiency in handling large datasets makes it suitable for applications running in both cloud and on-premise settings, ensuring consistent performance across different operational environments.
EdgeCortix’s MERA Compiler and Software Framework serves as a comprehensive platform for deploying neural network models across various systems. It facilitates AI inference by combining the Dynamic Neural Accelerator (DNA) technology, offering tools like APIs, a code generator, and runtime capabilities essential for implementing pre-trained deep neural networks. The framework is engineered to tackle innovative generative AI applications, accommodating a spectrum of leading processors, such as AMD, Intel, Arm, and RISC-V, ensuring speedy integration into existing infrastructures. MERA stands out by supporting an array of ML frameworks, including TensorFlow Lite and ONNX, and offering native interfaces for Python and C++ to customize AI workflows. It simplifies the development and deployment process with post-training model calibration and quantization. The inclusion of Apache TVM and MLIR adds flexibility, allowing developers to advance from modeling to deployment with ease. The framework is integral to the company's suite of offerings as it optimizes neural network computation, resource allocation, and execution order, all within a runtime reconfigurable architecture. The MERA platform thus grants software developers the ability to focus on AI model refinement without getting entangled with hardware intricacies, dramatically reducing latency and boosting throughput efficiency.
The Cobalt GNSS Receiver is a trailblazing IP core designed to integrate effortlessly with IoT System-on-Chip (SoC) platforms, delivering enhanced geolocation capabilities. Its strategic advantage lies in its ultra-low-power operation, which is crucial for IoT applications where power efficiency is paramount. Cobalt leverages shared resources between GNSS and modem functionalities, optimizing both cost and footprint for embedded systems. By utilizing software-defined technologies, it supports a range of satellite constellations, including Galileo, GPS, and Beidou, facilitating versatile and robust global positioning. What sets Cobalt apart is its ability to function in both standalone and cloud-assisted modes, allowing for tailored solutions depending on application needs. Its power-optimized design reduces processing demands while maintaining sensitivity and accuracy. The solution has been developed in collaboration with CEVA DSP and is supported by the European Space Agency, reinforcing its credibility and technical prowess. Cobalt's development ensures it is well-suited for mass-market applications that are sensitive to size and cost constraints, making it an ideal choice for logistics, agriculture, insurance, and various mobile and stationary assets tracking. Additionally, its enhanced resistance to multi-path interference and higher modulation rates foster optimal accuracy, crucial for environments that demand precise geolocation.
The Origin E2 NPU cores offer a balanced solution for AI inference by optimizing for both power and area without compromising performance. These cores are expertly crafted to save system power in devices such as smartphones and edge nodes. Their design supports a wide variety of networks, including RNNs and CNNs, catering to the dynamic demands of consumer and industrial applications. With customizable performance ranging from 1 to 20 TOPS, they are adept at handling various AI-driven tasks while reducing latency. The E2 architecture is ingeniously configured to enable parallel processing, affording high resource utilization that minimizes memory demands and system overhead. This results in a flexible NPU architecture that serves as a reliable backbone for deploying efficient AI models across different platforms.
Specialty Microcontrollers from Advanced Silicon harness the capabilities of the latest RISC-V architectures for advanced processing tasks. These microcontrollers are particularly suited to applications involving image processing, thanks to built-in coprocessing units that enhance their algorithm execution efficiency. They serve as ideal platforms for sophisticated touch screen interfaces, offering a balance of high performance, reliability, and low power consumption. The integrated features allow for the enhancement of complex user interfaces and their interaction with other system components to improve overall system functionality and user experience.
The iCEVision platform is built around enabling designers and developers to exploit the iCE40 UltraPlus FPGA's connectivity features. This board provides rapid prototyping and testing environments through exposed I/O interfaces compatible with popular camera modules such as ArduCam CSI and PMOD. Programming can be handled via the Lattice Diamond Programmer, which allows users to modify the on-board SPI flash with custom code. Moreover, iCEVision supports seamless multi-board connection through ArduCam connectors, offering a versatile tool for both learning and professional development phases in FPGA design and implementation.
The Origin E6 provides a formidable edge in AI processing demands for mobile and AR/VR applications, boasting performance specifications between 16 to 32 TOPS. Tailored to accommodate the latest AI models, the E6 benefits from Expedera's distinct packet-based architecture. This cutting-edge design simplifies parallel processing, which enhances efficiency while concurrently diminishing power and resource consumption. As an NPU, it supports an extensive array of video, audio, and text-based networks, thus delivering consistent performance even under complex specifications. The E6's high utilization rates minimize wastage and amplify throughput, certifying its position as an optimal choice for forward-thinking gadgets requiring potent due to its scalable and adaptable architecture.
FortiPKA-RISC-V is a powerful public key algorithm coprocessor designed to enhance cryptographic operations through streamlined modular multiplication techniques. This IP core offers robust protection against side-channel and fault injection attacks, ensuring high performance by eliminating Montgomery domain transformations. Engineered to maximize efficiency, FortiPKA-RISC-V supports a variety of cryptographic protocols, making it suitable for applications demanding high-speed data processing with minimal latency. Its architecture ensures seamless integration into systems requiring secure key exchanges and digital signature verifications, showcasing versatility across different computational platforms. Additionally, this coprocessor is built with a focus on reducing hardware footprint, making it ideal for space and power-conscious applications such as embedded systems and mobile devices. By aligning with industry-standard cryptographic requirements, FortiPKA-RISC-V provides an effective solution for environments requiring elevated security without compromising on computational speed or area efficiency.
The RV32EC_P2 processor core by IQonIC Works is a compact RISC-V processor designed for low-power embedded applications. It features a two-stage pipeline architecture ideal for running trusted firmware and offers a base RV32E instruction set. To enhance efficiency, the core supports RVC compressed instructions for reduced code sizes and optionally includes integer multiplication and division functionalities through the 'M' standard extension. Additionally, it accommodates custom instruction set extensions for tasks such as DSP operations, making it versatile for numerous applications. Designed for ASIC and FPGA implementations, the core provides interfaces like AHB-Lite or APB for memory and I/O operations, ensuring comprehensive system integration. Key features include a simple privileged architecture for machine-mode operations and clock gating for reduced power consumption during idle states. Furthermore, the core supports vectorized interrupts, enabling fast responses to system signals. The RV32EC_P2 is backed by a full suite of development and simulation tools, including synthesis scripts and firmware development environments based on the GNU tool chain. The Virtual Lab (VLAB) system-level tools offer enhanced support for developing and testing applications in a virtual context, ensuring a seamless development experience from conception to deployment.
The Mixed Radix FFT core caters to applications requiring diverse FFT lengths beyond traditional radix-2 implementations. This versatility enables users to execute FFT with different radix combinations, such as radix-3, radix-5, or radix-7, enhancing its adaptability across various transformative needs. As a result, it's a robust solution for critical data processing tasks where standard FFT cores might fall short. The architecture of the Mixed Radix FFT core supports flexible data processing requirements, ensuring compatibility with a wide range of FFT paradigms. This adaptability allows it to be integrated into bespoke systems that require specific FFT configurations, thereby expanding its usefulness in diverse applications. With efficient management of computational resources, it ensures that data transformation maintains speed without sacrificing precision. Focused on complex data transformation tasks, the Mixed Radix FFT core is designed to seamlessly accommodate FFT calculations with varying radix factors. This flexibility is invaluable for applications in advanced digital communications and multimedia processing, where data dynamics necessitate rapid yet accurate computational adjustments. By incorporating these capabilities, the core serves as a pivotal component in sophisticated digital transformation ecosystems.
The Load Unload FFT core is crafted to facilitate efficient data handling and transformation processes, essentially managing the input and output operations of FFT-based computations. It is particularly advantageous for applications where large volumes of data must be handled smoothly and without delay. Slightly more flexible compared to traditional FFT designs, this core allows for modification according to specific project requirements, making it an excellent choice for customized signal processing solutions. Designed to optimize data throughput with minimal latency, the Load Unload FFT core supports a variety of operational configurations. This allows it to accommodate different data structures and formats, enhancing its versatility across various digital processing environments. The core's architecture ensures consistent performance, even when integrated into complex systems requiring precise data transformation capabilities. The ability to orchestrate smooth data transitions from input to output is central to the Load Unload FFT core's functionality. By effectively managing these transitions, the core reduces potential bottlenecks in data processing, ensuring that systems operate at peak efficiency. For organizations involved in signal processing, this capability translates to improved productivity and enhanced data accuracy, essential for maintaining competitive advantage.
The Low Power Security Engine offers a compact yet comprehensive solution for securing IoT devices. This hardware acceleration engine provides efficient processing capabilities for encryption, hash computations, and cryptographic operations like elliptic curve scalar multiplication. Engineered for minimal power usage and to withstand side-channel and timing attacks, it features built-in support for protocols such as ECDHE and ECDSA, ensuring that devices remain secure against sophisticated threats while optimizing performance in constrained environments.
The RecAccel N3000 PCIe is crafted to revolutionize AI recommendation systems, significantly enhancing inference speed and accuracy. As a state-of-the-art ASIC, it specifically targets applications requiring high-throughput data processing, vital for efficient recommendation services. This PCIe-based solution integrates seamlessly with existing systems, providing a scalable platform that enhances user experience in digital services. By offloading intensive computation tasks from general-purpose processors, the RecAccel N3000 reduces system load and accelerates response times, crucial for real-time applications. Its architecture is optimized for deep learning recommendation models, ensuring unmatched power efficiency and cost-effectiveness in data center environments. This balance of performance and energy consumption is essential as the demand for AI-powered recommendations continues to rise. Moreover, the RecAccel N3000 is engineered for easy deployment across different platforms, making it a flexible option for businesses aiming to enhance their AI infrastructure without extensive reconfiguration. Its robust design ensures longevity and reliability, key factors for enterprises operating in fast-paced digital markets.
The Parallel FFT core exemplifies high-efficiency data processing by executing FFT operations simultaneously across multiple data inputs. This design significantly accelerates data transformation tasks, making it ideal for systems that require quick and reliable FFT computations. It is especially beneficial in scenarios where large data sets must be processed in parallel, such as in telecom systems or real-time analytics platforms. With an architecture optimized for concurrent operations, the Parallel FFT core effectively distributes data processing tasks among various computational paths. This reduces the time and resources needed to achieve desired computational results, allowing for higher bandwidth applications to be realized with greater ease. The core is crafted to adjust to various signal processing requirements, maintaining consistent performance across different use cases. The integration of multiple processing streams within the Parallel FFT core enables the quick transformation of data, effectively supporting applications that demand high throughput and low latency. By leveraging advanced parallel computation techniques, the core ensures that data processing tasks are handled efficiently, supporting real-time decision-making and processing in demanding environments.
IQonIC Works' RV32IC_P5 processor core is a high-performance RISC-V solution designed for medium-scale embedded systems requiring advanced processing capabilities and efficient multitasking. Its five-stage pipeline architecture supports complex operations with high-speed processing, catering to applications involving both trusted firmware and user code execution. The core is capable of handling a variety of tasks efficiently due to features like cache memories and privileged machine- and user-modes. This core offers a comprehensive RISC-V RV32I base instruction set and includes optional standard extensions for integer operations (M), user-mode execution (N), and critical section handling (A). It's designed to optimize branch prediction and interrupt response times with configurable buffers and vectorized handling capabilities, which are critical for high-performance applications. Supporting both ASIC and FPGA design flows, the RV32IC_P5 core integrates tightly with memory and I/O interfaces, using AHB-Lite buses for extensive connectivity. The accompanying development environment includes the GNU tool chain and ASTC's VLAB for prototyping and firmware testing, ensuring developers have robust tools for seamless application development and deployment.
The High-Performance FPGA & ASIC Networking Product by CetraC.io is a leading-edge solution for distributed architectures in critical systems across various sectors. It is specifically designed to cater to the demanding needs of industries requiring robust, high-speed networking capabilities with a primary focus on performance and reliability. This product combines FPGA and ASIC technologies, harnessing their synergies to deliver exceptional speed and precise control over data streams, making it ideal for complex, data-intensive environments. Engineered to support a wide range of protocols such as Ethernet, AFDX, PCI Express, and more, this networking product embodies flexibility and adaptability. Its ability to handle diverse data streams simultaneously, with ultra-low latency and high throughput, ensures that it can meet the needs of high-demand infrastructural setups, from aerospace and automotive to industrial networks. Moreover, this technology is pivotal in integrating seamlessly with existing network frameworks, enhancing overall system efficiency and communication accuracy. Security is a cornerstone of CetraC.io’s offering, with this product incorporating advanced hardware-based encryption mechanisms. Using AES256 GCM, the networking product ensures that all transmitted data remains secure and protected against unauthorized access, fulfilling stringent industry cybersecurity standards. This robust security framework works in tandem with its performance attributes to present a comprehensive solution to modern networking challenges. Furthermore, the product features high levels of cyber resilience and determinism, crucial for maintaining intact operations even under adverse conditions. Its hardware-based design replaces traditional software vulnerability points, offering a more secure, reliable, and efficient operation, perfectly suited to support the evolving landscape of industries transitioning towards increased automation and digitalization.
The RecAccel AI Platform is a powerful tool designed to facilitate high-accuracy computing for comprehensive AI applications. Tailored for environments requiring precise data handling and analysis, this platform merges robust hardware capabilities with sophisticated software frameworks. It is optimized to deliver superior performance with its underlying AI-specific architectures. Equipped with Neuchips' advanced ASIC technologies, the platform excels in demanding computational scenarios, ensuring efficient processing of complex algorithms. This enables businesses to deploy AI-driven solutions with confidence, knowing they have a reliable foundation that minimizes latency and maximizes output. As enterprises increasingly rely on artificial intelligence to drive decisions, such platforms become indispensable. Flexibility and scalability are core to the platform's design, allowing it to adapt to varied operational needs. Whether for deep learning tasks or machine learning model testing, the RecAccel AI Platform provides the tools and support necessary to execute these functions seamlessly, reducing overheads and enhancing productivity.
**DRV64IMZicsr – 64-bit RISC-V Performance. Designed for Demanding Innovation.** The DRV64IMZicsr is a powerful and versatile 64-bit RISC-V CPU core, built to meet the performance and safety needs of next-generation embedded systems. Featuring the M (Multiply/Divide), Zicsr (Control and Status Registers), and External Debug extensions, this core is engineered to scale—from edge computing to mission-critical applications. As part of the DRVX Core Family, the DRV64IMZicsr embodies DCD’s philosophy of combining open-standard freedom with customizable IP excellence—making it a smart and future-proof alternative to legacy architectures. ✅ Why Choose RISC-V? * No license fees – open-source instruction set means reduced TCO * Unmatched flexibility – tailor the architecture to your specific needs * A global, thriving ecosystem – support from toolchains, OSes, and hardware vendors * Security & longevity – open and verifiable architecture ensures trust and sustainability 🚀 DRV64IMZicsr – Core Advantages: * 64-bit RISC-V ISA with M, Zicsr, and Debug support * Five-stage pipeline, Harvard architecture, and efficient branch prediction * Configurable memory size and allocation for program and data spaces Performance optimized: * **Up to 2.38 CoreMark/MHz** * **Up to 1.17 DMIPS/MHz** * Compact footprint starting from just 17.6k gates * Interface options: AXI, AHB, or native * Compatible with Classical CAN, CAN FD, and CAN XL through additional IPs 🛡️ Safety, Compatibility & Flexibility Built In: * Developed as an ISO 26262 Safety Element out of Context (SEooC) * Technology-agnostic – works seamlessly across all FPGA and ASIC vendors * Expandable with DCD’s IP portfolio: DMA, SPI, UART, I²C, CAN, PWM, and more 🔍 Robust Feature Set for Real Applications: * Full 64-bit processing – ideal for performance-intensive, memory-heavy tasks * M extension enables high-speed multiplication/division via dedicated hardware unit * Zicsr extension gives full access to Control and Status Registers, enabling: * Interrupts and exception handling (per RISC-V Privileged Spec) * Performance counters and timers * JTAG-compatible debug interface – compliant with RISC-V Debug Spec (0.13.2 & 1.0.0) 🧪 Ready for Development & Integration: * Comes with a fully automated testbench * Includes a comprehensive suite of validation tests for smooth SoC integration * Supported by industry-standard tools, ensuring a hassle-free dev experience Whether you’re designing for automotive safety, industrial control, IoT gateways, or AI-enabled edge devices, the DRV64IMZicsr gives you the performance, flexibility, and future-readiness of RISC-V—without compromise. 💡 Build smarter, safer systems—on your terms. 📩 Contact us today at info@dcd.pl to start your next RISC-V-powered project.
DRV32IMZicsr – Scalable RISC-V Power. Tailored for Your Project. Ready for the Future. The DRV32IMZicsr is a high-performance, 32-bit RISC-V processor core, equipped with M (Multiply/Divide), Zicsr (Control and Status Registers), and External Debug support. Built as part of DCD’s latest DRVX Core Family, it delivers the full flexibility, openness, and innovation that RISC-V promises—without locking you into proprietary architectures. ✅ Why RISC-V? RISC-V is a rapidly growing open standard for modern computing—backed by a global ecosystem of developers and vendors. It brings: * Freedom from licensing fees and vendor lock-in * Scalability from embedded to high-performance systems * Customizability with standard and custom instruction sets * Strong toolchain & ecosystem support 🚀 DRV32IMZicsr Highlights: * Five-stage pipeline and Harvard architecture for optimized performance * Configurable memory architecture: size and address allocation tailored to your needs Performance metrics: * **Up to 1.15 DMIPS/MHz** * **Up to 2.36 CoreMark/MHz** * Minimal footprint starting from just 14k gates * Flexible interfaces: Choose from AXI, AHB, or native bus options 🛡️ Designed for Safety & Integration: * Developed as an ISO 26262 Safety Element out of Context (SEooC) * Fully technology-agnostic, compatible with all FPGA and ASIC platforms * Seamless integration with DCD’s rich portfolio of IPs: DMA, SPI, UART, PWM, CAN, and more 🔍 Advanced Feature Set: * 32 general-purpose registers * Support for arithmetic, logic, load/store, conditional and unconditional control flow * M extension enables efficient integer multiplication/division * Zicsr extension provides robust interrupt and exception handling, performance counters, and timers * External Debug via JTAG: compliant with RISC-V Debug Specification 0.13.2 and 1.0.0, compatible with all mainstream tools 🧪 Developer-Ready: * Delivered with a fully automated testbench * Includes a comprehensive validation test suite for smooth integration into your SoC flow Whether you're building for automotive, IoT, consumer electronics, or embedded systems, the DRV32IMZicsr offers a future-ready RISC-V solution—highly configurable, performance-optimized, and backed by DCD’s 25 years of experience. Interested? Let’s build the next generation together. 📩 Contact us at info@dcd.pl
The Miscellaneous FEC and DSP IP cores offered by Creonic extend beyond standard modulation and coding, contributing a suite of advanced signal processing components. These are crucial for specialized use cases in high-speed, multi-channel processing, supporting real-time applications smooth and efficiently. Among these offerings, the NCR Processor and DVB-GSE encapsulators are uniquely poised for time synchronization and protocol-specific tasks. Combined with digital downconverters and wideband channelizers, Creonic's miscellaneous cores fill essential gaps in protocol architectures, ensuring comprehensive support for system architectures. The inclusion of IPs like the Ultrafast BCH Decoder and Doppler Channel components underscores the company's commitment to delivering trusted building blocks for complex communication landscapes. For designers aiming to complete their projects with reliable, efficient components, Creonic's miscellaneous DSP cores are significant assets.
The D68000-CPU32 soft core is binary-compatible with the industry standard 68000's CPU32 version of the 32-bit microcontroller. The D68000-CPU32 has a 16-bit data bus and a 24-bit address data bus, and it is code compatible with the 68000's CPU32 (version of MC68020). The D68000-CPU32 includes an improved instruction set, allowing for higher performance than the standard 68000 core, and a built-in DoCD-BDM debugger interface. It is delivered with a fully automated test bench and a set of tests enabling easy package validation during different stages of the SoC design flow. The D68000-CPU32 is technology-agnostic, ensuring compatibility with all FPGA and ASIC vendors.
The BA25 Advanced Application Processor is designed for superior performance with independent functional units allowing out-of-order completion. It achieves 1.51 DMIPS/MHz and can reach operational frequencies up to 800 MHz using a 65 nm LP process, making it one of the most capable processors in Beyond's catalogue. Capable of higher instruction throughput, the BA25 stands out for its unparalleled code density, supporting sophisticated application processes and ensuring optimal performance metric achievement. The processor is especially adept at handling complex operating systems and demanding application requirements. This processor's design supports progressive data processing strategies, making it suitable for applications demanding high computational power without sacrificing efficiency, asserting itself as a premium choice for advanced processing needs.
The BA22-CE Cache Enabled Processor distinguishes itself through its efficient use of integrated cache to improve processing speed and performance. Operating at 1.79 DMIPS/MHz, this processor can exceed 450 MHz in a 65 nm technology, delivering substantial computational capability with a relatively low energy footprint. Optimized for rapid data access and execution, the BA22-CE incorporates a sophisticated cache system that enhances its operational efficiency. With a gate count of under 20,000 and power usage as low as 0.05 W/MHz, this processor effectively balances performance demands with energy conservation. This processor is particularly well-suited for applications that require frequent data retrievals, benefiting from the reduced latency that comes with its advanced cache design, making it a key choice for developers focusing on performance-centric tasks without excessive power consumption.
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