All IPs > Interface Controller & PHY > D2D
Device-to-Device (D2D) communication is a critical component in modern electronics, enabling direct interaction between devices without intermediary network infrastructure. Within our Interface Controller & PHY category, the D2D segment offers specialized semiconductor IPs designed to streamline and enhance these direct connections. These IPs are indispensable in creating an efficient communication link that can handle the increasing data demands seen in consumer electronics, automotive systems, and IoT devices.
Our D2D semiconductor IPs consist of essential building blocks such as interface controllers and Physical Layer (PHY) IP cores. These components are engineered to facilitate seamless communication between devices, whether it be for transferring data, synchronizing functions, or sharing resources in real-time. By leveraging these IPs, manufacturers can achieve low latency, high-speed data transfer, and robust connectivity, making these components suitable for applications requiring precise and rapid interaction.
Incorporating D2D IPs into your design allows for efficient use of bandwidth and power, critical factors in battery-operated or compact devices. The versatility of these semiconductor IPs makes them a popular choice in developing smart home devices, wearables, and vehicle infotainment systems, where direct and reliable device-to-device communication is paramount. These IPs also help minimize reliance on external network structures, providing a more secure and localized network environment.
The D2D interface controller and PHY IPs in our collection are developed to cater to the demanding needs of modern technological solutions. Whether you are designing a new IoT ecosystem or enhancing an automobile's connectivity suite, selecting the right D2D IP core can significantly impact your product’s performance and user experience. Explore our offerings to find the IP solutions that best align with your innovation goals, ensuring your devices communicate effectively and efficiently.
The CXL 3.1 Switch by Panmnesia is a high-performance solution facilitating flexible and scalable inter-device connectivity. Designed for data centers and HPC systems, this switch supports extensive device integration, including memory, CPUs, and accelerators, thanks to its advanced connectivity features. The switch's design allows for complex networking configurations, promoting efficient resource utilization while ensuring low-latency communication between connected devices. It stands as an essential component in disaggregated compute environments, driving down latency and operational costs.
The NuLink Die-to-Die PHY for Standard Packaging is a cutting-edge interconnect solution that bridges multiple dies on a single standard package substrate. This technology supports numerous industry standards, including UCIe and BoW, and adapts to both advanced and conventional packaging setups. It enables low-power, high-performance interconnections that are instrumental in the design of multi-die systems like SiPs, facilitating bandwidth and power efficiencies comparable to that of more costly packaging technologies. Eliyan's PHY technology, distinctive for its innovative implementation methods, offers similar performance attributes as advanced packaging alternatives but at a fraction of the thermal, cost, and production time expenditures. This design approach effectively utilizes standard packages, circumventing the complexities associated with silicon interposers, while still delivering robust data handling capabilities essential for sophisticated ASIC designs. With up to 64 data lanes, and operating at data rates that reach 32Gbps per lane, the NuLink Die-to-Die interconnect elements ensure consistent performance. Such specifications make them suitable for high-demand applications requiring reliable, efficient data transmission across multiple processing elements, reinforcing their role as a fundamental building block in the semiconductor landscape.
MAXVY UCIe VIP , a state-of-the-art solution that offers a comprehensive set of features and capabilities to ensure the quality and performance of your UCIe designs. MAXVY UCIe VIP is fully compliant with UCIe Specification version 1.0 and supports all the layers of the UCIe stack, such as FDI, RDI, LogPHY, PCIe, and CXL protocols. MAXVY UCIe VIP is also very user-friendly and flexible, with simple APIs, easy integrations, and configurable parameters. You can easily customize and control the UCIe functionality according to your needs. MAXVY UCIe VIP also provides a rich set of verification capabilities, such as protocol checks, functional coverage, traffic generation, error injection, and debug tools. You can easily monitor, detect, and report any issues or violations in your UCIe designs. MAXVY UCIe VIP is compatible with the industry-standard Universal Verification Methodology (UVM) and supports all leading simulators. With MAXVY UCIe VIP, very flexible for unit level testing, you can achieve faster verification closure and higher quality of your UCIe designs.
The CT25205 is a comprehensive digital core designed for IEEE 802.3cg® 10BASE-T1S Ethernet applications, incorporating the Physical Medium Attachment (PMA), Physical Coding Sublayer (PCS), and Physical Layer Coordination (PLCA) Reconciliation Sublayers. Written in Verilog 2005 HDL, this IP core is versatile enough to be implemented in standard cells and FPGA systems. It interfaces seamlessly with IEEE Ethernet MACs through a Media Independent Interface (MII), and the PLCA RS supports legacy MACs, enhancing functionality without additional extensions. The PMA is compatible with OPEN Alliance 10BASE-T1S PMD, perfect for Zonal Gateways and MCUs in advanced network architectures.
The ePHY-5616 is a high-performance SerDes solution from eTopus, designed for versatile use across enterprise, data center, and 5G applications. Operating efficiently at data rates from 1 to 56 Gbps, this product exploits advanced DSP techniques for superior signal integrity and robustness. It accommodates wide insertion loss ranges of 10dB to over 35dB, thus ensuring reliable performance in challenging communication environments. Its architecture supports direct optical drives and quad/octal configurations, making it ideal for network interface cards, routers, and high-speed switches in a data center setup. The embedded DSP architecture is developed with eTopus's proprietary algorithms, which enable rapid SerDes tuning and performance optimization. The ePHY-5616 is also characterized by its low Bit Error Rate (BER), ensuring data reliability and integrity. Moreover, it supports multiple protocols, including Ethernet and PCIe, enhancing its integration potential in modern broadband networks.
The Die-to-Die (D2D) Interconnect solution from SkyeChip optimizes intra-package communication channels between dies. Tailored for cutting-edge, multi-die applications, this lightweight interconnect solution includes a physical layer and protocol adaptations to seamlessly extend existing NOC capabilities across different die frames. Conforming to the Universal Chiplet Interconnect Express (UCIe) standards, it supports a high throughput of up to 32 Gbps per pin, ensuring efficient data migration across interconnected dies. With built-in self-test and repair functionalities, this D2D interconnect offers not only high performance but also increased reliability and diagnostic capabilities necessary for advanced chiplet designs.
YouSerdes by Brite Semiconductor is a versatile multi-rate serializer/deserializer solution, capable of handling data transfer speeds from 2.5Gbps to 32Gbps. It is known for its superior performance, compact area usage, and power efficiency among its peers. The IP is designed to accommodate a wide array of interfaces, including but not limited to PCIe Gen 4.0/3.0/2.0/1.0, USB 3.1/3.0, and various SATA and XAUI implementations. Its architecture supports dynamic reconfiguration, allowing flexible channel arrangements and optimal resource utilization. The core design of YouSerdes optimizes the use of high-performance physical layers to ensure reliable data throughput across different applications. The solution features internal clock generation that eliminates the need for additional components, simplifying design efforts and reducing associated costs. Moreover, the architecture supports diverse protocols while maintaining compliance with industry standards, ensuring broad applicability. Designed for robust applications, YouSerdes is suitable for implementations in data centers, enterprise networks, and high-speed computing environments where efficiency and performance cannot be compromised. Its ability to seamlessly interface with multiple protocols in a single design makes it an attractive choice for multi-functional devices requiring adaptive data processing capabilities.
YouSerdes by Brite Semiconductor is a versatile multi-rate serializer/deserializer solution, capable of handling data transfer speeds from 2.5Gbps to 32Gbps. It is known for its superior performance, compact area usage, and power efficiency among its peers. The IP is designed to accommodate a wide array of interfaces, including but not limited to PCIe Gen 4.0/3.0/2.0/1.0, USB 3.1/3.0, and various SATA and XAUI implementations. Its architecture supports dynamic reconfiguration, allowing flexible channel arrangements and optimal resource utilization. The core design of YouSerdes optimizes the use of high-performance physical layers to ensure reliable data throughput across different applications. The solution features internal clock generation that eliminates the need for additional components, simplifying design efforts and reducing associated costs. Moreover, the architecture supports diverse protocols while maintaining compliance with industry standards, ensuring broad applicability. Designed for robust applications, YouSerdes is suitable for implementations in data centers, enterprise networks, and high-speed computing environments where efficiency and performance cannot be compromised. Its ability to seamlessly interface with multiple protocols in a single design makes it an attractive choice for multi-functional devices requiring adaptive data processing capabilities.
eTopus's ePHY-11207 stands out in their SerDes lineup by achieving data rates up to 112 Gbps, a leap forward for scenarios demanding ultra-high bandwidth and low-latency communication. Constructed on a 7nm platform, this product is tailored for state-of-the-art applications in both enterprise and advanced data center environments. The architecture of the ePHY-11207 is conducive to handling extensive insertion loss ranges and high-sensitivity demands typical of contemporary optical and copper interconnects. Its adaptability is further enhanced by embedded proprietary DSP algorithms that permit fine-tuning of performance in sub-millisecond timeframes, a feature that assures operational stability even amidst jitter-inducing environments. In addition to backing numerous protocols such as Ethernet and PCIe, the ePHY-11207's low BER and extensive diagnostic capabilities make it a prime candidate for rapid deployment in high-density network settings. Such versatility not only supports robust infrastructure but also enhances overall throughput efficiency.
The ARINC 818 Streaming IP Core is engineered to deliver real-time streaming conversion between a pixel data bus and an ARINC 818 formatted Fibre Channel (FC) serial data stream, or vice versa. This core is pivotal in applications where precision and timing are critical, providing efficient data handling for high-resolution display systems commonly used in avionics. Tailored for flexibility, this IP core supports bidirectional conversion, which provides seamless integration into existing infrastructure, enhancing both legacy systems and new installations. By handling ARINC 818 formatted FC data, it ensures consistent and accurate data synchronization, making it ideal for mission-critical aerospace applications. This IP core excels in environments requiring advanced data processing and synchronization. Its design minimizes latency while maximizing throughput, ensuring high-quality transmission and reception of visual data. The ARINC 818 Streaming IP Core is a vital asset in enhancing the performance and reliability of communication and display systems in complex aerospace technologies.
The ARINC 818 Direct Memory Access (DMA) IP Core is specifically designed to optimize data transaction processes within ARINC 818 protocols, particularly emphasizing receipt and transmission efficiency. This core is an essential component for embedded applications where offloading of formatting, timing, and buffer management is crucial for operational success. Ideal for avionics applications, the core simplifies integration by efficiently managing data transfer operations between system nodes through coordinated DMA mechanisms. It provides a streamlined hardware solution, reducing the overhead typically associated with direct memory operations and improving the overall system performance. Built with scalability in mind, the ARINC 818 DMA IP Core supports various data rates and configurations, enhancing its adaptability to different system architectures. By minimizing CPU intervention in data handling, it increases processing efficiency, further ensuring high-speed data handling with minimal delay or disruption.
InnoSilicon's 56G SerDes Solution is crafted to address the growing need for high-bandwidth data transmission in data centers, telecommunications, and enterprise network infrastructures. SerDes, or Serializer/Deserializer technology, is crucial for enhancing data throughput and reducing latency, making it ideal for high-speed network operations. Designed to support multiple protocols including PCIe, Ethernet, and beyond, the 56G SerDes solution provides flexibility and robustness required by modern communication systems. Its high data rates allow for rapid data exchange that meets the demands of high-performance computing environments. This makes it an essential component in systems requiring extensive data processing capabilities. The architecture of the 56G SerDes combines low power consumption with high throughput, making it suitable for applications that require energy efficiency without compromising on speed. Its design incorporates advanced signal processing techniques to maintain data integrity, offering a reliable solution that scales with the requirements of evolving technologies.
APIX3 represents the latest evolution in high-speed data transmission modules, engineered specifically for automotive infotainment and cockpit architectures. Designed to interface seamlessly within vehicle IT landscapes, it supports transmissions up to 12 Gbps using shielded or quad twisted pair cables. APIX3 offers unique capabilities like multiple video stream handling on a single connection and supports advanced diagnostics, including cable health checks for predictive maintenance. This technology is backward compatible with APIX2, enhancing modular flexibility across previous and new vehicle designs. With support for UHD automotive display resolutions, APIX3 ensures all-in-one connectivity solutions for complex exterior and interior automotive systems. The APIX3 modules enable comprehensive networking through various serial interface protocols and are positioned as go-to solutions for future-proofing in-car data systems. Each channel within APIX3 is fine-tuned for specific needs, from video data handling to full-duplex telecommunications. Additionally, APIX3 supports Ethernet connectivity for seamless integration into the larger automotive communication network. Thanks to its efficient design, APIX3 provides stability and enhanced bandwidth support, delivering robust performance suited for both entry-level and high-end automotive systems.
The BlueLynx Chiplet Interconnect is a sophisticated die-to-die interconnect solution that offers industry-leading performance and flexibility for both advanced and conventional packaging applications. As an adaptable subsystem, BlueLynx supports the integration of Universal Chiplet Interconnect Express (UCIe) as well as Bunch of Wires (BoW) standards, facilitating high bandwidth capabilities essential for contemporary chip designs.\n\nBlueLynx IP emphasizes seamless connectivity to on-die buses and network-on-chip (NoCs) using standards such as AMBA, AXI, and ACE among others, thereby accelerating the design process from system-on-chip (SoC) architectures to chiplet-based designs. This innovative approach not only allows for faster deployment but also mitigates development risks through a predictable and silicon-friendly design process with comprehensive support for rapid first-pass silicon success.\n\nWith BlueLynx, designers can take advantage of a highly optimized performance per watt, offering customizable configurations tailored to specific application needs across various markets like AI, high-performance computing, and mobile technologies. The IP is crafted to deliver outstanding bandwidth density and energy efficiency, bridging the requirements of advanced nodal technologies with compatibility across several foundries, ensuring extensive applicability and cost-effectiveness for diverse semiconductor solutions.
Wormhole is a versatile communication system designed to enhance data flow within complex computational architectures. By employing state-of-the-art connectivity solutions, it enables efficient data exchange, critical for high-speed processing and low-latency communication. This technology is essential for maintaining optimal performance in environments demanding seamless data integration. Wormhole's ability to manage significant data loads with minimal latency makes it particularly suitable for applications requiring real-time data processing and transfer. Its integration into existing systems can enhance overall efficiency, fostering a more responsive computational environment. This makes it an invaluable asset for sectors undergoing digital transformation. The adaptability of Wormhole to various technological requirements ensures it remains relevant across diverse industry applications. This flexibility means that it can scale with ongoing technological advancements, cementing its role as a cornerstone in the evolving landscape of high-speed data communications.
The Universal Chiplet Interconnect Express (UCIe) by Extoll is a cutting-edge technology designed to meet the increasing demand for seamless integration of chiplets within a system. UCIe offers a highly efficient interconnect framework that underpins the foundational architecture of heterogeneous systems, enabling enhanced interoperability and performance across various chip components. UCIe distinguishes itself by offering an ultra-low power profile, making it a preferred option for power-sensitive applications. Its design focuses on facilitating high bandwidth data transfer, essential for modern computing environments that require the handling of vast amounts of data with speed and precision. Furthermore, UCIe supports a diverse range of process nodes, ensuring it integrates well with existing and emerging technologies. This innovation plays a pivotal role in accelerating the transition to advanced chiplet-based architectures, enabling developers to create systems that are both scalable and efficient. By providing a robust interconnect solution, UCIe helps reduce overall system complexity, lowers development costs, and improves design flexibility — making it an indispensable tool for forward-thinking semiconductor designs.
The CXL 3.0 solution from Rapid Silicon is an advanced Controller IP designed to enhance your FPGA design with superior performance and flexibility. This IP is compliant with CXL specifications up to version 3.0, along with support for earlier versions 2.0, 1.1, and 1.0. It offers seamless integration capabilities with PCIe, standing up to PCIe 6.0 and ensuring backward compatibility. The architecture of the CXL Controller IP is highly configurable, providing adaptability for specific application requirements, including lane configurations, datapath widths, and efficiency in power management. One of the standout features of the CXL 3.0 IP is its support for advanced functionalities such as lane bonding, multicast, and robust error correction mechanisms. These features ensure the IP delivers reliable and efficient performance in diverse environments. Ideal for critical data-intensive tasks, the IP is suited for telecommunications, industrial applications, and more, where data throughput and protocol bridging are crucial. With its focus on delivering unmatched speed, efficiency, and scalability, the CXL 3.0 IP from Rapid Silicon is positioned as a key component for enabling sophisticated FPGA designs tailored to meet modern technology demands. Its architecture is crafted to support the burgeoning needs of applications that require high degrees of data handling and processing accuracy, making it a preferred choice in the semiconductor industry.
The UCIe Chiplet Interconnect offered by InnoSilicon is a core solution for developers aiming to enhance system modularity and integration. This interconnect standard is crucial for designers focusing on enhancing chip-to-chip communication within complex multi-die architectures. It is particularly effective for next-gen applications in AI, cloud computing, and high-performance computing systems. Enabled by Innolink technology, InnoSilicon's UCIe Chiplet Interconnect facilitates high bandwidth and low latency interconnections. It supports various protocols and helps companies achieve a coherent design ecosystem, which allows for efficient scaling and upgrading of systems. This solution is an enabler for the transition towards chiplet-based design paradigms, offering improvements in power efficiency and overall performance. As chiplet architecture becomes more prevalent, the UCIe Chiplet Interconnect enables system designers to better manage power and performance trade-offs. By allowing different chiplets to communicate seamlessly, this interconnect solution supports the integration of heterogeneous processing elements, boosting the versatility and capability of emerging electronic systems.
The Photowave optical communications hardware is specifically engineered for disaggregated AI memory applications, offering compatibility with PCIe 5.0/6.0 and CXL 2.0/3.0 standards. With its focus on leveraging photonic technology, Photowave aims to provide substantial improvements in latency and energy efficiency, which are critical parameters in modern data center operations. This hardware enables seamless scaling of resources, ensuring that data flows efficiently across server racks within a data center environment. By incorporating photonics, Photowave optimizes communication channels to handle large volumes of data at high speeds, effectively reducing bottlenecks typically seen in electronic systems. This innovation is crucial for data center managers looking to enhance system performance without a commensurate increase in power consumption or heat generation, thereby maintaining a sustainable operational environment. With its robust design, Photowave ensures reliability and stability in managing complex data interactions within AI frameworks. It represents a paradigm shift in how data centers can manage and process information, highlighting the strategic importance of photonics in enhancing computational infrastructures. As industries continue to move towards more data-intensive processes, Photowave offers a future-proof solution that aligns seamlessly with the evolving needs of high-tech environments.
VITA 17.3 Serial FPDP Gen3 solution is engineered for next-generation serial communication systems, supporting intensive data transfer operations across numerous applications. Known for its stability and excellent throughput capabilities, this IP empowers efficient and robust operations even at the extremes of performance envelopes. StreamDSP's design ensures integration simplicity and operational reliability within various FPGA environments. The IP provides configurable options for data path flow, alignment precision, and ensures resilience with its comprehensive error detection and correction functionality. This adaptability makes it an ideal choice for advanced applications that demand spotlight focus on data accuracy and speed. As contemporary data-driven processes expand, the need for such adaptable, high-speed data solutions becomes paramount, and the VITA 17.3 Serial FPDP Gen3 solution meets these needs admirably.
The JESD204B Multi-Channel PHY is a high-performance interface solution designed to support the latest JESD204B standard. It facilitates efficient high-speed data transmission with a peak rate of 12.5Gbps and is built to handle complex data flow configurations, ensuring reliable and consistent communication. The PHY features robust support for deterministic latency, SYSREF synchronization, and additional functionalities that enhance data integrity and system coherence. Tailored for versatile deployment, this PHY core integrates seamlessly into numerous applications requiring precise data handling and speed. It includes support for 8b/10b encoding/decoding and scrambling to ensure signal quality and minimize error rates. The design accommodates both independent transmit and receive operations, providing flexibility in various system architectures. Manufactured with compatibility for multiple process nodes, including 65nm, 55nm, 40nm, and 28nm, the JESD204B PHY demonstrates significant adaptability across different manufacturing processes. This adaptability, coupled with systematic process support, positions the JESD204B Multi-Channel PHY as an optimal choice for advanced communication systems striving for enhanced performance and reliability.
The ePHY-5607 by eTopus is a versatile SerDes component operating at data rates between 1 to 56 Gbps, optimized for power, performance, and area (PPA) in a 7nm process environment. These features make it exceptionally suitable for modern data centers and AI applications, where space and energy efficiency are paramount. This component boasts superior BER and rapid Clock Data Recovery (CDR), ideal for high-speed optical and electrical interfaces. Its robust architecture is designed to minimize temperature-induced performance variations, which is crucial in maintaining consistent performance in data-dense environments. The ePHY-5607 enables scalable insertion loss, ensuring it can accommodate varying signal degradation scenarios in infrastructure deployments. Applications for the ePHY-5607 span enterprise networking and high-performance computing, addressing the critical needs for reduced latency and improved signal integrity.
The NuLink Die-to-Memory PHY products are exemplars of Eliyan’s innovative approach to overcoming traditional memory bandwidth limitations. These solutions provide critical interconnectivity between die and memory components within standard packaging frameworks, promoting both low power consumption and high throughput. These PHYs are strategically designed to complement diverse memory configurations, thereby enhancing overall system performance. Unlike fixed-direction interconnect options, Eliyan's NuLink technology supports dynamic communication with bidirectional capabilities. This allows an efficient balance between power savings and robust performance outcomes, while seamlessly integrating into existing package formats to maintain standardization and economic efficiencies. An alignment with industry standards, such as UCIe, underscores the NuLink Die-to-Memory solutions' versatility and adaptability across different sectors. Their dynamic capabilities make them ideal for applications that demand high-density, speed-sensitive memory interactions, providing an essential tool in the engineering of powerful, multi-die assemblies with optimized thermal and cost profiles.
The Interconnect Generator developed by Dyumnin Semiconductors is designed to construct protocol-agnostic interconnects capable of supporting AXI and OCP master/slave configurations. This generator allows for flexibility in the creation of interconnects that can be simple, pipelined, or crossbar. Additionally, it manages varying protocol behaviors, ranging from atomic transactions to split transactions with independent address and data phases. The built-in reorder buffer provides configurable depth, allowing for multiple outstanding requests while ensuring data is delivered in sequence.
The Chiplet Interface solutions provided by Neuron IP include cutting-edge PHY & D2D Adapter IP for chiplet products. These solutions are built around the latest UCIe v1.1 specification and are designed to support a wide range of application verticals. They are well-known for their unparalleled PPA-differentiated architecture, which includes 32Gbps UCIe-Advanced and Standard cores. These interfaces are set to revolutionize the way microprocessors work in ultra-low latency environments, enhancing both performance and efficiency.
Glasswing is a high-performance ultra-short reach SerDes solution that capitalizes on the power of CNRZ-5 Chord Signaling to deliver double the bandwidth with half the power compared to traditional solutions. It supports scalable, high-throughput connectivity tailored for applications in AI, ML, and data center environments. Glasswing is renowned for its high bandwidth efficiency, offering 500 Gbit/s per pin and achieving a bandwidth of up to 1 Tbps at under 1 Watt. Its versatile design allows for flexible chip assembly without the need for silicon interposers, making it an economical choice for complex multi-chip modules (MCMs).
The VITA 17.1 Serial FPDP Solution from StreamDSP is expertly crafted for high-speed serial data transmission, which is pivotal for real-time applications demanding reliable and continuous data handling. This IP solution supports seamless integration with popular FPGA platforms, enhancing performance without sacrificing flexibility. Whether for streaming, high-throughput scientific computations, or any number of real-time processing requirements, this IP core ensures low-latency and high-bandwidth data transfers. Besides, it offers advanced data handling features, including programmable data alignment, flexible data path configurations, and comprehensive error detection capabilities, thereby optimizing the core for diverse high-speed data tasks. With its versatile configuration options, the VITA 17.1 Serial FPDP Solution simplifies the manageability of complex system environments, providing a robust foundation for any high-performance digital system.
The Time Sensitive Network IP Core is an advanced solution explicitly crafted to support time-critical network environments. It offers remarkable precision and fault tolerance, making it ideal for applications where timing accuracy is paramount. Capable of scaling from 1Gbps to 10Gbps, this core is engineered to provide robust anti-masquerading and babbling protection functions. Integrated with the widely adopted AXI standard, the network core facilitates easy interfacing between hardware and software, which is essential for developers looking to integrate it within diverse systems efficiently. This ease of integration is coupled with its fault tolerance capabilities, ensuring network reliability in complex deployments. Applications that significantly benefit from this IP core include industrial automation, telecommunications, and any domain requiring synchronized processing and high-reliability data exchange. The Time Sensitive Network IP Core is invaluable in enhancing system efficiencies and ensuring data integrity across demanding operational environments.
The Prodigy FPGA-Based Emulator from Tachyum is designed to offer a testing and evaluation platform for their innovative Prodigy processors. This hardware emulator is essential for potential customers looking to assess performance metrics, software development, and ensuring compatibility. This FPGA-based platform is structured with several FPGA and IO boards interconnected, simulating multiple processing cores that include both vector and matrix processing capabilities. The emulator offers a robust environment for debugging and evaluating performance in real-time without the risk associated with proprietary or regulated data, ensuring a safe testing zone. Such a system is an invaluable resource for organizations that aim to validate their systems and software prior to full-scale deployment, making it possible to experience the Prodigy architecture's full capabilities in advance.
FireCore is a leading solution within the domain of synthesizable IEEE-1394-2008 components, integrating both PHY and Link Layer Controller functionality in a single product. Geared to support data rates from S100 up to S3200, it seamlessly combines the data capture, verification, and analysis strengths into one robust engine. FireCore enhances flexibility through various host interface options and PIN density configurations, making it suitable for diverse applications such as avionics and multimedia. FireCore's architecture is aimed at isolating the usual issues associated with off-the-shelf silicon and providing complete control over customization and optimization in-field. This means that users can readily adapt and upgrade their systems as needed, without the usual port, speed, or version constraints typical of commercial solutions. Key features include powerful error-handling, efficient bus management, flexible host connectivity, and both isochronous and asynchronous packet types, all with fast virtual-path computations. A further advancement is the AS5643 integration, which allows the device to support highly demanding aerospace and defense systems. Through direct support for the Mil1394 protocol, FireCore can be tailored for systems that demand reliability and precision, impacting sectors needing meticulous testing and sophisticated network architecture management.
The Evo Gen 5 PCIe Card is specifically crafted for AI inferencing tasks, aiming to enhance performance while optimizing power consumption. This card is a formidable tool in enabling enterprises to address the growing demand for AI inference capabilities, leveraging the Gen 5 architecture to deliver unparalleled speeds in processing AI tasks. Designed with flexibility in mind, the Evo Gen 5 easily slots into existing IT infrastructures, ensuring minimal disruption while significantly boosting computing capabilities. With its advanced architecture, it supports complex AI workloads, allowing businesses to explore AI applications with greater confidence and capability. The Evo Gen 5 PCIe Card is particularly beneficial for industries looking to handle large volumes of data swiftly and accurately, facilitating real-time AI analysis and boosting productivity through improved inference rates. Its efficient design ensures that energy costs are kept low, making it a cost-effective addition to any AI-driven enterprise.
AresCORE is a revolutionary PHY designed for UCIe (Universal Chiplet Interconnect Express) die-to-die connections, offering ultra-low power and latency solutions for connecting chips within the same package. This innovative PHY supports significant bandwidth capabilities, making it an ideal choice for performance-driven applications such as AI, HPC, and advanced computing. The design ensures minimal energy consumption while maintaining exceptional throughputs, allowing for efficient data routes between dies. One of the notable features of AresCORE is its compatibility with the latest inter-die communication standards, ensuring it meets current and emerging requirements for high-speed connectivity. It employs advanced signaling techniques to prevent data loss and ensure consistent throughput even under extensive usage scenarios. Its ability to integrate seamlessly into next-gen chiplet structures allows manufacturers to utilize AresCORE for a variety of platform-specific applications, supporting both bandwidth-intensive and power-sensitive projects. As devices become more heterogeneous, AresCORE positions itself as a critical component facilitating robust, intra-package communication and promoting scalability in electronic product designs.
Designed for high-performance and efficiency, the High-speed LVDS Solutions provide a robust differential signaling interface capable of operating frequencies up to 1 GHz. The module includes driver and receiver components optimized for low power consumption and operates from a 1.8V I/O power supply while maintaining core supply voltages within the 1.0V to 1.1V range. Featuring integrated low power consumption and a versatile common mode range, these solutions are perfectly designed for environments requiring reliable and high-speed data transmission. The LVDS driver is capable of handling 50Ω and 100Ω differential termination, supporting a wide range of data throughput requirements, which makes it suitable for modern high-speed circuit designs. Aragio Solutions ensures that these LVDS solutions are compliant with the IEEE standards, providing a reliable framework for both input and output components. Silicon validation ensures that the implementations are production-ready and can be easily integrated into a variety of applications demanding high-speed data transfer coupled with low energy consumption.
5G technology heralds a new era in mobile connectivity by significantly enhancing wireless data capacity and opening new possibilities in smart applications like autonomous vehicles and remote surgery. Faststream Technologies approaches the evolution from 4G to 5G with robust innovations in base stations, core networks, and RAN management systems. They strategically invest in key 5G technologies, differentiating their offerings and ensuring their position in the fast-evolving 5G ecosystem. Open RAN principles allow mobile networks to break free from traditional vendor dependencies, promoting a competitive landscape that fosters innovation and cost reduction through interoperability of hardware and software. The core component of a 5G network is its macrocell, a critical RAN ingredient that supports cellular network radio coverage. Utilizing Multiple Input, Multiple Output (MIMO) technology, 5G macrocells provide extensive radio signal transmission and reception capabilities, connecting billions of devices with minimal latency. This allows for broad data capacity and reduced network costs. Faststream's 5G base station solutions also involve intricate orchestration between central (CU) and distributed units (DU), leveraging FPGAs, network synchronization ICs, and precision oscillators. Such architecture not only meets the complex power and bandwidth requirements of modern telecom infrastructures but also addresses future needs with expandable capabilities for new applications.
The Regli PCIe Retimer is designed for high signal integrity and low latency in PCIe and CXL environments. It operates with a sub-10 nanosecond latency and maintains an impressive error rate of 1E-12, making it one of the fastest PCIe retimers available. This product supports PCIe 5.0 and CXL 2.0, offering extended system reach and improved signal integrity. With multiple control interfaces and support for secure boot, the Regli Retimer is ideal for high-speed data applications and is particularly suited for networking equipment and hyperscale data centers requiring longer distances and low-latency communications.
Sofics has verified its TakeCharge ESD protection clamps on technology nodes between 0.25um CMOS down to 3nm across various fabs and foundries. The ESD clamps are silicon and product proven in more than 5000 mass produced IC-products. The cells provide competitive advantage through improved yield, reduced silicon footprint and enable low-leakage, high-speed or high voltage tolerant interfaces. The ESD protection described in this document can be used for 1.6V chiplet (die-2-die) interface pads in the GF 22nm FDX technology. The ESD robustness is strongly reduced in order to reduce the size and capacitance.
GammaCORE serves as a leading-edge UCIe Die-to-Die controller, engineered for optimum efficiency in facilitating communication between chiplets in a package. With the rise of heterogeneous chip design, GammaCORE ensures seamless high-speed connectivity across silicon dies, enhancing interoperability within chiplet architectures. Specifically tailored for contemporary computing environments that demand high fidelity data exchange, GammaCORE's advanced control mechanisms guarantee data integrity and system robustness. It supports multiple interface protocols, ensuring that data flow remains consistent and efficient regardless of operational stressors or applications. The controller's design is aligned with the future of chiplet-based systems, making it an invaluable component in the evolution of modern computing. As device integration becomes progressively more complex, GammaCORE sustains the momentum of innovation by providing stable, high-efficiency data paths that can support the expansive bandwidth needs of today's tech landscape.
Actt's SerDes IP supports a variety of high-speed interface protocols such as USB, PCIe, and SATA, underscoring its adaptability and high-performance characteristics. The IP is engineered to facilitate seamless data communication across integrated circuits, crucial for applications necessitating speed and reliability.
The Automotive Multigigabit Ethernet Switch by Broadcom integrates advanced security protocols with high-speed data transmission capabilities, tailored specifically for the automotive sector. This switch supports multi-layered security features, ensuring safe and efficient communication across the vehicle's network. Engineered for modern automotive needs, this device facilitates seamless connectivity, boasting compatibility with current and emerging automotive standards. Its multigigabit throughput capacity addresses the growing demand for in-vehicle data exchange, providing the backbone infrastructure for connected and autonomous vehicle features. Broadcom's automotive Ethernet switch offers robust performance with low latency and high reliability, critical for safety and infotainment systems. Its scalable design ensures future-proofing, allowing for integration into evolving automotive technologies while maintaining stringent security measures against cyber threats.
ChipBridge provides a robust solution for extending AXI4 connectivity between chips, enabling a master FPGA or ASIC to control peripherals on a connected slave FPGA seamlessly. It offers a streamlined way to manage signal extension, overcoming challenges present in traditional designs, such as limited pin availability and complex wiring schemes. This IP requires only a couple of transceiver pairs and utilizes high-speed links for effective data management across devices. Designed to work with a variety of physical link protocols, ChipBridge ensures consistent communication between devices by capitalizing on the AXI4 standard, retaining high data throughput and low latency. The approach enables the physical separation of functions without compromising on performance, which is essential in optimizing design architecture while maintaining desirable speeds. ChipBridge has been developed to cater to Lattice and other popular FPGA brands. Its robust architecture facilitates a diverse range of applications, including those that confront real-world interface challenges, such as ESD protection and voltage level translation. Adopting such IP ensures that applications maintain their pace and precision by simplifying how peripherals are managed and interfaced with central control units.
The 32G UCIe PHY from GUC supports the UCIe 2.0 specification, achieving top speeds of 32Gbps per lane with high bandwidth density. Designed for advanced applications in AI, HPC, and complex networking environments, it utilizes TSMC's N3P process and CoWoS technology to interconnect multiple dies in a unified package. It features advanced monitoring and self-healing capabilities to ensure continuous, optimum performance. The IP supports dynamic voltage and frequency scaling and advanced preventive monitoring, enhancing system reliability.
CoaXPress is a leading standard for high-speed imaging applications, widely adopted across industrial vision, medical, and broadcast sectors. The CoaXPress Device & Host IP developed by EASii IC supports multi-stream and multi-device configurations, offering exceptional flexibility with bit rates up to 100 Gbps, fulfilling the demanding needs of modern high-resolution imaging tasks. The system enhances video transmission reliability with extensive interoperability with imaging peripherals, equipped with GenICam-compliant interfaces for seamless integration.
Aimed at high-speed data communication, the Aurora 64B/66B protocol supports chip-to-chip, board-to-board, and backplane applications. ALSE's implementation of the Aurora 64B/66B Core is notable for its compact and optimized design, offering increased compatibility and functionality without the trade-offs commonly seen in other designs. Fully interoperable with Xilinx IP cores, it has been thoroughly tested to ensure seamless integration across multiple platforms. One of the key advantages of the 64B/66B encoding is the improved bandwidth efficiency — up to 97% in comparison to 8B/10B's 80%. This provides an effective means for intra-board communications at higher rates, making it indispensable for cutting-edge applications and next-gen systems. Designed for FPGA platforms ranging from Intel's Stratix devices to Lattice's PolarFire, it has proven to be versatile for varied design needs, ensuring that the IP can cater to both FPGA and ASIC environments. Supporting up to 16 lanes per instance, the IP includes features such as full-duplex operation, framing and streaming interfaces, and native flow control. These capabilities make it an excellent choice for systems looking to leverage high-speed serial data paths efficiently. Incorporating reliability and performance, the Aurora 64B/66B Core stands as a valuable asset in modern high-demand data environments.
JESD204 is a serial data interface standard specifically crafted for high-speed ADC and DAC connectivity. The JESD204 IP from ALSE provides a robust solution for efficiently managing high-speed mixed signal data communication. Designed in line with the JEDEC committee's standards, it caters to the latest needs in serial data transmission, offering a framework for high-precision data acquisition with reduced pin requirements and proven reliability. Beyond basic data transfer, JESD204 ensures meticulous synchronization, vital for applications utilizing multiple ADCs or DACs. By structuring fields like frame and multiframe, it provides deterministic latency, precision time alignment, and the integration of multiple data lanes, guaranteeing performance under varied conditions. The latest versions, such as JESD204C, improve encoding efficiency and data rate capabilities, catering to more advanced devices while ensuring backward compatibility. ALSE's implementation extends across numerous FPGA platforms, ensuring adaptability and long-term application flexibility. The IP accommodates diverse ethernet requirements through comprehensive features such as scrambling and character alignment while maintaining simplicity in hardware use. With the growing complexity of modern electronics, JESD204's sophisticated approach to high-speed data interfacing makes it indispensable for developers seeking superior performance in demanding environments.
The Aurora 8B/10B Core facilitates high-speed serial communication suitable for various chip-to-chip and board-to-board applications. An open protocol, it is designed to offer low latency and efficient data transit across a range of systems. Unlike other protocols, Aurora 8B/10B enables high-speed interconnection without necessitating a processor or complex setup, making it a favorable choice for efficient data linkage across devices by minimizing the resource footprint. This IP is fully compatible with Xilinx Logicore IP, extending its utility to cover an extensive variety of FPGA platforms, including Altera/Intel, Lattice, and Microchip. It's engineered to work seamlessly with hardware from varied FPGA vendors, providing interoperability that ensures sustained service across multiple platforms. The design supports full-duplex, simplex Tx, and Rx operations, with operating speeds demonstrated at up to 6.6 Gbps per lane, depending on the transceiver core specifications of the FPGA. The Aurora 8B/10B Core can accommodate multiple transceiver lanes, providing scalable options for integrating into larger systems where data throughput is crucial. Paired with low power consumption and requiring minimal resources, it is an excellent choice for applications demanding high reliability and performance in constrained environments. This makes it particularly well-suited for communication-intensive applications spanning industrial and consumer markets.
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