All IPs > Interface Controller & PHY > AMBA AHB / APB/ AXI
AMBA, which stands for Advanced Microcontroller Bus Architecture, is a far-reaching and well-established open-standard, on-chip interconnect specification used widely in the design and structuring of system-on-chip (SoC) technologies. Among the most popular protocols under this architecture are AHB (Advanced High-performance Bus), APB (Advanced Peripheral Bus), and AXI (Advanced eXtensible Interface). These protocols facilitate effective communication between various components of a digital system, ensuring optimal performance and scalability.
**AHB, APB, and AXI Semiconductor IPs**
*AMBA AHB* is specifically designed for high-performance and high-bandwidth requirements. It's a parallel bus interface that is commonly employed for connecting processors and other high-speed components in a SoC. AHB IPs ensure that data is transferred efficiently across the components, making them ideal for applications where speed and reliability are crucial.
*AMBA APB* is tailored for low power and less complex communication needs. It is often used for interfacing with peripheral devices that do not require high throughput, such as UARTs or low-speed memory controllers. APB semiconductor IPs are valued for their simplicity and low power consumption, often being the choice for battery-operated or portable devices.
*AMBA AXI* is characterized by its advanced features, supporting high data bandwidth and flexible configurations. AXI IPs are used where the highest performance is needed, leveraging features like burst transactions, multiple outstanding addresses, and out-of-order transaction completion, making it suitable for complex and demanding tasks.
Integrating these semiconductor IPs into your system ensures that you leverage their specialized features for increased efficiency and performance. In products that require robust, flexible, and scalable communication channels, AMBA interface controllers and PHYs provide the backbone necessary to build systems that can meet current and future demands.
Designed for high-performance applications, the Metis AIPU PCIe AI Accelerator Card by Axelera AI offers powerful AI processing capabilities in a PCIe card format. This card is equipped with the Metis AI Processing Unit, capable of delivering up to 214 TOPS, making it ideal for intensive AI tasks and vision applications that require substantial computational power. With support for the Voyager SDK, this card ensures seamless integration and rapid deployment of AI models, helping developers leverage existing infrastructures efficiently. It's tailored for applications that demand robust AI processing like high-resolution video analysis and real-time object detection, handling complex networks with ease. Highlighted for its performance in ResNet-50 processing, which it can execute at a rate of up to 3,200 frames per second, the PCIe AI Accelerator Card perfectly meets the needs of cutting-edge AI applications. The software stack enhances the developer experience, simplifying the scaling of AI workloads while maintaining cost-effectiveness and energy efficiency for enterprise-grade solutions.
The LVDS IP from Sunplus is optimized for high-speed differential signaling, perfect for video, graphics, and other data-intensive applications. It offers robust performance with low electromagnetic interference, providing a reliable data communication channel. This IP is tailored for integration into systems that require efficient long-distance data transfer with minimal signal degradation.
Panmnesia's CXL 3.1 Switch is an integral component designed to facilitate high-speed, low-latency data transfers across multiple connected devices. It is architected to manage resource allocation seamlessly in AI and high-performance computing environments, supporting broad bandwidth, robust data throughput, and efficient power consumption, creating a cohesive foundation for scalable AI infrastructures. Its integration with advanced protocols ensures high system compatibility.
Silicon Creations' SerDes Interfaces are crafted to handle high-speed data transmission challenges over varied processes, ranging from 12nm to 180nm. Addressing multiple protocols such as CPRI, PCIe, and SATA, these interfaces demonstrate flexibility by supporting data transmission speeds from 100 Mbps to beyond 32 Gbps. The architecture incorporates a host of advanced features including adaptive equalization techniques and programmable de-serialization widths, making it stand out in terms of performance and signal integrity even under challenging conditions. With ultra-low latency PMAs, they sustain excellent operational speed and efficiency, imperative for sophisticated communication applications. Moreover, Silicon Creations partners with leading entities to provide comprehensive solutions, including complete PCIe PHY integrations. This synergy ensures that SerDes Interfaces are fully optimized for operational excellence, delivering stable and reliable communication signals. With an emphasis on low power and minimized area requirements, they cater to burgeoning industry needs for power-efficient and space-conservative designs.
EXTOLL's Universal Chiplet Interconnect Express (UCIe) is a cutting-edge solution designed to meet the evolving needs of chip-to-chip communication. UCIe enables seamless data exchange between chiplets, fostering a new era of modular and scalable processor designs. This technology is especially vital for applications requiring high bandwidth and low latency in data transfer between different chip components. Built to support heterogeneous integration, UCIe offers superior scalability and is compatible with a variety of process nodes, enabling easy adaptation to different technological requirements. This ensures that system architects can achieve optimal performance without compromising on design flexibility or efficiency. Furthermore, UCIe's design philosophy is centered around maintaining ultra-low power consumption, aligning with modern demands for energy-efficient technology. Through EXTOLL’s UCIe, developers have the capability to build versatile and multi-functional platforms that are more robust than ever. This interconnect technology not only facilitates communications between chips but enhances the overall architecture, paving the way for future innovations in chiplet systems.
Advanced Peripheral Bus (APB) is one of the Advanced Microcontroller Bus Architecture (AMBA) family protocols. It is a low-cost interface that is designed for low power consumption and interface simplicity. Unlike AHB, it is a non-pipelined protocol for connecting low-bandwidth peripherals. Mostly used to link external peripherals to the SOC. Every APB transfer requires at least two clock cycles (SETUP Cycle and ACCESS Cycle) to finish. The APB interface is designed for accessing the programmable control registers of peripheral devices. The APB protocol has two independent data buses, one for read data and one for write data. The buses can be 8, 16, or 32 bits wide. The read and write data buses must have the same width. Data transfers cannot occur concurrently because the read data and write data buses do not have their own individual handshake signals.
The Yitian 710 processor from T-Head represents a significant advancement in server chip technology, featuring an ARM-based architecture optimized for cloud applications. With its impressive multi-core design and high-speed memory access, this processor is engineered to handle intensive data processing tasks with efficiency and precision. It incorporates advanced fabrication techniques, offering high throughput and low latency to support next-generation cloud computing environments. Central to its architecture are 128 high-performance CPU cores utilizing the Armv9 structure, which facilitate superior computational capabilities. These cores are paired with substantial cache size and high-speed DDR5 memory interfaces, optimizing the processor's ability to manage massive workloads effectively. This attribute makes it an ideal choice for data centers looking to enhance processing speed and efficiency. In addition to its hardware prowess, the Yitian 710 is designed to deliver excellent energy efficiency. It boasts a sophisticated power management system that minimizes energy consumption without sacrificing performance, aligning with green computing trends. This combination of power, efficiency, and environmentally friendly design positions the Yitian 710 as a pivotal choice for enterprises propelling into the future of computing.
The Aries fgOTN processor family is engineered according to the ITU-T G.709.20 fgOTN standard. This line of processors handles a variety of signals, including E1/T1, FE/GE, and STM1/STM4, effectively monitoring and managing alarms and performance metrics. Aries processors excel at fine-grain traffic aggregation, efficiently channeling fgODUflex traffic across OTN lines to support Ethernet, SDH, PDH client services. Their capacity to map signals to fgODUflex containers, which are then multiplexed into higher order OTN signals, demonstrates their versatility and efficiency. By allowing cascaded configurations with other Aries devices or Apodis processors, Aries products optimize traffic routes through OTN infrastructures, positioning them as essential components in optical networking and next-generation access scenarios.
The Metis AIPU M.2 Accelerator Module from Axelera AI is a cutting-edge solution designed for enhancing AI performance directly within edge devices. Engineered to fit the M.2 form factor, this module packs powerful AI processing capabilities into a compact and efficient design, suitable for space-constrained applications. It leverages the Metis AI Processing Unit to deliver high-speed inference directly at the edge, minimizing latency and maximizing data throughput. The module is optimized for a range of computer vision tasks, making it ideal for applications like multi-channel video analytics, quality inspection, and real-time people monitoring. With its advanced architecture, the AIPU module supports a wide array of neural networks and can handle up to 24 concurrent video streams, making it incredibly versatile for industries looking to implement AI-driven solutions across various sectors. Providing seamless compatibility with AI frameworks such as TensorFlow, PyTorch, and ONNX, the Metis AIPU integrates seamlessly with existing systems to streamline AI model deployment and optimization. This not only boosts productivity but also significantly reduces time-to-market for edge AI solutions. Axelera's comprehensive software support ensures that users can achieve maximum performance from their AI models while maintaining operational efficiency.
The Chimera GPNPU from Quadric is engineered to meet the diverse needs of modern AI applications, bridging the gap between traditional processing and advanced AI model requirements. It's a fully licensable processor, designed to deliver high AI inference performance while eliminating the complexity of traditional multi-core systems. The GPNPU boasts an exceptional ability to execute various AI models, including classical backbones, state-of-the-art transformers, and large language models, all within a single execution pipeline.\n\nOne of the core strengths of the Chimera GPNPU is its unified architecture that integrates matrix, vector, and scalar processing capabilities. This singular design approach allows developers to manage complex tasks such as AI inference and data-parallel processing without resorting to multiple tools or artificial partitioning between processors. Users can expect heightened productivity thanks to its modeless operation, which is fully programmable and efficiently executes C++ code alongside AI graph code.\n\nIn terms of versatility and application potential, the Chimera GPNPU is adaptable across different market segments. It's available in various configurations to suit specific performance needs, from single-core designs to multi-core clusters capable of delivering up to 864 TOPS. This scalability, combined with future-proof programmability, ensures that the Chimera GPNPU not only addresses current AI challenges but also accommodates the ever-evolving landscape of cognitive computing requirements.
iWave Global introduces the ARINC 818 Switch, a pivotal component in the management and routing of video data within avionics systems. Designed for applications that require efficient video data distribution and management, the switch is optimized for performance in environments with stringent data handling requirements. The switch's architecture supports a high level of bandwidth, allowing for the smooth routing of multiple video streams in real-time. Its design includes advanced features that ensure low-latency, error-free data transfer, integral to maintaining the integrity and reliability of video data in critical applications. Featuring robust interoperability characteristics, the ARINC 818 Switch easily integrates into existing systems, facilitating modular expansion and adaptability to new technological standards. It is indispensable for any aerospace project that involves complex video data management, providing a stable platform for video data routing and switching.
Designed to cater to high-performance networking needs, this offload engine integrates multiple functionalities including TCP offloading, MAC, PCIe, and host interface in one low-latency package. It enables a complete bypass of the host CPU processing, drastically reducing the load and enhancing data throughput. The solution boasts an ultra-low latency of 77 ns, ensuring robust performance suited for critical applications that demand high-speed data processing. The architecture of this offload engine supports a vast number of concurrent TCP and UDP sessions, offering a consistent latency and impressive data transfer rate per session. By offloading network processing tasks, this solution frees up CPU resources, thus achieving efficient operation and lower power consumption. It is particularly advantageous for deployment in data-intensive environments such as cloud computing infrastructures and modern data centers. Equipped with dual-10G ports and advanced features like enterprise-class reliability and scalability, it has been widely adopted for its capability to execute networking tasks efficiently while consuming minimal resources. This engine integrates architecture that is designed to be immune to network jitter, providing a seamless networking experience across multiple ports.
The AHB-Lite APB4 Bridge is an adaptable soft interconnect bridge linking the AMBA 3 AHB-Lite protocol with the AMBA APB protocol. It facilitates seamless communication between these bus protocols, ensuring data transfers are conducted efficiently within an embedded system. This bridge supports parameterization, allowing engineers to configure it for their unique design needs, thereby improving system flexibility and performance in electronic projects.
RaiderChip's GenAI v1 is a pioneering hardware-based generative AI accelerator, designed to perform local inference at the Edge. This technology integrates optimally with on-premises servers and embedded devices, offering substantial benefits in privacy, performance, and energy efficiency over traditional hybrid AI solutions. The design of the GenAI v1 NPU streamlines the process of executing large language models by embedding them directly onto the hardware, eliminating the need for external components like CPUs or internet connections. With its ability to support complex models such as the Llama 3.2 with 4-bit quantization on LPDDR4 memory, the GenAI v1 achieves unprecedented efficiency in AI token processing, coupled with energy savings and reduced latency. What sets GenAI v1 apart is its scalability and cost-effectiveness, significantly outperforming competitive solutions such as Intel Gaudi 2, Nvidia's cloud GPUs, and Google's cloud TPUs in terms of memory efficiency. This solution maximizes the number of tokens generated per unit of memory bandwidth, thus addressing one of the primary limitations in generative AI workflow. Furthermore, the adept memory usage of GenAI v1 reduces the dependency on costly memory types like HBM, opening the door to more affordable alternatives without diminishing processing capabilities. With a target-agnostic approach, RaiderChip ensures the GenAI v1 can be adapted to various FPGAs and ASICs, offering configuration flexibility that allows users to balance performance with hardware costs. Its compatibility with a wide range of transformers-based models, including proprietary modifications, ensures GenAI v1's robust placement across sectors requiring high-speed processing, like finance, medical diagnostics, and autonomous systems. RaiderChip's innovation with GenAI v1 focuses on supporting both vanilla and quantized AI models, ensuring high computation speeds necessary for real-time applications without compromising accuracy. This capability underpins their strategic vision of enabling versatile and sustainable AI solutions across industries. By prioritizing integration ease and operational independence, RaiderChip provides a tangible edge in applying generative AI effectively and widely.
The ARINC 818 Product Suite is a comprehensive collection of tools and resources designed to support the full development lifecycle for ARINC 818 enabled equipment. This suite assists in the implementation and testing of ARINC 818 protocols, which are crucial for systems that require high-performance video and data transmission, such as in avionics and defense applications. The product suite is built to facilitate not only the development and qualification but also the simulation of ARINC 818 products, ensuring effective integration into mission-critical environments. The suite’s tools include development software and Implementer's guides, enabling seamless access to ARINC 818 capabilities.
The NuLink Die-to-Die PHY for Standard Packaging represents Eliyan's cornerstone technology, engineered to harness the power of standard packaging for die-to-die interconnects. This technology circumvents the limitations of advanced packaging by providing superior performance and power efficiencies traditionally associated only with high-end solutions. Designed to support multiple standards, such as UCIe and BoW, the NuLink D2D PHY is an ideal solution for applications requiring high bandwidth and low latency without the cost and complexity of silicon interposers or silicon bridges. In practical terms, the NuLink D2D PHY enables chiplets to achieve unprecedented bandwidth and power efficiency, allowing for increased flexibility in chiplet configurations. It supports a diverse range of substrates, providing advantages in thermal management, production cycle, and cost-effectiveness. The technology's ability to split a Network on Chip (NoC) across multiple chiplets, while maintaining performance integrity, makes it invaluable in ASIC designs. Eliyan's NuLink D2D PHY is particularly beneficial for systems requiring physical separation between high-performance ASICs and heat-sensitive components. By delivering interposer-like bandwidth and power in standard organic or laminate packages, this product ensures optimal system performance across varied applications, including those in AI, data processing, and high-speed computing.
AMBA AHB is a bus interface designed for high-performance synthesizable applications. It specifies the interface between components such as initiator , interconnects, and targets. AMBA AHB incorporates the features needed for high-performance, high clock frequency systems. The most common AHB targets are internal memory devices, external memory interfaces, and high-bandwidth peripherals.
The bus converter module transforms wide initiator data buses to smaller target data buses or vice-versa. A narrow target on a wide bus, only requires external logic and no internal design changes. * APB: 32-bit wide initiator data buses to 16-bit target data buses. * AHB: 64-bit wide initiator data buses to 32-bit target data buses. * AXI: 256-bit wide initiator data buses to 64-bit target data buses A wide target on a narrow bus, only requires external logic and no internal design changes. * APB: 16-bit wide initiator data buses to 32-bit target data buses. * AHB: 32-bit wide initiator data buses to 64-bit target data buses. * AXI: 64-bit wide initiator data buses to 256-bit target data buses.
EXOSTIV is a versatile tool providing extensive capture capabilities for monitoring FPGA internal signals. It's designed to visualize operation in real-time, thus offering immense savings by mitigating FPGA bugs during production and lowering engineering costs. The tool adapts to different prototyping boards and supports a variety of FPGA configurations. A hallmark of EXOSTIV's functionality is its ability to perform at-speed analysis in complex FPGA designs. It features robust probes like the EP16000, which connects to FPGA chip transceivers, supporting significant data rates per transceiver. This setup ensures that engineers can conduct real-world testing and accurate data capture, overcoming the hindrances often encountered with simulation-only methods. The tool boasts a user-friendly interface centered around its Core Inserter and Probe Client software, allowing for efficient IP generation and integration into the target design. By providing comprehensive connectivity options via QSFP28 and supporting multiple platforms, EXOSTIV remains an essential asset for engineers aiming to enhance their FPGA design and validation processes.
With a focus on maintaining signal integrity in high-speed interfaces, the PCIe Retimer extends the reach of PCI Express connections while preserving data quality. Essential for long signal paths, it works by regenerating signals to boost performance and provide reliable connections across distances. The retimer is particularly effective in environments with substantial electromagnetic interference, ensuring data transmission remains error-free and efficient across extended cable runs. By including line equalization and using advanced clock recovery techniques, the PCIe Retimer strengthens signal quality, allowing for greater system performance and reliability in a wide array of computing applications.
The Advanced eXtensible Interface(AXI) bus is a high-performance parallel bus that connects on-chip peripheral circuits (or IP blocks) to processor cores. The AXI bus employs "channels" to divide read and write transactions into semi-independent activities that can run at their own pace. The Read Address and Read Data channels send data from the target to the initiator, whereas the Write Address, Write Data, and Write Response channels transfer data from the initiator to the target.
Roa Logic's AHB-Lite Multilayer Switch is engineered to provide high-performance, low-latency interconnectivity for AHB-Lite based systems. This switch supports numerous bus masters and slaves, facilitating robust data throughput across the system's architecture. By optimizing data traffic management, it enhances the overall efficiency of electronic devices that require complex data processing capabilities.
The USB PHY offered by Silicon Library Inc. is meticulously designed to support seamless data transfer across USB interfaces, pivotal in modern digital consumption. This USB 2.0 PHY is integral to many applications, providing reliable connectivity and power efficiency that meet high-performance requirements. Designed with cutting-edge technology, the USB PHY integrates efficiently in various systems, ensuring data transfer integrity and speed. Its robust architecture makes it compatible with a myriad of devices, facilitating seamless data communication while optimizing power consumption. Furthermore, the USB PHY from Silicon Library Inc. is engineered to comply with the necessary quality standards, ensuring it can handle the rigorous demands of data-centric applications. Its implementation is straightforward, making it a preferred choice for system integrators seeking reliability and performance.
eSi-Connect offers an extensive suite of AMBA-compliant peripheral IPs designed to streamline SoC integration. This suite encompasses versatile memory controllers, standard off-chip interface support, and essential control functions. Its configurability and compatibility with low-level software drivers make it suitable for real-time deployment in complex system architectures, promoting reliable connectivity across various applications.
The Multi-Protocol SERDES offered by Pico Semiconductor is a versatile solution capable of handling a variety of communication protocols. This series of SERDES includes a 4-channel configuration that supports data rates up to 32Gbps, designed for integration with XAUI, RXAUI, and SGMII. It is compatible with multiple process nodes provided by foundries like TSMC and GF, offering robust performance across different semiconductor environments. These SERDES are crafted to meet high-performance metrics, capturing speeds up to 16Gbps and 6.5Gbps across various models, with advanced versions reaching up to 32Gbps. This exceptional range not only ensures compatibility with current technologies but also prepares systems for future updates, sustaining high data throughput. By delivering reliable high-speed data transmission capabilities, the Multi-Protocol SERDES from Pico Semiconductor is integral for networking, high-speed computing, and data storage applications, where efficient and speedy data transfer is paramount.
The PDM-to-PCM Converter from Archband Labs leads in transforming pulse density modulation signals into pulse code modulation signals. This converter is essential in applications where high fidelity of audio signal processing is vital, including digital audio systems and communication devices. Archband’s solution ensures accurate conversion, preserving the integrity and clarity of the original audio. This converter is crafted to seamlessly integrate with a wide array of systems, offering flexibility and ease-of-use in various configurations. Its robust design supports a wide range of input frequencies, making it adaptable to different signal environments. The PDM-to-PCM Converter also excels in minimizing latency and reducing overhead processing times. It’s engineered for environments where precision and sound quality are paramount, ensuring that audio signals remain crisp and undistorted during conversion processes.
The Apodis family of Optical Transport Network processors adheres to ITU-T standards, offering a comprehensive suite for signal termination, processing, and multiplexing. Designed to handle both SONET/SDH and Ethernet client services, these processors map signals to Optical Transport Network (OTN), empowering versatile any-port, any-service configurations. Apodis processors are notable for their capacity to support up to 16 client ports and four 10G OTN line ports, delivering bandwidth scalability up to 40G, crucial for wireless backhaul and fronthaul deployments. With a robust, non-blocking OTN switching fabric, Apodis facilitates seamless client-to-line and line-to-line connections while optimally managing network bandwidth. This adaptability makes the Apodis processors an ideal choice for next-generation access networks and optical infrastructures.
The ePHY-5616 delivers data rates from 1 to 56Gbps across technology nodes of 16nm and 12nm. Designed for a diverse range of applications, this product offers superior BER and low latency, making it ideal for enterprise equipment like routers, switches, and network interface cards. The ePHY-5616 employs a highly configurable DSP-based receiver architecture designed to manage various insertion loss scenarios, from 10dB up to over 35dB. This ensures robust and reliable data transfer across multiple setups.
Roa Logic's AHB-Lite Timer is a timer module that adheres to the RISC-V Privileged 1.9.1 specification, designed for use in RISC-V compliant systems. This module offers reliable timing functions essential for task scheduling and precise time control in embedded applications, delivering dependable performance required in various electronic applications.
The GenAI v1-Q from RaiderChip brings forth a specialized focus on quantized AI operations, reducing memory requirements significantly while maintaining impressive precision and speed. This innovative accelerator is engineered to execute large language models in real-time, utilizing advanced quantization techniques such as Q4_K and Q5_K, thereby enhancing AI inference efficiency especially in memory-constrained environments. By offering a 276% boost in processing speed alongside a 75% reduction in memory footprint, GenAI v1-Q empowers developers to integrate advanced AI capabilities into smaller, less powerful devices without sacrificing operational quality. This makes it particularly advantageous for applications demanding swift response times and low latency, including real-time translation, autonomous navigation, and responsive customer interactions. The GenAI v1-Q diverges from conventional AI solutions by functioning independently, free from external network or cloud auxiliaries. Its design harmonizes superior computational performance with scalability, allowing seamless adaptation across variegated hardware platforms including FPGAs and ASIC implementations. This flexibility is crucial for tailoring performance parameters like model scale, inference velocity, and power consumption to meet exacting user specifications effectively. RaiderChip's GenAI v1-Q addresses crucial AI industry needs with its ability to manage multiple transformer-based models and confidential data securely on-premises. This opens doors for its application in sensitive areas such as defense, healthcare, and financial services, where confidentiality and rapid processing are paramount. With GenAI v1-Q, RaiderChip underscores its commitment to advancing AI solutions that are both environmentally sustainable and economically viable.
The LPDDR4/4X/5 Secondary/Slave PHY offers targeted solutions for optimized memory interfacing in systems where primary and secondary controllers operate in tandem. This design is critical for addressing the needs of high-performance computing devices that require scalable memory management solutions. With its focus on efficient data handling and reduced latency, the Secondary/Slave PHY ensures seamless operation in complex memory systems. The design incorporates advanced control techniques to maximize memory throughput while adhering to rigorous power management standards. This positions it as a vital component for devices requiring high-speed memory access. Adaptability is a key feature of this PHY, with support for multiple LPDDR standards allowing it to interface with modern memory technologies. Its robust construction provides consistent performance across a range of operating conditions, catering to industries demanding high efficiency and reliability. The Secondary/Slave PHY thus enhances system capabilities, ensuring data integrity and reduced latency for innovative computational applications.
Ethernet MAC 10M/100M/1G/2.5G IP is a solution that enables the host to communicate data using the IEEE 802.3 standard for 10M, 100M, 1G, 2.5G speeds and is suited for use in networking equipment such as switches and routers. The Client-side interface for the IP is AXI-S and the Ethernet MAC IP comes with GMII, RGMII or MII interfaces on the PHY side. The Ethernet MAC 10M/100M/1G/2.5G IP features a compact and low latency solution, it is highly configurable and can optionally include IEEE 1588 Timestamping Unit (TSU). The Silicon agnostic Ethernet MAC IP, suitable for ASICs and FPGAs, is prepared for easy integration with Ethernet PCS 10M/ 100M/1G/2.5G IP from Comcores.
The ARINC 818-3 IP Core from iWave Global represents an advancement in avionics video interface technology, designed for high-speed and high-fidelity video data transmission. This IP core addresses the needs of modern aerospace systems that require robust video communication links both for military and commercial use. It supports a wide array of enhancements over previous generations, including increased bandwidth and improved signal integrity. This ensures that the ARINC 818-3 IP Core can handle the demands of next-generation avionic systems seamlessly, supporting advanced video processing and display systems. The core's design prioritizes modularity and scalability, allowing for easy integration and expansion to meet evolving system requirements. It is positioned as an essential tool for aviation applications demanding high reliability and accuracy in video data handling and display solutions, making it indispensable for new and retrofitted aerospace projects.
The pPLL03F-GF22FDX is a sophisticated all-digital fractional-N PLL optimized for performance computing applications using GlobalFoundries 22FDX technology. This PLL is engineered for environments with rigorous timing requirements, offering low jitter performance of less than 10 picoseconds RMS at operational frequencies as high as 4GHz. Compact and power-efficient, it typically occupies less than 0.01 square millimeters and consumes under 5 milliwatts of power. The architecture of the pPLL03F-GF22FDX is built on Perceptia's advanced second-generation digital PLL technology, which provides consistent performance across various processes, regardless of PVT conditions. This design is particularly well-suited to applications where multiple clock domains are present, each controlled by its dedicated PLL, thanks to integrated power supply regulation that simplifies system design and power sharing. Integration into complex SoC designs is seamless, supported by comprehensive deliverables that include models and views necessary for modern backend design flows. The adaptable nature of this PLL allows it to be configured as either an integer-N or fractional-N PLL, offering flexibility in aligning system-level input and output clock frequencies. Clients are also offered extensive customization and integration support, ensuring optimal fit and functionality in diverse applications.
The H.264 FPGA Encoder and CODEC Micro Footprint Cores from A2e Technologies is a highly customizable IP core designed specifically for FPGAs. This core is notable for its small size and high speed, capable of supporting 1080p60 H.264 Baseline video with a single core. Featuring exceptionally low latency, as little as 1ms at 1080p30, it offers a customizable solution for various video resolutions and pixel depths. These capabilities make it a competitive choice for applications requiring high-performance video compression with minimal footprint. Designed to be ITAR compliant and licensable, the H.264 core can be tailored to meet specific requirements, offering flexibility in video applications. This product is especially suitable for industries where space and performance are critical, such as defense and industrial controls. The core can work efficiently across a range of resolutions and color depths, providing the potential for integration into a wide array of devices and systems. The company's expertise ensures that this H.264 core is not only versatile but also comes with the option of a low-cost evaluation license, allowing potential users to explore its capabilities before committing fully. With A2e's strong support and integration services, customers have assurance that even complex design requirements can be met with experienced guidance.
The HOTLink II Product Suite constitutes a range of resources specifically tailored for systems utilizing HOTLink II™ technology. This suite is engineered to manage high-speed video and data communication in environments where reliability and precision are paramount. It is ideal for applications in aerospace where maintaining high data integrity is critical. The suite provides robust solutions for both the development and operational stages, enhancing system performance. With its extensive support for different phases of product lifecycle management, the HOTLink II suite ensures that products meet the high standards required for mission-critical military and industrial applications.
The CANmodule-III is an advanced CAN controller designed to efficiently manage communication over the Controller Area Network. It features a mailbox architecture with a robust 32 receive and 32 transmit mailboxes, offering full compliance with the CAN2.0B standard. This core is optimized for a variety of high-demanding applications across aerospace, automotive, and industrial sectors. In terms of integration, the CANmodule-III is crafted for seamless incorporation into systems-on-chip, adapting easily to both FPGA and ASIC designs. The architecture, originally based on Bosch’s fundamental CAN design, allows for customizable message filtering, providing flexibility in handling different communication scenarios. The integration of application-specific functions as add-ons means that the core itself remains unaffected, ensuring consistent performance. This CAN controller is also known for its efficient transaction management on the bus, making it a preferred choice for environments where reliability and precision are critical. The CANmodule-III’s system support functions and streamlined processing capabilities see it effectively used in various industry-specific applications where optimized communication is paramount.
The Multi-Protocol SerDes provided by Silicon Creations serves as an essential component for high-speed data interfaces across multiple industry protocols. This SerDes portfolio accommodates a vast array of protocols such as PCIe, JESD204, XAUI, and many more, facilitating broad compatibility with industry standards. Operating across 12nm to 180nm processes, these interfaces support data rates from 100 Mbps to an impressive 32.75 Gbps. Incorporating advanced features like programmable de-serialization widths and adaptive equalization, the Multi-Protocol SerDes ensures optimal signal integrity and performance even in demanding environments. The design includes jitter cleaner functions and employs low-latency optimized PMAs, delivering high precision and speed across various operational scenarios. This comprehensive adaptability ensures seamless integration into a wide range of applications from communications to high-performance computing. Supported by robust architectures, the SerDes enables enhanced efficiency and reliability, featuring low power consumption and reduced area overheads. With a commitment to customer satisfaction, Silicon Creations offers complete solutions through partnerships with leading controller vendors, cementing its products as high-value choices for modern electronic systems.
The AXI4 DMA Controller from Digital Blocks revolutionizes data management in System-on-Chip architectures through high-performance Direct Memory Access capabilities. Supporting a span of 1 to 16 channels, it handles data transfers between memory and peripherals with agility, ideal for both small and large datasets. Designed for high throughput, it includes a multi-channel architecture that can expand from 32 to up to 256 channels, demonstrating exceptional scalability for future data demands. Each channel within the DMA Controller operates independently with dedicated Read and Write Controllers, ensuring minimal overhead during transfers. It facilitates complex data flow configurations including scatter-gather linked-list data controls and comprehensive support for different burst modes within the AXI3 and AXI4 protocols. Its design incorporates advanced features that users can selectively enable to optimize silicon resource usage and cost efficiency. Additionally, it accommodates complex AXI4-Stream to memory-mapped interface transfers, making it versatile for a variety of applications, from high-speed data environments to embedded systems requiring optimized memory access and control.
The Chipchain C100 is a pioneering solution in IoT applications, providing a highly integrated single-chip design that focuses on low power consumption without compromising performance. Its design incorporates a powerful 32-bit RISC-V CPU which can reach speeds up to 1.5GHz. This processing power ensures efficient and capable computing for diverse IoT applications. This chip stands out with its comprehensive integrated features including embedded RAM and ROM, making it efficient in both processing and computing tasks. Additionally, the C100 comes with integrated Wi-Fi and multiple interfaces for transmission, broadening its application potential significantly. Other notable features of the C100 include an ADC, LDO, and a temperature sensor, enabling it to handle a wide array of IoT tasks more seamlessly. With considerations for security and stability, the Chipchain C100 facilitates easier and faster development in IoT applications, proving itself as a versatile component in smart devices like security systems, home automation products, and wearable technology.
The Ultra-Low Latency 10G Ethernet MAC from Chevin Technology is designed to deliver exceptional speed and efficiency for cutting-edge FPGA applications. Its primary focus is on reducing latency to the bare minimum while maintaining a high data throughput. This Ethernet MAC is universally compatible with Intel and AMD FPGA platforms, offering seamless adaptation to various projects. This solution is especially advantageous for environments where near-instantaneous data transmission is a necessity. Ideal for applications in high-frequency trading, telecommunications, and advanced scientific instrumentation, the Ultra-Low Latency 10G Ethernet MAC ensures that data integrity is preserved even at high speeds. Chevin Technology's meticulous in-house testing and development processes guarantee that this IP core meets stringent quality and performance standards. It offers a scalable, all-hardware architecture that slashes the usual implementation time, allowing more resources to be dedicated to expanding functionality and securing additional data pathways.
ChipJuice is a powerful and user-friendly tool designed for the reverse engineering of integrated circuits (ICs). This tool is particularly beneficial for digital forensics activities, offering capabilities such as backdoor research, supply chain assessment, and comprehensive hardware architecture analysis. ChipJuice aids in technology intelligence by performing security assessments, investigating digital IP infringement, and analyzing pirate devices. It also supports the recovery of obsolete devices and is instrumental in semiconductor education. The tool is crafted to be intuitive, combining a robust set of features that cater to chip explorers of all kinds. It supports various chip types regardless of their size, technology node, or material composition like aluminum and copper. With a focus on versatility, ChipJuice can handle microcontrollers, microprocessors, FPGAs, and SoCs efficiently. Its embedded feature for Automated Standard Cell Research helps to identify and catalog standard cells for use in subsequent chip evaluations, making it a valuable asset for lab environments and forensic analyses. ChipJuice's high-performance algorithms allow for quick and efficient processing, recovering a chip's internal architecture in the form of netlists and HDL files. The tool provides a physical netlist where nodes are localized on the chip, enabling rapid signal tracing and annotation. It operates seamlessly with just the electronic images of a chip's digital core, making it an easy-to-use yet powerful solution for exploring and understanding ICs' complexities.
Credo's SerDes PHY solutions are pivotal in enabling high-performance interconnects for custom ASICs and advanced signal processing applications. Specifically engineered to balance performance with power efficiency, these solutions leverage unique, patented DSP architectures that can be implemented using mature process nodes, thereby maintaining cost efficiency without compromising on quality. The design flexibility allows the seamless integration of SerDes PHY into various ASIC platforms, making it ideal for complex digital signal processing and AI tasks. Credo’s SerDes PHYs are available as both licensed IP and chiplets to cater to a broad spectrum of customer needs. These solutions are also adaptable, capable of accommodating a range of signaling, from 112G to 56G, in various modes like PAM4 and NRZ. The architecture is further configured to support diverse operating conditions, ensuring compatibility across different fabrication technologies and design scenarios. The adaptability of SerDes PHY makes it highly suitable for integration into multiple platforms such as Multi-Chip Modules (MCM) and 2.5D interposers. This characteristic simplifies the design process for high-speed interconnects and assists in overcoming conventional barriers associated with the same-process logic and SerDes integration. As a result, Credo enables more accessible and economically viable solutions for pioneering ASIC designs that demand robust performance and scalability.
The Time-Triggered Protocol (TTP) stands out as a robust framework for ensuring synchronous communication in embedded control systems. Developed to meet stringent aerospace industry criteria, TTP offers a high degree of reliability with its fault-tolerant configuration, integral to maintaining synchrony across various systems. This technology excels in environments where timing precision and data integrity are critical, facilitating accurate information exchange across diverse subsystems. TTTech’s TTP implementation adheres to the SAE AS6003 standard, making it a trusted component among industry leaders. As part of its wide-ranging applications, this protocol enhances system communication within commercial avionic solutions, providing dependable real-time data handling that ensures system stability. Beyond aviation, TTP's applications can also extend into the energy sector, demonstrating its versatility and robustness. Characterized by its deterministic nature, TTP provides a framework where every operation is scheduled, leading to predictable data flow without unscheduled interruptions. Its suitability for field-programmable gate arrays (FPGAs) allows for easy adaptation into existing infrastructures, making it a versatile tool for companies aiming to upgrade their communication systems without a complete overhaul. For engineers and developers, TTP provides a dependable foundation that streamlines the integration process while safeguarding communication integrity.
The THOR platform is a versatile tool for developing application-specific NFC sensor and data logging solutions. It incorporates silicon-proven IP blocks, creating a comprehensive ASIC platform suitable for rigorous monitoring and continuous data logging applications across various industries. THOR is designed for accelerated development timelines, leveraging low power and high-security features. Equipped with multi-protocol NFC capabilities and integrated temperature sensors, the THOR platform supports a wide range of external sensors, enhancing its adaptability to diverse monitoring needs. Its energy-efficient design allows operations via energy harvesting or battery power, ensuring sustainability in its applications. This platform finds particular utility in sectors demanding precise environmental monitoring and data management, such as logistics, pharmaceuticals, and industrial automation. The platform's capacity for AES/DES encrypted data logging ensures secure data handling, making it a reliable choice for sectors with stringent data protection needs.
The Ethernet Real-Time Publish-Subscribe (RTPS) IP Core offers a thorough hardware implementation of the Ethernet RTPS protocol, which is utilized for real-time communication in Ethernet networks. Its architecture supports efficient and deterministic data transfer, crucial in environments that demand reliable and high-speed data exchanges. The IP core is particularly beneficial within applications that require consistent communication and reduced latency, fostering robust network infrastructures.
The Network Protocol Accelerator Platform (NPAP) is engineered to accelerate network protocol processing and offload tasks at speeds reaching up to 100 Gbps when implemented on FPGAs, and beyond in ASICs. This platform offers patented and patent-pending technologies that provide significant performance boosts, aiding in efficient network management. With its support for multiple protocols like TCP, UDP, and IP, it meets the demands of modern networking environments effectively, ensuring low latency and high throughput solutions for critical infrastructure. NPAP facilitates the construction of function accelerator cards (FACs) that support 10/25/50/100G speeds, effectively handling intense data workloads. The stunning capabilities of NPAP make it an indispensable tool for businesses needing to process vast amounts of data with precision and speed, thereby greatly enhancing network operations. Moreover, the NPAP emphasizes flexibility by allowing integration with a variety of network setups. Its capability to streamline data transfer with minimal delay supports modern computational demands, paving the way for optimized digital communication in diverse industries.
The High-Speed SerDes designed for chiplets by EXTOLL represents a pinnacle in data transfer technologies. This high-performance SerDes is specifically crafted to support the latest chiplet technologies by enabling rapid data movement across chip boundaries. Its implementation ensures minimal latency, critical for time-sensitive applications, all the while maintaining a structure that is easy to integrate within various semiconductor designs. This SerDes offers unparalleled flexibility and adaptability for users seeking high-speed connectivity within chiplet environments. It supports a wide range of mainstream process nodes, thus ensuring compatibility with a diverse array of design requirements. Moreover, its architecture is optimized for energy efficiency, reducing the overall power consumption of systems which is crucial in today’s power-conscious technological landscape. EXTOLL’s High-Speed SerDes is not only about performance but also about reliability and scalability. As systems require more data and increased processing power, maintaining data integrity becomes a mission-critical requirement. This SerDes is engineered to provide robust error correction and data integrity, thus ensuring high standards of reliability while supporting the data bandwidth needs of modern, complex semiconductor applications.
The Hyperspectral Imaging System developed by Imec is a revolutionary tool for capturing and analyzing light across a wide range of wavelengths. This system is particularly valuable for applications requiring detailed spectral analysis, such as agricultural inspection, environmental monitoring, and medical diagnostics. By capturing hundreds of narrow spectral bands, the system provides a comprehensive spectral profile of the subject, enabling precise identification of materials and substances. What sets Imec's Hyperspectral Imaging System apart is its ability to integrate seamlessly into existing devices, allowing for versatile use across various industries. The compact and efficient design ensures that it can be deployed in field conditions, offering real-time analysis capabilities that are crucial for immediate decision-making processes. The Hyperspectral Imaging System is designed with cutting-edge CMOS technology, ensuring high sensitivity and accuracy. This integration with CMOS technology not only enhances the performance but also ensures that the system is cost-effective and accessible to a broader range of applications and markets. As hyperspectral imaging continues to evolve, Imec's system stands as a leader in the field, providing unmatched resolution and reliability.
An interconnect component connects multi initiators and multi targets in a system. A single initiator system simply requires a decoder and multiplexor.
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