All IPs > Analog & Mixed Signal > PLL
The Analog & Mixed Signal PLL (Phase-Locked Loop) category of semiconductor IP at Silicon Hub encompasses a collection of sophisticated circuit designs used primarily for frequency synthesis, clock management, and timing in integrated circuits. PLLs are indispensable in a variety of electronic applications where synchronized frequency and phase-locked signals are crucial. This class of semiconductor IPs is pivotal for ensuring stable and reliable operations in digital and analog systems alike.
PLLs are widely utilized in communication systems, consumer electronics, and computing devices. In communication systems, they play a critical role in modulating and demodulating signals, ensuring accurate data transmission. Consumer electronics, such as smartphones, tablets, and gaming devices, leverage PLL technology to maintain accurate system clocks, which is essential for digital signal processing and multimedia performance. In computing, PLLs help in maintaining synchronous operations between processors and memory, allowing seamless multitasking and high-speed data processing.
Within this category, you will find a variety of PLL designs and architectures, each tailored to specific application needs, including fractional-N PLLs, integer-N PLLs, and Delay-Locked Loops (DLLs). These variants offer different advantages, such as reduced phase noise, higher frequency stability, and improved design flexibility. Additionally, some advanced PLL IPs incorporate features like spread spectrum clocking to minimize electromagnetic interference, making them suitable for use in sensitive electronic environments.
Overall, the Analog & Mixed Signal PLL semiconductor IPs available at Silicon Hub are integral components that help optimize the performance, efficiency, and reliability of modern electronic systems. They enable designers and engineers to tackle complex clocking requirements and achieve precise control over signal timing, which is a cornerstone of innovation in technology sectors ranging from telecom to computing and beyond.
Silicon Creations delivers precision LC-PLLs designed for ultra-low jitter applications requiring high-end performance. These LC-tank PLLs are equipped with advanced digital architectures supporting wide frequency tuning capabilities, primarily suited for converter and PHY applications. They ensure exceptional jitter performance, maintaining values well below 300fs RMS. The LC-PLLs from Silicon Creations are characterized by their capacity to handle fractional-N operations, with active noise cancellation features allowing for clean signal synthesis free of unwanted spurs. This architecture leads to significant power efficiencies, with some IPs consuming less than 10mW. Their low footprint and high frequency integrative capabilities enable seamless deployments across various chip designs, creating a perfect balance between performance and size. Particular strength lies in these PLLs' ability to meet stringent PCIe6 reference clocking requirements. With programmable loop bandwidth and an impressive tuning range, they offer designers a powerful toolset for achieving precise signal control within cramped system on chip environments. These products highlight Silicon Creations’ commitment to providing industry-leading performance and reliability in semiconductor design.
The Ring PLLs offered by Silicon Creations illustrate a versatile clocking solution, well-suited for numerous frequency generation tasks within integrated circuit designs. Known for their general-purpose and specialized applications, these PLLs are crafted to serve a massive array of industries. Their high configurability makes them applicable for diverse synthesis needs, acting as the backbone for multiple clocking strategies across different environments. Silicon Creations' Ring PLLs epitomize high integration with functions tailored for low jitter and precision clock generation, suitable for battery-operated devices and systems demanding high accuracy. Applications span from general clocking to precise Audio Codecs and SerDes configurations requiring dedicated performance metrics. The Ring PLL architecture achieves best-in-class long-term and period jitter performance with both integer and fractional modes available. Designed to support high volumes of frequencies with minimal footprint, these PLLs aid in efficient space allocation within system designs. Their use of silicon-proven architectures and modern validation methodologies assure customers of high reliability and quick integration into existing SoC designs, emphasizing low risk and high reward configurations.
Designed for performance computing, the pPLL03F-GF22FDX is an advanced all-digital fractional-N PLL developed for low-jitter and compact applications. It operates efficiently at clock frequencies reaching up to 4GHz, specifically crafted to meet the demands of performance computing blocks and ADCs/DACs that have moderate SNR prerequisites. A crucial aspect of its design is its compatibility with multi-PLL systems, enabling implementations in complex SoCs with numerous clock domains. Tailored for GlobalFoundries 22FDX, this IP ensures robust and reliable performance across varied PVT conditions.
The VCO24G is engineered as a 24GHz Colpitts Voltage-Controlled Oscillator, offering low noise performance and a differential architecture ideal for integrating within PLL systems and broadband testing environments. This VCO capitalizes on the low-cost, high-output capabilities of the 0.18um SiGe process, ensuring it meets rigorous demands for precision and long-term reliability in various telecommunication applications. Its design lends itself to high-frequency operations with exceptional signal stability.
Dillon Engineering's 2D FFT core delivers robust performance for transforming two-dimensional data sets into the frequency domain with high precision and efficiency. By leveraging both internal and external memory between dual FFT engines, this core optimizes the data processing pipeline, ensuring fast and reliable results even as data complexity increases. Ideal for applications that handle image processing and data matrix transformations, the 2D FFT core navigates data bandwidth constraints with ease, maintaining throughput even for larger data sets. This core's design maximizes data accuracy and minimizes processing delays, crucial for applications requiring precise image recognition and analysis. Thanks to the adaptable nature provided by Dillon's ParaCore Architect, this IP core is easily customized for various FPGA and ASIC environments. Its flexibility and robust processing capabilities make the 2D FFT core a key component for cutting-edge applications in fields where data translation and processing are critical.
The Ultra-Low Latency 10G Ethernet MAC IP core by Chevin Technology exemplifies cutting-edge design for high-speed network communications, catered specifically to deliver the lowest possible latency. It is meticulously constructed to meet the demands of applications that require minimal delay in data exchange, thus maximising data throughput. The IP core is finely tuned for deployment in FPGAs, optimizing the balance between performance and resource utilization. Benefiting from a streamlined logic architecture, this IP core enhances the efficiency of hardware accelerations and simplifies the incorporation of Ethernet connectivity into customer systems. Its fundamental construction is rooted in Chevin’s extensive experience with Ethernet technologies and it has been thoroughly tested to ensure reliable operation across a diverse range of settings. This Ethernet MAC utilises all-logic architecture which removes need for additional CPU or software intervention, providing immense power savings and reduced system complexity. Features like programmable interframe gap control and flexible licensing allow for the tailored installation in both traditional and contemporary systems. The combination of robust performance capabilities alongside expert support creates a compelling choice for integrators focused on high-speed, low-latency Ethernet solutions.
The THOR platform is a versatile tool for developing application-specific NFC sensor and data logging solutions. It incorporates silicon-proven IP blocks, creating a comprehensive ASIC platform suitable for rigorous monitoring and continuous data logging applications across various industries. THOR is designed for accelerated development timelines, leveraging low power and high-security features. Equipped with multi-protocol NFC capabilities and integrated temperature sensors, the THOR platform supports a wide range of external sensors, enhancing its adaptability to diverse monitoring needs. Its energy-efficient design allows operations via energy harvesting or battery power, ensuring sustainability in its applications. This platform finds particular utility in sectors demanding precise environmental monitoring and data management, such as logistics, pharmaceuticals, and industrial automation. The platform's capacity for AES/DES encrypted data logging ensures secure data handling, making it a reliable choice for sectors with stringent data protection needs.
Systems4Silicon's Digital PreDistortion (DPD) Solution is designed to significantly enhance the power efficiency of RF power amplifiers. This subsystem is complete and adaptive, providing a scalable solution that transcends the limitations typical of vendor-specific dependencies. On account of its universal compatibility, this IP core can be compiled for any ASIC or FPGA/SoC platform, serving as an all-encompassing solution suited for a diverse array of wireless communication systems such as 5G and multi-carrier setups. One of the standout features of the DPD technology is its capability to improve transmission bandwidth efficiently, offering scalability for bandwidths of up to 1 GHz or more. This positions the DPD solution as a forward-thinking technology, catering to modern demands for higher data rates and broader communication ranges. The adaptive nature of the solution ensures that it can modulate performance parameters in real-time, responding dynamically to varying operational conditions and system requirements, thereby maximizing amplifier efficiency across different setups. In operational terms, the DPD Solution is field-proven, reflecting its reliability and performance in real-world applications. It represents a versatile technology that integrates seamlessly with existing systems, delivering a robust enhancement to power amplifier efficiency while maintaining high compatibility with emerging communication standards. The flexibility of this technology makes it a vital asset in the infrastructure of contemporary wireless networks, ensuring smooth and efficient signal transmission.
The FCM1401 is a 14GHz CMOS Power Amplifier tailored for Ku-band applications, operating over a frequency range of 12.4 to 16 GHz. This amplifier exhibits a gain of 22 dB and a saturated output power (Psat) of 19.24 dBm, ensuring optimal performance with a power-added efficiency (PAE) of 47%. The architecture enables reduction in battery consumption and heat output, making it ideal for satellite and telecom applications. Its small silicon footprint facilitates integration in space-constrained environments.
SkyeChip's High-Speed PLL is designed for advanced clock management in ICs, accommodating a reference clock frequency range from 100MHz to 350MHz. This phase-locked loop offers a flexible feedback division (FBDIV) from 2 to 32, allowing extensive customization potential for various applications. The PLL produces output frequencies ranging from 300MHz to 3.2GHz, ideal for high-performance computing and communication systems. Its design guarantees a high degree of frequency stability and precision, crucial for effective clock distribution in chip designs. Equipped to operate efficiently even in challenging environments, it offers minimal power consumption, ensuring enhanced power efficiency. This makes it particularly valuable in designs sensitive to power usage and heat generation.
The 10G Ethernet MAC and PCS IP core from Chevin Technology is crafted to ensure seamless integration of high-speed Ethernet connectivity within FPGA platforms. This solution underscores Chevin Technology’s commitment to providing adaptable and resource-efficient Ethernet IP cores. Supporting a range of interfaces, it optimizes the synthesis of duplex 10Gbit/s Ethernet, making it ideal for implementation in systems that require high data throughput. The integration process is made effortless through detailed user guides and expert support, making it possible to incorporate this IP into varied FPGA platforms effectively. Its low-latency architecture supports high-performance communications while occupying minimal FPGA resources. Designed in accordance with IEEE 802.3 standards, this MAC/PCS core facilitates transmitting and receiving data at unrivalled speeds. The compact design ensures that broader functionalities and additional IP can comfortably reside on the FPGA, thereby enriching the application possibilities without inflating costs. Streamlining data transfer processes, the core offers flexible licensing to support various project needs, providing an unparalleled level of adaptability. With strategically laid out features that include CRC32 error detection and correction capabilities, the 10G Ethernet MAC and PCS IP core supports rapid data transfers while maintaining reliability. It incorporates advanced fault management and statistics blocks for detailed operational insights and robust performance monitoring. The core is compatible with leading industry boards and comes equipped with all necessary integrations to ensure optimal functionality across various platforms.
D2D® Technology, developed by ParkerVision, is a revolutionary approach to RF conversion that transforms how wireless communication operates. This technology eliminates traditional intermediary stages, directly converting RF signals to digital data. The result is a more streamlined and efficient communication process that reduces complexity and power consumption. By bypassing conventional analog-to-digital conversion steps, D2D® achieves higher data accuracy and reliability. Its direct conversion approach not only enhances data processing speeds but also minimizes energy usage, making it an ideal solution for modern wireless devices that demand both performance and efficiency. ParkerVision's D2D® technology continues to influence a broad spectrum of wireless applications. From improving the connectivity in smartphones and wearable devices to optimizing signal processing in telecommunication networks, D2D® is a cornerstone of ParkerVision's technological offerings, illustrating their commitment to advancing communication technology through innovative RF solutions.
The VCO25G is a Colpitts Voltage-Controlled Oscillator, featuring a low noise differential architecture suitable for applications up to 25.5GHz. Built using a cost-effective 0.18um SiGe process, this VCO is integral to high-performance PLLs, offering valuable benefits in broadband measurement and testing environments. It is designed for seamless integration within complex telecommunication systems, ensuring reliability and precision in frequency control with minimal environmental interference.
Silicon Creations offers a diverse suite of PLLs designed for a wide range of clocking solutions in modern SoCs. The Robust PLLs cover an extensive range of applications with their multi-functional capability, adaptable for various frequency synthesis needs. With ultra-wide input and output capabilities, and best-in-class jitter performances, these PLLs are ideal for complex SoC environments. Their construction ensures modest area consumption and application-appropriate power levels, making them a versatile choice for numerous clocking applications. The Robust PLLs integrate advanced designs like Low-Area Integer PLLs that minimize component usage while maximizing performance metrics, crucial for achieving high figures of merit concerning period jitter. High operational frequencies and superior jitter characteristics further position these PLLs as highly competitive solutions in applications requiring precision and reliability. By incorporating innovative architectures, they support precision data conversion and adaptable clock synthesis for systems requiring both integer and fractional-N modes without the significant die area demands found in traditional designs.
The CC-205 Wideband CMOS Rectifier stands out for its wide frequency rectification range, effectively working from 6 MHz to 5.8 GHz. This rectifier is capable of handling input power signals from -18 dBm up to +33 dBm, whilst maintaining impressive conversion efficiency between 40% to 90%. Without the need for a matching network, it directly interfaces with antennas, facilitating efficient power transfer. Its design includes a low S11 return loss of -40 dB, ensuring optimal power reception and usability in applications requiring broad frequency operation.
The mmWave PLL is meticulously designed to cater to applications that operate in the millimeter-wave frequency bands, delivering high frequency stability and low phase noise. This innovative product serves as a critical component in RF systems, particularly where high-frequency signals are required. Fantastically well-suited for cutting-edge wireless communication applications and advanced radar systems, the mmWave PLL's architecture supports frequencies up to 110 GHz. This provides a robust solution that enhances signal integrity and performance in complex communication systems. Versatile and adaptable, the mmWave PLL advances the capabilities of mmWave technology, making it indispensable for industries seeking to push the boundaries of data transmission and signal processing.
The pPLL08 Family represents Perceptia's suite of all-digital RF frequency synthesizer PLLs designed for high-frequency applications, such as 5G and WiFi. With frequencies reaching up to 8GHz and jitter below 300fs RMS, this PLL family is ideal for both RF LO clocks and the clocking of ADCs/DACs in rigorous RF environments. Featuring a compact architecture, these PLLs are built with a LC tank DCO to meet stringent performance specifications. Flexibility is a hallmark of this IP; it allows for seamless integration across various SoC designs, supported by robust performance across multiple foundry process nodes from 5nm to 40nm.
The JPEG2000 Video Compression Solution from StreamDSP offers a highly versatile compression framework capable of both lossless and lossy compression within a single codestream. Designed to support high-quality and high-compression-rate applications, this solution integrates seamlessly into a wide range of FPGA platforms. It stands out by enabling compression and decompression tasks to be performed directly within the FPGA, eliminating the need for external processors and reducing system complexity. This capability is particularly beneficial for applications such as digital cinema, surveillance, and archival digital imaging, where maintaining high fidelity while minimizing storage is critical.
The pPLL05 Family offers a line of low-power all-digital fractional-N PLLs that are ideally suited for IoT and embedded applications where energy efficiency is paramount. These PLLs operate at frequencies up to 1GHz, delivering clocking capabilities for moderate speed microprocessor blocks under a reduced power footprint of less than 1.0mW. The architecture is easily integrable into any system design, maintaining performance consistency across diverse processes. Silicon-proven from 40nm down to 5nm, these PLLs support integer and fractional multiplication for flexible frequency management in a variety of digital systems.
The DIV60G is a high frequency, fully differential frequency divider reaching up to 60GHz, ideal for sophisticated PLL applications and broadband measurement equipment. It includes an active balun with differential I/Q outputs, offering unparalleled frequency dividing capabilities. Its ultra-high frequency operating parameters are supported by a 0.18um SiGe process, making it particularly effective for use in environments requiring precision and low phase noise. Tailored for advanced industrial use, this divider provides substantial flexibility with differential inputs and outputs.
eSi-Analog integrates critical analog functionality into custom ASIC and SoC devices using leading foundry processes. It is optimized for low-power usage, ensuring efficiency and adaptability across a range of applications. This IP has been silicon-proven to meet custom specifications, providing reliability and performance in various high-demand sectors.
The Aeonic Integrated Droop Response System addresses droop issues in complex integrated circuits by combining mitigation and detection mechanisms in a seamlessly integrated package. This system supports fine-grained DVFS capability and rapid adaptation, providing significant power savings for SoCs. It offers comprehensive observability tools crucial for modern silicon health management, including multi-threshold detection and rapid response features within just a few clock cycles. This integration promotes energy efficiency by reducing voltage margins and supports various process technologies through a process portable design.
Moonstone Laser Sources by Lightelligence provide cutting-edge photonic solutions aimed at facilitating advanced optical computing applications. These laser sources are tailored for high precision and efficiency, essential for tasks demanding robust photonic performance. The unique attributes of Moonstone make it suitable for integration into diverse technological frameworks where precision and reliability are paramount. As the backbone of optical computing, laser sources like Moonstone ensure that photonic applications achieve desired speed and accuracy, fostering greater innovation in photonics-driven technologies. With their focus on precision and application flexibility, Moonstone Laser Sources empower industries to explore new frontiers in photonics, supporting the evolution of next-generation computing technologies.
The 802.11 LDPC is a high-throughput solution designed for efficient wireless communication. This product supports frame-to-frame, on-the-fly configurations, offering flexibility in decoding iterations to balance throughput and error correction. It is engineered to conform to necessary performance specifications, ensuring optimal bit-error-rate and packet-error-rate performance in wireless networks. Functionality-wise, the design excels in meeting demanding throughput requirements while maintaining superior error correction capabilities. By allowing flexible configuration of LDPC decoding iterations, the product empowers users to tailor performance based on specific needs. This flexibility is essential for networks requiring dynamic adaptation to changing conditions or varying environmental factors. Technically, the 802.11 LDPC is crafted to integrate seamlessly into existing communication infrastructures, providing robust support for maintaining high data rates even under challenging conditions. Its unique ability to balance performance and energy efficiency makes it a preferred choice for modern wireless applications, strengthening connectivity reliability across multiple devices and environments.
Aeonic Generate, part of Movellus' product family, offers a range of synthesizable, area-efficient clock generation solutions. These modules support high observability, enabling innovative approaches like per-core distributed clocking while also facilitating fine-grained droop response and DVFS innovation. The architecture is designed for broad process portability and post-silicon tunability, allowing features to adapt to different silicon conditions and application needs. Aeonic Generate is particularly beneficial for systems requiring exceptional testability and reliability, such as datacenter CPUs, AI accelerators, and automotive SoCs.
Analog Bits offers a diverse range of high-quality clocking solutions, optimized for low power consumption and customizable to meet specific customer requirements. These solutions include advanced phase-locked loops (PLLs) and oscillators designed for high-performance, wide-range integer/fractional applications across a variety of processes. The clocking products from Analog Bits are silicon-proven at advanced nodes such as 5nm and are in high-volume production. They are available at major fabrication facilities, ensuring availability and feasibility for various system-on-chip (SoC) designs. Their adaptability enables seamless integration into consumer, server, and automotive applications, supporting robust and reliable clock generation across multiple platforms. By offering customizable options, Analog Bits addresses specific needs, providing superior phase noise performance and low jitter. Their clocking solutions also support PCIe reference clock subsystems, ensuring broad compatibility and high integration for modern semiconductor technologies.
The pPLL02F Family is a comprehensive collection of all-digital fractional-N PLLs tailored for general-purpose applications. It integrates seamlessly into systems requiring moderate speed digital logic, especially suitable as a clock source for microprocessor blocks. Operating at up to 2GHz, these PLLs maintain low jitter (<18ps RMS) and consume minimal power (<3.5mW), making them ideal for multi-domain clock systems. The architecture supports both integer and fractional multiplication, offering flexibility in clock frequency configuration. This IP is silicon-proven across process technologies spanning from 5nm to 40nm, enabling broad adaptability across various foundries.
The PLL12G, serving as a Clock Multiplication Unit, is engineered to generate clock outputs in the 8.5GHz to 11.3GHz range, complementing a host of transceiver standards like 10GbE and OC-192. It operates with low power consumption, courtesy of IBM's 65nm process, making it suitable for various clocking modes crucial in phase-locked loop systems. Its diverse functionality ensures it's integral to telecommunications infrastructures where multiple clocking modes, including FEC support, are required.
The UltraLong FFT core from Dillon Engineering offers exceptional performance for applications requiring extensive sequence lengths. This core utilizes external memory in coordination with dual FFT engines to facilitate high throughput. While it typically hinges on memory bandwidth for its speed, the UltraLong FFT effectively processes lengthy data sequences in a streamlined manner. This core is characterized by its medium to high-speed capabilities and is an excellent choice for applications where external memory can be leveraged to support processing requirements. Its architecture allows for flexible design implementation, ensuring seamless integration with existing systems, and is particularly well-suited for advanced signal processing applications in both FPGA and ASIC environments. With Dillon's ParaCore Architect tool, customization and re-targeting of the IP core towards any technology are straightforward, offering maximum adaptability. This FFT solution stands out for its capacity to manage complex data tasks, making it an ideal fit for cutting-edge technologies demanding extensive data length processing efficiency.
The DIV50G1 is a programmable prescaler operating up to 50GHz with various dividing coefficients. Its design caters to high-precision applications requiring careful frequency management and offers single-ended or differential inputs with differential outputs. This flexibility supports integration into complex PLL circuits and broadband measurement gear. The technological foundation is a robust 0.18um SiGe process, ensuring reliability and superior performance for advanced technological applications demanding frequency adjustability and precision.
Thermal oxide, often referred to as SiO2, is an essential film used in creating various semiconductor devices, ranging from simple to complex structures. This dielectric film is created by oxidizing silicon wafers under controlled conditions using high-purity, low-defect silicon substrates. This process produces a high-quality oxide layer that serves two main purposes: it acts as a field oxide to electrically insulate different layers, such as polysilicon or metal, from the silicon substrate, and as a gate oxide essential for device function. The thermal oxidation process occurs in furnaces set between 800°C to 1050°C. Utilizing high-purity steam and oxygen, the growth of thermal oxide is meticulously controlled, offering batch thickness uniformity of ±5% and within-wafer uniformity of ±3%. With different techniques used for growth, dry oxidation results in slower growth, higher density, and increased breakdown voltage, whereas wet oxidation allows faster growth, even at lower temperatures, facilitating the formation of thicker oxides. NanoSILICON, Inc. is equipped with state-of-the-art horizontal furnaces that manage such high-precision oxidation processes. These furnaces, due to their durable quartz construction, ensure stability and defect-free production. Additionally, the processing equipment, like the Nanometrics 210, inspects film thickness and uniformity using advanced optical reflection techniques, guaranteeing a high standard of production. With these capabilities, NanoSILICON Inc. supports a diverse range of wafer sizes and materials, ensuring superior quality oxide films that meet specific needs for your semiconductor designs.
TechwidU's Band-Gap Reference provides a stable voltage output ranging from 0.6V to 1.2V, crucial for ensuring the reliable operation of electronic circuits. This component is pivotal in generating a consistent reference voltage across variations in environmental conditions such as temperature and power supply changes. Designed with Magna, Samsung, and TSMC’s advanced nodes, it promises precision and efficiency with an operational current of 25µA.
Certus Semiconductor's Analog I/O offerings bring ultra-low capacitance and robust ESD protection to the forefront. These solutions are crafted to handle extreme voltage conditions while securing signal integrity by minimizing impedance mismatches. Key features include integrated ESD and power clamps, support for broad RF frequencies, and the ability to handle signal swings below ground. Ideal for high-speed RF applications, these Analog I/Os provide superior protection and performance, aligning with the most demanding circuit requirements.
The EAMD12G serves as a modulator driver for EA/MZ applications, tailored specifically to drive up to 11.3Gb/s in fiber optic communications. It features programmable output voltage swing and DC offset adjustment, with built-in monitoring capabilities to ensure precision in modulation tasks. Integrated within the robust TowerJazz 0.18um SiGe process, it is adept for high-frequency operation necessary for effective data transmission in modern broadband setups.
CoreVCO stands as a versatile voltage-controlled oscillator design, optimized for high performance in RF and mixed-signal environments. Known for its rapid switching capabilities and wide frequency range, it's ideal for applications that require agile frequency control. This VCO maintains low phase noise and a high tuning linearity, ensuring stable outputs across variable conditions. Its design emphasizes compactness and power efficiency, making it suitable for portable and space-constrained devices. The robust output power and phase noise characteristics make CoreVCO particularly appealing for high-fidelity electronic systems. CoreVCO is engineered to integrate seamlessly into a range of electronic applications, enhancing the functionality and reliability of RF transceivers, signal generators, and phase-locked loops. Its adaptability allows customization to meet specific project demands, supporting diverse technologies across various sectors.
The AFX010x Product Family by SCALINX is a leading-edge range of Analog Front Ends designed for both benchtop and portable data-acquisition systems. These AFEs offer up to four channels, each with up to a 16-bit resolution and a high sampling rate reaching 5 GSps. Additionally, they come with a digitally-selectable 3dB bandwidth, which can range up to 300MHz, and feature an integrated single-to-differential amplifier and offset DAC. These AFEs are known for their low power consumption and high signal integrity. This makes them suitable for high sampling rate and wide bandwidth requirements, ensuring a high level of integration. The package includes programmable input capacitance, a programmable gain amplifier (PGA), an offset DAC, an ADC, and a digital processor within each channel, all within a standard 12mm × 12mm, 196-Ball BGA. The AFX010x family uses SCALINX’s proprietary SCCORE™ technology, which reduces the PCB footprint and cuts power consumption by up to 50%. This results in products that are pin-to-pin compatible across different AFX010x variants, providing users with flexibility in terms of power modes and performance configurations.
Aeonic Insight provides advanced on-die telemetry for actionable insights across various system components. Built specifically for SoCs, it enhances observability and programmability in environments ranging from datacenters and AI accelerators to aerospace and automotive applications. The sensors offer deep visibility into power grids, clock health, and other essential elements, maintaining high efficiency across advanced technology nodes. With industry-standard interfaces, these sensors enable easy collaboration with third-party analytic platforms, allowing teams to tailor design operations to specific requirements and conditions.
The VCOMB12G is an advanced low noise multi-band LC voltage-controlled oscillator designed for sophisticated phase-locked loop applications, particularly in fiber optic systems. This oscillator offers a wide frequency range and supports multiple clocking modes, providing essential flexibility in cutting-edge communication systems. It is capable of integrating seamlessly into complex digital frameworks where accurate frequency tuning is crucial. Its design ensures minimal power consumption, promoting energy efficiency without sacrificing performance.
Tower Semiconductor's RF-SOI and RF-CMOS platforms are tailored for cutting-edge wireless communication systems. These technologies cater to the burgeoning need for high-speed and high-performance RF solutions essential for modern telecommunications and mobile platforms. RF-SOI technology offers exceptional isolation and integration capabilities, significantly boosting performance in RF front-end modules. It's particularly optimal for devices operating in multi-band and carrier aggregation situations, ensuring seamless connectivity and data integrity. On the other hand, the RF-CMOS platform leverages CMOS processes to achieve cost-effective solutions while maintaining high RF performance levels, ideal for mass-produced consumer electronics. The combination of SOI and CMOS processes leads to advanced flexibility and improved yield, supporting the stringent requirements of mobile workloads. These technologies empower the development of compact, power-efficient, and high-performance wireless communication devices, positioning them well ahead in the fast-evolving telecommunications landscape.
hellaPHY Positioning Solution is an advanced edge-based software that significantly enhances cellular positioning capabilities by leveraging 5G and existing LTE networks. This revolutionary solution provides accurate indoor and outdoor location services with remarkable efficiency, outperforming GNSS in scenarios such as indoor environments or dense urban areas. By using the sparsest PRS standards from 3GPP, it achieves high precision while maintaining extremely low power and data utilization, making it ideal for massive IoT deployments. The hellaPHY technology allows devices to calculate their location autonomously without relying on external servers, which safeguards the privacy of the users. The software's lightweight design ensures it can be integrated into the baseband MCU or application processors, offering seamless compatibility with existing hardware ecosystems. It supports rapid deployment through an API that facilitates easy integration, as well as Over-The-Air updates, which enable continuous performance improvements. With its capability to operate efficiently on the cutting edge of cellular standards, hellaPHY provides a compelling cost-effective alternative to traditional GPS and similar technologies. Additionally, its design ensures high spectral efficiency, reducing strain on network resources by utilizing minimal data transmission, thus supporting a wide range of emerging applications from industrial to consumer IoT solutions.
Kamaten's General Use PLL is an integer-N phase-locked loop solution that offers notable versatility across various applications. Capable of operating across a wide frequency range from 0.5 GHz to 4.0 GHz, it is engineered for low noise and minimal spurious outputs, ensuring signal integrity and high performance in electronic and communication systems. This PLL is optimized for seamless adaptability, providing any division from 1 to 32 or 1 to 64 at lower frequencies. Its architecture incorporates auto-calibration and fast lock features to enhance accuracy and efficiency, reducing the design time and complexity associated with tuning analog phase-locked loops. Fabricated on TSMC’s 28HPC process, this PLL is well-suited for applications needing stable clock generation and low noise characteristics. Designed for efficient power consumption, it draws only 4 mA at 400 MHz. The PLL is poised to meet the demands of modern high-frequency systems, offering a reliable solution for engineers focused on minimizing jitter and achieving rapid lock times.
The FCM3801-BD is designed for those requiring 39GHz CMOS Power Amplification within the 5G mmWave range. It supports frequencies from 32 to 44 GHz, featuring a 19 dB gain and a Psat of 18.34 dBm. With a PAE of 45%, this amplifier is engineered for high-power applications where efficiency and thermal management are crucial. It's particularly suited for modern telecom environments requiring minimal energy use and weight savings.
This product provides high-accuracy hardware synchronization for video equipment over IP networks, essential for generating precise timing signals crucial for audio and video systems. It is compliant with IEEE1588v2 and supports both 2059-1 and 2059-2 standards. The synchronization system combines both software and hardware elements to offer a versatile solution for industries reliant on synchronized media equipment.
The JESD204B Multi-Channel PHY is a versatile high-speed data interface designed to handle numerous channels simultaneously. Its architecture supports top speeds reaching 12.5Gbps, which is crucial in applications where data transfer efficiency and reliability are paramount. This technology is often employed in systems requiring high bandwidth and precision synchronization, making it ideal for advanced communication networks and high-resolution broadcasting environments. This product stands out for its capacity to neatly integrate with various semiconductor processes, ensuring seamless compatibility and broad functionality. Whether in complex signal processing or high-speed data acquisition contexts, it provides the necessary infrastructure to maintain robust data transmission with minimal latency and power consumption. Moreover, the JESD204B Multi-Channel PHY is designed to support multiple serial data rates, offering great flexibility to developers working within diverse technology applications. Its comprehensive design ensures that it meets the standards of modern digital systems, helping to push the envelope of data-transfer capabilities in state-of-the-art technological infrastructures.
The Pipelined FFT core by Dillon Engineering is engineered to support continuous data streams with its ranked pipelined architecture. This design accommodates efficient data processing with minimal memory requirement, making it an exceptional option for ongoing signal processing tasks requiring low latency. This architecture utilizes a single butterfly per rank, optimizing the processing capability for applications where minimal memory footprint and consistent throughput are paramount. The Pipelined FFT stands as a streamlined solution for real-time digital signal processing, ensuring data accuracy and swift computations without the need for significant storage or delay operations. Dillon's ParaCore Architect allows for seamless adaptation of this IP core across a wide range of hardware platforms, ensuring its applicability to both FPGA and ASIC designs. Its versatile nature accommodates rapid design shifts, making the Pipelined FFT a preferred choice for projects requiring quick and efficient data stream processing.
SiGe BiCMOS technology is tailored for RF applications, delivering excellent performance for high-frequency communications. This technology supports low noise figures and high linearity, vital for advanced communication systems. In the growing landscape of RF solutions, this process technology allows for enhanced integration and miniaturization of components, driving innovations in wireless communication. High precision transistors in this technology facilitate the development of superior RF transceivers, suitable for complex and demanding applications. It's well-suited for use in infrastructure systems where robust and reliable RF signal processing is crucial. By integrating both bipolar and CMOS transistors, this platform offers the best of both worlds, combining high-speed performance with power efficiency. Designed for versatility, the SiGe BiCMOS technology simplifies the design of RF circuits by allowing adaptability in circuit design and process options. This feature is particularly beneficial for designers working on next-generation wireless devices, pushing boundaries in speed and functionality.
The Integer-N PLL-based HF Frequency Synthesizer and Clock Generator is designed for high-frequency applications requiring precise timing and signal generation. It operates on a PLL architecture that ensures accurate frequency synthesis and signal stability, making it essential for communication systems and high-performance computing applications.
TimeServoPTP extends the capabilities of the TimeServo core, providing a comprehensive IEEE 1588v2 PTP compliant ordinary clock slave implementation for FPGAs. This solution enables the achievement of high-level synchronization through both 1-Step and 2-Step processes with external network time grandmasters, addressing the needs for precise timing in distributed systems. By communicating with PTP masters via standard Ethernet L2 frames, TimeServoPTP ensures consistent time coherence across varied output domains, proving essential in applications where clock synchronization is critical. The single-component structure eases the implementation in complex FPGA systems, reducing dependency on external processors while maintaining a flexible architecture that supports multiple clock domains and user-defined outputs. Incorporating a digital phase locked loop, TimeServoPTP ensures accuracy and stability in timing to a microsecond level, making it ideal for synchronization tasks in telecom networks and data centers. The solution's compatibility with both Intel Agilex and Xilinx UltraScalePlus enhances its deployability across major FPGA platforms.
Pico Semiconductor's high-performance PLLs and DLLs are designed to minimize noise while delivering robust performance across various frequency ranges. These components support critical operations in electronics by synchronizing the timing of various integrated circuits, ensuring smooth and efficient performance. The PLL offerings include low noise capabilities with operating frequencies reaching up to 5GHz, suitable for a diverse set of applications that require precise clock generation and signal synchronization. Variants include designs that operate at 3.25GHz and a wide range from 135MHz to 945MHz, adapting to the needs of different systems and environmental conditions. These PLLs and DLLs are particularly essential in multichannel and high-speed data applications where timing accuracy and signal integrity are crucial. They facilitate high-speed data transfer and integration with other components, enhancing the overall system efficiency while reducing power consumption.
Cobalt is a cutting-edge GNSS receiver that is expertly designed to offer ultra-low-power functionality, specifically tailored to IoT Systems-on-Chip. It is engineered to extend the market potential of IoT devices by integrating essential GNSS capabilities into modem SoCs. This not only conserves energy but also ensures that devices maintain compact sizes, essential for applications sensitive to size constraints and energy efficiency. Cobalt features a software-defined receiver capable of supporting major constellations such as Galileo, GPS, and Beidou, ensuring a broad reach and reliable performance in varied environments. Its standalone and cloud-assisted positioning functions optimize power usage, allowing for enhanced sensitivity and finer accuracy even in challenging conditions. Developed in collaboration with CEVA DSP and backed by the European Space Program Agency, Cobalt incorporates advanced processing techniques that improve resistance to multi-path interference and enhance modulation rates. This ensures that IoT devices utilizing Cobalt are equipped with state-of-the-art geolocation services, vital for sectors like logistics, agriculture, and mobility solutions.
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