All IPs > Analog & Mixed Signal > PLL
The Analog & Mixed Signal PLL (Phase-Locked Loop) category of semiconductor IP at Silicon Hub encompasses a collection of sophisticated circuit designs used primarily for frequency synthesis, clock management, and timing in integrated circuits. PLLs are indispensable in a variety of electronic applications where synchronized frequency and phase-locked signals are crucial. This class of semiconductor IPs is pivotal for ensuring stable and reliable operations in digital and analog systems alike.
PLLs are widely utilized in communication systems, consumer electronics, and computing devices. In communication systems, they play a critical role in modulating and demodulating signals, ensuring accurate data transmission. Consumer electronics, such as smartphones, tablets, and gaming devices, leverage PLL technology to maintain accurate system clocks, which is essential for digital signal processing and multimedia performance. In computing, PLLs help in maintaining synchronous operations between processors and memory, allowing seamless multitasking and high-speed data processing.
Within this category, you will find a variety of PLL designs and architectures, each tailored to specific application needs, including fractional-N PLLs, integer-N PLLs, and Delay-Locked Loops (DLLs). These variants offer different advantages, such as reduced phase noise, higher frequency stability, and improved design flexibility. Additionally, some advanced PLL IPs incorporate features like spread spectrum clocking to minimize electromagnetic interference, making them suitable for use in sensitive electronic environments.
Overall, the Analog & Mixed Signal PLL semiconductor IPs available at Silicon Hub are integral components that help optimize the performance, efficiency, and reliability of modern electronic systems. They enable designers and engineers to tackle complex clocking requirements and achieve precise control over signal timing, which is a cornerstone of innovation in technology sectors ranging from telecom to computing and beyond.
Silicon Creations delivers precision LC-PLLs designed for ultra-low jitter applications requiring high-end performance. These LC-tank PLLs are equipped with advanced digital architectures supporting wide frequency tuning capabilities, primarily suited for converter and PHY applications. They ensure exceptional jitter performance, maintaining values well below 300fs RMS. The LC-PLLs from Silicon Creations are characterized by their capacity to handle fractional-N operations, with active noise cancellation features allowing for clean signal synthesis free of unwanted spurs. This architecture leads to significant power efficiencies, with some IPs consuming less than 10mW. Their low footprint and high frequency integrative capabilities enable seamless deployments across various chip designs, creating a perfect balance between performance and size. Particular strength lies in these PLLs' ability to meet stringent PCIe6 reference clocking requirements. With programmable loop bandwidth and an impressive tuning range, they offer designers a powerful toolset for achieving precise signal control within cramped system on chip environments. These products highlight Silicon Creations’ commitment to providing industry-leading performance and reliability in semiconductor design.
The Ring PLLs offered by Silicon Creations illustrate a versatile clocking solution, well-suited for numerous frequency generation tasks within integrated circuit designs. Known for their general-purpose and specialized applications, these PLLs are crafted to serve a massive array of industries. Their high configurability makes them applicable for diverse synthesis needs, acting as the backbone for multiple clocking strategies across different environments. Silicon Creations' Ring PLLs epitomize high integration with functions tailored for low jitter and precision clock generation, suitable for battery-operated devices and systems demanding high accuracy. Applications span from general clocking to precise Audio Codecs and SerDes configurations requiring dedicated performance metrics. The Ring PLL architecture achieves best-in-class long-term and period jitter performance with both integer and fractional modes available. Designed to support high volumes of frequencies with minimal footprint, these PLLs aid in efficient space allocation within system designs. Their use of silicon-proven architectures and modern validation methodologies assure customers of high reliability and quick integration into existing SoC designs, emphasizing low risk and high reward configurations.
Altek's 3D Imaging Chip is a breakthrough in the field of vision technology. Designed with an emphasis on depth perception, it enhances the accuracy of 3D scene capturing, making it ideal for applications requiring precise distance gauging such as autonomous vehicles and drones. The chip integrates seamlessly within complex systems, boasting superior recognition accuracy that ensures reliable and robust performance. Building upon years of expertise in 3D imaging, this chip supports multiple 3D modes, offering flexible solutions for devices from surveillance robots to delivery mechanisms. It facilitates medium-to-long-range detection needs thanks to its refined depth sensing capabilities. Altek's approach ensures a comprehensive package from modular design to chip production, creating a cohesive system that marries both hardware and software effectively. Deployed within various market segments, it delivers adaptable image solutions with dynamic design agility. Its imaging prowess is further enhanced by state-of-the-art algorithms that refine image quality and facilitate facial detection and recognition, thereby expanding its utility across diverse domains.
Digital Predistortion (DPD) is a sophisticated technology crafted to optimize the power efficiency of RF power amplifiers. The flagship product, FlexDPD, presents a complete, adaptable sub-system that can be customized to any ASIC or FPGA/SoC platform. Thanks to its scalability, it is compatible with various device vendors. Designed for high performance, this DPD solution significantly boosts RF efficiencies by counteracting signal distortion, ensuring clear and effective transmission. The core of the DPD solution lies in its adaptability to a broad range of systems including 5G, multi-carrier platforms, and O-RAN frameworks. It's built to handle transmission bandwidths exceeding 1 GHz, making it a versatile and future-proof technology. This capability not only enhances system robustness but also offers a seamless integration pathway for next-generation communication standards. Additionally, Systems4Silicon’s DPD solution is field-tested, ensuring reliability in real-world applications. The solution is particularly beneficial for projects that demand high signal integrity and efficiency, providing a tangible advantage in competitive markets. Its compatibility with both ASIC and FPGA implementations offers flexibility and choice to partners, significantly reducing development time and cost.
This IP core is engineered for applications where minimal latency is of paramount importance. The Ultra-Low Latency 10G Ethernet MAC features an optimized architecture to provide rapid data transmission and reception capabilities, ensuring that all processes occur smoothly and efficiently. It is tailored specifically for real-time operations where every millisecond counts, like high-frequency trading and real-time monitoring systems. By focusing on reducing latency, this Ethernet MAC core delivers exceptional performance, making it an excellent choice for demanding environments that cannot afford delayed communication. The core's architecture reduces overhead and maximizes throughput, leveraging Chevin Technology's advanced design expertise to minimize signal interference and processing delays. Its seamless integration with both AMD and Intel FPGA platforms makes it versatile for a variety of implementations across industry sectors. Moreover, it's designed to maintain optimal performance while managing high data loads, showcasing a consistent ability to handle extensive network traffic efficiently.
This core is designed for high-performance applications requiring robust Ethernet connectivity with a high data throughput. The 10G Ethernet MAC and PCS solutions are developed to reliably handle speeds up to 10Gbps, optimizing the interface between Ethernet transmission and physical network layers. These IPs provide key functionality that helps maintain efficient data handling and transfer across networks, ensuring minimal latency and maximum productivity. Featuring refined architecture and robust design, this solution integrates seamlessly into FPGA frameworks, especially targeting Intel and AMD platforms. Its compatibility and reliability make it ideal for advanced networking tasks in a broad range of applications—from data centers to complex cloud infrastructures. The efficient management of data streams through this MAC and PCS combination ensures high-speed communication and responsiveness critical to high-demand environments. Its plug-and-play usability allows it to be quickly incorporated into existing systems, providing a flexible solution that maintains the scalability and performance needs of high-end systems. Additionally, Chevin Technology's expertise ensures that these cores come with comprehensive support tailored to enhance product integration and deployment efficiency.
Silicon Creations offers a diverse suite of PLLs designed for a wide range of clocking solutions in modern SoCs. The Robust PLLs cover an extensive range of applications with their multi-functional capability, adaptable for various frequency synthesis needs. With ultra-wide input and output capabilities, and best-in-class jitter performances, these PLLs are ideal for complex SoC environments. Their construction ensures modest area consumption and application-appropriate power levels, making them a versatile choice for numerous clocking applications. The Robust PLLs integrate advanced designs like Low-Area Integer PLLs that minimize component usage while maximizing performance metrics, crucial for achieving high figures of merit concerning period jitter. High operational frequencies and superior jitter characteristics further position these PLLs as highly competitive solutions in applications requiring precision and reliability. By incorporating innovative architectures, they support precision data conversion and adaptable clock synthesis for systems requiring both integer and fractional-N modes without the significant die area demands found in traditional designs.
The High-Speed Phase-Locked Loop (PLL) is a versatile frequency synthesizer designed to accommodate a broad range of applications. Offering a clock frequency range from 100 MHz to 350 MHz, with VCO capabilities extending up to 3.2 GHz, this PLL ensures precise timing synchronization essential for high-speed data communications and processing. By providing output frequencies ranging from 300 MHz to 3.2 GHz, this PLL is ideal for optimizing performance in sophisticated electronic systems, delivering high fidelity and stability across variable operating conditions. Its configurable nature allows for tailored frequency division, supporting both synchronous and source-synchronous setups. Such flexibility and performance make it an indispensable component for enhancing clock system reliability and efficiency in modern digital architectures.
This mmWave PLL is engineered to deliver exceptional performance in high-frequency applications, such as mmWave communications and advanced radar systems. The IP offers remarkable frequency synthesis capabilities, essential for the operation of modern communication networks and sensors, including the growing 5G infrastructure and automotive radar technologies. The design incorporates mechanisms to optimize phase noise and enhance frequency stability, which are critical in minimizing signal distortion in high-bandwidth transmissions. This PLL is compact yet powerful, making it an excellent choice for systems where space and performance are at a premium. Suitable for integration into a variety of RF and mmWave architectures, the mmWave PLL supports applications across telecommunications, automotive, and beyond. It helps designers achieve superior system performance while maintaining low latency and high data throughput.
The THOR platform is a versatile tool for developing application-specific NFC sensor and data logging solutions. It incorporates silicon-proven IP blocks, creating a comprehensive ASIC platform suitable for rigorous monitoring and continuous data logging applications across various industries. THOR is designed for accelerated development timelines, leveraging low power and high-security features. Equipped with multi-protocol NFC capabilities and integrated temperature sensors, the THOR platform supports a wide range of external sensors, enhancing its adaptability to diverse monitoring needs. Its energy-efficient design allows operations via energy harvesting or battery power, ensuring sustainability in its applications. This platform finds particular utility in sectors demanding precise environmental monitoring and data management, such as logistics, pharmaceuticals, and industrial automation. The platform's capacity for AES/DES encrypted data logging ensures secure data handling, making it a reliable choice for sectors with stringent data protection needs.
The CC-205 Wideband CMOS Rectifier is engineered for direct interfacing with antennas without the necessity of a matching network, accommodating a rectification range from 6MHz to 5.8GHz. It ensures efficient power conversion with a flexible input power range from -18dBm to over +33dBm, offering conversion efficiencies between 40% and 90%. This rectifier optimizes power transfer through very low return losses, enhancing the applicability in a range of RF environments and systems, thus maximizing efficiency.
D2D® Technology, developed by ParkerVision, is a revolutionary approach to RF conversion that transforms how wireless communication operates. This technology eliminates traditional intermediary stages, directly converting RF signals to digital data. The result is a more streamlined and efficient communication process that reduces complexity and power consumption. By bypassing conventional analog-to-digital conversion steps, D2D® achieves higher data accuracy and reliability. Its direct conversion approach not only enhances data processing speeds but also minimizes energy usage, making it an ideal solution for modern wireless devices that demand both performance and efficiency. ParkerVision's D2D® technology continues to influence a broad spectrum of wireless applications. From improving the connectivity in smartphones and wearable devices to optimizing signal processing in telecommunication networks, D2D® is a cornerstone of ParkerVision's technological offerings, illustrating their commitment to advancing communication technology through innovative RF solutions.
The Silicon Creations Programmable Delta-Sigma Fractional PLL is a multi-function, general purpose frequency synthesizer. Ultra-wide input and output ranges along with best-in-class jitter performance allow the PLL to be used for almost any clocking application. With excellent supply noise immunity, the PLL is ideal for use in noisy mixed-signal SoC environments. By combining ultra-low jitter output clocks into a low power, low area, widely programmable design, Silicon Creations can greatly simplify an SoC by enabling a single macro to be used for all clocking applications in the system.
Analog Bits specializes in delivering high-performance clocking solutions that are crucial for synchronizing operations within complex semiconductor systems. Their clocking IP includes a range of highly programmable Phase-Locked Loops (PLLs), which ensure precise timing control across a wide frequency range. These solutions are designed to support stringent power management requirements, offering low jitter and high reliability, which are critical in maintaining system integrity. The company's clocking IPs are silicon-proven across multiple process nodes, including some of the most advanced in the industry like TSMC's N3 and N5, ensuring robust performance in a variety of environmental conditions. These solutions are suitable for applications requiring sophisticated timing precision such as data centers, telecommunications, and consumer electronics, where downtime or errors can lead to significant operational costs. Incorporating features such as programmable frequency settings and dynamic power scaling, these IPs offer flexibility and adaptability, meeting the diverse needs of different design architectures. Their clock generators are pivotal in managing the distribution and synchronization of signals, making them indispensable in modern chip designs.
The FCM1401 Dual-Drive™ Power Amplifier is tailored for Ku-band applications, utilizing CMOS technology to deliver solutions between 12.4 to 16 GHz. This product is designed to optimize power output while maintaining a compact silicon footprint. Notable for its excellent efficiency, the FCM1401 addresses the specific demands of telecom and satellite communications applications. The amplifier provides reliable performance characterized by a gain of 22 dB and a Psat of 19.2 dBm, achieving a power-added efficiency of 47% while operating at a supply voltage of 1.8V. Through these specifications, it positions itself as an ideal solution for applications requiring high power output and minimal heat generation. This product benefits from world-class CMOS integration, ensuring compatibility with modern telecom systems, enhancing their range and reducing their energy costs. The FCM1401 is equipped with a QFN/EVB package, allowing for straightforward implementation in various industrial contexts. It sets itself apart by offering an increased frequency range while delivering robust power handling capabilities, facilitating the high RF power needs of contemporary communication systems. The dual-drive capability of the FCM1401 means that it can effectively double the input signal power into the output without losing efficiency, making it highly suited for use in mission-critical operations where reliability and performance are paramount. Its high power-added efficiency also translates to cooler operation, reducing the need for extensive thermal management solutions, thus lowering associated costs.
The BlueLynx Chiplet Interconnect system provides an advanced die-to-die connectivity solution designed to meet the demanding needs of diverse packaging configurations. This interconnect solution stands out for its compliance with recognized industry standards like UCIe and BoW, while offering unparalleled customization to fit specific applications and workloads. By enabling seamless connection to on-die buses and Networks-on-Chip (NoCs) through standards such as AMBA, AXI, ACE, and CHI, BlueLynx facilitates faster and cost-effective integration processes. The BlueLynx system is distinguished by its adaptive architecture that maximizes silicon utilization, ensuring high bandwidth along with low latency and power efficiency. Designed for scalability, the system supports a remarkable range of data rates from 2 to 40+ Gb/s, with an impressive bandwidth density of 15+ Tbps/mm. It also provides support for multiple serialization and deserialization ratios, ensuring flexibility for various packaging methods, from 2D to 3D applications. Compatible with numerous process nodes, including today’s most advanced nodes like 3nm and 4nm, BlueLynx offers a progressive pathway for chiplet designers aiming to streamline transitions from traditional SoCs to advanced chiplet architectures.
The Aeonic Integrated Droop Response System is a groundbreaking approach to managing voltage droop in complex IC environments. This solution combines fast multi-threshold detection with churn-key integration of fine-grained dynamic voltage and frequency scaling capabilities. It offers advanced features such as tight coupling of droop detection and response, leading to the fastest commercial adaptation times that can significantly reduce margin requirements and power usage. The system’s observability features provide valuable data for silicon health assessments and lifecycle management. Process portability ensures scalability across different technology nodes, making the solution versatile for use in various sophisticated systems. This system is crucial for managing droop-induced challenges, and its integration with current architectures leads to enhanced system power and performance efficiency.
The Band-Gap Reference is a vital component in sustaining circuit stability by providing a precise voltage reference. It delivers adjustable output from 0.6V to 1.2V, optimized for generating stable voltage references critical in precision electronic applications. Leveraging process technologies from Magna, Samsung, and TSMC at various nodes including 130nm, 180nm, and 65nm, this component assures silicon-proven reliability under diverse operations. Its minimal operational current of 25 microamperes combined with 1% to 3% accuracy allows it to fit key roles in power-sensitive and precision-demanding components. Incorporated in numerous semiconductor designs, the Band-Gap Reference aids in achieving consistent circuit performance, underpinning the accuracy of analog-to-digital conversions and other signal processing tasks. It is fundamental for maintaining system stability across a range of conditions due to its resilient design characteristics.
Tailored to modern SoC requirements, Aeonic Generate provides synthesizable and highly area-efficient solutions for clock generation. These solutions are central to innovative architectural strategies, including per-core distributed clocking, offering robust observability for system diagnostics and optimization. The Aeonic Generate family includes mechanisms to enable dynamic voltage and frequency scaling (DVFS), catering to specific needs such as fast droop response and fine-grained control. This flexibility enhances system power efficiency and supports architectural innovation. Moreover, the product offers extensive telemetry for droop and clock health, thus ensuring that post-silicon debug and operational fidelity are maintained. The modules ensure swift adaptation across numerous nodes due to their process portability. Aeonic Generate's systems provide practical benefits in diverse sectors, including data centers, 5G, aerospace, and automotive, showcasing high reliability and testability crucial for these demanding applications.
The MVWS4000 series integrates three crucial environmental sensing modalities—humidity, pressure, and temperature—into a single, compact package. These digital sensors are built on a proprietary Silicon Carbide platform, offering enhanced reliability and energy efficiency. Ideal for OEM and battery-operated devices, they bridge the gap between performance and power conservation.\n\nThese sensors exhibit remarkable accuracy, with 1.5% for humidity, 1.0 hPa for pressure, and 0.3°C for temperature. Crafted for long-term stability, the sensors are suitable for demanding, resource-constrained applications. Their compact dimensions, along with a desirable operating range, make them versatile for various implementations.\n\nGiven their design for reduced energy use, these sensors are excellent for portable and embedded systems. With digital interfaces, including I2C and SPI, they offer flexible integration paths for manufacturers aiming to meet varied application requirements in industrial, consumer, medical, and automotive sectors.
Thermal oxide, often referred to as SiO2, is an essential film used in creating various semiconductor devices, ranging from simple to complex structures. This dielectric film is created by oxidizing silicon wafers under controlled conditions using high-purity, low-defect silicon substrates. This process produces a high-quality oxide layer that serves two main purposes: it acts as a field oxide to electrically insulate different layers, such as polysilicon or metal, from the silicon substrate, and as a gate oxide essential for device function. The thermal oxidation process occurs in furnaces set between 800°C to 1050°C. Utilizing high-purity steam and oxygen, the growth of thermal oxide is meticulously controlled, offering batch thickness uniformity of ±5% and within-wafer uniformity of ±3%. With different techniques used for growth, dry oxidation results in slower growth, higher density, and increased breakdown voltage, whereas wet oxidation allows faster growth, even at lower temperatures, facilitating the formation of thicker oxides. NanoSILICON, Inc. is equipped with state-of-the-art horizontal furnaces that manage such high-precision oxidation processes. These furnaces, due to their durable quartz construction, ensure stability and defect-free production. Additionally, the processing equipment, like the Nanometrics 210, inspects film thickness and uniformity using advanced optical reflection techniques, guaranteeing a high standard of production. With these capabilities, NanoSILICON Inc. supports a diverse range of wafer sizes and materials, ensuring superior quality oxide films that meet specific needs for your semiconductor designs.
This technology represents a significant innovation in the field of wireless energy transfer, allowing for the efficient transmission of power without physical connections or radiation. By leveraging magnetic resonance, this non-radiative energy transfer system can power devices over distances with high efficiency. It's designed to be safe and environmentally friendly, avoiding the pitfalls of electromagnetic radiation while maintaining a high level of power transfer efficiency. The technology finds its applications in various sectors, including consumer electronics, automotive, and industrial applications where it provides a seamless and reliable solution to power transfer needs. The system's capability to transfer power efficiently without contact makes it ideal for scenarios where traditional power connections might be impractical or inconvenient, enabling new levels of convenience and flexibility for users. Designed to integrate smoothly with existing infrastructure, this energy transfer system can significantly reduce reliance on traditional charging methods, paving the way for more innovative and sustainable energy solutions. Furthermore, the system's architecture is geared towards scalability and adaptability, making it suitable for a wide range of devices and use cases.
This technology leverages the strengths of both Silicon-Germanium (SiGe) and BiCMOS processes to produce highly efficient RF solutions. SiGe BiCMOS technology is particularly advantageous for its performance in high-frequency applications, making it ideal for RF and wireless communication technologies. The integration of BiCMOS allows for the combination of bipolar and CMOS transistors on a single chip, enhancing the capacity for analog signal processing alongside digital logic. The SiGe component offers a significant advantage in terms of speed and frequency, ensuring high-performance operation suitable for cutting-edge communication standards. By merging these technologies, the process achieves low-noise amplification and superior linearity, which are crucial for advanced telecommunication systems and data transfer technologies. This makes it a go-to choice for various industries, including aerospace and defense, where precision signal processing is paramount. Additionally, the technology comes with a comprehensive suite of design kits that facilitate seamless integration with existing systems. These kits provide everything from standard libraries to bespoke IP configurations, helping customers tailor their solutions efficiently and effectively. The flexibility and performance it offers make this technology a standout in the realm of RF engineering, addressing the needs of high-speed communication infrastructure.
Certus Semiconductor's Analog I/O offerings bring ultra-low capacitance and robust ESD protection to the forefront. These solutions are crafted to handle extreme voltage conditions while securing signal integrity by minimizing impedance mismatches. Key features include integrated ESD and power clamps, support for broad RF frequencies, and the ability to handle signal swings below ground. Ideal for high-speed RF applications, these Analog I/Os provide superior protection and performance, aligning with the most demanding circuit requirements.
The JESD204B Multi-Channel PHY from Naneng Microelectronics is designed to meet the rigorous demands of high-speed data transmission. Featuring a data rate capability of up to 12.5Gbps, this physical layer multi-channel interface supports a wide array of applications requiring reliable and efficient data transfer. Its versatile architecture ensures seamless integration into complex systems, providing robust performance benefits in the field of data communications. A comprehensive design enhances usability and flexibility, allowing customization for specific industrial needs. This PHY is particularly adept in high-density environments, ensuring precision synchronization across multiple channels, critical for signal integrity in today's intricate electronic ecosystems. Furthermore, the solution's efficient layout allows for ease of interoperability with existing infrastructure, reducing integration costs and time-to-market for end-users. This makes the JESD204B Multi-Channel PHY an attractive choice for enterprises aiming for optimal performance in digital communication systems without compromising efficiency.
The hellaPHY Positioning Solution is designed to revolutionize cellular location technology, especially in the sphere of massive IoT. Utilizing advanced algorithms and 5G networks, it significantly reduces data usage by operating efficiently even with sparse Position Reference Signal (PRS) frameworks. Unlike conventional systems that heavily depend on GPS and external servers, hellaPHY executes real-time location calculations directly on the device. This approach ensures heightened privacy and fortified security of the location data, as it remains encrypted on the user's device and never leaves it. In addition to data privacy, one of the standout features of the hellaPHY solution is its capability for high-precision indoor and outdoor positioning. By leveraging the cutting-edge telecommunication infrastructure like 4G and 5G, hellaPHY delivers near-GNSS precision without the challenges common in densely populated or indoor environments. The solution also extends the battery life of devices by operating efficiently even when in sleep mode, a crucial advantage for IoT devices where battery life is often a constraint. Furthermore, hellaPHY is crafted to be easily integrated into existing systems, courtesy of its streamlined API. This compatibility ensures that current and future devices can adopt the technology without significant overhaul. PHY Wireless has also ensured that the hellaPHY solution is future-proof with frequent over-the-air updates, reinforcing its adaptability and performance over time. This holistic approach not only optimizes costs and power consumption but also reduces spectrum usage by an impressive 300x compared to traditional methods, ensuring scalability for extensive IoT deployments.
EnSilica's eSi-Analog offerings encompass a wide range of silicon-proven analog IP solutions designed to meet the demands of competitive markets where analog capabilities are essential for system performance. These solutions stand out for their high performance and easy integration, which help reduce time-to-market and costs while supporting successful custom ASIC and SoC devices.\n\nThe eSi-Analog IP portfolio includes critical components such as oscillators, SMPSs, LDOs, temperature sensors, PLLs, and ultra-low-power radio elements like sub-GHz BLE, NFC Tag Front-end, and sensor interfaces. These blocks are optimized for low power consumption and high resolution, making them suitable for a wide array of applications.\n\nBy offering flexible configuration options, eSi-Analog IP allows customization according to specific project needs, leveraging EnSilica's expertise in full SoC integration. This facilitates the development of complex designs across multiple process nodes, ensuring customers achieve their design goals efficiently and effectively.
Specialized for advanced radio frequency applications, the RF-SOI and RF-CMOS platform merges high-performance substrates with CMOS design flexibility to enable sophisticated wireless communication solutions. SOI (Silicon-On-Insulator) technology in this platform excels in reducing parasitic capacitance, thereby enhancing speed and power efficiency – critical for RF applications where performance must meet stringent wireless standards. This platform offers extensive frequency range support, from sub-GHz to millimeter wave frequencies, making it a suitable choice for cellular infrastructure, IoT devices, and automotive radar systems. By integrating RF-SOI, the solutions achieve low-loss and high linearity, addressing the demands of next-generation wireless networks. The additional benefit of leveraging RF-CMOS provides improved integration capabilities for multi-function devices on a single chip. Tower Semiconductor's platform is augmented by its comprehensive design enablement resources, including standard cell libraries and PDKs, to facilitate efficient design cycles. The enhanced capabilities of the RF-SOI and RF-CMOS platform thus continue to push forward the frontier of wireless technology, supporting the evolution of high-speed data communications.
The JPEG2000 Video Compression Solution from StreamDSP offers a highly versatile compression framework capable of both lossless and lossy compression within a single codestream. Designed to support high-quality and high-compression-rate applications, this solution integrates seamlessly into a wide range of FPGA platforms. It stands out by enabling compression and decompression tasks to be performed directly within the FPGA, eliminating the need for external processors and reducing system complexity. This capability is particularly beneficial for applications such as digital cinema, surveillance, and archival digital imaging, where maintaining high fidelity while minimizing storage is critical.
TimeServo is a sophisticated System Timer IP Core for FPGAs, providing high-resolution timing essential for line-rate independent packet timestamping. Its architecture allows seamless operation without the need for associated host processor interaction, leveraging a flexible PI-DPLL which utilizes an external 1 PPS signal, ensuring time precision and stability across applications. Besides functioning as a standalone timing solution within an FPGA, TimeServo offers multi-output capabilities with up to 32 independent time domains. Each time output can be individually configured, supporting multiple timing formats, including Binary 48.32 and IEEE standards, which offer great flexibility for timing-sensitive applications. TimeServo uniquely combines software control via an AXI interface with an internal, logically-heavy phase accumulator and Digital Phase Locked Loop mechanisms, achieving impressive jitter performance. Consequently, TimeServo serves as an unparalleled solution for network operators and developers requiring precise timing and synchronization in their systems.
Optimized for simplicity and compact design requirements, the Cap-less LDO is tailored to provide a stable 100mA output without needing an external compensation capacitor. This makes it suitable for applications where board space is limited or minimal design complexity is desired. Leveraging Magna's proven 130nm and 180nm process technology, the Cap-less LDO offers a sound balance between power performance and chip area savings. It accepts a diverse input voltage range from 1.7V to 5.5V, maintaining up to 2% output accuracy. Ideal for portable and battery-operated devices, this LDO's innovative design allows for efficient power management, complementing modern electronic designs focused on miniaturization and energy conservation. Its silicon-proven status assures operators of its consistent and reliable performance.
The TimeServoPTP is an advanced system timer designed for FPGAs that enhances the capabilities laid out by the standard TimeServo, incorporating an IEEE 1588v2 PTP compliant ordinary clock implementation directly into the FPGA hardware. This solution enables both 1-step and 2-step synchronization with external network time masters, facilitating precise timekeeping with minimal drift. This single-component solution operates independently, providing accurate synchronized time across different network applications. It supports a variety of output configurations, adapted for unique user requirements, each capable of outputting a distinct pulse per second at designated times according to user-supplied clocks. Operating with atomic resolution, the TimeServoPTP is equipped with sophisticated logical controls and a Gardner Type-2 Digital Phase Locked Loop, making it ideal for distributed systems where precise timekeeping is essential. Designed with high compatibility, it functions across leading FPGA devices from Intel and Xilinx, ensuring wide feasibile deployment across technological environments.
CoreVCO is a versatile voltage-controlled oscillator designed for high-frequency applications where stability and precision are vital. This VCO is tailored to deliver optimal performance over a range of frequencies, making it suitable for integration in a variety of RF systems including communication networks and signal processing applications. CoreHW's VCO features advanced phase noise management, which is critical in maintaining signal integrity for high-speed data transmissions. Its design facilitates seamless adaptability to different electronic environments, supporting robust performance across sectors like telecommunications and consumer electronics. The compact and energy-efficient design of CoreVCO allows for its use in portable and battery-powered devices. This adaptability ensures that CoreVCO can meet the demands of modern, high-tech environments requiring stable and precise frequency generation.
Aeonic Insight is a leading-edge solution offering on-die telemetry for obtaining vital insights. This technology employs sophisticated sensors to provide design teams with unmatched visibility into power grids and clock states, which are critical for ensuring robust SoC operation. This sensory capability can be integrated effortlessly with third-party silicon analytic platforms, facilitating enhanced data-driven design decisions. The product is pivotal for complex applications spanning datacenter CPUs, AI accelerators, and other advanced SoCs requiring high observability and reliability. Its programmable nature allows customization to match specific architecture and operational conditions, further optimizing performance. Moreover, its process-portable architecture ensures efficient scaling across advanced nodes, preserving area and power efficiency. Aeonic Insight generates comprehensive on-die metrics supporting silicon lifecycle analytics. These metrics enable design teams to optimize power grids, manage clocking systems, and safeguard against hardware security breaches, ensuring long-term system integrity.
Designed for advanced 5G mmWave implementations, the FCM3801-BD Dual-Drive™ Power Amplifier cover frequency ranges of 32 to 44 GHz. Utilizing sophisticated CMOS technology, this amplifier is positioned for excellence with a gain of 19 dB and Psat of 18.3 dBm, attaining a power-added efficiency of 45% at a supply voltage of 1.8V. Its development caters to high-performance applications within the realm of 5G infrastructure. The FCM3801-BD stands out with its bare die format, offering versatility in design incorporation and enabling engineers to customize their system layouts to optimize performance. It's tailored for contexts that demand significant RF power and minimal total thermal output, minimizing cooling requirements. This power amplifier leverages the dual-drive architecture to multiply the input signal with maximum efficiency, appealing to high-demand telecom operations. The combination of high efficiency and elevated power levels make the FCM3801-BD integral for forward-looking communication technologies, providing solutions that meet the intense data demands of modern networks.
Pico Semiconductor's high-performance PLLs and DLLs are designed to minimize noise while delivering robust performance across various frequency ranges. These components support critical operations in electronics by synchronizing the timing of various integrated circuits, ensuring smooth and efficient performance. The PLL offerings include low noise capabilities with operating frequencies reaching up to 5GHz, suitable for a diverse set of applications that require precise clock generation and signal synchronization. Variants include designs that operate at 3.25GHz and a wide range from 135MHz to 945MHz, adapting to the needs of different systems and environmental conditions. These PLLs and DLLs are particularly essential in multichannel and high-speed data applications where timing accuracy and signal integrity are crucial. They facilitate high-speed data transfer and integration with other components, enhancing the overall system efficiency while reducing power consumption.
VeriSyno's Analog Solutions portfolio provides a full spectrum of offerings designed to meet a wide array of application demands. These solutions are based on advanced process nodes ranging from 28nm to 65nm, allowing manufacturers to leverage cutting-edge technology effectively. The analog solutions include essential components such as ADCs, DACs, PLLs, and power management devices like LDOs and power-on-reset circuits. One of the core strengths of VeriSyno's Analog Solutions is their ability to support various applications with great flexibility and efficiency. These solutions cater to needs in signal conversion, timing, and power management, vital for the performance of modern electronic devices. The robustness of these IPs makes them an integral part of systems requiring precise signal processing and control, thus enhancing end-product reliability and functionality. Furthermore, VeriSyno offers a tailored design service to migrate these IPs to processes between 65nm and 180nm, as well as for more advanced technologies. By doing so, they ensure that their clients can maintain the highest quality standards while adapting to ever-changing technological landscapes. This adaptability underscores VeriSyno's commitment to facilitating innovation and addressing the unique challenges faced by their customers.
This general-use Phase Locked Loop (PLL) offers a versatile and reliable solution for frequency synthesis in a range of electronic applications. Supporting any integer division between 1 and 32, or 1 and 64 at lower frequencies, it accommodates a wide variety of input and feedback configurations. The PLL is designed with low noise and suppresses spurious signals, ensuring clean and stable frequency outputs suitable for precision electronics. Implemented on TSMC's 28HPC process node, this PLL can handle frequencies up to a maximum of 4.0 GHz, with a baseline as low as 500 MHz. At this minimum frequency, it operates efficiently with a power consumption of just 4mA. The compact design occupies a space of 150×150 µm, making it ideal for applications where board real estate is limited. With auto-calibration and fast locking features, the PLL enhances system performance by quickly achieving desired frequency parameters, minimizing setup time and improving overall system responsiveness. This makes it particularly suitable for telecommunications, consumer electronics, and other data-driven industries requiring precise timing mechanisms.
The Integer-N PLL-based HF Frequency Synthesizer and Clock Generator delivers high-frequency synthesis and clock generation capabilities. Its integrated loop filter and VCO ensure precise frequency control, making it suitable for high-performance communication systems requiring complex signal generation.
Korusys' SMPTE 2059-2 Synchronization solution offers a comprehensive, high-accuracy hardware synchronization for video equipment leveraging IP networks. It generates precise timing signals crucial for both audio and video systems, ensuring seamless integration in professional environments. The solution is fully compliant with IEEE1588v2 standards, and supports both 2059-1 and 2059-2 frameworks, delivering a holistic timing solution through an integrated software and hardware approach.
The AFX010x Product Family by SCALINX consists of advanced Analog Front Ends (AFEs) ideal for data-acquisition systems, particularly for benchtop and portable applications. This product family is designed to cater to needs for low power consumption, high signal fidelity, broad bandwidth, and impressive sampling rates. Each Integrated Circuit (IC) features four independent channels, each equipped with a programmable input capacitance, a single-ended to differential-output programmable gain amplifier (PGA), an offset DAC, an ADC, and a digital processor. Housed in a standard 12 mm × 12 mm, 196-ball BGA, these products benefit from the proprietary SCCORE™ technology, which facilitates a compact PCB footprint and energy savings of up to 50%. The AFEs offer a maximum sampling rate of 5 GS/s and maintain consistency with applications requiring high resolution data acquisition, such as USB and PC-based oscilloscopes and non-destructive testing systems. By featuring on-chip clock synthesizers and voltage references, they ensure superior performance with power consumption rates as low as 425 mW per channel. Moreover, these AFEs boast a range of programmable gains and bandwidths, adaptable over wide bipolar voltage ranges, making them extremely flexible to suit various signal processing needs. Their pin-to-pin compatibility across different models simplifies upgrades and customization, maximizing flexibility and adaptability in diverse technological contexts.
This innovative system is designed to enhance the user experience of wireless power transfer applications by ensuring precise alignment and compatibility between power transmitters and receivers. It includes mechanisms for detecting the positioning of a device relative to a charging source, optimizing the alignment process to ensure efficient energy transfer. The system's compatibility detection capabilities allow it to recognize and adapt to various device specifications and charging standards, reducing the risk of charging errors and improving overall system reliability. With this system, users can achieve optimal alignment automatically, making the process of wireless charging simpler and more intuitive. The technology is particularly beneficial in scenarios where positioning is critical for energy transfer efficiency, such as in automotive or portable device applications. It addresses common challenges in wireless power systems, such as alignment drift and signal path obstructions, ensuring that power is delivered smoothly and consistently.
The Cobalt GNSS Receiver is a trailblazing IP core designed to integrate effortlessly with IoT System-on-Chip (SoC) platforms, delivering enhanced geolocation capabilities. Its strategic advantage lies in its ultra-low-power operation, which is crucial for IoT applications where power efficiency is paramount. Cobalt leverages shared resources between GNSS and modem functionalities, optimizing both cost and footprint for embedded systems. By utilizing software-defined technologies, it supports a range of satellite constellations, including Galileo, GPS, and Beidou, facilitating versatile and robust global positioning. What sets Cobalt apart is its ability to function in both standalone and cloud-assisted modes, allowing for tailored solutions depending on application needs. Its power-optimized design reduces processing demands while maintaining sensitivity and accuracy. The solution has been developed in collaboration with CEVA DSP and is supported by the European Space Agency, reinforcing its credibility and technical prowess. Cobalt's development ensures it is well-suited for mass-market applications that are sensitive to size and cost constraints, making it an ideal choice for logistics, agriculture, insurance, and various mobile and stationary assets tracking. Additionally, its enhanced resistance to multi-path interference and higher modulation rates foster optimal accuracy, crucial for environments that demand precise geolocation.
The PLL for Satellite Receiver from Bruco Integrated Circuits is a specialized phase-locked loop designed to meet the stringent requirements of satellite communication systems. This PLL excels in maintaining synchronization over long distances, crucial for satellite communications where signal integrity is paramount. It provides precise frequency and phase alignment, essential for demodulating received signals accurately. Built on cutting-edge mixed-signal technology, this PLL offers superior noise performance and frequency stability, making it ideal for use in environments with varying signal conditions. Its design facilitates seamless integration into satellite receivers, enabling them to capture and process signals with high reliability. The robustness of this PLL ensures continued operation in challenging conditions, such as those encountered in space. Additionally, the PLL's low power consumption and compact design make it suitable for the constrained power budgets and space limitations typical of satellite systems. Its ability to quickly lock onto frequencies, even amidst potential interference, ensures satellite receivers remain agile and responsive to signal changes, enhancing overall system performance.
The SMS Fully Integrated Gigabit Ethernet & Fibre Channel Transceiver Core is an advanced solution designed for high-speed data transmission applications. This core incorporates all necessary high-speed serial link blocks, such as high-speed drivers and PLL architectures, which enable precise clock recovery and signal synchronization.\n\nThe transceiver core is compliant with IEEE 802.3z for Gigabit Ethernet and is also compatible with Fibre Channel standards, ensuring robust performance across a variety of network settings. It features an inherently full-duplex operation, providing simultaneous bidirectional data paths through its 10-bit controller interface. This enhances communication efficiency and overall data throughput.\n\nParticularly suited for networks requiring low jitter and high-speed operation, this transceiver includes proprietary technology for superior jitter performance and noise immunity. Its implementation in low-cost, low-power CMOS further provides a cost-effective and energy-efficient solution for high-speed networking requirements.
The 802.11 LDPC solution offers a high-throughput design intended to meet demanding specifications for wireless communication standards. It features the flexibility to adjust LDPC decoding iterations, balancing throughput with error correction performance based on specific requirements. The system is designed to accommodate on-the-fly configuration from one frame to another, ensuring adaptability in various operating conditions. This feature-rich IP aims to maintain optimal bit-error-rate and packet-error-rate performance to ensure data integrity and reliability in dynamic digital communication environments.
Advinno Technologies' PLLs are crucial components used in a variety of electronic systems for frequency synthesis and timing management. Essential for achieving precise timing, these phase-locked loops are integrated into numerous applications, ensuring reliable and stable frequency control. The technology is fundamental for improving signal integrity and optimizing system performance, pertinent in communication and processing devices. These PLLs are designed to meet the diverse needs of modern electronic applications, supporting a broad range of frequencies and offering exceptional phase noise performance. Their architecture facilitates seamless integration into complex systems, enabling efficient resource management and bandwidth optimization. The versatility of Advinno's PLLs makes them an invaluable asset in various sectors, including telecommunications and consumer electronics. With a focus on innovation, Advinno's PLLs are crafted using state-of-the-art processes to ensure maximum efficiency and reliability. These components are adaptable to numerous process nodes and foundries, underscoring their flexibility in design and application. This adaptability is matched with robust support for clients, ensuring optimal outcomes across various deployment scenarios.
The FCM2801-BD Dual-Drive™ Power Amplifier is crafted to excel in 5G mmWave applications, focusing on frequencies from 23 to 36 GHz. It integrates CMOS technology to maximize power delivery while minimizing heat output, offering a gain of 22 dB and Psat of 19.5 dBm with power-added efficiency standing at 53%. The supply voltage for this amplifier is 1.8V, highlighting its compatibility with modern power supply requirements. Designed for 5G infrastructure, the FCM2801-BD supports critical applications necessitating superior RF power and reliability. This amplifier makes use of a bare die package, opening options for flexible design integration in advanced communication systems. Its efficiency and high power output contribute to better coverage with reduced energy utilization, aligning perfectly with modern 5G deployment goals. Incorporating the dual-drive architecture, the FCM2801-BD enhances operational stability and output capabilities, making it highly suitable for deployment in stringent network environments. With the capability to lower energy costs while maintaining high throughput and high-bandwidth performance, this amplifier becomes a valuable asset for telecommunications and related industries.
IPGoal's Clock IP module is expertly crafted to provide precise timing solutions necessary for synchronizing operations in digital systems. Acknowledged for its reliability and accuracy, this IP is essential in applications that demand stringent timing criteria, such as telecommunication networks and embedded systems. Engineered to deliver ultra-low jitter and stable frequency outputs, IPGoal's Clock IP ensures optimal performance in high-speed digital circuits. This makes it an indispensable component in the design and development of systems that rely on accurate timing to function correctly. Its robust design offers compatibility with various process technologies and adaptability to a range of application environments, emphasizing IPGoal's commitment to providing its clients with flexible and dependable solutions tailored to meet diverse operational requirements.
CorePLL is a high-performance phase-locked loop (PLL) designed to provide precise clock generation needed for synchronized processes in complex systems. It is specifically optimized for a broad range of applications, ensuring system reliability and efficiency. CoreHW integrates advanced design strategies to enhance frequency stability and jitter reduction, supporting both wired and wireless communication standards. This PLL is ideal for applications requiring low phase noise and high-frequency outputs. With its compact design, CorePLL fits seamlessly into various system architectures, providing flexibility for different design needs. The integration of CorePLL allows for consistent and accurate timings critical for processes in sectors like telecommunications, automotive, and industrial controls. CoreHW ensures that CorePLL meets rigorous quality standards, which makes it suitable for critical applications that demand precision and reliability. Its compatibility across a multitude of platforms enhances its utility for developers seeking coherent clock solutions.
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