The Universal PHY Technology developed by Yorchip Inc. serves as a cornerstone in offering advanced packaging solutions suitable for both standard interface technologies and bespoke interposer designs. This PHY is characterized by its micro-pitch compatibility, going as low as 20 microns, which substantially enhances its applicability in high-density packaging scenarios. Its low-power design requires less than 0.1 picojoules per bit during operation, making it a preferred choice for energy-conscious applications.
This PHY solution is specifically engineered for efficiency, utilizing a 20X reduced area compared to conventional UCIe SP offerings. It includes Built-In Self-Test (BIST) features for Known Good Dies (KGD), ensuring robust quality assurance. Moreover, the technology covers a broad spectrum of foundry support, adaptable from older 28nm processes to modern advanced FinFet nodes, underscoring its versatility and adaptability to various technological needs.
Yorchip’s Universal PHY Technology is particularly advantageous for those aiming to deploy accessible, high-volume chiplets that are both cost-efficient and capable of rapid market integration. By employing this technology, companies can significantly streamline their product development cycles and reduce overall deployment costs, enabling them to swiftly respond to market demands with chiplets tailored for mass-market use cases.
