All IPs > Wireline Communication > Ethernet
The wireline communication category of Ethernet semiconductor IPs is pivotal in the development of modern high-speed data transfer technologies. Ethernet technology, a mainstay in networking, facilitates the connection of computers to local networks (LANs) and wide-area networks (WANs). This category focuses on semiconductor IPs that implement Ethernet protocols, enabling manufacturers to integrate high-performance networking capabilities into their electronic devices efficiently and cost-effectively.
Ethernet semiconductor IPs are crucial for designing networking chips used in a variety of enterprise, consumer, and industrial applications. These IPs provide the foundational building blocks for implementing Ethernet standards from legacy 10/100 Mbps to the latest Multi-Gigabit Ethernet, including 1G, 10G, 25G, and beyond. Enhanced with features like Energy Efficient Ethernet (EEE) and advanced security mechanisms, these semiconductor IPs ensure optimized performance and reliability essential for today’s data-intensive applications.
The products in this category include a diverse range of Ethernet MAC(medium access control) cores, PHY(physical layer) cores, and network interface controllers, among others. These components work together to manage data packet transmission over Ethernet networks, ensuring seamless communication between connected devices. Designers leverage these Ethernet IPs to create routers, switches, servers, and Internet of Things (IoT) devices that require sophisticated data handling capabilities.
By integrating Ethernet semiconductor IPs, developers and OEMs can achieve faster time-to-market while reducing design risk and cost. These IPs are pre-verified, ensuring compliance with the current Ethernet standards, which accelerates the development cycle for networking equipment. Consequently, Ethernet semiconductor IPs are indispensable for any entity aiming to innovate within the competitive landscape of wireline communication technologies.
The Metis AIPU PCIe AI Accelerator Card by Axelera AI is designed for developers seeking top-tier performance in vision applications. Powered by a single Metis AIPU, this PCIe card delivers up to 214 TOPS, handling demanding AI tasks with ease. It is well-suited for high-performance AI inference, featuring two configurations: 4GB and 16GB memory options. The card benefits from the Voyager SDK, which enhances the developer experience by simplifying the deployment of applications and extending the card's capabilities. This accelerator PCIe card is engineered to run multiple AI models and support numerous parallel neural networks, enabling significant processing power for advanced AI applications. The Metis PCIe card performs at an industry-leading level, achieving up to 3,200 frames per second for ResNet-50 tasks and offering exceptional scalability. This makes it an excellent choice for applications demanding high throughput and low latency, particularly in computer vision fields.
Panmnesia's CXL 3.1 Switch is an integral component designed to facilitate high-speed, low-latency data transfers across multiple connected devices. It is architected to manage resource allocation seamlessly in AI and high-performance computing environments, supporting broad bandwidth, robust data throughput, and efficient power consumption, creating a cohesive foundation for scalable AI infrastructures. Its integration with advanced protocols ensures high system compatibility.
RaiderChip's GenAI v1 is a pioneering hardware-based generative AI accelerator, designed to perform local inference at the Edge. This technology integrates optimally with on-premises servers and embedded devices, offering substantial benefits in privacy, performance, and energy efficiency over traditional hybrid AI solutions. The design of the GenAI v1 NPU streamlines the process of executing large language models by embedding them directly onto the hardware, eliminating the need for external components like CPUs or internet connections. With its ability to support complex models such as the Llama 3.2 with 4-bit quantization on LPDDR4 memory, the GenAI v1 achieves unprecedented efficiency in AI token processing, coupled with energy savings and reduced latency. What sets GenAI v1 apart is its scalability and cost-effectiveness, significantly outperforming competitive solutions such as Intel Gaudi 2, Nvidia's cloud GPUs, and Google's cloud TPUs in terms of memory efficiency. This solution maximizes the number of tokens generated per unit of memory bandwidth, thus addressing one of the primary limitations in generative AI workflow. Furthermore, the adept memory usage of GenAI v1 reduces the dependency on costly memory types like HBM, opening the door to more affordable alternatives without diminishing processing capabilities. With a target-agnostic approach, RaiderChip ensures the GenAI v1 can be adapted to various FPGAs and ASICs, offering configuration flexibility that allows users to balance performance with hardware costs. Its compatibility with a wide range of transformers-based models, including proprietary modifications, ensures GenAI v1's robust placement across sectors requiring high-speed processing, like finance, medical diagnostics, and autonomous systems. RaiderChip's innovation with GenAI v1 focuses on supporting both vanilla and quantized AI models, ensuring high computation speeds necessary for real-time applications without compromising accuracy. This capability underpins their strategic vision of enabling versatile and sustainable AI solutions across industries. By prioritizing integration ease and operational independence, RaiderChip provides a tangible edge in applying generative AI effectively and widely.
Intilop offers a sophisticated 10G TCP Offload Engine that integrates MAC, PCIe, and Host IF to deliver ultra-low latency performance. This engine is designed to significantly reduce CPU workload by offloading TCP/IP processing onto the hardware, ensuring faster data transmission with minimal delay. It efficiently supports extensive data flow and high-speed connectivity through its advanced architecture, making it an optimal solution for enterprises seeking high-performance network infrastructure. The engine is specifically engineered to handle up to 10 Gbps speed, maintaining consistent levels of performance even under heavy data loads. Its robust design supports full state offload, checksum offload, and large send offload, making it adept at managing high volumes of data without compromising speed or reliability. By including features like dual 10G SFP+ ports, it offers users flexibility and increased bandwidth, catering to the needs of bandwidth-intensive applications. Additional highlights include zero jitter and the ability to manage multiple sessions simultaneously, thereby enhancing data throughput while minimizing network latency. The integration of features such as kernel bypass and no-CPU-needed architecture underscores its design geared towards efficiency and resource optimization. Ideal for data centers, cloud computing environments, and high-speed network servers, this offload engine is structured to provide significant improvements in cost, space, and overall network infrastructure efficiency.
The ARINC 818 Product Suite is a comprehensive solution set designed to support the entire lifecycle of ARINC 818 enabled equipment. This suite offers tools and resources essential for developing, qualifying, testing, and simulating ARINC 818 products. It is recognized for its robust design and ability to address the complexities of high-performance avionics systems. Within the product suite, users can access the ARINC 818 Development Suite and Flyable Products, providing a framework for both development and in-field application. The suite is indispensable for organizations aiming to integrate ARINC 818 into their systems, ensuring precise data handling and compatibility. Great River Technology's experience in crafting over 100 mission-critical systems is embedded into the suite, offering unmatched expertise and dependability. By leveraging this suite, companies can ensure the reliable operation and seamless integration of ARINC 818 technologies.
Time-Triggered Ethernet (TTEthernet) is an advanced form of Ethernet designed for applications that require high levels of determinism and redundancy, particularly evident in aerospace and space projects. TTEthernet offers an integrated solution for complex systems that mandates reliable time-sensitive operations, such as those required in human spaceflight where triple redundancy is crucial for mission-critical environments. This technology supports dual fault-tolerance by using triple-redundant networks, ensuring that the system continues to function if failures occur. It's exceptionally suited for systems with rigorous safety-critical requirements and has been employed in ventures like NASA's Orion spacecraft thanks to its robust standard compliance and support for fault-tolerant synchronization protocols. Adhering to the ECSS engineering standards, TTEthernet facilitates seamless integration and enables bandwidth efficiencies that are significant for both onboard and ground-based operations. TTTech's TTEthernet solutions have been further complemented by their proprietary scheduling tools and chip IP offerings, which continue to set industry benchmarks in network precision and dependability.
KPIT Technologies' Integrated Diagnostics & Aftersales Transformation (iDART) platform addresses the evolving complexities of maintaining software-defined vehicles. Offering a comprehensive suite of tools and services, iDART facilitates efficient diagnostic development, validation, and aftersales service transformation. As vehicles become more software-centric, iDART assists in managing diagnostics across varied hardware and software configurations, ensuring seamless integration and service continuity. The platform excels in automated validation processes, ensuring data accuracy and compliance from legacy to modern systems. KPIT's guided diagnostics and remote troubleshooting solutions enhance first-time-right repair ratios by providing technicians with precise insights, reducing vehicle downtime and improving service throughput. This diagnostic content management streamlines operations and reduces warranty costs, vital for OEMs balancing innovation with sustainability. iDART's focus on service lifecycle management ensures that OEMs can offer enhanced customer engagement beyond the first vehicle owner, fostering lasting customer relationships. Through advanced diagnostic frameworks, KPIT sets a new standard for vehicle service operations, addressing the growing complexities within the automotive industry. By integrating thoroughly tested frameworks and leveraging machine learning-driven diagnostics, KPIT aligns its services with future vehicle ecosystem demands.
The ntLDPC_G98042 (17664,14592) IP Core is defined in IEEE 802.3ca-2020, it is used by ITU-T G.9804.2-09.2021 standard document and it is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes. These LDPC codes are based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that they offer high throughput at low implementation complexity. The ntLDPCΕ_G98042 encoder IP implements a 256-bit parallel systematic LDPC encoder. The Generator LDPC Matrix is calculated off-line, compressed and stored in ROM. It is partitioned to 12 layers and each layer, when multiplied by the 14592 payload block, produces 256 parity bits. The multiplier architecture may be parameterized before synthesis to generate multiple multiplier instances [1:4,6], in order to effectively process multiple layers in parallel and improve the IP throughput rate. Shortened blocks are supported with granularity of 128-bit boundaries and 384 or 512 parity bits puncturing is also optionally supported. The ntLDPCD_G98042 decoder IP Core may optionally implement one of two approximations of the log-domain LDPC iterative decoding algorithm (Belief propagation) known as either Layered Offset Min-Sum Algorithm (OMS) or Layered Lambda-min Algorithm (LMIN). Selecting between the two algorithms presents a decoding performance vs. system resources utilization trade-off. The OMS algorithm is chosen for this implementation, given the high code rate of the Parity Check Matrix (PCM). The ntLDPCD_G98042 decoder IP implements a 256-bit parallel systematic LDPC layered decoder. Each layer corresponds to Z=256 expanded rows of the original LDPC matrix. Each layer element corresponds to the active ZxZ shifted identity sub-matrices within the layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit, in order to update the layers’ LLR estimates and extrinsic information iteratively until the required number of decoding iterations has been run. The decoder IP also features a powerful optional syndrome check early termination (ET) criterion, to maintain identical error correction performance, while significantly increasing its throughput rate and/or reducing hardware cost. Additionally it reports how many decoding iterations have been performed when ET is activated, for system performance observation and calibration purposes. A top level architecture deployment wrapper allows to expand the parallelism degree of the decoder before synthesis, effec-tively implementing a trade-off between utilized area and throughput rate. Finally a simple, yet robust, flow control handshaking mechanism is included in both IPs, which is used to communicate the IPs availability to adjacent system components at 128-bit parallel bus interface. This logic is easily portable into any communication protocol, like AXI4 stream IF.
The CT25205 is a robust digital IP core designed for IEEE 802.3cg 10BASE-T1S Ethernet Physical Layer. It includes PMA, PCS, and PLCA Reconciliation Sublayer blocks, enhancing compatibility with standard IEEE MACs via the MII. Featuring a fully synthesizable Verilog design, it is deployable on standard cells and FPGAs. With integrated PLCA RS, this IP provides advanced features without necessitating additional extensions, making it a vital component for Zonal Gateways SoCs.
The HOTLink II Product Suite is engineered to deliver advanced capabilities in high-speed data and video link technologies. It serves as an essential toolset for developing and implementing HOTLink II protocols effectively, catering to the specific needs of modern avionics systems requiring reliable and high-throughput data transfer. This suite includes various components that enable the seamless transmission and conversion of data, supporting both development and operational phases. Its design incorporates technologies that enhance data integrity and efficiency, making it integral to systems where performance and reliability are critical. Great River Technology ensures that each component of the HOTLink II suite is crafted with precision, providing comprehensive support and simplifying integration processes. The suite redounds to the extensive expertise of Great River Technology in the sector, reinforcing their standing as providers of pioneering solutions.
The ePHY-5616 delivers data rates from 1 to 56Gbps across technology nodes of 16nm and 12nm. Designed for a diverse range of applications, this product offers superior BER and low latency, making it ideal for enterprise equipment like routers, switches, and network interface cards. The ePHY-5616 employs a highly configurable DSP-based receiver architecture designed to manage various insertion loss scenarios, from 10dB up to over 35dB. This ensures robust and reliable data transfer across multiple setups.
Designed for performance computing, the pPLL03F-GF22FDX is an advanced all-digital fractional-N PLL developed for low-jitter and compact applications. It operates efficiently at clock frequencies reaching up to 4GHz, specifically crafted to meet the demands of performance computing blocks and ADCs/DACs that have moderate SNR prerequisites. A crucial aspect of its design is its compatibility with multi-PLL systems, enabling implementations in complex SoCs with numerous clock domains. Tailored for GlobalFoundries 22FDX, this IP ensures robust and reliable performance across varied PVT conditions.
The 10G TCP Offload Engine (TOE) from Intilop is crafted to deliver exceptional networking performance with minimal CPU involvement. This engine is pivotal for organizations seeking to optimize their network setups by offloading TCP/IP processing to dedicated hardware, allowing the main CPU to focus on critical applications instead. By doing so, it ensures that data packets are transmitted swiftly across the network, supporting significant bandwidth requirements. Its architecture is tailored to sustain a 10 Gbps data transfer rate, providing a vital boost in efficiency for bandwidth-heavy applications. The TOE is equipped with comprehensive state offload capabilities, large send offload, and checksum offload functions, contributing to its superior data processing and transmission prowess. This not only enhances speed but also reduces latency, allowing for smoother, more stable network performance. Designed for applications demanding high data reliability and speed, this TCP Offload Engine is invaluable for data centers, cloud-based services, and enterprise-level networks. Its implementation facilitates enhanced scalability and responsiveness, crucial for maintaining the competitiveness of modern digital infrastructures. With an efficient bypass of OS kernel functions, it provides a predictable network performance, minimizing the typical overhead associated with TCP processing.
CT25203 is an Analog Front-End IP core compliant with IEEE 802.3cg standard for 10BASE-T1S applications. It is part of Canova Tech's strategic offerings in analog domain, enhancing high-performance communication. The IP supports integral interoperability with digital PHYs, such as the CT25205, and is designed to operate with a high-voltage process technology, ensuring exceptional electromagnetic compatibility (EMC) performance. Its features facilitate reliable communication for industrial and automotive applications, proven in diverse environments.
Ethernet MAC 10M/100M/1G/2.5G IP is a solution that enables the host to communicate data using the IEEE 802.3 standard for 10M, 100M, 1G, 2.5G speeds and is suited for use in networking equipment such as switches and routers. The Client-side interface for the IP is AXI-S and the Ethernet MAC IP comes with GMII, RGMII or MII interfaces on the PHY side. The Ethernet MAC 10M/100M/1G/2.5G IP features a compact and low latency solution, it is highly configurable and can optionally include IEEE 1588 Timestamping Unit (TSU). The Silicon agnostic Ethernet MAC IP, suitable for ASICs and FPGAs, is prepared for easy integration with Ethernet PCS 10M/ 100M/1G/2.5G IP from Comcores.
The GenAI v1-Q from RaiderChip brings forth a specialized focus on quantized AI operations, reducing memory requirements significantly while maintaining impressive precision and speed. This innovative accelerator is engineered to execute large language models in real-time, utilizing advanced quantization techniques such as Q4_K and Q5_K, thereby enhancing AI inference efficiency especially in memory-constrained environments. By offering a 276% boost in processing speed alongside a 75% reduction in memory footprint, GenAI v1-Q empowers developers to integrate advanced AI capabilities into smaller, less powerful devices without sacrificing operational quality. This makes it particularly advantageous for applications demanding swift response times and low latency, including real-time translation, autonomous navigation, and responsive customer interactions. The GenAI v1-Q diverges from conventional AI solutions by functioning independently, free from external network or cloud auxiliaries. Its design harmonizes superior computational performance with scalability, allowing seamless adaptation across variegated hardware platforms including FPGAs and ASIC implementations. This flexibility is crucial for tailoring performance parameters like model scale, inference velocity, and power consumption to meet exacting user specifications effectively. RaiderChip's GenAI v1-Q addresses crucial AI industry needs with its ability to manage multiple transformer-based models and confidential data securely on-premises. This opens doors for its application in sensitive areas such as defense, healthcare, and financial services, where confidentiality and rapid processing are paramount. With GenAI v1-Q, RaiderChip underscores its commitment to advancing AI solutions that are both environmentally sustainable and economically viable.
The Ultra-Low Latency 10G Ethernet MAC IP core by Chevin Technology exemplifies cutting-edge design for high-speed network communications, catered specifically to deliver the lowest possible latency. It is meticulously constructed to meet the demands of applications that require minimal delay in data exchange, thus maximising data throughput. The IP core is finely tuned for deployment in FPGAs, optimizing the balance between performance and resource utilization. Benefiting from a streamlined logic architecture, this IP core enhances the efficiency of hardware accelerations and simplifies the incorporation of Ethernet connectivity into customer systems. Its fundamental construction is rooted in Chevin’s extensive experience with Ethernet technologies and it has been thoroughly tested to ensure reliable operation across a diverse range of settings. This Ethernet MAC utilises all-logic architecture which removes need for additional CPU or software intervention, providing immense power savings and reduced system complexity. Features like programmable interframe gap control and flexible licensing allow for the tailored installation in both traditional and contemporary systems. The combination of robust performance capabilities alongside expert support creates a compelling choice for integrators focused on high-speed, low-latency Ethernet solutions.
KPIT's digital connected solutions revolutionize the automotive cockpit and in-cabin experience, enhancing personalization, productivity, and safety for drivers. These solutions are driven by technologies such as high-resolution displays, augmented reality head-up displays, and AI-powered virtual assistants, all integrated to create a seamless and dynamic digital environment within the vehicle. The cloud and over-the-air (OTA) updates further enrich the consumer experience by providing regular enhancements and new features. The innovative market leadership KPIT demonstrates is evident in their rapid development and integration capabilities, which meet the growing demands of OEMs for swift market entry. KPIT addresses critical challenges in cost constraints and system integration, ensuring that advanced features coexist with the necessary affordability and cohesion between hardware and software components. Through these digital solutions, KPIT stands as a preferred partner for automakers pursuing cutting-edge cockpit and connectivity advancements. By continuously innovating and expanding their offering, KPIT enhances the value proposition of modern vehicles, ensuring that automakers remain competitive in the fast-evolving automotive landscape.
The Flexibilis Ethernet Switch (FES) is an advanced Layer 2 switch IP core designed to enable gigabit forwarding capabilities across multiple Ethernet ports. Compatible with IEEE 802.1D MAC bridges, FES features triple-speed Ethernet interfaces for efficient handling and prioritization of network traffic. Its integration with IEEE 1588 Precision Time Protocol ensures accurate timekeeping across the network, which is crucial for applications requiring precise timing. The FES supports various configurations and interfaces, making it adaptable to specific application requirements while maintaining robust network performance.
The Network Protocol Accelerator Platform (NPAP) is engineered to accelerate network protocol processing and offload tasks at speeds reaching up to 100 Gbps when implemented on FPGAs, and beyond in ASICs. This platform offers patented and patent-pending technologies that provide significant performance boosts, aiding in efficient network management. With its support for multiple protocols like TCP, UDP, and IP, it meets the demands of modern networking environments effectively, ensuring low latency and high throughput solutions for critical infrastructure. NPAP facilitates the construction of function accelerator cards (FACs) that support 10/25/50/100G speeds, effectively handling intense data workloads. The stunning capabilities of NPAP make it an indispensable tool for businesses needing to process vast amounts of data with precision and speed, thereby greatly enhancing network operations. Moreover, the NPAP emphasizes flexibility by allowing integration with a variety of network setups. Its capability to streamline data transfer with minimal delay supports modern computational demands, paving the way for optimized digital communication in diverse industries.
Credo's SerDes PHY stands at the forefront of customizable analog and digital signal processing technology, specifically engineered for integration into sophisticated ASIC designs. This high-performance technology seamlessly addresses the demands of today's advanced computing and data environments, offering a robust solution with optimal power consumption and cost-efficiency. The architecture of Credo's SerDes PHY is particularly notable for its unique design, which optimally balances the performance, power cost, and risks associated with the semiconductor manufacturing process. By employing a patented mixed signal DSP framework, this IP delivers unparalleled signal integrity across a variety of environments, including data centers, AI applications, and high-performance computing scenarios. Reliably designed to operate across a wide range of process nodes, Credo's technology is adaptable to various company-specific needs, supporting integration into multichip module systems on chip (MCM SoC) as well as 2.5D silicon interposer architectures. This adaptability and high precision signal management ensure Credo's customers can meet the evolving requirements of their industries with confidence.
The High PHY Accelerators from AccelerComm are a collection of signal processing cores designed for ASIC, FPGA, and SoC applications, primarily focused on boosting 5G NR communications. These accelerators incorporate proprietary algorithms that allow users to attain the highest levels of throughput, efficiency, and power savings. These accelerator cores are engineered to facilitate seamless integration into existing systems, significantly improving spectral efficiency through advanced processing techniques. The use of patented algorithms allows for overcoming system noise and interference, delivering superior performance for complex wireless communication networks. Moreover, these accelerators excel at minimizing latency and resource consumption, providing an optimal balance between high performance and low power requirements. Recognized for their flexibility, these accelerators support scalable architectures, customizable for various deployment scenarios. This versatility ensures operators and developers can adapt solutions to fit small, cost-sensitive applications or larger enterprise demands, enhancing the ability to handle high data volumes with integrity and reliability.
The ADQ35 is a high-throughput digitizer designed for critical signal processing applications. Known for its 12-bit accuracy and high sampling rates, it stands out in delivering up to 10 GSPS, supporting single or dual-channel data streams. This ensures data integrity and speed for applications that demand precision and reliability, such as telecommunications and high-speed imaging. Equipped with enhanced processing capabilities, the ADQ35 ensures superior handling of complex datasets, making it suitable for scientific research and advanced electronics projects. Its robust design caters to the needs of modern digital systems, allowing for a seamless integration into existing infrastructure to facilitate expansive projects. This device also features streaming capabilities that provide a continuous flow of high-quality data, excelling in applications that require constant monitoring and data analysis. The ADQ35 digitizer is an excellent choice for industries that rely on swift and accurate data interpretation, enhancing overall system performance and technical output.
This Ethernet RTPS Core provides a complete IP solution for the Ethernet RTPS protocol, essential in mission-critical networks. It supports real-time communication and data synchronization across devices, critical for systems requiring precise timing and reliable data exchange.
The Time-Triggered Protocol (TTP) is a technology that offers deterministic communication for distributed real-time systems. This protocol is vital in applications where timing precision is crucial, such as in the aerospace industry, ensuring tasks are executed at precisely scheduled intervals. TTP is known for its reliability, configuring data communication parameters by defining send/receive slots within a network, and is adaptable for use in high-integrity systems like those found in avionics and deep space missions. This protocol underpins systems where fault-tolerance and coordination are necessary across diverse nodes within the network, offering a redundant communication pathway that safeguards against data loss. With this protocol, TTTech ensures that methodologies for verification and scheduling are incorporated into the systems, facilitating smoother qualification and certification in civil aviation projects. TTP is also SAE AS6003 compliant, meeting the stringent requirements needed for critical applications and ensuring compatibility with various forms of systems, including both integrated circuits and more complex system-on-chip arrangements. Widely acknowledged in industries demanding high reliability, TTP continues to support industry needs for robust protocol solutions.
Systems4Silicon's Digital PreDistortion (DPD) Solution is designed to significantly enhance the power efficiency of RF power amplifiers. This subsystem is complete and adaptive, providing a scalable solution that transcends the limitations typical of vendor-specific dependencies. On account of its universal compatibility, this IP core can be compiled for any ASIC or FPGA/SoC platform, serving as an all-encompassing solution suited for a diverse array of wireless communication systems such as 5G and multi-carrier setups. One of the standout features of the DPD technology is its capability to improve transmission bandwidth efficiently, offering scalability for bandwidths of up to 1 GHz or more. This positions the DPD solution as a forward-thinking technology, catering to modern demands for higher data rates and broader communication ranges. The adaptive nature of the solution ensures that it can modulate performance parameters in real-time, responding dynamically to varying operational conditions and system requirements, thereby maximizing amplifier efficiency across different setups. In operational terms, the DPD Solution is field-proven, reflecting its reliability and performance in real-world applications. It represents a versatile technology that integrates seamlessly with existing systems, delivering a robust enhancement to power amplifier efficiency while maintaining high compatibility with emerging communication standards. The flexibility of this technology makes it a vital asset in the infrastructure of contemporary wireless networks, ensuring smooth and efficient signal transmission.
The High-Speed SerDes is an advanced solution engineered to deliver high-performance data transmission in chiplet architectures. Leveraging our innovative digital-centric design, this SerDes offers unmatched low power consumption, making it ideal for high-speed ASIC applications. It ensures optimal performance and efficiency, supporting systems with varying speeds and complexities. This SerDes is adept at handling the demands of modern data transfer, ensuring reliable and fast communication between chiplets in an integrated system. Its ability to function at high speeds while maintaining energy efficiency is what sets it apart in the domain of interconnect technologies. Designed to be scalable, it facilitates the development of systems that are not just current with today’s technological demands but are also prepared for the innovations of tomorrow. This makes it a critical component in the expansion of semiconductor capabilities, supporting diverse applications across multiple sectors.
The DisplayPort 1.4 IP core by Parretto is designed for efficient video signal transmission, providing comprehensive solutions for both source (DPTX) and sink (DPRX) configurations. Supporting link rates from 1.62 to 8.1 Gbps, this core offers flexibility for different applications, including embedded DisplayPort (eDP) rates. It can handle 1, 2, and 4 DP lanes, and supports diverse video interfaces such as native video and AXI stream. This IP core accommodates Single Stream Transport (SST) and Multi Stream Transport (MST) modes, adapting to different output requirements. Its dual and quad pixels per clock with rich color managing capabilities—including RGB and various YCbCr formats—enable it to meet high-quality video standards. A secondary data packet interface allows for straightforward audio and metadata transport. Equipped with a Video Toolbox (VTB), it simplifies video processing tasks, including clock recovery and pattern generation. The core is compatible with several FPGA devices like AMD's UltraScale+ and Artix-7, as well as Intel's Cyclone 10 GX and Arria 10 GX.
Designed for the FC-AE-ASM protocol, this ASM Core offers hardware-based solutions including label lookup, DMA controllers, and message chains, compatible with F-35 applications. Its robust architecture ensures secure and reliable communication, reinforcing its critical role in secure military data transmission tasks.
The FCM1401 is a 14GHz CMOS Power Amplifier tailored for Ku-band applications, operating over a frequency range of 12.4 to 16 GHz. This amplifier exhibits a gain of 22 dB and a saturated output power (Psat) of 19.24 dBm, ensuring optimal performance with a power-added efficiency (PAE) of 47%. The architecture enables reduction in battery consumption and heat output, making it ideal for satellite and telecom applications. Its small silicon footprint facilitates integration in space-constrained environments.
The Digital Radio (GDR) from GIRD Systems is an advanced software-defined radio (SDR) platform that offers extensive flexibility and adaptability. It is characterized by its multi-channel capabilities and high-speed signal processing resources, allowing it to meet a diverse range of system requirements. Built on a core single board module, this radio can be configured for both embedded and standalone operations, supporting a wide frequency range. The GDR can operate with either one or two independent transceivers, with options for full or half duplex configurations. It supports single channel setups as well as multiple-input multiple-output (MIMO) configurations, providing significant adaptability in communication scenarios. This flexibility makes it an ideal choice for systems that require rapid reconfiguration or scalability. Known for its robust construction, the GDR is designed to address challenging signal processing needs in congested environments, making it suitable for a variety of applications. Whether used in defense, communications, or electronic warfare, the GDR's ability to seamlessly switch configurations ensures it meets the evolving demands of modern communications technology.
Intilop's UDP Offload Engine (UOE) is a cutting-edge solution aimed at optimizing UDP traffic management while alleviating CPU load. Specially designed for high-performance environments, this engine offloads the handling of UDP communications, which are critical for applications that require low-latency data transmission such as voice, video, and real-time streaming services. The UOE is engineered to support a broad range of UDP sessions simultaneously, ensuring smooth data flow across networks with minimal interruptions. By managing functions such as checksum validation and data packet reordering on the hardware level, it allows the host CPU to concentrate on primary processing tasks, thereby enhancing overall system performance. Its design guarantees robust data throughput, even for extensive and demanding applications. With its capabilities, the UOE is especially advantageous for networking scenarios where speed and reliability are paramount. It supports ultra-low latency communication, making it ideal for real-time applications requiring swift data exchange and minimal response lag. This application-centric design highlights Intilop's commitment to delivering comprehensive solutions for advanced network control and optimization.
The 10G Ethernet MAC and PCS IP core from Chevin Technology is crafted to ensure seamless integration of high-speed Ethernet connectivity within FPGA platforms. This solution underscores Chevin Technology’s commitment to providing adaptable and resource-efficient Ethernet IP cores. Supporting a range of interfaces, it optimizes the synthesis of duplex 10Gbit/s Ethernet, making it ideal for implementation in systems that require high data throughput. The integration process is made effortless through detailed user guides and expert support, making it possible to incorporate this IP into varied FPGA platforms effectively. Its low-latency architecture supports high-performance communications while occupying minimal FPGA resources. Designed in accordance with IEEE 802.3 standards, this MAC/PCS core facilitates transmitting and receiving data at unrivalled speeds. The compact design ensures that broader functionalities and additional IP can comfortably reside on the FPGA, thereby enriching the application possibilities without inflating costs. Streamlining data transfer processes, the core offers flexible licensing to support various project needs, providing an unparalleled level of adaptability. With strategically laid out features that include CRC32 error detection and correction capabilities, the 10G Ethernet MAC and PCS IP core supports rapid data transfers while maintaining reliability. It incorporates advanced fault management and statistics blocks for detailed operational insights and robust performance monitoring. The core is compatible with leading industry boards and comes equipped with all necessary integrations to ensure optimal functionality across various platforms.
CLOP Technologies' 60GHz Wireless Solution offers businesses an impressive alternative to traditional networking systems. Leveraging the IEEE 802.11ad WiFi standard and Wireless Gigabit Alliance MAC/PHY specifications, this solution achieves a peak data rate of up to 4.6Gbps. This makes it particularly suited for applications that require significant bandwidth, such as real-time, uncompressed HD video streaming and high-speed data transfers — operations that are notably quicker compared to current WiFi systems. The solution is engineered to support 802.11ad IP networking, providing a platform for IP-based applications like peer-to-peer data transfer and serving as a router or access point. Its architecture includes a USB 3.0 host interface and mechanisms for RF impairment compensation, ensuring both ease of access for host compatibility and robust performance even under high data rate operations. Operating on a frequency band ranging from 57GHz to 66GHz, the wireless solution utilizes modulation modes such as BPSK, QPSK, and 16QAM. It incorporates forward error correction (FEC) with LDPC codes, providing various coding rates for enhanced data integrity. Furthermore, the system boasts AES-128 hardware security, with quality of service maintained through IEEE 802.11e standards.
This core offers a comprehensive hardware solution for FC-AE-RDMA or FC-AV protocols, incorporating buffer mapping, DMA controllers, and message chain engines. Its compatibility with F-18/F-15 interfaces makes it pivotal for military communication operations, ensuring robust data handling and streamlined communication channels.
The SMPTE ST 2110 suite of standards enables professional media to be transported over IP networks, allowing the convergence of IT and broadcast infrastructures. The core is modular and flexible, supporting various sub-standards like video and audio transmission, traffic shaping, and ancillary data. Designed for seamless operation over networks, it caters to the needs of both broadcasters and professional AV users by allowing the transmission of uncompressed video and audio, synchronizing multimedia streams precisely. The ST 2110 IP core simplifies the daunting task of transitioning to IP-based workflows by offering system timing features, compressed video capabilities, and support for ancillary data management. By implementing these cores, businesses can ensure precise media transport aligned with international standards, facilitating interoperability and reducing deployment complexities. This technology is vital for companies looking to enhance their production capabilities without being restricted by outdated infrastructure. Nextera Video's ST 2110 cores are crucial for media professionals aiming to capture the benefits of IP, such as cost-effectiveness and scalability. These cores facilitate the creation of robust systems capable of handling modern media demands and are tested through JT-NM programs, ensuring interoperability with other IP-based media solutions.
Dyumnin's RISCV SoC is a versatile platform centered around a 64-bit quad-core server-class RISCV CPU, offering extensive subsystems, including AI/ML, automotive, multimedia, memory, cryptographic, and communication systems. This test chip can be reviewed in an FPGA format, ensuring adaptability and extensive testing possibilities. The AI/ML subsystem is particularly noteworthy due to its custom CPU configuration paired with a tensor flow unit, accelerating AI operations significantly. This adaptability lends itself to innovations in artificial intelligence, setting it apart in the competitive landscape of processors. Additionally, the automotive subsystem caters robustly to the needs of the automotive sector with CAN, CAN-FD, and SafeSPI IPs, all designed to enhance systems connectivity within vehicles. Moreover, the multimedia subsystem boasts a complete range of IPs to support HDMI, Display Port, MIPI, and more, facilitating rich audio and visual experiences across devices.
eSi-Comms offers highly parametric communication solutions tailored for complex projects. It encompasses a range of communication protocols and standards, ensuring seamless integration and high performance. This solutions package is ideal for optimizations across telecommunications systems, supporting a variety of communication needs.
The RWM6050 Baseband Modem is engineered to facilitate high-data rate applications across wireless communication networks. Designed to serve as a versatile component within various telecommunication systems, it processes signals with precision to enhance data throughput across diverse transmission environments. At its core, the RWM6050 is optimized for operation in complex wireless networks where bandwidth efficiency and robust signal integrity are paramount. It seamlessly integrates into wireless communication frameworks, providing the needed flexibility and scalability to support next-generation network deployments. Through its advanced capabilities, this baseband modem establishes itself as a pivotal element in ensuring reliable, high-speed data transmission. Whether supporting conventional networks or cutting-edge mmWave technology applications, the RWM6050 maintains stellar performance, thereby enhancing the efficiency of communication infrastructures in both commercial and defence sectors.
APIX3 technology represents the pinnacle of data communication solutions for advanced automotive infotainment and cockpit systems. It supports ultra-high definition video resolutions, facilitated by its capacity for multi-channel high-speed data transmission. The technology enables a scalable bandwidth that adapts from entry-level to luxurious, high-end automotive systems, ensuring a broad range of application compatibilities. APIX3 modules are engineered to transmit data at rates of up to 6 Gbps over a shielded twisted pair cable and up to 12 Gbps over a quad twisted pair. This makes them invaluable in systems requiring high levels of data integrity and precision, such as those found in modern, connected vehicle architectures. In addition to supporting complex video channels, APIX3 is compatible with 100 Mbps Ethernet and integrates advanced diagnostic capabilities for cable monitoring, which allows for predictive maintenance by detecting cable degradation. Its backwards compatibility with APIX2 ensures seamless integration and upgradability in existing infrastructures, reinforcing its status as a future-proof solution.
The High Speed Data Bus (HSDB) Core offers a comprehensive implementation of the physical layer and media access control layer suitable for HSDB. It ensures seamless integration with an F-22 compatible interface, offering a high-performance solution for ensuring efficient communication. The IP core is engineered to support a frame interface for easy integration, a fundamental requirement in demanding aerospace environments.
EZiD211 is a state-of-the-art modulator and demodulator designed to enhance satellite communication systems, supporting DVB-S2X. This product focuses on managing low Earth, medium Earth, and geostationary satellite communications with advanced features such as beam hopping, VLSNR, and superframe support, making it an ideal choice for future satellite technologies. The aim of EZiD211 is to improve satellite communication efficiency and accuracy, providing a robust solution for data, IoT, and modem infrastructure. The design has been executed under European programs to showcase new functionalities and ensure the product meets the highest standards for commercial use. EASii IC leverages the latest developments in DVB standards to ensure that EZiD211 can handle various environments, offering enhanced performance through its wide range of features. The product is available in a QFN 13×13 package, with options for evaluation boards, supporting seamless integration into existing systems.
Engineered for high-performance mobile graphics, the IMG DXT GPU provides advanced capabilities such as real-time ray tracing and scalable performance. This GPU's architecture is designed to cater to premium mobile devices, ensuring both graphical fidelity and power efficiency. With its scalable Ray Acceleration Cluster, it offers multiple configurations to tailor performance and cost, making it suitable for flagship mobile platforms seeking premium visual output while maintaining energy efficiency.
LightningBlu is designed specifically to transform the connectivity landscape of high-speed rail by providing uninterrupted, on-the-move multi-gigabit connectivity. By bridging the gap between trackside infrastructure and the train, it offers onboard services such as internet access, entertainment, and passenger information. Operating within the mmWave range, LightningBlu ensures a seamless communication experience even at high speeds, significantly enhancing the onboard experience for passengers. Integrating robust mmWave technology, the solution supports high data throughput, ensuring passengers can enjoy swift internet access and other online services while traveling. This wireless solution eliminates the need for traditional wired networks, reducing complexities and enhancing operational flexibility. With a profound ability to support high-speed data-intensive applications, LightningBlu sets a new benchmark in transportation connectivity. This platform's design facilitates smooth operation at velocities exceeding 300 km/h; coupled with its ability to maintain service over several kilometers, it is a critical component in advancing modern rail systems. LightningBlu not only meets today’s connectivity demands but also future-proofs the necessities of tomorrow's rail network implementations.
The INAP375R Receiver complements its transmitter counterpart in offering comprehensive high-speed data reception for automotive applications. It supports multiple video and audio channels, facilitating seamless data conversion and transfer for automotive entertainment systems. Designed to work effectively with up to 12 meters of cable, the receiver ensures consistent data fidelity over distance. Incorporating an advanced current mode logic, the INAP375R efficiently handles differential signals, maintaining data integrity even in demanding environments. Its capacity to deliver up to 3Gbps over a single cable ensures compatibility with various automotive applications, be it infotainment or safety-related systems. The versatile interface options of the INAP375R enable it to adapt to varying automotive standards while ensuring reliable performance. With built-in support for AShell protocol for error detection and correction, the receiver guarantees the safe and accurate transmission of critical data across automotive networks, underpinning its suitability for high-reliability applications.
IPM-NVMe Device is a high-performance data transfer management solution crafted for PCIe-based storage systems. This IP core functions as a vital interface between communication and NAND flash controllers, effectively relieving host CPU workloads. Fully compliant with UNH-IOL NVM Express, it provides extensive integration options for a host of system designs. The IPM-NVMe Device supports automatic command processing and multi-channel DMA, capable of managing up to 65,536 I/O queues. It features advanced capabilities such as weighted round-robin queue arbitration, asynchronous event management, and low-power architecture, all optimized for seamless scalability and integration into multiple PCIe generations. Manufacturers benefit from its standardized driver, facilitating easier software development and reducing costs. Whether in FPGA or SoC designs, this IP core is designed to support next-generation emerging memory solutions like MRAM and ReRAM, making it adaptable for use in both consumer and enterprise products.
The ntLDPC_8023CA (17664,14592) IP Core is defined in IEEE 802.3ca-2020 standard document and it is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes. These LDPC codes are based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that they offer high throughput at low implementation complexity. The ntLDPCE_8023CA encoder IP implements a 256-bit parallel systematic LDPC encoder. The Generator LDPC Matrix is calculated off-line, compressed and stored in ROM. It is partitioned to 12 layers and each layer when multiplied by the 14592 payload block pro-duces 256 parity bits. The multiplier architecture may be parameterized before synthesis to generate multiple multiplier instances [1 to 6], in order to effectively process multiple layers in parallel and improve the IP throughput rate. Shortened blocks are supported with granularity of 128-bit boundaries and 384 or 512 parity bits puncturing is also optionally supported. The ntLDPCD_8023CA decoder IP Core may optionally implement one of two approximations of the log-domain LDPC iterative decoding algorithm (Belief propagation) known as either Layered Offset Min-Sum Algorithm (OMS) or Layered Lambda-min Algorithm (LMIN). Selecting between the two algorithms presents a decoding performance vs system resources utilization trade-off. The OMS algorithm is chosen for this implementation, given the high code rate of the Parity Check Matrix (PCM). The ntLDPCD_8023CA decoder IP implements a 256-bit parallel systematic LDPC layered decoder. Each layer corresponds to Z=256 expanded rows of the original LDPC matrix. Each layer element corresponds to the active ZxZ shifted identity sub-matrices within the layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit, in order to update the layers LLR estimates and extrinsic information iteratively until the required number of decoding iterations has been run. The decoder IP also features a powerful optional early termination (ET) criterion, to maintain practically equivalent error correction performance, while significantly increasing its throughput rate and/or reducing hardware cost. Additionally it reports how many decoding iterations have been performed when ET is activated, for system performance observation and calibration purposes. Finally a simple, yet robust, flow control handshaking mechanism is included in both IPs, which is used to communicate the IPs availability to adjacent system components. This logic is easily portable into any communication protocol, like AXI4 stream IF.
The HOTLink II Core provides a complete layer 2 hardware implementation for high-speed interconnects. It is designed for full-rate, half-rate, and quarter-rate operations, making it versatile for various high-speed communication applications. With its F-18 compatible interface, it offers straightforward integration of frame-level interfaces, supporting high-speed signaling across devices.
The FC Link Layer Core implements the FC-1 and FC-2 layers, offering a full suite IP solution for Fibre Channel communication. Its design ensures high-reliability data transmission, crucial for military and aerospace applications requiring dependable networking capabilities.
ntRSD core implements a time-domain Reed-Solomon decoding algorithm. The core is parameterized in terms of bits per symbol, maximum codeword length and maximum number of parity symbols. It also supports varying on the fly shortened codes. Therefore any desirable code-rate can be easily achieved rendering the decoder ideal for fully adaptive FEC applications. ntRSD core supports erasure decoding thus doubling its error correction capability. The core also supports continuous or burst decoding. The implementation is very low latency, high speed with a simple interface for easy integration in SoC applications.
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