All IPs > Security IP > Security Protocol Accelerators
Security Protocol Accelerators are crucial components within the realm of semiconductor IP, designed to boost the performance of security protocols in various applications. These accelerators play a pivotal role in enhancing the speed, efficiency, and reliability of data encryption and decryption processes, which are fundamental for secure communications and transactions across networks. By implementing specialized hardware for protocol acceleration, these semiconductor IPs offer significant improvements in processing speed compared to software-only solutions.
One of the primary uses of Security Protocol Accelerators is in network security devices, including routers, firewalls, and VPNs, where they ensure secure communication by accelerating tasks such as data encryption and IPsec processing. As data breaches and cyber threats continue to evolve, the demand for robust and efficient security solutions has never been higher. These accelerators enable the optimization of cryptographic operations, providing enterprises and individuals with the confidence that their sensitive data is well-protected during transmission.
In consumer electronics like smartphones, tablets, and smart home devices, security protocol accelerators are key to maintaining user privacy without compromising on performance. They ensure that devices can handle complex security tasks quickly, extending battery life and maintaining seamless user experiences. Whether it’s ensuring the security of cloud-based services or protecting communications over Wi-Fi and cellular networks, these semiconductor IPs are increasingly vital in an interconnected world.
Moreover, the rise of IoT devices and edge computing has expanded the need for security protocol accelerators. With the massive data exchange happening at the edge of networks, having efficient security IPs ensures not just the safety of the data but also compliance with regulatory standards. As companies continue to push for innovations in AI and machine learning, the integration of security protocol accelerators in their systems helps to safeguard intellectual property and sensitive algorithms, thereby maintaining a secure operational environment. Through leveraging these semiconductor IPs, creators can focus on innovation while relying on proven security foundations.
The Akida 2nd Generation processor further advances BrainChip's AI capabilities with enhanced programmability and efficiency for complex neural network operations. Building on the principles of its predecessor, this generation is optimized for 8-, 4-, and 1-bit weights and activations, offering more robust activation functions and support for advanced temporal and spatial neural networks. A standout feature of the Akida 2nd Generation is its enhanced teaching capability, which includes learning directly on the chip. This enables the system to perform one-shot and few-shot learning, significantly boosting its ability to adapt to new tasks without extensive reprogramming. Its architecture supports more sophisticated machine learning models such as Convolutional Neural Networks (CNNs) and Spatio-Temporal Event-Based Neural Networks, optimizing them for energy-efficient application at the edge. The processor's design reduces the necessity for host CPU involvement, thus minimizing communication overhead and conserving energy. This makes it particularly suitable for real-time data processing applications where quick and efficient data handling is crucial. With event-based hardware that accelerates processing, the Akida 2nd Generation is designed for scalability, providing flexible solutions across a wide range of AI-driven tasks.
KPIT Technologies offers comprehensive AUTOSAR solutions that are pivotal for the development of modern, adaptive automotive systems. Emphasizing middleware integration and E/E architecture transformation, their solutions simplify the complexities of implementing adaptive AUTOSAR platforms, enabling streamlined application development and expeditious vehicle deployment. With extensive experience in traditional and adaptive AUTOSAR ecosystems, KPIT assists OEMs in navigating the challenges associated with software-defined vehicles. Their expertise facilitates the separation of hardware and software components, which is crucial for the future of vehicle digital transformation. KPIT's middleware development capabilities enhance vehicle systems' robustness and scalability, allowing for seamless integration across various automotive applications and ensuring compliance with industry standards. By fostering strategic partnerships and investing in cutting-edge technology solutions, KPIT ensures that its clients can confidently transition to and maintain advanced AUTOSAR platforms. The company's commitment to innovation and excellence positions it as a trusted partner for automakers striving to stay ahead in the competitive automotive landscape by embracing the shift towards fully software-defined vehicles.
aiWare is engineered as a high-performance neural processing unit tailored for automotive AI applications, delivering exceptional power efficiency and computational capability across a broad spectrum of neural network tasks. Its design centers around achieving the utmost efficiency in AI inference, providing flexibility and scalability for various levels of autonomous driving, from basic L2 assistance systems to complex L4 self-driving operations. The aiWare architecture exemplifies leading-edge NPU efficiencies, reaching up to 98% across diverse neural network workloads like CNNs and RNNs, making it a premier choice for AI tasks in the automotive sector. It boasts an industry-leading 1024 TOPS capability, making it suitable for multi-sensor and multi-camera setups required by advanced autonomous vehicle systems. The NPU's hardware determinism aids in achieving high ISO 26262 ASIL B certification standards, ensuring it meets the rigorous safety specifications essential in automotive applications. Incorporating an easy-to-integrate RTL design and a comprehensive SDK, aiWare simplifies system integration and accelerates development timelines for automotive manufacturers. Its highly optimized dataflow and minimal external memory traffic significantly enhance system power economy, providing crucial benefits in reducing operational costs for deployed automotive AI solutions. Vibrant with efficiency, aiWare assures OEMs the capabilities needed to handle modern automotive workloads while maintaining minimal system constraints.
Polar ID is a groundbreaking biometric security solution designed for smartphones, providing a secure and convenient face unlock feature. Employing advanced meta-optic technology, Polar ID captures the polarization signature of a human face, offering an additional layer of security that easily identifies human tissue and foils sophisticated 3D mask attempts. This technology enables ultra-secure facial recognition in diverse environments, from daylight to complete darkness, without compromising on the user experience. Unlike traditional facial recognition systems, Polar ID operates using a simple, compact design that eliminates the need for multiple optical modules. Its unique capability to function in any lighting condition, including bright sunlight or total darkness, distinguishes it from conventional systems that struggle under such scenarios. Furthermore, the high resolution and precision of Polar ID ensure reliable performance even when users have their face partially obscured by sunglasses or masks. With its cost-effectiveness and small form factor, Polar ID is set to disrupt the mobile device market by making secure biometric authentication accessible to a broader range of smartphones, not just high-end models. By simplifying the integration of facial recognition technology, Polar ID empowers mobile devices to replace less secure, inconvenient fingerprint sensors, thus broadening the reach and applicability of facial biometrics in consumer electronics.
The AES-XTS core is optimized for encryption of storage devices, providing advanced data protection by implementing the AES-XTS mode. XTS-AES is specifically designed for encrypting data storage, such as hard drives and SSDs, ensuring that sensitive information remains secure and inaccessible to unauthorized users. This core delivers high-speed encryption and decryption capabilities, making it ideal for disk encryption applications where performance is a critical factor. It adheres to the IEEE P1619 standard, which outlines the AES consistency in securing data at rest. By employing the AES-XTS core, storage devices can achieve comprehensive protection against data breaches, safeguarding important data across various storage media in personal computers, corporate databases, and portable external devices, ensuring data security and regulatory compliance.
PUFrt stands as a flagship hardware root of trust solution, incorporating PUF technology to create a unique and unclonable UID directly on the chip. This ensures robust security from the ground up, offering features such as TRNG, secure OTP, and an attack-resistant shell. The architecture of PUFrt provides a resilient foundation for semiconductor devices, helping to mitigate reverse engineering and counterfeiting risks. It integrates seamlessly with various systems, offering a trusted base for lightweight hardware security keys and full-function security coprocessors.
Trilinear Technologies' HDCP Encryption-Decryption Engine is a sophisticated solution designed to safeguard digital content as it traverses various transmission channels. This engine is compliant with the HDCP standards 1.4 and 2.3, offering robust protection mechanisms to ensure that digital media investments are secure from unauthorized access and piracy. The engine’s hardware acceleration capabilities represent a crucial advantage, significantly reducing the load on the system processor while maintaining real-time encryption and decryption functions. This not only enhances performance but also extends the operational life of the hardware involved, making it suitable for high-demand media applications across sectors such as broadcast, entertainment, and corporate environments. Trilinear’s HDCP Encryption-Decryption Engine ensures compatibility with a wide array of consumer and professional-grade video equipment, providing seamless protection without interference in media quality or transmission speed. Its flexible integration options allow it to be smoothly incorporated into existing infrastructures, whether in standalone media devices or complex SoC architectures. Supported by comprehensive software resources, the HDCP Encryption-Decryption Engine provides an all-encompassing solution that includes necessary software stacks for managing device authentication and link maintenance. Its ability to safeguard high-definition content effectively makes it an invaluable asset for entities focused on secure content delivery and rights management.
Securyzr iSSP is an advanced security lifecycle management solution, designed to offer seamless integration of security features throughout the device lifecycle. It provides a comprehensive platform for managing security tasks such as provisioning, firmware updates, security monitoring, and device identity management. The iSSP is built to facilitate zero-touch security lifecycle services, ensuring robust protection against potential cyber threats from chip to cloud. It stands out with its ability to handle post-quantum cryptography (PQC), making it future-ready and capable of addressing upcoming security challenges in an evolving digital landscape.
eSi-Crypto provides advanced features in encryption and authentication, offering an impressive suite of solutions including True Random Number Generators (TRNGs), cryptographic processing, and Public Key Acceleration. Engineered to optimize resource usage without compromising throughput, it is designed to secure devices effectively in various critical applications.
The HOTLink II Core provides a complete layer 2 hardware implementation for high-speed interconnects. It is designed for full-rate, half-rate, and quarter-rate operations, making it versatile for various high-speed communication applications. With its F-18 compatible interface, it offers straightforward integration of frame-level interfaces, supporting high-speed signaling across devices.
The L5-Direct GNSS Receiver represents a sophisticated leap in positioning technology, offering a robust solution that directly captures L5-band signals, ensuring high precision in urban canyons and resilience to interference and jamming. This groundbreaking technology operates independently of the legacy L1 signals, utilizing innovative Application Specific Array Processor (ASAP) architecture to optimize signal processing for GNSS applications. The receiver's capabilities include support for a multitude of satellite constellations like GPS, Galileo, QZSS, and BeiDou, providing unmatched versatility and accuracy. Engineered for environments prone to signal disruption, the L5-direct receiver employs machine learning algorithms to effectively mitigate multipath errors, leveraging data from all GNSS signals. The result is a performance that ensures reliable location data, crucial for applications ranging from wearables and IoT devices to defense systems. This technology's design incorporates a single RF chain, reducing the overall size and cost while simplifying antenna integration and system complexity. In addition to its technological prowess, the L5-direct receiver offers scalable integration potential, from standalone ASICs to IP cores adaptable across various silicon processes. Through ongoing R&D and strategic partnerships with leading foundries such as TSMC and GlobalFoundries, oneNav ensures that this receiver not only meets current demands but also evolves with future GNSS innovations, maintaining a competitive edge in global positioning solutions.
The Individual IP Core Modules by ResQuant are comprehensive components engineered to support diverse post-quantum cryptographic standards, including Dilithium, Kyber, XMSS, SPHINCS+, AES, and the SHA-2 family. These modules offer organizations the flexibility to select specific cryptographic functionalities tailored to their security needs, without the necessity of entire systems or hardware changes. Each module is designed to integrate easily into existing infrastructure, ensuring minimal disruption while enhancing security measures against potential future quantum threats. This approach allows industries to gradually implement PQC standards, ensuring a seamless transition to quantum-resistant cryptographic measures. Tailored for flexibility, the ResQuant Individual IP Core Modules can be used across a wide array of applications, from IoT devices to complex military and IT systems. By offering component-level integration, these modules empower companies to future-proof their offerings incrementally while maintaining robust security practices in their operations.
Offering an efficient solution for lossless image compression, the JPEG-LS Encoder represents Parretto's dedication to high-performance design. This encoder implements the JPEG-LS standard—renowned for its superior performance in lossless compression without the excessive resource demand seen in alternatives like JPEG-2000. With capabilities to handle 8 to 16 bits image depths, it delivers leading compression results while maintaining a low requirement for additional computational resources, such as external memory. The encoder achieves impressive efficiency, performing encoding with less than one line of latency. Its flexible interface options, including pixel and data FIFO input/output and an Avalon Streaming interface, accommodate back-pressure, supporting one pixel per clock cycle. Additionally, configurable options for output data word width and sizes reaching ultra-high-definition ensure versatility in various applications.
Secure Protocol Engines by Secure-IC are high-performance IP blocks designed to offload the intensive computational tasks of network and security processing from primary processors. These engines improve overall system efficiency by handling complex security protocols, ensuring that the main computing resources are available for critical applications. They are architected to provide robust protection against security breaches while ensuring swift data processing, maintaining the integrity, confidentiality, and availability of data across networks.
The Securyzr Key Management System offers a robust solution integrated into Secure-IC's security ecosystem to manage cryptographic keys effectively and securely. This system ensures that key generation, distribution, and storage processes are carried out in a highly secure manner, facilitating strong encryption and digital signature functions. Its integration into a wide range of devices guarantees secure communication and data handling across various applications, making it a critical component in safeguarding sensitive data.
The AES-GCM core is developed for authenticated encryption, delivering enhanced data protection through a combination of encryption and integrity assurance. AES-GCM (Galois/Counter Mode) is a mode of operation for AES that offers authenticated encryption, which is crucial for secure communications requiring both confidentiality and authenticity. This core is designed for high-performance environments, ensuring minimal latency while maximizing throughput. It is suitable for a variety of applications including secure network communications, storage encryption, and high-speed data transfer systems. With its integrated authentication mechanisms, the AES-GCM core protects data against unauthorized modifications and ensures secure, tamper-proof communication channels, making it indispensable for industries like financial services, telecommunications, and cloud computing where data integrity and confidentiality are paramount.
The AES standard modes core is designed for secure encryption applications, adhering to the Advanced Encryption Standard (AES). It offers reliable and efficient encryption capabilities essential for safeguarding sensitive data across various platforms. Developed with a robust architecture, this core ensures optimal performance in both resource-constrained and high-throughput environments. The core supports multiple AES modes including ECB, CBC, CFB, OFB, and CTR, making it versatile for different encryption needs. It provides high security and flexibility, essential for applications such as telecommunications, storage, and secure communication networks. By incorporating this core into their systems, users can meet stringent security standards while enjoying ease of integration and minimal resource consumption.
The FPGA Lock Core is an innovative FPGA solution designed to secure FPGAs and hardware against unauthorized access and counterfeiting, leveraging a Microchip ATSHA204A crypto authentication IC. It reads a unique ID, generates a 256-bit challenge, and uses secure hashing to verify the hardware's authenticity, ensuring hardware integrity in sensitive applications like military and medical fields. This solution allows hardware protection against IP theft by enforcing authentication and disables FPGA functionality if unauthorized access is detected. The core utilizes minimal logic resources and one FPGA pin, communicating through a bidirectional open drain link. The clarity of this system is enhanced by providing the core in VHDL, allowing users to thoroughly understand its functionality, supported by example designs on Cyclone10 and Artix 7 boards, catering to both Intel and Xilinx FPGA platforms. Complementing this security measure is the Key Writer Core, which allows programming of custom secret keys into the ATSHA204A in situ on assembled boards, ensuring a seamless integration with the FPGA Lock system. Available for various FPGA platforms, the Efinix version, distributed with TRS Star, expands its applicability, with webinars and user guides offering in-depth implementation insights.
NeoPUF is a pioneering hardware security solution aimed at enhancing the protection of semiconductor devices. Leveraging physical unclonable function (PUF) technology, NeoPUF generates unique identifiers for each chip, providing an essential root of trust for secure applications. This capability is crucial in environments where robust data security is paramount, such as IoT, AI, and automotive sectors. Unlike traditional security measures that rely on stored keys, NeoPUF derives keys directly from the inherent physical characteristics of the silicon, making it resistant to cloning and reverse engineering. This approach ensures that each device can authenticate itself and safeguard sensitive information without exposing it to potential threats. Such a methodology significantly strengthens the overall security infrastructure of modern digital systems. NeoPUF not only facilitates secure communication but also aids in protecting intellectual property against piracy and counterfeiting. It is a versatile technology that integrates smoothly into existing systems and requires no additional hardware, minimizing costs while maximizing security. As security becomes an increasingly critical aspect of semiconductor design, NeoPUF stands out as a forward-thinking solution ready to meet the challenges of emerging technologies.
PUFcc is an all-encompassing Crypto Coprocessor that delivers key generation, storage, and complete crypto operations in one solution. It builds on the PUFrt's hardware root of trust, offering secure boot, OTA updates, TLS, and key management. Its comprehensive design includes NIST-certified cryptographic algorithms, customizable for a wide range of IoT applications. PUFcc simplifies SoC design with standardized control interfaces and secure memory access, enhancing system security effortlessly.
The QUIC Protocol Core is designed to facilitate ultrafast data transfers over the internet, making it ideal for modern web applications that require secure and reliable data transmission. It fully implements the QUIC protocol, known for its efficiency and built-in security, including support for TLS 1.3, which underpins the core. This design offers a robust hardware logic system that handles packet encryption and decryption, significantly offloading these tasks from the CPU to enhance overall system performance. The core's architecture ensures minimal latency and maximum throughput, making it suitable for applications that demand rapid, encrypted network communications without compromising on speed. By offloading the primary CPU, the QUIC Protocol Core allows efficient CPU resource management, contributing to reduced operating costs in data-intensive environments. It is particularly beneficial in high-frequency trading, video conferencing, and gaming, where low latency and high security are critical. Further enhancing its appeal, the core integrates efficiently with existing FPGA-based systems, providing a versatile solution for upgrading network communication capabilities. Its scalability allows it to cater to varying data processing demands, while its energy-efficient design helps minimize power consumption. The QUIC Protocol Core therefore offers a compelling proposition for industries seeking to optimize their high-speed data transmission infrastructure.
The Customizable Cryptography Accelerator offered by ResQuant is designed to meet varied client needs with an extensive array of configurable options. It integrates seamlessly with all NIST PQC standards like Dilithium, Kyber, XMSS, and SPHINCS+, and is extendible with additional algorithms, including customer-specific implementations. The accelerator is built to be DPA, timing, and SCA resistant, and is AXI 4 ready, ensuring robust protection in a variety of applications. This innovation allows for customizable tuning in performance and size, addressing the specific security requirements of customers from various industries. The accelerator demonstrates ResQuant's commitment to flexibility and adaptability, enabling clients to implement cutting-edge encryption with ease. With ongoing enhancements to extend its capabilities, the accelerator stands as a critical component in defenses against future computational threats posed by quantum technologies. In addition to its technical capabilities, the ResQuant Customizable Cryptography Accelerator is engineered for efficient power use and minimized physical footprint, making it suitable for integration into a wide range of hardware setups. This solution underscores ResQuant's dedication to delivering high-security standards and unmatched versatility in cryptographic processing solutions.
PUFhsm is an advanced embedded hardware security module designed for automotive and complex applications. It acts as an embedded security enclave, isolating key functions from the main system to ensure secure operations. With integrated cryptographic engines and dedicated CPUs, PUFhsm supports secure boot, updates, and key management within a compliant framework. It enhances designs by bolstering security while optimizing efficiency and reducing time-to-market.
The QDID PUF is an innovative hardware experience designed to generate a unique cryptographic identity through quantum tunneling current variations. Utilizing standard CMOS processes, it taps into randomness deriving from oxide thickness variations and defect distribution in gate oxide, creating a robust hardware root-of-trust. This enables the establishment of secure architectures by providing on-the-fly identity generation that does not rely on memory storage, making it resistant to side-channel and machine learning attacks. The QDID PUF is especially noteworthy for its high entropy seed generation, supporting customizable security strengths up to 256 bits, and is designed with built-in resistance against secret leakage through advanced countermeasures. The technology is thoroughly tested under diverse environmental conditions, consistently maintaining reliability and longevity, and has achieved extensive verification across major fabs including TSMC, GF, and UMC across various process nodes in Bulk CMOS, FDSOI, and FinFET technologies. It enables key generation and device authentication, serving as a cornerstone for secure provisioning and post-quantum cryptography, thus supporting various applications in device identification, supply chain security, and more. Successfully verified under NIST standards, QDID PUF ensures excellent performance across voltage, temperature, and ageing tests, offering a robust solution for future-proof IoT device integration.
Designed as a public key algorithm coprocessor, the FortiPKA-RISC-V stands out for its ability to streamline operations typically bogged down by Montgomery domain transformations. This component is tailored for high performance in embedded systems, ensuring enhanced data security through its advanced modular multiplication and robust protection against SCA and FIA. Particularly suited for secure System on Chip (SoC) integration, FortiPKA-RISC-V offers significant performance improvements without increasing area constraints.
PhantomBlu is a milestone in tactical communications, providing high-performance, data-rich connectivity solutions tailored for defence environments. Delivering on-the-move gigabit connectivity capabilities, it is designed to support demanding applications in mission-critical scenarios. With independently configurable options as PCP (hub) or STA (client), this solution excels in providing high-speed tactical communications over extensive ranges, making it indispensable in strategic defence operations. The platform leverages Blu Wireless’s advanced mmWave technology to ensure low SWAP (size, weight, and power) features, crucial for mobile and portable military applications. This adaptability and lack of reliance on cabled networks ensure PhantomBlu is not only agile but also highly effective across diverse operational environments. Through meticulous design, PhantomBlu supports interoperability with existing and future military assets, thereby extending the life and usability of defence communications infrastructure. By enabling high-bandwidth networks and low-latency communications, it stands as a cornerstone for modern defence strategies, allowing rapid data exchange vital for decision-making in fast-evolving tactical circumstances.
The CANsec Controller Core is engineered to enhance the security of CAN networks by integrating robust cryptographic protocols and mechanisms that protect data integrity and confidentiality. This cutting-edge solution is tailored for automotive applications, providing an extra layer of security to combat the rising threats in vehicle systems as they increasingly connect to broader networks and the internet. CAN networks, widely used in vehicular communications, were originally designed without security in mind. This leaves them vulnerable to potential cyber-attacks, which is where the CANsec Controller Core comes into play. It bolsters the data transmission network by encrypting messages and authenticating commands, thus significantly mitigating the risk of interception or malicious tampering. With its seamless integration capabilities, the CANsec Controller Core can be adopted without major modifications to existing network infrastructures, making it an ideal choice for gradual implementation in both new and legacy systems. Its flexibility and robust security features make it an invaluable tool for manufacturers aiming to enhance the security resilience of their automotive technologies while adhering to evolving industry standards.
The AES Crypto core by Dillon Engineering is designed to provide robust encryption and decryption capabilities, compliant with the Federal Information Processing Standard (FIPS) 197. This highly parameterized core supports a multitude of operating modes including ECB, CBC, CFB, OFB, and CTR as outlined in NIST special publication 800-38A. Engineered to handle up to 12.8 Gb/s data throughput, this core manages dynamic key changes without affecting performance, ensuring secure data handling per advanced encryption standards. The core is versatile, offered in configurations that balance throughput and area, fulfilling diverse security demands. Employing Dillon's ParaCore Architect, the AES Crypto core is adaptable to both FPGA and ASIC platforms, designed as a self-contained module with a comprehensive testbench. This core provides a seamless security solution for applications that demand high-speed encryption, effectively supporting secure communications and data protection in different deployment contexts.
Suite-Q HW is a comprehensive system-on-chip (SoC) design by PQ Secure that integrates all necessary cryptographic components for secure protocols. Targeted at both high-end servers and low-end embedded systems, Suite-Q HW offers versatile hardware accelerators capable of conducting symmetric and asymmetric cryptographic operations efficiently. Key features of this hardware include a NIST 800-90-compliant true random number generator (TRNG), support for a variety of elliptic curve cryptographies, and capabilities for post-quantum cryptography operations such as isogeny-based and lattice-based cryptographies. It also supports traditional algorithms like AES and SHA, ensuring compatibility with established security protocols. Suite-Q HW is engineered to offload heavy cryptographic computations, reducing system demands while providing substantial power savings over software implementations. This makes it ideal for applications requiring high security and efficiency, such as in IoT devices where power consumption is a critical concern. Enhanced by optional DPA countermeasures, it provides robust security in a compact and efficient package.
FortiCrypt is an advanced encryption technology developed for protecting data against side-channel and fault injection attacks. This solution implements algorithmic resistance using finite field arithmetic, ensuring secure handling of data without adding extra latency or requiring custom silicon processing. It stands out for its successful passage of rigorous evaluations, including the Test Vector Leakage Assessment conducted on one billion traces. This ensures FortiCrypt can be used flexibly across various technologies and platforms while maintaining high security.
The SHA-3 Crypto Engine is a robust hardware accelerator specifically designed for cryptographic hashing functions. It presents a balance of high throughput and area efficiency and aligns with the FIPS 202 standards set by NIST. This engine supports all SHA-3 hash functions, including SHA-3-224, SHA-3-256, SHA-3-384, and SHA-3-512, as well as SHAKE-128 and SHAKE-256. Built to mitigate security vulnerabilities, it provides comprehensive defense against time-based side-channel attacks, ensuring data integrity. Operating within a single clock domain, the SHA-3 Crypto Engine is adequately verified, boasting automatic byte padding and effortless integration into existing systems. Its versatility spans numerous applications ranging from Message Authentication Codes (MACs) to protocol engines like IPsec and TLS/SSL, alongside secure boot engines and encrypted data storage solutions. Through integrating this engine, clients can guarantee the integrity and security of financial transactions, e-commerce platforms, and even blockchain applications. Delivered in System Verilog RTL with supportive testbenches and integration examples, the SHA-3 Crypto Engine offers straightforward deployment while maintaining compliance with industry standards. Its resource utilization spans a variety of FPGA families such as AMD Spartan, Kintex-7, and AMD Zynq MPSoC, presenting adaptability and efficiency across diverse platforms.
PQ Secure's Cryptographic Core is designed to handle a variety of cryptographic operations required for secure communication and data protection. This core supports both symmetric and asymmetric cryptographic algorithms, ensuring a comprehensive range of security features. With adaptability for different system requirements, it can be integrated into various hardware platforms including FPGAs and ASICs, offering efficient and secure processing. This core is capable of executing classical public key operations such as ECDSA, Ed25519, Curve25519, and Curve448, as well as supporting advanced encryption standards like AES and SHA algorithms. These capabilities ensure that the cryptographic core can handle multiple cryptographic needs, maintaining the integrity and confidentiality of data within digital systems. Designed with flexibility in mind, the core can be configured to meet specific performance and security requirements, making it suitable for applications that range from high-performance servers to low-power IoT devices. Alongside these features, the core is fortified against potential side-channel attacks, providing robust security in various application environments.
CoMira Solutions offers a Media Access Control Security (MACSec) solution adhering to IEEE standards aimed at safeguarding communication within 802.1 LAN environments. MACSec ensures data confidentiality and integrity, preventing unauthorized access and disruptions. It employs advanced encryption standards and supports flexible traffic management through various port configurations. The MACSec IP's time-division multiplexed architecture aligns seamlessly with CoMira's UMAC, ensuring synchronous operation despite differing link speeds. This implementation includes FIPS-compliant encryption methods such as GCM-AES-128 and GCM-AES-256, supporting robust security needs. Furthermore, CoMira's MACSec supports multiple secure channels and security associations per port, adding layers of protection to client systems. The configurability of Secure Channels and the ability to strip security tags enhances its adaptability in varied networking scenarios, reflecting CoMira's commitment to delivering tailor-fit security solutions.
Comcores' MACsec solution addresses the needs for secure communication on Ethernet links by implementing the IEEE 802.1AE standard for MAC Security. It provides comprehensive protection against eavesdropping and manipulation, making it suitable for applications demanding high security over public and private networks. Built to support various data rates, the MACsec IP core integrates robust cryptographic suites like AES-GCM to encrypt and authenticate network traffic. Its deployment ensures data confidentiality and integrity, fostering a secure environment for transmitting sensitive information such as in military communication systems and data centers.
The Security Protocol Accelerator from PQ Secure is engineered to enhance the efficiency of cryptographic protocols by offloading computationally intensive processes onto a dedicated hardware unit. This approach not only speeds up operations but also reduces the load on primary processors, enhancing overall system performance. Supporting a broad range of cryptographic protocols, this accelerator is designed to integrate seamlessly with existing infrastructure, ensuring backward compatibility and operational efficiency. Its robust architecture allows it to support various established and emerging cryptographic standards, making it adaptable to both current and future security needs. Additionally, the Security Protocol Accelerator features built-in protections against advanced security threats, such as side-channel attacks, ensuring that data remains protected against evolving tactics used by attackers. The accelerator is a valuable addition to systems needing enhanced security measures alongside optimal performance.
The Keccak Hash Engine is renowned for its adaptability and capability, primarily recognized as a cryptographic hash function. Its core structure is based on a unique sponge construction featuring the Keccak-f cryptographic permutation, allowing for extensive customization in output length and security strength. This flexibility has secured its adoption in mobile telephony standards like 3GPP TS 35.231 and NIST standards, namely FIPS 202 and SP 800-185. Capable of executing hash functions and providing support for authentication, encryption, and pseudo-random number generation, the Keccak Hash Engine is a versatile asset in various cryptographic applications. Its design rests on simplicity and ease of integration, coupled with a single clock domain to ensure seamless deployment and operation across platforms. Due to its extensively verified code, the Keccak Hash Engine is dependable for applications demanding high security levels, like blockchain, random number generation, and authentication protocols. Available in System Verilog RTL, it is suitable for diverse industrial applications that demand robust cryptographic functions adaptable to evolving security needs.
Synopsys Security Protocol Accelerators provide robust cryptographic support to meet the growing demand for secure communication in digital systems. These accelerators are designed for high efficiency, offering hardware-level security that enhances data protection without compromising on system speed. Supporting a plethora of protocols such as IPsec, SSL/TLS, and more, they ensure data confidentiality, integrity, and authenticity, making them ideal for secure applications across multiple domains, including financial services, telecommunications, and government sectors. Synopsys security solutions prioritize compliance and interoperability, ensuring secure data exchanges across secure and untrusted networks.
The Stellar Packet Classification Platform is specifically designed for ultra-high-speed search performance within FPGA environments. It manages lookup operations using complex Access Control List (ACL) and Longest Prefix Match (LPM) rules, making it an ideal solution for scenarios requiring rigorous data filtering and sorting. This platform enables hundreds of millions of lookup operations per second, adaptable to data rates stretching from 25Gbps to over 1Tbps, handling millions of intricate rules with the capacity for live updates. This scalability ensures that the platform can meet the needs of current and future network enhancements, especially as demand for high reliability and speed grows. Feature-rich, the Stellar platform facilitates extensive key matching, allowing up to 480-bit keys to be processed, ensuring effective handling of vast knowledge sets in high-speed environments. It supports functions critical to maintaining robust and efficient data routing and security protocols, helping to safeguard infrastructures from threats and optimizing data packet handling. Perfect for applications that demand precise data routing and protection, such as IPv4/6 address lookups, network firewalls, and anti-DDoS measures. The Stellar Platform's adaptability makes it a preferred choice for emerging technologies and capabilities in evolving network setups like 5G networks and beyond.
This IP core offers advanced technology to resist side-channel attacks, crucial for maintaining the integrity and confidentiality of sensitive data. It is specifically engineered to withstand efforts to extract cryptographic keys via analysis of physical emanations from hardware devices. The side-channel attack resistance feature of this product ensures that it can be deployed in environments where data protection is paramount, such as in financial systems and secure communications.
The Geon Secure Execution Processor, built on the foundational BA22 architecture, is designed for high-performance cryptographic isolation of sensitive data. Operating at up to 450 MHz in a 65 nm process, it offers DMIPS/MHz performance of 1.79, making it suitable for diverse security needs. This processor has been verified at the system level, ensuring robust protection for sensitive applications.
ReRAM Secure Keys by CrossBar utilize the company's innovative ReRAM technology to provide a robust solution for creating physical unclonable function (PUF) based cryptographic keys. This application of ReRAM capitalizes on the inherent security features of resistive RAM technology to offer a superior alternative to traditional SRAM PUF solutions, which often suffer from high bit error rates and vulnerabilities to tampering. CrossBar's ReRAM PUF keys are designed with high randomness and low error rates, giving them significant resistance to invasive and side-channel attacks. This resilience makes them ideal for securing communications and operations in devices subject to high security demands, such as IoT endpoints, medical devices, and critical infrastructure. The ReRAM cells offer the added benefit of handling various environmental conditions seamlessly, ensuring that the system's security functions reliably across different scenarios. By delivering cryptographic keys that serve as the basis of trust ('root of trust'), these secure keys make it feasible to embed highly secure non-volatile memory functions into smaller manufacturing nodes where other NVM technologies may not be available.
FortiMac offers a secure implementation of HMAC SHA2, aimed at providing strong resistance to side-channel and fault injection attacks. Utilizing the Threshold Implementation paradigm ensures its ability to protect critical applications, both in software and hardware deployments. FortiMac's market distinction lies in its unique capability of employing only a minimal number of standard digital gates, while concurrently offering robust security for SCA and FIA threats.
This advanced Polar Encoder and Decoder IP offers high-speed encoding and decoding capabilities, reaching up to 100 Gbps. It's tailored for next-generation communication systems that require efficient data processing without compromising speed. The use of Polar coding, known for its capacity-achieving properties, provides superior error correction compared to other coding techniques. The IP supports a variety of modern communication protocols and is designed to be implemented on high-performance FPGA platforms. Its ability to handle large amounts of data quickly makes it ideal for use in data centers, high-speed networks, and telecommunications infrastructure seeking to enhance data throughput and reliability. This encoder and decoder solution not only improves data throughput but also ensures data integrity through advanced error correction mechanisms, thereby enhancing overall network performance and reliability. Its robustness and efficiency make it a critical component in any high-speed data transmission system.
Low Power Futures offers a formidable solution in the Low Power Security Engine, tailored to enhance the security measures of resource-constrained embedded devices. This advanced IP features a compact design that combines power efficiency with robust security capabilities, including support for ECDHE and ECDSA protocols. Its integrated acceleration engine offers protection against timing and side-channel attacks while enabling efficient cryptographic operations. Designed for seamless prototyping and real-world application, this security engine makes an impressive addition to any smart IoT device looking to emphasize security without compromising on performance.
The SHA-3 Secure Hash Function Core is designed compliant with FIPS 180-4 and FIPS 202 standards, supporting multiple hash functions like SHA3-224 and SHA3-512. Operating with as few as 28K gates, it achieves a throughput of up to 48 Mbit/MHz. This core offers developers a robust solution for integrating secure hash functionalities into various systems.
The CCSDS LDPC (8160, 7136) IP is a meticulously crafted Low-Density Parity-Check encoder and decoder tailored for space communication standards. The Consultative Committee for Space Data Systems (CCSDS) has specified these LDPC codes to enhance data integrity and reliability for space missions where error-free transmission is crucial. This IP core offers significant improvements in error correction performance, making it ideal for deep space and near-Earth missions requiring high data throughput and reliability. The use of LDPC coding provides a significant advantage over traditional error correction methods, enabling efficient data recovery even under challenging conditions. Designed for FPGA implementation, the IP can be seamlessly integrated into space communication systems, offering reliable performance and ensuring compliance with CCSDS standards. Its efficient use of resources makes it a preferred choice for space agencies looking to maximize mission success.
The KiviPQC-KEM is an advanced cryptographic solution developed for the post-quantum era, designed to support all ML-KEM variants standardized under NIST's FIPS 203. This IP core performs key operations necessary for key generation, encapsulation, and decapsulation, ensuring robust defenses against quantum computer attacks. The engine is a central asset in post-quantum cryptography, facilitating secure secret key establishment over public channels. Targeted for integration within ASIC and FPGA systems, the KiviPQC-KEM distinguishes itself with its minimalistic logic utilization and efficient resource management. It incorporates hardware acceleration to bolster performance during computationally intense tasks, bridging the gap between security needs and computational capabilities. KiviPQC-KEM is encapsulated as a standalone unit, allowing easy integration without extensive resources. Applications for this core cover a broad spectrum of secure communications, from quantum-resistant networks to electronic transactions. It also features seamless compatibility with network security protocols like MACsec, IPsec, and transport protocols such as TLS and SSL. The KiviPQC-KEM is delivered with comprehensive supporting documentation and source codes, ensuring that it meets the needs of developers seeking robust, quantum-safe solutions.
QRoot Lite is designed for resource-constrained MCUs and IoT devices, offering a lightweight, configurable root-of-trust. Built on TCG MARS specification, it simplifies integration and reduces cost, ensuring secure boot, attestation, and key protection. The IP minimizes silicon and power requirements, making it ideal for low-power device applications. Its flexible architecture allows seamless inclusion into SoC designs, offering not only secure boot and firmware validation but also tamper protection and unauthorized access prevention during device operation. QRoot Lite provides secure attestation using Trusted Computing Group standards, making it an excellent choice for meeting compliance and security standards in smart sensors, medical devices, and gateway products. It supports integration with standard industry interfaces and is optimized for low silicon footprint, reinforcing its versatility in diverse IoT environments.
Crypto Quantique's Cryptographic Cores are scalable cryptographic accelerators offering comprehensive algorithm coverage including AES, SHA, ECC, Ascon, and emerging post-quantum cryptography standards like Kyber and Dilithium. These cores are engineered for high-performance deployments in secure SoC designs, optimized for low-area and low-latency operation. Designed to resist side-channel and fault injection attacks, these cores provide a secure foundation for enforcement of secure boot, identity verification, and encryption protocols across various device implementations. This ensures reliable cryptographic operations in industry sectors like IoT, automotive, and medical devices. The cores offer configurable integration options, accommodating a variety of interface standards such as APB and AXI, which ease incorporation into existing development workflows. Focused on achieving compliance, these cores come with processes streamlined for regulatory certification, making them a pragmatic choice for forward-thinking system designs.
The Agile Secure Element is a configurable security enclave designed for integrating robust, flexible security features directly into SoC designs. It includes an embedded microprocessor and various cryptographic engines, supporting tasks like secure boot and trusted execution, making it an ideal tool for creating trusted zones in multi-core or subsystem-based SoC designs. With support for high-speed cryptographic operations and customizable architecture, the Agile Secure Element is prepared for regulatory compliance, ensuring capabilities align with standards like CRA and ISO. Its modular, certifiable design allows efficient security integration without the need for extensive modifications to existing systems. The IP features a rich set of cryptographic primitives and integration flexibility, accommodating standard interfaces like APB and AXI, which facilitates its adoption within various system architectures. The support for post-quantum cryptographic (PQC) implementations further enhances its readiness for future security requirements, ensuring next-generation SoC robustness, while maintaining efficient power and area ratios.
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