All IPs > Processor > Microcontroller
Microcontrollers form the backbone of many modern electronic devices, offering precise control and processing capabilities that power everything from consumer electronics to industrial machines. In the world of semiconductor IPs, microcontrollers provide the essential building blocks that allow developers to design complex functionalities tailored to specific applications. This category is vital for those looking to integrate processing and control functionalities directly into their embedded systems, providing efficiencies in both performance and energy use.
Microcontrollers available as semiconductor IPs are used in a broad spectrum of applications, from automotive and aerospace to smart home devices and IoT gadgets. By selecting a microcontroller IP, developers can customize core functions such as CPU architecture, memory management, input/output controls, and specialized peripherals to meet the specific needs of their projects. These IPs are designed to streamline the development process, reduce time-to-market, and offer flexibility in the design and scalability of end products.
One of the key advantages of utilizing microcontroller semiconductor IPs is the ability to incorporate proprietary or emerging technologies seamlessly into existing systems. This not only helps in keeping the product line up-to-date with the latest technology trends but also ensures that the devices remain competitive in the rapidly evolving electronics marketplace. Moreover, integrating microcontroller IPs can lead to cost savings by minimizing the need for additional chips and lowering power consumption through optimized architectures and process technologies.
As you explore the Processor > Microcontroller category in our Silicon Hub, you'll discover a wealth of options that cater to various industry needs, ranging from low-power designs suitable for portable devices to high-performance solutions required for complex computing tasks. Whether you are designing a simple control unit or a sophisticated embedded application, microcontroller semiconductor IPs provide the versatility and functionality necessary to drive innovation.
The NMP-750 is a high-performance accelerator designed for edge computing, particularly suited for automotive, AR/VR, and telecommunications sectors. It boasts an impressive capacity of up to 16 TOPS and 16 MB local memory, powered by a RISC-V or Arm Cortex-R/A 32-bit CPU. The three AXI4 interfaces ensure seamless data transfer and processing. This advanced accelerator supports multifaceted applications such as mobility control, building automation, and multi-camera processing. It's designed to cope with the rigorous demands of modern digital and autonomous systems, offering substantial processing power and efficiency for intensive computational tasks. The NMP-750's ability to integrate into smart systems and manage spectral efficiency makes it crucial for communications and smart infrastructure management. It helps streamline operations, maintain effective energy management, and facilitate sophisticated AI-driven automation, ensuring that even the most complex data flows are handled efficiently.
RaiderChip's GenAI v1 is a pioneering hardware-based generative AI accelerator, designed to perform local inference at the Edge. This technology integrates optimally with on-premises servers and embedded devices, offering substantial benefits in privacy, performance, and energy efficiency over traditional hybrid AI solutions. The design of the GenAI v1 NPU streamlines the process of executing large language models by embedding them directly onto the hardware, eliminating the need for external components like CPUs or internet connections. With its ability to support complex models such as the Llama 3.2 with 4-bit quantization on LPDDR4 memory, the GenAI v1 achieves unprecedented efficiency in AI token processing, coupled with energy savings and reduced latency. What sets GenAI v1 apart is its scalability and cost-effectiveness, significantly outperforming competitive solutions such as Intel Gaudi 2, Nvidia's cloud GPUs, and Google's cloud TPUs in terms of memory efficiency. This solution maximizes the number of tokens generated per unit of memory bandwidth, thus addressing one of the primary limitations in generative AI workflow. Furthermore, the adept memory usage of GenAI v1 reduces the dependency on costly memory types like HBM, opening the door to more affordable alternatives without diminishing processing capabilities. With a target-agnostic approach, RaiderChip ensures the GenAI v1 can be adapted to various FPGAs and ASICs, offering configuration flexibility that allows users to balance performance with hardware costs. Its compatibility with a wide range of transformers-based models, including proprietary modifications, ensures GenAI v1's robust placement across sectors requiring high-speed processing, like finance, medical diagnostics, and autonomous systems. RaiderChip's innovation with GenAI v1 focuses on supporting both vanilla and quantized AI models, ensuring high computation speeds necessary for real-time applications without compromising accuracy. This capability underpins their strategic vision of enabling versatile and sustainable AI solutions across industries. By prioritizing integration ease and operational independence, RaiderChip provides a tangible edge in applying generative AI effectively and widely.
Designed for entry-level server-class applications, the SCR9 is a 64-bit RISC-V processor core that comes equipped with cutting-edge features, such as an out-of-order superscalar pipeline, making it apt for processing-intensive environments. It supports both single and double-precision floating-point operations adhering to IEEE standards, which ensure precise computation results. This processor core is tailored for high-performance computing needs, with a focus on AI and ML, as well as conventional data processing tasks. It integrates an advanced interrupt system featuring APLIC configurations, enabling responsive operations even under heavy workloads. SCR9 supports up to 16 cores in a multi-cluster arrangement, each utilizing coherent multi-level caches to maintain rapid data processing and management. The comprehensive development package for SCR9 includes ready-to-deploy toolchains and simulators that expedite software development, particularly within Linux environments. The core is well-suited for deployment in entry-level server markets and data-intensive applications, with robust support for virtualization and heterogeneous architectures.
The NMP-350 is a cutting-edge endpoint accelerator designed to optimize power usage and reduce costs. It is ideal for markets like automotive, AIoT/sensors, and smart appliances. Its applications span from driver authentication and predictive maintenance to health monitoring. With a capacity of up to 1 TOPS and 1 MB of local memory, it incorporates a RISC-V/Arm Cortex-M 32-bit CPU and supports three AXI4 interfaces. This makes the NMP-350 a versatile component for various industrial applications, ensuring efficient performance and integration. Developed as a low-power solution, the NMP-350 is pivotal for applications requiring efficient processing power without inflating energy consumption. It is crucial for mobile and battery-operated devices where every watt conserved adds to the operational longevity of the product. This product aligns with modern demands for eco-friendly and cost-effective technologies, supporting enhanced performance in compact electronic devices. Technical specifications further define its role in the industry, exemplifying how it brings robust and scalable solutions to its users. Its adaptability across different applications, coupled with its cost-efficiency, makes it an indispensable tool for developers working on next-gen AI solutions. The NMP-350 is instrumental for developers looking to seamlessly incorporate AI capabilities into their designs without compromising on economy or efficiency.
The A25 processor model is a versatile CPU suitable for a variety of embedded applications. With its 5-stage pipeline and 32/64-bit architecture, it delivers high performance even with a low gate count, which translates to efficiency in power-sensitive environments. The A25 is equipped with Andes Custom Extensions that enable tailored instruction sets for specific application accelerations. Supporting robust high-frequency operations, this model shines in its ability to manage data prefetching and cache coherence in multicore setups, making it adept at handling complex processing tasks within constrained spaces.
The Yitian 710 Processor is an advanced Arm-based server chip developed by T-Head, designed to meet the extensive demands of modern data centers and enterprise applications. This processor boasts 128 high-performance Armv9 CPU cores, each coupled with robust caches, ensuring superior processing speeds and efficiency. With a 2.5D packaging technology, the Yitian 710 integrates multiple dies into a single unit, facilitating enhanced computational capability and energy efficiency. One of the key features of the Yitian 710 is its memory subsystem, which supports up to 8 channels of DDR5 memory, achieving a peak bandwidth of 281 GB/s. This configuration guarantees rapid data access and processing, crucial for high-throughput computing environments. Additionally, the processor is equipped with 96 PCIe 5.0 lanes, offering a dual-direction bandwidth of 768 GB/s, enabling seamless connectivity with peripheral devices and boosting system performance overall. The Yitian 710 Processor is meticulously crafted for applications in cloud services, big data analytics, and AI inference, providing organizations with a robust platform for their computing needs. By combining high core count, extensive memory support, and advanced I/O capabilities, the Yitian 710 stands as a cornerstone for deploying powerful, scalable, and energy-efficient data processing solutions.
The eSi-3250 32-bit RISC processor core excels in applications needing efficient caching structures and high-performance computation, thanks to its support for both instruction and data caches. This core targets applications where slower memory technologies or higher core/bus clock ratios exist, by leveraging configurable caches which reduce power consumption and boost performance. This advanced processor design integrates a wide range of arithmetic capabilities, supporting IEEE-754 floating-point functions and 32-bit SIMD operations to facilitate complex data processing. It uses an optional memory management unit (MMU) for virtual memory implementation and memory protection, enhancing its functional safety in various operating environments.
The eSi-3200 is a versatile 32-bit RISC processor core that combines low power usage with high performance, ideal for embedded control applications using on-chip memory. Its structure supports a wide range of computational tasks with a modified-Harvard architecture that allows simultaneous instruction and data fetching. This design facilitates deterministic performance, making it perfect for real-time control. The eSi-3200 processor supports extensive arithmetic operations, offering optional IEEE-754 floating-point units for both single-precision and SIMD instructions which optimize parallel data processing. Its compatibility with AMBA AXI or AHB interconnects ensures easy integration into various systems.
The eSi-1600 is a highly efficient 16-bit RISC processor core designed for applications that require low power and cost-effective solutions. Despite its 16-bit architecture, it offers performance akin to pricier 32-bit processors, making it an ideal choice for controlling functions in mature mixed-signal processes. The eSi-1600 is renowned for its power efficiency, running applications in fewer clock cycles compared to traditional 8-bit CPUs. Its instruction set includes 92 basic instructions and the capability for 74 user-defined ones, enhancing its adaptability. With support for a wide range of peripherals through AMBA AHB and APB buses, this core is versatile for various integration needs.
The xcore.ai platform from XMOS is engineered to revolutionize the scope of intelligent IoT by offering a powerful yet cost-efficient solution that combines high-performance AI processing with flexible I/O and DSP capabilities. At its heart, xcore.ai boasts a multi-threaded architecture with 16 logical cores divided across two processor tiles, each equipped with substantial SRAM and a vector processing unit. This setup ensures seamless execution of integer and floating-point operations while facilitating high-speed communication between multiple xcore.ai systems, allowing for scalable deployments in varied applications. One of the standout features of xcore.ai is its software-defined I/O, enabling deterministic processing and precise timing accuracy, which is crucial for time-sensitive applications. It integrates embedded PHYs for various interfaces such as MIPI, USB, and LPDDR, enhancing its adaptability in meeting custom application needs. The device's clock frequency can be adjusted to optimize power consumption, affirming its cost-effectiveness for IoT solutions demanding high efficiency. The platform's DSP and AI performances are equally impressive. The 32-bit floating-point pipeline can deliver up to 1600 MFLOPS with additional block floating point capabilities, accommodating complex arithmetic computations and FFT operations essential for audio and vision processing. Its AI performance reaches peaks of 51.2 GMACC/s for 8-bit operations, maintaining substantial throughput even under intensive AI workloads, making xcore.ai an ideal candidate for AI-enhanced IoT device creation.
The NaviSoC by ChipCraft is a highly integrated GNSS system-on-chip (SoC) designed to bring navigation technologies to a single die. Combining a GNSS receiver with an application processor, the NaviSoC delivers unmatched precision in a dependable, scalable, and cost-effective package. Designed for minimal energy consumption, it caters to cutting-edge applications in location-based services (LBS), the Internet of Things (IoT), and autonomous systems like UAVs and drones. This innovative product facilitates a wide range of customizations, adaptable to varied market needs. Whether the application involves precise lane-level navigation or asset tracking and management, the NaviSoC meets and exceeds market expectations by offering enhanced security and reliability, essential for synchronization and smart agricultural processes. Its compact design, which maintains high efficiency and flexibility, ensures that clients can tailor their systems to exact specifications without compromise. NaviSoC stands as a testament to ChipCraft's pioneering approach to GNSS technologies.
The NMP-550 is tailored for enhanced performance efficiency, serving sectors like automotive, mobile, AR/VR, drones, and robotics. It supports applications such as driver monitoring, image/video analytics, and security surveillance. With a capacity of up to 6 TOPS and 6 MB local memory, this accelerator leverages either a RISC-V or Arm Cortex-M/A 32-bit CPU. Its three AXI4 interface support ensures robust interconnections and data flow. This performance boost makes the NMP-550 exceptionally suited for devices requiring high-frequency AI computations. Typical use cases include industrial surveillance and smart robotics, where precise and fast data analysis is critical. The NMP-550 offers a blend of high computational power and energy efficiency, facilitating complex AI tasks like video super-resolution and fleet management. Its architecture supports modern digital ecosystems, paving the way for new digital experiences through reliable and efficient data processing capabilities. By addressing the needs of modern AI workloads, the NMP-550 stands as a significant upgrade for those needing robust processing power in compact form factors.
The SCR7 is a 64-bit RISC-V application core crafted to meet high-performance demands of applications requiring powerful data processing. Featuring a sophisticated dual-issue pipeline with out-of-order execution, it enhances computational efficiency across varied tasks. The core is equipped with a robust floating-point unit and supports extensive RISC-V ISA extensions for advanced computing capabilities. SCR7's memory system includes L1 to L3 caches, with options for expansive up to 16MB L3 caching, ensuring data availability and integrity in demanding environments. Its multicore architecture supports up to eight cores, facilitating intensive computational tasks across industries such as AI and machine learning. Ideal for high-performance computing and big data applications, the SCR7 leverages its advanced interrupt systems and intelligent memory management for seamless operation. Comprehensive development resources, from simulators to SDKs, augment its integration across Linux-based systems, accelerating project development timelines.
The Y180 is a streamlined microprocessor design, incorporating approximately 8K gates and serving primarily as a CPU clone of the Zilog Z180. It caters to applications requiring efficient, compact processing power without extensive resource demands. Its design is particularly apt for systems that benefit from Z80 architecture compatibility, ensuring effortless integration and functionality within a variety of technological landscapes.
The AndeShape Platforms are designed to streamline system development by providing a diverse suite of IP solutions for SoC architecture. These platforms encompass a variety of product categories, including the AE210P for microcontroller applications, AE300 and AE350 AXI fabric packages for scalable SoCs, and AE250 AHB platform IP. These solutions facilitate efficient system integration with Andes processors. Furthermore, AndeShape offers a sophisticated range of development platforms and debugging tools, such as ADP-XC7K160/410, which reinforce the system design and verification processes, providing a comprehensive environment for the innovative realization of IoT and other embedded applications.
The Avispado core is a 64-bit in-order RISC-V processor that provides an excellent balance of performance and power efficiency. With a focus on energy-conscious designs, Avispado facilitates the development of machine learning applications and is prime for environments with limited silicon resources. It leverages Semidynamics' innovative Gazzillion Misses™ technology to address challenges with sparse tensor weights, enhancing energy efficiency and operational performance for AI tasks. Structured to support multiprocessor configurations, Avispado is integral in systems requiring cache coherence and high memory throughput. It is particularly suitable for setups aimed at recommendation systems due to its ability to manage numerous outstanding memory requests, thanks to its advanced memory interface architectures. Integration with Semidynamics' Vector Unit enriches its offering, allowing dense computations and providing optimal performance in handling vector tasks. The ability to engage with Linux-ready environments and support for RISC-V Vector Specification 1.0 ensures that Avispado integrates seamlessly into existing frameworks, fostering innovative applications in fields like data centers and beyond.
The eSi-3264 is a cutting-edge 32/64-bit processor core that incorporates SIMD DSP extensions, making it suitable for applications requiring both efficient data parallelism and minimal silicon footprint. Designed for high-accuracy DSP tasks, this processor's multifunctional capabilities target audio processing, sensor hubs, and complex arithmetic operations. The eSi-3264 processor supports sizeable instruction and data caches, which significantly enhance system performance when accessing slower external memory sources. With dual and quad MAC operations that include 64-bit accumulation, it enhances DSP execution, applying 8, 16, and 32-bit SIMD instructions for real-time data handling and minimizing CPU load.
The GenAI v1-Q from RaiderChip brings forth a specialized focus on quantized AI operations, reducing memory requirements significantly while maintaining impressive precision and speed. This innovative accelerator is engineered to execute large language models in real-time, utilizing advanced quantization techniques such as Q4_K and Q5_K, thereby enhancing AI inference efficiency especially in memory-constrained environments. By offering a 276% boost in processing speed alongside a 75% reduction in memory footprint, GenAI v1-Q empowers developers to integrate advanced AI capabilities into smaller, less powerful devices without sacrificing operational quality. This makes it particularly advantageous for applications demanding swift response times and low latency, including real-time translation, autonomous navigation, and responsive customer interactions. The GenAI v1-Q diverges from conventional AI solutions by functioning independently, free from external network or cloud auxiliaries. Its design harmonizes superior computational performance with scalability, allowing seamless adaptation across variegated hardware platforms including FPGAs and ASIC implementations. This flexibility is crucial for tailoring performance parameters like model scale, inference velocity, and power consumption to meet exacting user specifications effectively. RaiderChip's GenAI v1-Q addresses crucial AI industry needs with its ability to manage multiple transformer-based models and confidential data securely on-premises. This opens doors for its application in sensitive areas such as defense, healthcare, and financial services, where confidentiality and rapid processing are paramount. With GenAI v1-Q, RaiderChip underscores its commitment to advancing AI solutions that are both environmentally sustainable and economically viable.
SCR1 is an open-source and silicon-proven microcontroller core, tailored for deeply embedded applications. This 32-bit RISC-V core supports the standard ISA with optional extensions for multiplication, division, and compressed instructions. The design comprises a simple in-order 4-stage pipeline, providing efficient interrupt handling with an IPIC unit. It connects seamlessly with various interfaces, including AXI4, AHB-Lite, and JTAG, enhancing its adaptability across different systems. The SCR1 core boasts a Tightly-Coupled Memory (TCM) subsystem supporting up to 64KB. It features up to 16 interrupt lines and a range of performance monitoring tools making it ideal for IoT, control systems, and smart card applications. Pre-configured software development tools, including IDEs like Eclipse and Visual Studio Code plugins, complement the core, enabling developers to quickly deploy applications tailored to SCR1’s architecture. Additionally, SCR1 comes packaged with a rich suite of documentation and pre-configured FPGA-based SDK, ensuring a smooth transition from development to implementation. Its GPL-compliant open-source license ensures flexibility for commercial and educational use, making it a versatile choice for a wide range of projects.
The SCR6 is a high-performance microcontroller core optimized for demanding embedded applications requiring substantial computational power. Its out-of-order 12-stage pipeline, complemented by a superscalar architecture, enhances processing speeds, making it ideal for real-time systems. Supporting a wide range of RISC-V ISA extensions, including cryptography and bit manipulation, SCR6 caters to secure and efficient data operations. The SCR6's memory subsystem is robust, featuring dual-level caches augmented with an L3 network-on-chip option. This rich memory architecture, along with efficient interrupt processing via APLIC units, ensures smooth high-speed data throughput in intensive applications. The core supports heterogeneous multicore configurations, enhancing parallel task execution. Designed for industrial and IoT environments, SCR6 comes with extensive development support. Its toolkit includes simulations, FPGA-based SDKs, and integration resources, facilitated through industry-standard interfaces, ensuring rapid development cycles and application deployment.
Designed for low-power applications, the eSi-1650 16-bit processor IP core includes an instruction cache, enhancing performance efficiency in systems using OTP or Flash for program memory. This core offers a low gate count, similar to many 8-bit cores, while the inclusion of a cache allows it to operate at higher speeds than standalone memory performance would normally allow. Its instruction set is robust, featuring a multitude of arithmetic and optional application-specific instructions, adaptations which facilitate lower power consumption and higher performance by allowing more immediate processing and reduced clock speeds.
The SCR4 core is a high-performance, area-efficient RISC-V processor with floating-point computation capabilities. Targeting mobile and industrial applications, it supports both single and double precision, adhering to IEEE 754-2008 standards. Its instruction set is complete with advanced extensions, including atomic and cryptography functions for secure and efficient operations. With a powerful 5-stage in-order pipeline and a dedicated FPU, the SCR4 can handle complex mathematical tasks swiftly. Its memory architecture features both L1 and L2 caches, alongside a TCM unit, enabling rapid data access and management essential in real-time environments. Incorporating a robust branch prediction unit and support for multicore setups, the SCR4 excels in environments demanding synchronized computing tasks across multiple processors. It’s supported by comprehensive development kits and detailed documentation to expedite the design and implementation processes across diverse platforms.
SiFive Essential family offers a highly customizable set of processor IPs suitable for a range of applications, from embedded microcontrollers to full-fledged Linux-capable designs. This family presents the flexibility to tailor power, area, and performance metrics according to specific market needs, ensuring that designers can optimize their solutions for diverse applications. The Essential lineup is structured to allow easy adaptability, featuring scalable microarchitectures that cater to every stage of product development. From lightweight, power-efficient processors optimized for IoT devices to more robust configurations designed for real-time control and processing, SiFive Essential processors cover a broad spectrum of use cases. Key features include advanced trace and debug capabilities and an open, scalable platform enhancing the overall security of SoC designs. With its comprehensive customization options, the Essential family is perfect for designers who need to strike a balance between performance and power efficiency. This versatility positions the SiFive Essential series as a cornerstone in providing quality RISC-V solutions, allowing for innovation without compromise on customizability and scalability.
The Spiking Neural Processor T1 is an innovative ultra-low power microcontroller designed for always-on sensing applications, bringing intelligence directly to the sensor edge. This processor utilizes the processing power of spiking neural networks, combined with a nimble RISC-V processor core, to form a singular chip solution. Its design supports next-generation AI and signal processing capabilities, all while operating within a very narrow power envelope, crucial for battery-powered and latency-sensitive devices. This microcontroller's architecture supports advanced on-chip signal processing capabilities that include both Spiking Neural Networks (SNNs) and Deep Neural Networks (DNNs). These processing capabilities enable rapid pattern recognition and data processing similar to how the human brain functions. Notably, it operates efficiently under sub-milliwatt power consumption and offers fast response times, making it an ideal choice for devices such as wearables and other portable electronics that require continuous operation without significant energy draw. The T1 is also equipped with diverse interface options, such as QSPI, I2C, UART, JTAG, GPIO, and a front-end ADC, contained within a compact 2.16mm x 3mm, 35-pin WLCSP package. The device boosts applications by enabling them to execute with incredible efficiency and minimal power, allowing for direct connection and interaction with multiple sensor types, including audio and image sensors, radar, and inertial units for comprehensive data analysis and interaction.
The C100 from Chipchain is a highly integrated, low-power consumption single-chip solution tailored for IoT applications. Featuring an advanced 32-bit RISC-V CPU capable of operating at speeds up to 1.5GHz, it houses embedded RAM and ROM for efficient processing and computational tasks. This chip's core strength lies in its multifunctional nature, integrating Wi-Fi, various transmission interfaces, an ADC, LDO, and temperature sensors, facilitating a streamlined and rapid application development process. The C100 chip is engineered to support a diverse set of applications, focusing heavily on expanding IoT capabilities with enhanced control and connectivity features. Beyond its technical prowess, the C100 stands out with its high-performance wireless microcontrollers, designed specifically for the burgeoning IoT market. By leveraging various embedded technologies, the C100 enables simplified, fast, and adaptive application deployment across a wide array of sectors including security, healthcare, smart home devices, and digital entertainment. The chip’s integrated features ensure it can meet the rigorous demands of modern IoT applications, characterized by high integration and reliability. Moreover, the C100 represents a leap forward in IoT product development with its extensive focus on energy efficiency, compact size, and secure operations. Providing a complete IoT solution, this chip is instrumental in advancing robust IoT ecosystems, driving innovation in smart connectivity. Its comprehensive integration provides IoT developers with a significant advantage, allowing them to develop solutions that are not only high-performing but also ensure sustainability and user safety.
The M8051EW expands upon the M8051W's impressive performance by incorporating on-chip debugging capabilities. This microcontroller core offers not only rapid execution but also integrates a JTAG debug port for compatibility with external debugging tools. Additionally, this core is designed with hardware breakpoints and instruction tracebacks, providing full read and write access across all register and memory locations. Such capabilities, together with its fast execution cycle, make it an ideal choice for designs requiring advanced debugging and real-time control.
The Azurite Core-hub by InCore Semiconductors is a sophisticated solution designed to offer scalable RISC-V SoCs with high-speed secure interconnect capabilities. This processor is tailored for performance-demanding applications, ensuring that systems maintain robust security while executing tasks at high speeds. Azurite leverages advanced interconnect technologies to enhance the communication between components within a SoC, making it ideal for industries that require rapid data transfer and high processing capabilities. The core is engineered to be scalable, supporting a wide range of applications from edge AI to functional safety systems, adapting seamlessly to various industry needs. Engineered with a focus on security, the Azurite Core-hub incorporates features that protect data integrity and system operation in a dynamic technological landscape. This makes it a reliable choice for companies seeking to integrate advanced RISC-V architectures into their security-focused applications, offering not just innovation but also peace of mind with its secure design.
The Rabbit 4000 microprocessor represents a significant escalation in processing capabilities, boasting an impressive 161K gate design and 128-pin configuration. Developed to cater to demanding digital environments, this processor delivers advanced performance alongside flexible deployment options. It is particularly tailored for use in complex systems requiring both potent processing power and diverse interface options, while still adhering to industry standards for adaptability and integration.
The Nerve IIoT Platform by TTTech Industrial is engineered to bridge the gap between real-time data and IT functionalities in industrial environments. This platform allows machine builders and operators to effectively manage edge computing needs with a cloud-managed approach, ensuring safe and flexible deployment of applications and data handling. At its core, Nerve is designed to deliver real-time data processing capabilities that enhance operational efficiency. This platform is distinguished by its integration with off-the-shelf hardware, providing scalability from gateways to industrial PCs. Its architecture supports virtual machines and network protocols such as CODESYS and Docker, thereby enabling a diverse range of functionalities. Nerve’s modular system allows users to license features as needed, optimizing both edge and cloud operations. Additionally, Nerve delivers substantial business benefits by increasing machine performance and generating new digital revenue streams. It supports remote management and updates, reducing service costs and downtime, while improving cybersecurity through standards compliant measures. Enterprises can use Nerve to connect multiple machines globally, facilitating seamless integration into existing infrastructures and expanding digital capabilities. Overall, Nerve positions itself as a formidable IIoT solution that combines technical sophistication with practical business applications, merging the physical and digital worlds for smarter industry operations.
The SCR3 core by Syntacore is a silicon-proven microcontroller aimed at applications requiring both high performance and power efficiency. This 32/64-bit processor core supports a variety of RISC-V standard extensions, including atomic operations and bit manipulation, optimizing it for real-time applications needing reliable interrupt handling through its PLIC, ACLINT, and IPIC units. It features a 5-stage in-order pipeline paired with branch prediction and cache systems to enhance speed and execution efficiency. With considerable support for seamless memory operations, it includes both L1 and L2 caches and a TCM unit capable of housing up to 256KB of data, alongside an integrated Memory Protection Unit for executing multiple privilege modes. Ideal for industrial automation and IoT usage, the SCR3 core facilitates multicore operations with cache coherency for up to 4 simultaneous cores. Extensive development tools are provided, including simulators, IDE support, and a comprehensive FPGA-based SDK, allowing for immediate application development and deployment.
The NeuroSense AI Chip is a remarkable innovation for wearable technology, designed to address the key pain points of power consumption and data privacy in mass-market devices. It significantly enhances the accuracy of heart rate measurements and human activity recognition, operating independently of the cloud. The chip processes data at the sensor level, which not only increases precision but also extends battery life, a crucial factor for fitness trackers, smartwatches, and health monitoring devices. With unparalleled power efficiency, the NeuroSense chip maintains high accuracy by implementing analog computation and neural network strategies, translating to more effective biometrics extraction. NeuroSense excels in reducing the typical power burdens of AI-capable wearables. The diminutive size allows for easy integration into small devices without compromising functionality. By bypassing the need for cloud data processing, it ensures faster response times and greater privacy for users. Its capacity to learn from and accurately classify human activity transcends simple monitoring, offering potential expansions into fields like exercise coaching and senior care. Additionally, the NeuroSense chip allows for extended device operation times, which conventional sensor units struggle to deliver. It supports a broader range of applications by making wearables more intelligent and adaptive to various user needs. This positions the NeuroSense as a leading choice for developers seeking to enhance product features while minimizing cost and energy demands.
The RISC-V CPU IP N Class from Nuclei System Technology offers a versatile 32-bit architecture designed for microcontroller units (MCUs) and AIoT applications. Engineered with the RISC-V open standard, this processor IP provides extensive configurability options, allowing users to tailor the IP to meet their specific system requirements. It supports a variety of security features and functional safety protocols, making it suitable for applications demanding reliable and robust performance. This CPU IP is perfect for those implementing advanced RISC-V technology in fields that require agility and cutting-edge functionality. Its ease of customization ensures seamless integration into existing systems, supporting an array of ecosystem resources such as tool-chains, SDKs, and support for operating systems including RTOS and Linux. With a local R&D team backing its development, the N Class IP sees rapid iteration and enhancement, aligning with the technological demands and trends in high-performance computing. This positions it as a leading choice for firms looking to adopt RISC-V technology in innovative and emergent applications.
Syntacore's SCR5 is an efficient application-class processor core, crafted to deliver exceptional performance with Linux compatibility. It integrates a 9-stage in-order pipeline along with floating-point capabilities, making it suitable for diverse processing tasks. Adopting the latest RISC-V ISA extensions, SCR5 ensures high-speed computations and secure operations equipped with bit manipulation and cryptography features. The SCR5’s robust memory subsystem ensures data integrity and rapid access, featuring L1 and L2 caches, a TCM, and an MMU. High-performance multicore support extends up to four cores, promoting parallel processing capabilities necessary in industrial and IoT environments. Its interface support, including JTAG and AXI4, streamlines integration into varied infrastructures. For developers, the SCR5 core is accompanied by advanced toolkits designed to accelerate application deployment. These include pre-built OS options and native toolchains, all backed by thorough documentation to enhance the development lifecycle.
The RV32EC_P2 Processor Core is a compact, high-efficiency RISC-V processor designed for low-power, small-scale embedded applications. Featuring a 2-stage pipeline architecture, it efficiently executes trusted firmware. It supports the RISC-V RV32E base instruction set, complemented by compression and optional integer multiplication instructions, greatly optimizing code size and runtime efficiency. This processor accommodates both ASIC and FPGA workflows, offering tightly-coupled memory interfaces for robust design flexibility. With a simple machine-mode architecture, the RV32EC_P2 ensures swift data access. It boasts extended compatibility with AHB-Lite and APB interfaces, allowing seamless interaction with memory and I/O peripherals. Designed for enhanced power management, it features an interrupt system and clock-gating abilities, effectively minimizing idle power consumption. Developers can benefit from its comprehensive toolchain support, ensuring smooth firmware and virtual prototype development through platforms such as the ASTC VLAB. Further distinguished by its vectored interrupt system and support for application-specific instruction sets, the RV32EC_P2 is adaptable to various embedded applications. Enhancements include wait-for-interrupt commands for reduced power usage during inactivity and multiple timer interfaces. This versatility, along with integrated GNU and Eclipse tools, makes the RV32EC_P2 a prime choice for efficient, low-power technology integrations.
The Y51 processor utilizes the 8051 Instruction Set Architecture, operating with a 2-clock machine cycle for streamlined execution. This design is optimized for tasks that require swift, efficient instruction handling while maintaining architectural simplicity. The balanced configuration facilitates rapid processing, making it suitably versatile for various embedded systems that benefit from the established 8051 architecture.
The Rabbit 2000 microprocessor is a compact yet powerful design consisting of 19K gates and supports 100 pins. Tailored for seamless integration across various technologies, this microprocessor offers platform independence that ensures high adaptability in design implementation. It exemplifies a balanced architecture, achieving efficient performance while maintaining modest resource usage, making it ideal for a range of applications requiring robust control and processing capabilities.
An evolution of the Y180, the Y180S offers a safe-state version of its predecessor, encompassing approximately 10K gates. This enhanced version is tailored for applications where safety and state retention are critical, maintaining all the beneficial features of the Y180 while incorporating additional safety mechanisms. Its architecture remains compatible with Z80 instruction sets, ensuring consistent integration across platforms necessitating reliable and secure processing.
The Y8002 microprocessor is a replication of a known Zilog device, with a gate count of approximately 15K. Designed to offer consistent performance aligned with Zilog's benchmarks, it supports projects requiring both reliability and compatibility with Zilog's infrastructure. Its gate efficiency and operational familiarity make it an optimal choice for tasks needing precision alongside established interface standards.
Built with a focus on versatility and resource efficiency, the Rabbit 3000 microprocessor expands on its predecessor with a gate count of 31K and 128 pins. This design accommodates more complex applications and demands, offering greater processing power while sustaining high levels of flexibility and integration. Ideal for sophisticated systems, the Rabbit 3000 balances enhanced computational capabilities with effective resource distribution while ensuring seamless functionality across various platforms.
At the pinnacle of the Rabbit microprocessor line is the Rabbit 6000, featuring an expansive 760K gate architecture paired with a 292-pin configuration. Designed for cutting-edge technology demands, this processor excels in environments that require maximum performance, reliability, and integration. Whether for ambitious digital projects or high-performance computing solutions, the Rabbit 6000 offers unparalleled processing power and design flexibility, assuring adaptability across multiple platforms and systems.
iCEVision facilitates rapid prototyping and evaluation of connectivity features using the Lattice iCE40 UltraPlus FPGA. Designers can take advantage of exposed I/Os for quick implementation and validation of solutions, while enjoying compatibility with common camera interfaces such as ArduCam CSI and PMOD. This flexibility is complemented by software tools such as the Lattice Diamond Programmer and iCEcube2, which allow designers to reprogram the onboard SPI Flash and develop custom solutions. The platform comes preloaded with a bootloader and an RGB demo application, making it quick and easy for users to begin experimenting with their projects. Its design includes features like a 50mmx50mm form factor, LED applications, and multiple connectivity options, ensuring broad usability across various rapid prototyping scenarios. With its user-friendly setup and comprehensive toolkit, iCEVision is perfect for developers who need a streamlined path from initial design to functional prototype, especially in environments where connectivity and sensor integration are key.
The Neuropixels Probe is a groundbreaking neural recording device that has transformed the study of brain activity. It features an array of closely spaced electrodes on a thin probe, capable of simultaneously recording the electrical activity from hundreds of neurons. This fine-scale recording capability enables neuroscientists to map complex neural circuits and delve deeper into understanding cognitive processes, neural disorders, and sensory functions. Its applications extend to both basic and clinical research, providing insights that are crucial for the development of new treatments and therapies for neurological conditions.
The Rabbit 5000 takes processing efficiency to new heights with its extensive 540K gate count and substantial 289 pin configuration. Engineered for high-end, complex applications, this processor excels in systems demanding advanced computational power and high data throughput. Its expansive architecture accommodates intricate processing requirements while ensuring robust compatibility across a plethora of platforms, making it a formidable choice for expansive and demanding digital ecosystems.
The NPU (Neural Processing Unit) by OPENEDGES is a specialized processor designed to accelerate machine learning and AI workloads. This unit is engineered to deliver high performance in processing neural network computations, ensuring rapid data processing which is essential in AI applications. Combining the latest advancements in semiconductor technology, this NPU optimizes both speed and efficiency in data-centric tasks, making it an indispensable component for AI-driven systems. What distinguishes the OPENEDGES' NPU is its capacity to handle a wide array of AI models, offering flexibility and adaptability to various AI frameworks and environments. This allows developers to implement and model complex neural networks with reduced latency and increased throughput, crucial factors in sectors like autonomous driving, smart devices, and edge computing. Moreover, the NPU's architecture emphasizes power efficiency without sacrificing computing power, enabling its integration into battery-operated and energy-sensitive environments. This efficacy in managing power and performance makes the NPU suitable for both edge and cloud-based AI applications, serving as a key player in the evolution of intelligent technology infrastructures. Overall, it positions OPENEDGES as a frontrunner in the field of AI processing.
The RV32IC_P5 Processor Core from IQonIC Works is designed for medium-scale embedded applications requiring higher performance and enhanced processing capabilities. This 5-stage pipeline processor supports the RISC-V RV32I base instruction set, alongside standard extension instructions such as 'A' for atomic operations, boosting system efficiency. Its ability to run a mix of trusted firmware and user applications allows for diverse operational integration. Supporting both ASIC and FPGA design flows, the RV32IC_P5 incorporates advanced memory interfaces, offering optional instruction and write-back data caches for improved performance and adaptability. It features a tightly-coupled scratchpad memory architecture, ensuring efficient data handling and reduced latency. The processor's architecture also incorporates AHB-Lite interfaces and optional physical memory protections for robust security management. With a vectored interrupt system and support for platform-specific instruction extensions, the RV32IC_P5 provides tailored options for DSP operations. Its toolchain support includes GNU and Eclipse environments, affording developers a streamlined path from concept to execution. The RV32IC_P5 demonstrates a firm focus on power efficiency and enhanced processing capabilities, making it ideal for complex applications demanding reliable processing power and flexibility.
The ULYSS MCU is tailored for the demanding requirements of the automotive sector. Built upon a 32/64-bit RISC-V architecture, this microcontroller facilitates high-performance applications ranging from 120MHz up to 2GHz. It combines cost-effectiveness with cutting-edge automotive features, making it an ideal choice for modern vehicles that require robust computing capabilities. This microcontroller is engineered to support a wide array of automotive applications, providing the power and reliability needed for complex automotive systems. From advanced driver assistance systems (ADAS) to autonomous driving technologies, the ULYSS MCU ensures that automotive electronics can meet both current and future needs with minimal adjustments. By incorporating sophisticated RISC-V technology, the ULYSS MCU stands out in the competitive landscape as a powerful and flexible solution. It reflects Cortus's dedication to innovation and excellence in semiconductor design, positioning itself as a key player in the evolution of the automotive electronics industry.
The RISC-V CPU IP NX Class offers a robust 64-bit architecture tailored for storage solutions, augmented reality/virtual reality (AR/VR), and artificial intelligence (AI) applications. This offering from Nuclei System Technology exemplifies scalability and flexibility, adhering to the RISC-V open standard to deliver a processor IP that is both versatile and high performing. This class of IP ensures that businesses can integrate sophisticated computational capabilities into their products, enhancing functionality in storage and emerging technology fields. The NX Class supports a wide array of security and functional safety features, ensuring reliable performance across various high-tech scenarios. With continued advancements and support from the local R&D team, the NX Class is equipped to meet the evolving demands of cutting-edge technology sectors, facilitating innovation and superior performance in complex environments where these attributes are crucial.
The 32-bit RISC CPU Core from VinChip Systems is designed to deliver enhanced processing power suitable for embedded system applications. This CPU core is ideal for resource-constrained environments where energy efficiency and performance are critical. It adopts a Reduced Instruction Set Computing (RISC) architecture, streamlined to execute simpler instruction sets with more efficiency, thereby enabling faster performance and lower power consumption. This architecture is particularly advantageous for applications needing quick response times without compromising on power usage. With capability to be integrated across various platforms, the VinChip RISC core provides versatility for manufacturers building systems across different sectors, including communications, computing, and consumer electronics. This CPU core is supplemented by comprehensive software stacks to aid in application development and deployment.
SkyeChip's Low Power RISC-V CPU is a highly efficient processor core designed for low power and embedded applications. It implements the RISC-V RV32 instruction set with full support for integer and compressed instructions, and partial support for multiplication, aligning with modern computing needs. This processor is engineered for high reliability with 32 vectorized interrupts and adheres to standard RISC-V debugging protocols. It is tailored for use in resource-constrained environments where power efficiency and performance are key, lending itself to a wide array of applications from IoT devices to mobile computing.
The RISC-V CPU IP NS Class, by Nuclei System Technology, is designed to focus on security-centric applications. It is ideal for fintech payments, IoT security, and other sectors where information security is of utmost importance. Built with a RISC-V foundation, this IP emphasizes modularity, allowing specialized configurations to meet specific security standards and requirements. With functionality geared towards comprehensive information security solutions, the NS Class provides support for Trusted Execution Environments (TEE) and additional physical security packages. It is tailored to satisfy stringent safety regulations, making it an apt choice for addressing vulnerabilities in high-stakes technological settings. This IP stands out due to its support for cutting-edge security protocols and adherence to top-tier safety standards such as ASIL-B and ASIL-D functional safety packages. Partners utilizing the NS Class can expect highly reliable, secure, and compliant solutions that maintain integrity and confidentiality across various application domains.
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