All IPs > Processor > Microcontroller
Microcontrollers form the backbone of many modern electronic devices, offering precise control and processing capabilities that power everything from consumer electronics to industrial machines. In the world of semiconductor IPs, microcontrollers provide the essential building blocks that allow developers to design complex functionalities tailored to specific applications. This category is vital for those looking to integrate processing and control functionalities directly into their embedded systems, providing efficiencies in both performance and energy use.
Microcontrollers available as semiconductor IPs are used in a broad spectrum of applications, from automotive and aerospace to smart home devices and IoT gadgets. By selecting a microcontroller IP, developers can customize core functions such as CPU architecture, memory management, input/output controls, and specialized peripherals to meet the specific needs of their projects. These IPs are designed to streamline the development process, reduce time-to-market, and offer flexibility in the design and scalability of end products.
One of the key advantages of utilizing microcontroller semiconductor IPs is the ability to incorporate proprietary or emerging technologies seamlessly into existing systems. This not only helps in keeping the product line up-to-date with the latest technology trends but also ensures that the devices remain competitive in the rapidly evolving electronics marketplace. Moreover, integrating microcontroller IPs can lead to cost savings by minimizing the need for additional chips and lowering power consumption through optimized architectures and process technologies.
As you explore the Processor > Microcontroller category in our Silicon Hub, you'll discover a wealth of options that cater to various industry needs, ranging from low-power designs suitable for portable devices to high-performance solutions required for complex computing tasks. Whether you are designing a simple control unit or a sophisticated embedded application, microcontroller semiconductor IPs provide the versatility and functionality necessary to drive innovation.
The Yitian 710 Processor is an advanced Arm-based server chip developed by T-Head, designed to meet the extensive demands of modern data centers and enterprise applications. This processor boasts 128 high-performance Armv9 CPU cores, each coupled with robust caches, ensuring superior processing speeds and efficiency. With a 2.5D packaging technology, the Yitian 710 integrates multiple dies into a single unit, facilitating enhanced computational capability and energy efficiency. One of the key features of the Yitian 710 is its memory subsystem, which supports up to 8 channels of DDR5 memory, achieving a peak bandwidth of 281 GB/s. This configuration guarantees rapid data access and processing, crucial for high-throughput computing environments. Additionally, the processor is equipped with 96 PCIe 5.0 lanes, offering a dual-direction bandwidth of 768 GB/s, enabling seamless connectivity with peripheral devices and boosting system performance overall. The Yitian 710 Processor is meticulously crafted for applications in cloud services, big data analytics, and AI inference, providing organizations with a robust platform for their computing needs. By combining high core count, extensive memory support, and advanced I/O capabilities, the Yitian 710 stands as a cornerstone for deploying powerful, scalable, and energy-efficient data processing solutions.
The NMP-750 is a high-performance accelerator designed for edge computing, particularly suited for automotive, AR/VR, and telecommunications sectors. It boasts an impressive capacity of up to 16 TOPS and 16 MB local memory, powered by a RISC-V or Arm Cortex-R/A 32-bit CPU. The three AXI4 interfaces ensure seamless data transfer and processing. This advanced accelerator supports multifaceted applications such as mobility control, building automation, and multi-camera processing. It's designed to cope with the rigorous demands of modern digital and autonomous systems, offering substantial processing power and efficiency for intensive computational tasks. The NMP-750's ability to integrate into smart systems and manage spectral efficiency makes it crucial for communications and smart infrastructure management. It helps streamline operations, maintain effective energy management, and facilitate sophisticated AI-driven automation, ensuring that even the most complex data flows are handled efficiently.
RaiderChip's GenAI v1 is a pioneering hardware-based generative AI accelerator, designed to perform local inference at the Edge. This technology integrates optimally with on-premises servers and embedded devices, offering substantial benefits in privacy, performance, and energy efficiency over traditional hybrid AI solutions. The design of the GenAI v1 NPU streamlines the process of executing large language models by embedding them directly onto the hardware, eliminating the need for external components like CPUs or internet connections. With its ability to support complex models such as the Llama 3.2 with 4-bit quantization on LPDDR4 memory, the GenAI v1 achieves unprecedented efficiency in AI token processing, coupled with energy savings and reduced latency. What sets GenAI v1 apart is its scalability and cost-effectiveness, significantly outperforming competitive solutions such as Intel Gaudi 2, Nvidia's cloud GPUs, and Google's cloud TPUs in terms of memory efficiency. This solution maximizes the number of tokens generated per unit of memory bandwidth, thus addressing one of the primary limitations in generative AI workflow. Furthermore, the adept memory usage of GenAI v1 reduces the dependency on costly memory types like HBM, opening the door to more affordable alternatives without diminishing processing capabilities. With a target-agnostic approach, RaiderChip ensures the GenAI v1 can be adapted to various FPGAs and ASICs, offering configuration flexibility that allows users to balance performance with hardware costs. Its compatibility with a wide range of transformers-based models, including proprietary modifications, ensures GenAI v1's robust placement across sectors requiring high-speed processing, like finance, medical diagnostics, and autonomous systems. RaiderChip's innovation with GenAI v1 focuses on supporting both vanilla and quantized AI models, ensuring high computation speeds necessary for real-time applications without compromising accuracy. This capability underpins their strategic vision of enabling versatile and sustainable AI solutions across industries. By prioritizing integration ease and operational independence, RaiderChip provides a tangible edge in applying generative AI effectively and widely.
The A25 processor model is a versatile CPU suitable for a variety of embedded applications. With its 5-stage pipeline and 32/64-bit architecture, it delivers high performance even with a low gate count, which translates to efficiency in power-sensitive environments. The A25 is equipped with Andes Custom Extensions that enable tailored instruction sets for specific application accelerations. Supporting robust high-frequency operations, this model shines in its ability to manage data prefetching and cache coherence in multicore setups, making it adept at handling complex processing tasks within constrained spaces.
The Chimera GPNPU from Quadric is designed as a general-purpose neural processing unit intended to meet a broad range of demands in machine learning inference applications. It is engineered to perform both matrix and vector operations along with scalar code within a single execution pipeline, which offers significant flexibility and efficiency across various computational tasks. This product achieves up to 864 Tera Operations per Second (TOPs), making it suitable for intensive applications including automotive safety systems. Notably, the GPNPU simplifies system-on-chip (SoC) hardware integration by consolidating hardware functions into one processor core. This unification reduces complexity in system design tasks, enhances memory usage profiling, and optimizes power consumption when compared to systems involving multiple heterogeneous cores such as NPUs and DSPs. Additionally, its single-core setup enables developers to efficiently compile and execute diverse workloads, improving performance tuning and reducing development time. The architecture of the Chimera GPNPU supports state-of-the-art models with its Forward Programming Interface that facilitates easy adaptation to changes, allowing support for new network models and neural network operators. It’s an ideal solution for products requiring a mix of traditional digital signal processing and AI inference like radar and lidar signal processing, showcasing a rare blend of programming simplicity and long-term flexibility. This capability future-proofs devices, expanding their lifespan significantly in a rapidly evolving tech landscape.
Designed for entry-level server-class applications, the SCR9 is a 64-bit RISC-V processor core that comes equipped with cutting-edge features, such as an out-of-order superscalar pipeline, making it apt for processing-intensive environments. It supports both single and double-precision floating-point operations adhering to IEEE standards, which ensure precise computation results. This processor core is tailored for high-performance computing needs, with a focus on AI and ML, as well as conventional data processing tasks. It integrates an advanced interrupt system featuring APLIC configurations, enabling responsive operations even under heavy workloads. SCR9 supports up to 16 cores in a multi-cluster arrangement, each utilizing coherent multi-level caches to maintain rapid data processing and management. The comprehensive development package for SCR9 includes ready-to-deploy toolchains and simulators that expedite software development, particularly within Linux environments. The core is well-suited for deployment in entry-level server markets and data-intensive applications, with robust support for virtualization and heterogeneous architectures.
The RV12 RISC-V Processor from Roa Logic is a highly versatile CPU designed for embedded applications. It complies with the RV32I and RV64I specifications of the RISC-V instruction set, supporting single-core configurations. The RV12 processor is renowned for its configurability, allowing it to be tailored to specific application requirements. It implements a Harvard architecture, which enables concurrent access to both instruction and data memory, optimizing performance and efficiency. Roa Logic's RV12 processor is part of their broader portfolio of 32/64-bit CPU solutions that leverage the open-source RISC-V instruction set. This architecture is favored for its simplicity and scalability, making it ideal for various embedded systems. The processor is equipped with an optimizing feature set that enhances its processing capabilities, ensuring it meets the rigorous demands of modern applications. Incorporating the RV12 processor into projects is streamlined thanks to its comprehensive support documentation and available test benches. These resources facilitate smooth integration into larger systems, providing developers with a reliable foundation for building advanced embedded systems. Its design is a testament to Roa Logic's commitment to delivering high-performance, adaptable IP solutions to the semiconductor industry.
The NMP-350 is a cutting-edge endpoint accelerator designed to optimize power usage and reduce costs. It is ideal for markets like automotive, AIoT/sensors, and smart appliances. Its applications span from driver authentication and predictive maintenance to health monitoring. With a capacity of up to 1 TOPS and 1 MB of local memory, it incorporates a RISC-V/Arm Cortex-M 32-bit CPU and supports three AXI4 interfaces. This makes the NMP-350 a versatile component for various industrial applications, ensuring efficient performance and integration. Developed as a low-power solution, the NMP-350 is pivotal for applications requiring efficient processing power without inflating energy consumption. It is crucial for mobile and battery-operated devices where every watt conserved adds to the operational longevity of the product. This product aligns with modern demands for eco-friendly and cost-effective technologies, supporting enhanced performance in compact electronic devices. Technical specifications further define its role in the industry, exemplifying how it brings robust and scalable solutions to its users. Its adaptability across different applications, coupled with its cost-efficiency, makes it an indispensable tool for developers working on next-gen AI solutions. The NMP-350 is instrumental for developers looking to seamlessly incorporate AI capabilities into their designs without compromising on economy or efficiency.
The eSi-3250 stands as a high-performance 32-bit RISC IP processor, optimized for implementations within ASIC or FPGA environments that demand rigorous caching strategies due to slower internal or external memories. Noteworthy for its adaptable instruction and data cache capabilities, this core is tailored to excel in scenarios where the CPU core to bus clock ratio exceeds singularity. The eSi-3250 integrates dual separate caches for both data and instructions, enabling configuration in various associativity forms optimizing for elevated performance while maintaining power efficiency. It includes a specialized optional memory management unit, vital for memory protection and the deployment of virtual memory, accommodating sophisticated system requirements. Incorporating an expansive instruction set, the processor is equipped for intensive computational tasks with a multitude of optional additional instruction types and addressing modes. Additional requisite supporting hardware includes incorporated debug features conducive to efficient system analysis and troubleshooting, solidifying the eSi-3250's position as a favored choice for high-throughput, low-power applications across a spectrum of technology processes.
The NMP-550 is tailored for enhanced performance efficiency, serving sectors like automotive, mobile, AR/VR, drones, and robotics. It supports applications such as driver monitoring, image/video analytics, and security surveillance. With a capacity of up to 6 TOPS and 6 MB local memory, this accelerator leverages either a RISC-V or Arm Cortex-M/A 32-bit CPU. Its three AXI4 interface support ensures robust interconnections and data flow. This performance boost makes the NMP-550 exceptionally suited for devices requiring high-frequency AI computations. Typical use cases include industrial surveillance and smart robotics, where precise and fast data analysis is critical. The NMP-550 offers a blend of high computational power and energy efficiency, facilitating complex AI tasks like video super-resolution and fleet management. Its architecture supports modern digital ecosystems, paving the way for new digital experiences through reliable and efficient data processing capabilities. By addressing the needs of modern AI workloads, the NMP-550 stands as a significant upgrade for those needing robust processing power in compact form factors.
The eSi-1600 is a compact, low-power, and cost-effective processor core specifically engineered for integration into both ASIC and FPGA designs. It delivers performance comparable to costlier 32-bit processors while maintaining an affordability akin to 8-bit options, making it suited for control tasks within mature mixed-signal environments requiring less than 64kB memory. Despite its 16-bit design, it achieves notable power savings by executing applications in fewer clock cycles, reducing the need for high-frequency operations and enabling faster power-down states. Boasting a versatile instruction set, the eSi-1600 encompasses both general-purpose and optional custom functions, enhancing flexibility for specialized computations. Innovative architectural features like a 5-stage pipeline facilitate high clock speeds even in older technologies. This processor supports intricate arithmetic operations including multiply-accumulate and division, along with diverse bit manipulation instructions beneficial for efficient data handling and algorithm execution. Moreover, its capacity to intermingle 16 and 32-bit instructions increases code density, optimizing both performance and power efficiency. The eSi-1600 supports various operating modes and privileges via an optional memory protection unit, providing secure execution for multiple applications. Comprehensive debugging support assists in effective program diagnosis and optimization. This processor core is thoroughly validated across technological processes and included as a Verilog RTL IP core, illustrating its adaptability, reliability, and readiness for broad deployment.
xcore.ai is a powerful platform tailored for the intelligent IoT market, offering unmatched flexibility and performance. It boasts a unique multi-threaded micro-architecture that provides low-latency and deterministic performance, perfect for smart applications. Each xcore.ai contains 16 logical cores distributed across two multi-threaded processor tiles, each equipped with 512kB of SRAM and capable of both integer and floating-point operations. The integrated interprocessor communication allows high-speed data exchange, ensuring ultimate scalability across multiple xcore.ai SoCs within a unified development environment.
SCR1 is an open-source and silicon-proven microcontroller core, tailored for deeply embedded applications. This 32-bit RISC-V core supports the standard ISA with optional extensions for multiplication, division, and compressed instructions. The design comprises a simple in-order 4-stage pipeline, providing efficient interrupt handling with an IPIC unit. It connects seamlessly with various interfaces, including AXI4, AHB-Lite, and JTAG, enhancing its adaptability across different systems. The SCR1 core boasts a Tightly-Coupled Memory (TCM) subsystem supporting up to 64KB. It features up to 16 interrupt lines and a range of performance monitoring tools making it ideal for IoT, control systems, and smart card applications. Pre-configured software development tools, including IDEs like Eclipse and Visual Studio Code plugins, complement the core, enabling developers to quickly deploy applications tailored to SCR1’s architecture. Additionally, SCR1 comes packaged with a rich suite of documentation and pre-configured FPGA-based SDK, ensuring a smooth transition from development to implementation. Its GPL-compliant open-source license ensures flexibility for commercial and educational use, making it a versatile choice for a wide range of projects.
The Y180 is a compact CPU-only design, serving as a clone of the Zilog Z180 CPU, and involves approximately 8K gates. It caters to applications that require compatibility with the Zilog architecture and prefer a minimalistic yet effective microprocessor implementation.
The eSi-3200 represents the mid-tier solution in the eSi-RISC family, bringing a high degree of versatility and performance to embedded control systems. This 32-bit processor is proficiently designed for scenarios demanding enhanced computational capabilities or extended address spaces without compromise on power efficiency, suitably fitting applications with on-chip memory implementations. Engineered without a cache, the eSi-3200 facilitates deterministic performance essential for real-time applications. It leverages a modified-Harvard architecture allowing concurrent instruction and data fetches, maximizing throughput. With a 5-stage pipeline, the processor achieves high clock frequencies suitable for time-critical operations enhancing responsiveness and efficiency. The comprehensive instruction set encompasses core arithmetic functions, including advanced IEEE-754 single-precision floating-point operations, which cater to data-intensive and mathematically challenging applications. Designed with optimal flexibility, it can accommodate optional custom instructions tailored to specific processing needs, offering a well-balanced solution for versatile embedded applications. Delivered as a Verilog RTL IP core, it ensures platform compatibility, simplifying integration into diverse silicon nodes.
The Nerve IIoT Platform is a comprehensive solution for machine builders, offering cloud-managed edge computing capabilities. This innovative platform delivers high levels of openness, security, flexibility, and real-time data handling, enabling businesses to embark on their digital transformation journeys. Nerve's architecture allows for seamless integration with a variety of hardware devices, from basic gateways to advanced IPCs, ensuring scalability and operational efficiency across different industrial settings. Nerve facilitates the collection, processing, and analysis of machine data in real-time, which is crucial for optimizing production and enhancing operational efficiency. By providing robust remote management functionalities, businesses can efficiently handle device operations and application deployments from any location. This capacity to manage data flows between the factory floor and the cloud transitions enterprises into a new era of digital management, thereby minimizing costs and maximizing productivity. The platform also supports multiple cloud environments, empowering businesses to select their preferred cloud service while maintaining operational continuity. With its secure, IEC 62443-4-1 certified infrastructure, Nerve ensures that both data and applications remain protected from cyber threats. Its integration of open technologies, such as Docker and virtual machines, further facilitates rapid implementation and prototyping, enabling businesses to adapt swiftly to ever-changing demands.
The RISC-V CPU IP N Class is designed to cater to the needs of 32-bit microcontroller units (MCUs) and AIoT (Artificial Intelligence of Things) applications. It is engineered to provide a balance of performance and power efficiency, making it suitable for a range of general computing needs. With its adaptable architecture, the N Class processor allows for customization, enabling developers to configure the core to meet specific application requirements while minimizing unnecessary overhead. Incorporating the RISC-V open standard, the N Class delivers robust functional features, supporting both security and functional safety needs. This processor core is ideal for applications that require reliable performance combined with low energy consumption. Developers benefit from an extensive set of resources and tools available in the RISC-V ecosystem to facilitate the integration and deployment of this processor across diverse use cases. The RISC-V CPU IP N Class demonstrates excellent scalability, allowing for configuration that aligns with the specific demands of IoT devices and embedded systems. Whether for implementing sophisticated sensor data processing or managing communication protocols within a smart device, the N Class provides the foundation necessary for developing innovative and efficient solutions.
The AndeShape Platforms are designed to streamline system development by providing a diverse suite of IP solutions for SoC architecture. These platforms encompass a variety of product categories, including the AE210P for microcontroller applications, AE300 and AE350 AXI fabric packages for scalable SoCs, and AE250 AHB platform IP. These solutions facilitate efficient system integration with Andes processors. Furthermore, AndeShape offers a sophisticated range of development platforms and debugging tools, such as ADP-XC7K160/410, which reinforce the system design and verification processes, providing a comprehensive environment for the innovative realization of IoT and other embedded applications.
The C100 is designed to enhance IoT connectivity and performance with its highly integrated architecture. Built around a robust 32-bit RISC-V CPU running up to 1.5GHz, this chip offers powerful processing capabilities ideal for IoT applications. Its architecture includes embedded RAM and ROM memory, facilitating efficient data handling and computations. A prime feature of the C100 is its integration of Wi-Fi components and various transmission interfaces, enhancing its utility in diverse IoT environments. The inclusion of an ADC, LDO, and a temperature sensor supports myriad applications, ensuring devices can operate in a wide range of conditions and applications. The chip's low power consumption is a critical factor in this design, enabling longer operation duration in connected devices and reducing maintenance frequency due to less charging or battery replacement needs. This makes the C100 chip suitable for secure smart home systems, interactive toys, and healthcare devices.
The SCR7 is a 64-bit RISC-V application core crafted to meet high-performance demands of applications requiring powerful data processing. Featuring a sophisticated dual-issue pipeline with out-of-order execution, it enhances computational efficiency across varied tasks. The core is equipped with a robust floating-point unit and supports extensive RISC-V ISA extensions for advanced computing capabilities. SCR7's memory system includes L1 to L3 caches, with options for expansive up to 16MB L3 caching, ensuring data availability and integrity in demanding environments. Its multicore architecture supports up to eight cores, facilitating intensive computational tasks across industries such as AI and machine learning. Ideal for high-performance computing and big data applications, the SCR7 leverages its advanced interrupt systems and intelligent memory management for seamless operation. Comprehensive development resources, from simulators to SDKs, augment its integration across Linux-based systems, accelerating project development timelines.
The GenAI v1-Q from RaiderChip brings forth a specialized focus on quantized AI operations, reducing memory requirements significantly while maintaining impressive precision and speed. This innovative accelerator is engineered to execute large language models in real-time, utilizing advanced quantization techniques such as Q4_K and Q5_K, thereby enhancing AI inference efficiency especially in memory-constrained environments. By offering a 276% boost in processing speed alongside a 75% reduction in memory footprint, GenAI v1-Q empowers developers to integrate advanced AI capabilities into smaller, less powerful devices without sacrificing operational quality. This makes it particularly advantageous for applications demanding swift response times and low latency, including real-time translation, autonomous navigation, and responsive customer interactions. The GenAI v1-Q diverges from conventional AI solutions by functioning independently, free from external network or cloud auxiliaries. Its design harmonizes superior computational performance with scalability, allowing seamless adaptation across variegated hardware platforms including FPGAs and ASIC implementations. This flexibility is crucial for tailoring performance parameters like model scale, inference velocity, and power consumption to meet exacting user specifications effectively. RaiderChip's GenAI v1-Q addresses crucial AI industry needs with its ability to manage multiple transformer-based models and confidential data securely on-premises. This opens doors for its application in sensitive areas such as defense, healthcare, and financial services, where confidentiality and rapid processing are paramount. With GenAI v1-Q, RaiderChip underscores its commitment to advancing AI solutions that are both environmentally sustainable and economically viable.
SiFive's Essential family of processor cores is designed to offer flexible and scalable performance for embedded applications and IoT devices. These cores provide a wide range of custom configurations that cater to specific power and area requirements across various markets. From minimal configuration microcontrollers to more complex, Linux-capable processors, the Essential family is geared to meet diverse needs while maintaining high efficiency. The Essential lineup includes 2-Series, 6-Series, and 7-Series cores, each offering different levels of scalability and performance efficiency. The 2-Series, for instance, focuses on power optimization, making it ideal for energy-constrained environments. The 6-Series and 7-Series expand these capabilities with richer feature sets, supporting more advanced applications with scalable infrastructure. Engineered for maximum configurability, SiFive Essential cores are equipped with robust debugging and tracing capabilities. They are customizable to optimize integration within System-on-Chip (SoC) applications, ensuring reliable and secure processing across a wide range of technologies. This ability to tailor the core designs ensures that developers can achieve a seamless balance between performance and energy consumption.
The eSi-3264 epitomizes the pinnacle of the eSi-RISC portfolio, presenting a 32/64-bit processor furnished with SIMD extensions catering to high-performance requirements. Designed for applications demanding digital signal processing functionality, this processor capitalizes on minimal silicon usage while ensuring exceedingly low power consumption. Incorporating an extensive pipeline capable of dual and quad multiply-accumulate operations, the eSi-3264 significantly benefits applications in audio processing, sensor control, and touch interfacing. Its built-in IEEE-754 single and double-precision floating point operations promote comprehensive data processing capabilities, extending versatility across computationally intensive domains. The processor accommodates configurable caching attributes and a memory management unit to bolster performance amidst off-chip memory access. Its robust instruction repertoire, optional custom operations, and user-privilege modes ensure full control in secure execution environments, supporting diverse operational requirements with unmatched resource efficiency.
The Spiking Neural Processor T1 is a microcontroller tailored for ultra-low-power applications demanding high-performance pattern recognition at the sensor edge. It features an advanced neuromorphic architecture that leverages spiking neural network engines combined with RISC-V core capabilities. This architecture allows for sub-milliwatt power dissipation and sub-millisecond latency, enabling the processor to conduct real-time analysis and identification of embedded patterns in sensor data while operating in always-on scenarios. Additionally, the T1 provides diverse interfaces, making it adaptable for use with various sensor types.
Designed for high-performance and cost-effective processing, the eSi-1650 CPU core is a 16-bit processor that introduces an instruction cache to boost efficiency in power and area. This processor is tailored to work with mature process nodes utilizing OTP or Flash for program memory, eliminating the dependence on large on-chip shadow RAMs and allowing maximum CPU frequency operation independent of OTP/Flash limitations. This core presents an efficient power utilization as it allows running switch applications utilizing an instruction cache, thereby reducing memory fetch time and conserving power. Equipped with an impressive instruction set and optional custom operations, the core ensures adept handling of complex computations and data manipulations. The RISC architecture ensures streamlined performance by executing applications in fewer clock cycles, which can either enhance throughput or extend low-power states. The eSi-1650 features a 5-stage pipeline supporting complex bit and arithmetic instructions, multiprocessor configurations, and high code density through sophisticated instruction encoding. Debugging and troubleshooting are facilitated through advanced hardware debugging capabilities. Also included is an optional Memory Protection Unit for secure operations that distinguish between user and kernel spaces, contributing to system security and robustness. Delivered in a Verilog RTL format, it aligns with diverse technological processes, making it a versatile option for various embedded applications.
The SCR6 is a high-performance microcontroller core optimized for demanding embedded applications requiring substantial computational power. Its out-of-order 12-stage pipeline, complemented by a superscalar architecture, enhances processing speeds, making it ideal for real-time systems. Supporting a wide range of RISC-V ISA extensions, including cryptography and bit manipulation, SCR6 caters to secure and efficient data operations. The SCR6's memory subsystem is robust, featuring dual-level caches augmented with an L3 network-on-chip option. This rich memory architecture, along with efficient interrupt processing via APLIC units, ensures smooth high-speed data throughput in intensive applications. The core supports heterogeneous multicore configurations, enhancing parallel task execution. Designed for industrial and IoT environments, SCR6 comes with extensive development support. Its toolkit includes simulations, FPGA-based SDKs, and integration resources, facilitated through industry-standard interfaces, ensuring rapid development cycles and application deployment.
The Azurite Core-hub by InCore Semiconductors is a sophisticated solution designed to offer scalable RISC-V SoCs with high-speed secure interconnect capabilities. This processor is tailored for performance-demanding applications, ensuring that systems maintain robust security while executing tasks at high speeds. Azurite leverages advanced interconnect technologies to enhance the communication between components within a SoC, making it ideal for industries that require rapid data transfer and high processing capabilities. The core is engineered to be scalable, supporting a wide range of applications from edge AI to functional safety systems, adapting seamlessly to various industry needs. Engineered with a focus on security, the Azurite Core-hub incorporates features that protect data integrity and system operation in a dynamic technological landscape. This makes it a reliable choice for companies seeking to integrate advanced RISC-V architectures into their security-focused applications, offering not just innovation but also peace of mind with its secure design.
The Codasip RISC-V BK Core Series is designed to offer highly performant solutions suitable for a range of tasks from embedded applications to more demanding compute environments. By leveraging the RISC-V architecture, the BK Core Series provides a balance of power efficiency and processing capability, which is ideal for IoT edge applications and sensor controllers. The series is built around the philosophy of flexibility, allowing for modifications and enhancements to meet specific application requirements, including the integration of custom instructions to accommodate special workloads. This series also supports functional safety and security measures as outlined by industry standards, ensuring a robust foundation for critical applications.
The SCR3 core by Syntacore is a silicon-proven microcontroller aimed at applications requiring both high performance and power efficiency. This 32/64-bit processor core supports a variety of RISC-V standard extensions, including atomic operations and bit manipulation, optimizing it for real-time applications needing reliable interrupt handling through its PLIC, ACLINT, and IPIC units. It features a 5-stage in-order pipeline paired with branch prediction and cache systems to enhance speed and execution efficiency. With considerable support for seamless memory operations, it includes both L1 and L2 caches and a TCM unit capable of housing up to 256KB of data, alongside an integrated Memory Protection Unit for executing multiple privilege modes. Ideal for industrial automation and IoT usage, the SCR3 core facilitates multicore operations with cache coherency for up to 4 simultaneous cores. Extensive development tools are provided, including simulators, IDE support, and a comprehensive FPGA-based SDK, allowing for immediate application development and deployment.
Designed for high-performance computing environments, the RISC-V CPU IP UX Class incorporates a 64-bit architecture enriched with MMU capabilities, making it an excellent choice for Linux-based applications within data centers and network infrastructures. This class of processors is optimized to meet the demanding requirements of modern computing systems, where throughput and reliability are critical. The UX Class supports advanced features like multi-core designs, which enable it to efficiently manage parallel processing tasks. This capability allows for significant performance improvements in applications where simultaneous process execution is desired. Moreover, the UX Class adheres to the RISC-V open architecture, promoting flexibility and innovation among developers who require customized, high-performance processor cores. Accompanied by an extensive ecosystem, the UX Class provides developers with a wealth of resources needed to maximize the processor's capabilities. From toolchains to development kits, these resources streamline the deployment process, allowing for the quick adaptation and integration of UX Class processors into existing and new systems alike. The UX Class is instrumental in advancing the development of data-centric applications and infrastructures.
The Y51 microprocessor features an 8051 Instruction Set Architecture, operating with a 2-clock machine cycle. This efficient configuration makes it a solid choice for projects needing the 8051 architecture with improved clock efficiency, optimizing processing speed and power consumption for embedded applications.
The SCR4 core is a high-performance, area-efficient RISC-V processor with floating-point computation capabilities. Targeting mobile and industrial applications, it supports both single and double precision, adhering to IEEE 754-2008 standards. Its instruction set is complete with advanced extensions, including atomic and cryptography functions for secure and efficient operations. With a powerful 5-stage in-order pipeline and a dedicated FPU, the SCR4 can handle complex mathematical tasks swiftly. Its memory architecture features both L1 and L2 caches, alongside a TCM unit, enabling rapid data access and management essential in real-time environments. Incorporating a robust branch prediction unit and support for multicore setups, the SCR4 excels in environments demanding synchronized computing tasks across multiple processors. It’s supported by comprehensive development kits and detailed documentation to expedite the design and implementation processes across diverse platforms.
The Rabbit 4000 microprocessor represents a significant leap in processing capabilities, featuring 161K gates within a 128-pin architecture. Its design is well-suited for demanding applications that require higher processing power and performance reliability. This generation is crafted to support expansive software execution and integration, making it ideal for advanced embedded systems.
Syntacore's SCR5 is an efficient application-class processor core, crafted to deliver exceptional performance with Linux compatibility. It integrates a 9-stage in-order pipeline along with floating-point capabilities, making it suitable for diverse processing tasks. Adopting the latest RISC-V ISA extensions, SCR5 ensures high-speed computations and secure operations equipped with bit manipulation and cryptography features. The SCR5’s robust memory subsystem ensures data integrity and rapid access, featuring L1 and L2 caches, a TCM, and an MMU. High-performance multicore support extends up to four cores, promoting parallel processing capabilities necessary in industrial and IoT environments. Its interface support, including JTAG and AXI4, streamlines integration into varied infrastructures. For developers, the SCR5 core is accompanied by advanced toolkits designed to accelerate application deployment. These include pre-built OS options and native toolchains, all backed by thorough documentation to enhance the development lifecycle.
The Y180S differentiates itself as a safe-state version of the Z180 CPU, accommodating around 10K gates. It is designed for environments where robust error-handling and reliability are crucial, offering enhanced stability and integrity for mission-critical applications.
The RV32EC_P2 core is a streamlined 2-stage pipeline RISC-V processor core aimed at small, low-power embedded applications. This processor core is designed to run only trusted firmware and can be implemented in both ASIC and FPGA-based design flows. It is compliant with RISC-V User-Level ISA V2.2, incorporating standard compressed instructions to minimize code size and optional integer multiplication and division instructions for flexibility. With a simple machine-mode privileged architecture, it supports direct physical memory addressing, along with an external interrupt controller for expanded interrupt handling. The core also integrates tightly-coupled memory interfaces and a low-power idle state option, making it highly adaptable for various low-energy applications.
The NeuroSense is a compact AI chip designed specifically for wearable devices, featuring neuromorphic analog signal processing technology. Its main focus lies in resolving common challenges faced by wearable tech, such as high power consumption, and limited battery life. By enabling highly accurate heart rate monitoring and activity recognition, this chip facilitates better fitness tracking without excessively draining battery resources. The NeuroSense's capability of operating independently from cloud connections addresses significant privacy concerns and data latency issues. It excels in delivering enhanced accuracy in heart rate measurements by utilizing a simple photoplethysmogram (PPG) configuration, which involves minimalistic hardware components like two LEDs and one photodiode. Through this setup, it achieves precision in bio-signal extraction far beyond conventional algorithmic methods, particularly when the wearer is in motion. Furthermore, the NeuroSense empowers wearables with advanced features like learning and recognizing user-specific activity patterns. With ultra-low power consumption and a compact size, the NeuroSense enables manufacturers to preserve space within constrained wearable designs while simultaneously enhancing battery life—solving a key concern in the realm of constantly operating smart devices.
The RISC-V CPU IP NS Class is crafted explicitly for applications requiring heightened security and robustness, such as fintech payment systems and IoT security solutions. This processor class is equipped to support secure operations, incorporating features essential for protecting data and ensuring secure communications within devices. This processor integrates security protocols aligned with the RISC-V open standard, offering developers the ability to embed reliable security measures directly at the hardware level. Its architecture provides the foundation for developing systems where data integrity and secure processing are non-negotiable, ensuring that sensitive applications run safely and efficiently. The RISC-V CPU IP NS Class is supported by a strong ecosystem offering tools and resources to facilitate the secure application development process. With its ability to integrate seamlessly with other embedded systems, the NS Class empowers designers to create solutions that prioritize and enhance security in modern digital environments, where threats are constantly evolving.
The M8051EW expands upon the M8051W's impressive performance by incorporating on-chip debugging capabilities. This microcontroller core offers not only rapid execution but also integrates a JTAG debug port for compatibility with external debugging tools. Additionally, this core is designed with hardware breakpoints and instruction tracebacks, providing full read and write access across all register and memory locations. Such capabilities, together with its fast execution cycle, make it an ideal choice for designs requiring advanced debugging and real-time control.
The Rabbit 3000 microprocessor expands on the capabilities of its predecessor with 31K gates and a 128-pin setup. This substantial increase in complexity supports a wider range of applications, offering enhanced processing power and connectivity options, making it an ideal choice for designs needing an efficient 8-bit microprocessor with extended functionalities.
The Rabbit 6000 flagship microprocessor maximizes the series' potential with approximately 760K gates and a 292-pin layout. This design provides unparalleled support for intensive computational tasks and complex system configurations, making it the go-to choice for high-performance applications that demand peak processing efficiency and multifunctional integration.
The iniCPU is a versatile 8-bit microprocessor designed for embedded systems, compatible with the 6809 standard. It is optimized for seamless system-on-chip integration and offers a robust platform for a variety of applications that require efficient computation and minimal system costs. This processor core supports essential features like illegal opcode recognition and provides a convenient path for programming through C compilers and assemblers. It also includes hardware debugging circuits, enabling effective error detection and correction, thus improving system reliability. Particularly suited for cost-sensitive applications, the iniCPU allows for the reduction of component count while enhancing system performance and flexibility. Its technology-independent design ensures compatibility across various platforms, making it possible to integrate easily with custom peripherals and memory interfaces, enhancing the overall system performance.
The AIoT Platform from SEMIFIVE is crafted to create specialized IoT and edge processing devices with efficiency and cutting-edge technology. Leveraging silicon-proven design components on Samsung's 14nm process, it streamlines the development of high-performance, power-efficient applications. This platform is equipped with dual SiFive U54 RISC-V CPUs, LPDDR4 memory, and comprehensive interfaces like MIPI-CSI and USB3.0. Targeted at consumer electronics such as wearables and smart home devices, this platform supports a wide array of IoT applications, including industrial IoT and smart security systems. Its architectural flexibility allows customization of system specifications, enabling designers to address the unique requirements of diverse IoT deployments. The AIoT platform supports applications with rigorous demands for power efficiency and cost-effectiveness, ensuring swift time-to-market and reduced development cycles. With a collaborative ecosystem of package design, board evaluation, and software, it paves the way for innovative IoT solutions that seamlessly integrate advanced technologies into everyday devices.
The Rabbit 2000 microprocessor boasts 19K gates and comes with a 100-pin configuration, making it a compact yet powerful solution for various applications. Designed for optimal performance and versatility, the Rabbit 2000 provides a balanced integration of functionality and hardware efficiency, suitable for projects requiring a reliable 8-bit microprocessor.
The Rabbit 5000 further extends the Rabbit line with 540K gates and a 289-pin configuration. It addresses the needs for more complex and multifunctional applications, allowing for sophisticated system designs that require comprehensive processing capabilities and robust peripheral interactions, particularly benefiting from its high pin count for increased I/O flexibility.
The i.MX RT700 Crossover MCU is a part of NXP's dynamic series of microcontrollers, characterized by its high performance and integrated feature set, designed specifically for AI-enabled edge devices. It carries the distinction of having five computing cores, contributing to its robust handling of intensive processing tasks. Within automotive and IoT domains, the i.MX RT700 excels by providing unprecedented computing power and integration. This crossover microcontroller balances the needs of hardware functionality with seamless software integration, which is vital for deploying advanced smart systems. Ideal for situations that demand optimal interaction between various components, the RT700 facilitates AI processes, driving forward features like voice and speech recognition, which are increasingly being integrated into consumer electronics. Its features make it indispensable for innovative edge devices aiming to push technological boundaries.
The Y8002 microprocessor is engineered as a compact clone of a Zilog device, involving approximately 15K gates. It is tailored for use in systems that benefit from the functional mimicry of its Zilog counterpart, delivering consistent performance and compatibility for integrated designs.
iCEVision facilitates rapid prototyping and evaluation of connectivity features using the Lattice iCE40 UltraPlus FPGA. Designers can take advantage of exposed I/Os for quick implementation and validation of solutions, while enjoying compatibility with common camera interfaces such as ArduCam CSI and PMOD. This flexibility is complemented by software tools such as the Lattice Diamond Programmer and iCEcube2, which allow designers to reprogram the onboard SPI Flash and develop custom solutions. The platform comes preloaded with a bootloader and an RGB demo application, making it quick and easy for users to begin experimenting with their projects. Its design includes features like a 50mmx50mm form factor, LED applications, and multiple connectivity options, ensuring broad usability across various rapid prototyping scenarios. With its user-friendly setup and comprehensive toolkit, iCEVision is perfect for developers who need a streamlined path from initial design to functional prototype, especially in environments where connectivity and sensor integration are key.
Dedicated to energy-efficient computing, SkyeChip's Low Power RISC-V CPU IP offers a streamlined design utilizing the RV32 instruction set, with full support for base integer operations and extensions like M and C. This makes it a versatile processor core for embedded applications requiring minimal power. The CPU is tailored for machine mode operations with features such as vectored interrupts and standard debugging, in line with RISC-V specifications. This ensures great adaptability across various embedded systems looking for a balance between performance and power consumption. Ideal for IoT devices and applications demanding efficient processing with a small footprint, this IP supports a broad spectrum of applications while adhering to industry standards for low power consumption. It is a key component for developers focusing on optimizing performance without expending excessive energy.
The NPU from OPENEDGES represents a cutting-edge approach to neural processing, designed to enhance AI computations with superior efficiency and high-performance capabilities. This processing unit is optimized for tasks involving complex data operations, such as machine learning and real-time analytics, making it invaluable for AI-driven applications. Boasting an architecture that supports parallel processing, the NPU delivers significant speed-ups in data processing time, crucial for handling the vast datasets typical in AI workloads. It integrates seamlessly with existing infrastructure, providing a balanced mix of power efficiency and computational prowess to accelerate AI functionalities. The NPU's design allows for flexibility in deployment across various platforms, whether it's edge devices requiring energy-efficient processing or large data centers needing scalable AI performance. As a result, it stands as a versatile solution for companies looking to advance their AI capabilities.
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