All IPs > Multimedia > H.265
The Multimedia > H.265 category features semiconductor IPs specifically designed for optimizing High-Efficiency Video Coding (HEVC) technology. H.265, a successor to H.264, is renowned for doubling the data compression ratio compared to its predecessor while maintaining the same level of video quality. This allows developers to deliver ultra-high-definition video content at significantly reduced bandwidths and storage requirements, making it an essential technology in today's data-driven multimedia landscape.
In this category, you will find a range of H.265 semiconductor IPs aimed at facilitating the efficient encoding and decoding of video streams. These IPs are highly sought after by industries looking to integrate 4K and 8K video content, such as in smart televisions, streaming devices, video conferencing systems, and mobile devices. By implementing H.265 semiconductor IPs, companies can ensure their products offer superb visual experiences while optimizing performance and minimizing power consumption.
The products available in the H.265 semiconductor IP category are designed to support a variety of applications beyond standard video playback and streaming. They are integral in enabling next-generation technologies such as virtual reality (VR) and augmented reality (AR), where seamless, high-resolution video streaming is crucial for immersive user experiences. Additionally, these IPs provide robust support for live broadcasting solutions, cloud video storage, and advanced surveillance systems, showcasing their versatility across numerous technology sectors.
Overall, the H.265 semiconductor IP offerings from Silicon Hub empower developers with the tools needed to meet escalating consumer expectations for high-quality video performance. Whether your focus is on improving end-user video experiences or optimizing backend video processing systems, H.265 IPs provide the foundational technology to achieve these goals, all while adhering to stringent industry standards for efficiency and quality. Explore our comprehensive collection to find the IP solution that best suits your multimedia product development needs.
Allegro DVT’s HEVC/H.265 Encoder is designed for those requiring efficient video encoding solutions that deliver high-quality video streams. This encoder supports high dynamic range content and scales to support up to 8K resolution, making it particularly suitable for cutting-edge applications seeking superior video quality and compression efficiency. The encoder integrates seamlessly into various systems, thanks to its flexible architecture which allows for customization based on user requirements. It captures extensive detail in the video while maintaining exceptional compression ratios, thereby reducing bandwidth usage without sacrificing image integrity. Emphasizing both performance and power efficiency, the encoder is tailored for use in environments where these factors are paramount, such as broadcasting, surveillance, and media streaming solutions. With its support for an array of advanced video processing functions, the HEVC/H.265 Encoder is a preferred choice for industries pushing the boundaries of video technology.
The MIPITM V-NLM-01 is a specialized non-local mean image noise reduction product designed to enhance image quality through sophisticated noise reduction techniques. This hardware core features a parameterized search-window size and adjustable bits per pixel, ensuring a high degree of customization and efficiency. Supporting HDMI with resolutions up to 2048×1080 at 30 to 60 fps, it is ideally suited for applications requiring image enhancement and processing.
XtremeSilica's H.265 Codec IP provides an advanced, efficient solution for high-quality video encoding and decoding. Crafted to meet the stringent requirements of modern multimedia applications, this IP ensures efficient video compression, which is crucial for removing data transmission constraints and enhancing storage capabilities. The H.265 Codec IP offers superior performance by delivering exceptional image quality even at lower bit rates compared to its predecessors. This efficiency in compression not only saves on bandwidth but also ensures smoother playback across various devices and platforms, which is vital for today's diverse digital media landscape. Incorporating the H.265 Codec into your design can significantly enhance application versatility, making it suitable for a range of end uses from consumer electronics to professional broadcasting equipment. Its adaptability to different resolutions and frame rates allows developers to create scalable systems that accommodate both current and future media formats.
The H.265 HEVC Decoder System is an advanced, standalone FPGA solution built for ultra-low latency decoding of the H.265 standard. It is ideal for high-end broadcast and consumer applications, offering durable performance with superior error concealment. Engineered for adaptability, this system is available either as an IP core or in a custom design, fully compliant with ITU-T H.265, covering profiles up to 4k at 60 fps. Users can integrate this decoder into broader systems via a simple API, ensuring its easy assimilation into varied platforms requiring high-quality video processing. Targeted at Intel FPGA technologies, this system proves essential for diverse fields including broadcast, medical imaging, and consumer applications. It supports multiple configurations, with varying chroma and precision options, ensuring exceptional performance tailored to specific scenarios. Its architecture allows for seamless deployment, boosting system capabilities through robust and reliable video decoding.
The HEVC Decoder from VYUsync Design Solutions is a top-tier video decoder built for high performance. It complies with HEVC/H.265 standards, providing up to Main 12 422 Profile compatibility. The HEVC Decoder is specially designed for deployment on a wide variety of target FPGAs. Its capability to handle complex video data efficiently makes it ideal for high-definition video streaming applications, ensuring seamless video playback and advanced video processing. This decoder is flexible, scalable, and tailored to meet the rigorous demands of modern video applications, whether they're for broadcasting, professional video recording, or any high-demand video processing role. Focused on maintaining superior color fidelity, the HEVC Decoder supports the 4:4:4 color format, accommodating larger bit depths to ensure refined and nuanced color reproduction. This makes it exceptionally suited for applications in fields that demand high visual fidelity such as professional film production and medical imaging. The decoder’s design assures low latency, enhancing the responsiveness and effectiveness of visual data transmission, which is particularly critical when real-time processing is necessary. The HEVC Decoder is an invaluable component in mission-critical environments. Its robust performance ensures that it can reliably transport and decode video streams even in high-pressure situations. This decoder is also an asset for companies looking to enhance their current video processing capabilities, offering a highly efficient, field-proven IP that can be integrated seamlessly into existing systems.
HEVC/H.265 Main/Main10/ Main Still Picture Profile @L5.2 AVC/H.264 BP/CBP/MP/HP/HP10 @L5.2 Capable of encoding up to 8K ((8192x4096) A 32-bit AMBA3 APB bus for host CPU system control 128-bit AMBA3 AXI for data transfer (Optionally, additional secondary AXI) Latency tolerance Low power consumption Programmability Configurable IP Multi-instances Frame buffer compression (CFrame) Rotation & Mirroring Bit-depth & chroma sub-sample conversion Background detection 3DNR Lambda table QP Map Custom mode decision, etc.
The AVC/H.264 Decoder by Allegro DVT is tailored for high-efficiency video decoding, capable of handling a wide array of video streams with precision. This decoder is engineered for versatile applications, supporting high-definition video content with minimal latency. It is particularly beneficial for applications requiring robust compression solutions without compromising on video quality. Designed to accommodate modern and legacy video formats, the solution efficiently manages high-resolution streams, enabling seamless playback and interaction. The decoder's architecture focuses on optimizing memory usage and power efficiency, ensuring that it meets the demanding requirements of today's multimedia applications. Ideal for integration into various systems, the AVC/H.264 Decoder provides the flexibility and scalability needed to support next-generation video applications. Its compatibility with extensive video standards makes it a valuable asset for developers looking to enhance their video processing capabilities.
The Advanced Video Transmission Toolkit (FV-VTT) from FastVDO is a cutting-edge solution designed to simulate video encoding, forward error correction (FEC), transmission channels, and video quality assessment. This toolkit supports popular video standards like H.264, H.265, H.266, and AV1, along with advanced FECs such as Polar, LDPC, and Turbo codes used in Wifi and 5G standards. Incorporating diverse channel models like AWGN, Rayleigh fading, and burst error channels, FV-VTT is a comprehensive package for video transmission analysis. By accurately simulating varying conditions and assessing received video quality, this toolkit aids in the development of robust video transmission systems capable of maintaining fidelity across different environments. FastVDO's toolkit is instrumental for developers and researchers focused on optimizing video communication technologies, offering insights to improve video delivery and quality in real-world applications. This innovative product embodies FastVDO's commitment to advancing multimedia communication standards, providing powerful tools for video engineers.
The G-Series Controller from MEMTECH is designed for applications requiring high memory bandwidth, such as graphics processing, AI video processing, and gaming. This GDDR6 solution supports dual 16-channel configurations with speeds reaching up to 20 Gbps, making it an ideal solution for compute-intensive tasks that demand swift data handling and processing. Advanced scheduling engines enhance its efficiency by optimizing throughput, while hardware auto-initialization and comprehensive error correction modes ensure error-free operation and data integrity. G-Series Controllers boast a DFI 5.0 interface, allowing easy integration with memory systems and reducing development complexities. G-Series Controllers are crafted to meet high-performance computing and graphics needs within tight power budgets, delivering enhancements in latency and speed without requiring a large footprint. As a fully optimized controller, it provides exceptional performance for advanced computing environments where power and space are precious resources.
HEVC/H.265 - Main/Main10 Profile @L5.1 AVC/H.264 - BP/CBP/MP/HP/HP10 Profile @ L5.2 Capable of decoding up to 4K60fps (8192x4096) A 32-bit APB bus and 128-bit AMBA3 AXI buses (w/ additional secondary AXI) Burst Write Back Map converter Low delay Low power consumption Configurable IP Latency tolerance Programmability Multi-instances Frame buffer compression (CFrame) Secondary AXI interfaces Downscaler (on-the-fly mode)
Video Codec Standard HEVC/H.265: Main profile @ L5.1 High tier AVC/H.264: Baseline/Constrained Baseline/Main/High profile @ L5.2 Performance 4K60fps@500MHz Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit depth and YUV format conversion of the source picture Encoder Features I/P picture coding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer (Optional AXI can be used to alleviate bandwidth usage.)
Video Codec Standard AV1: Main profile @ L5.1 HEVC: Main/Main10 profile, Main/Main 10 Still Picture profile @ L5.1 High tier AVC: Baseline/Constrained Baseline/Main/High/High 10 profile @ L5.2 (Interlaced coding tools are not supported) Performance 4K60fps@500MHz Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit depth and YUV format conversion of the source picture Encoder Features I/P/B picture encoding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer * Optional AXI can be used to alleviate bandwidth usage
MPEG-H Audio, pioneered by Fraunhofer IIS, is an advanced audio solution tailored for the evolving demands of television and virtual reality (VR) environments. It enhances user experiences by delivering immersive 3D soundscapes and providing greater interactivity through personalizable features. For broadcasters, MPEG-H Audio offers a remarkably flexible setup, allowing for seamless integration with existing broadcasting systems while ensuring compatibility with various formats and platforms. One of its standout features is the ability to adapt audio output to specific environments or user preferences, such as adjusting the volume of commentary during a sports broadcast or enhancing dialogue clarity in films. This is achieved through the system's object-based audio technology, enabling precise sound positioning and dynamic adjustments in real-time. MPEG-H Audio also supports a wide range of operating environments, from high-definition TVs to intricate VR setups, including headsets and specialized sound systems. It is designed with forward compatibility in mind, which means it is well-prepared for integration with future audio advancements and standards. Across the globe, MPEG-H Audio is recognized as a key component for delivering high-quality audio experiences, emphasizing Fraunhofer IIS's leadership in audio technology innovation.
Video Codec Standard AV1: Main profile @ L5.1 Main tier 50Mbps HEVC/H.265: Main/Main 10 profile @ L5.1 High tier AVC/H.264: Baseline/Constrained Baseline/Main/High/High10 profile @ L5.2 (Interlaced coding tools are not supported.) VP9 (Decoder only): Profile 0 and Profile 2 (12-bit not supported) Performance 4K60fps@500MHz with a single-core Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit depth and YUV format conversion of the source picture Encoder Features I/P/B picture coding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer (Optional AXI can be used to alleviate bandwidth usage.)
The IMG CXM High-Efficiency GPU provides a compact, yet powerful solution tailored for use in a wide range of consumer devices. As the smallest GPU supporting HDR (High Dynamic Range) user interfaces, it combines efficient performance with enhanced visual quality, delivering exceptional graphics while maintaining low power consumption, particularly important for cost-sensitive markets. Designed to support a variety of configurations, IMG CXM is adept in handling multimedia-rich content, thus making it a prime choice for devices that require dynamic and engaging visual experiences. Its support for advanced graphics processing units allows integration in applications ranging from digital televisions to smart home devices, enabling these products to offer modern, cinematic user interfaces. The hallmark of IMG CXM lies in its power and memory efficiency, which employs Imagination's Tiny Frame Buffer Compression (TFBC) technology to further reduce the demands on bandwidth. This makes the GPU ideal for applications in wearables, smart homes, and other devices where space and resource management are pivotal, ensuring that performance does not come at the cost of increased energy consumption.
The AL-H264E-4KI422-HW is crafted to provide a robust, hardware-based video encoding solution that excels in delivering high-quality, low-latency performance. Known for its effectiveness in managing UHD video encoding, this encoder implements the H.264/AVC codec, tailored for applications demanding exceptional visual quality and low latency. Medical imaging processes benefit from its exceptional color fidelity, a testament to its support for the high-422 profile and 10-bit color depth. Industries requiring precise video editing, such as broadcasting and film production, rely on this encoder for seamless video data handling. Its proficient encoding capabilities are complemented by its implementation on the Xilinx Zynq series, enhancing its operational efficiency and flexibility in system design.
The AL-H264D-4KI422-HW decoder is a sophisticated hardware-based solution engineered for high-quality and low-latency video decoding. This MPEG video decoder handles high-422 profile H.264 streams at Level 5.1, ensuring superior image quality for UHD resolutions. It finds its place specifically in medical, broadcast, and industrial sectors where high color accuracy and minimal latency are crucial. Medical applications benefit from its capability to deliver precise color reproduction essential in surgeries and diagnostics, while the broadcast sector sees its potential in real-time monitoring and production processes. Its integrated support for IP streaming and extreme efficiency on Xilinx devices highlight its advanced design, positioning it as a leader for enterprises needing rapid, reliable video processing solutions.
Video Codec Standard AV1: Main profile @ L6 High tier HEVC/H.265: Main/Main10 profile @ L6 High tier AVC/H.264: Baseline/Constrained Baseline/Main/High/High 10 profile @ L6 Performance 4K120fps@500MHz with a dual-core 4K240fps@1GHz or 8K60fps@1GHz with a dual-core Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit depth and YUV format conversion of the source picture Encoder Features I/P/B picture coding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer (Optional AXI can be used to alleviate bandwidth usage.)
The v-MP6000UDX Visual Processing Unit from videantis is an advanced processor that suits a wide array of AI and embedded applications needing deep learning and computer vision. This universal architecture is designed to handle not just computationally heavy deep learning processes but also video coding, signal, and image processing tasks all within a single unified framework. The platform is tailored for minimizing power consumption while maximizing performance, making it ideal for automotive, gaming, surveillance, and beyond. With versatility at its core, the v-MP6000UDX efficiently runs embedded tasks with seemingly unmatched performance and flexibility. Its architecture allows seamless updates and scaling, which is a game changer for evolving markets that require AI and high-performance computation. It's engineered to support multiple neural network models such as ResNet and MobileNet, alongside customized networks, making integration with the latest AI frameworks like TensorFlow or PyTorch effortless. Moreover, it's crafted with a unique memory architecture to enhance bandwidth while keeping energy use low. This processor's expansive codec library and accelerated video coding support various media standards ideal for modern high-resolution video applications. All these features are manageable through a single software development suite, further simplifying the complexities of advanced AI and high-bandwidth multimedia applications.
VISENGI presents the Bayer To RGB Converter, which utilizes bilinear interpolation techniques to convert Bayer patterned sensor data into high-quality RGB images. This converter works with various bit widths, from 8 through 12 bits on the input, producing RGB outputs accordingly, with a configurable bit width of up to 36 bits. It's engineered to efficiently handle corner cases, ensuring seamless conversion even at the borders of captured images.\n\nThe IP core's operation revolves around a pipelined architecture that secures optimal throughput, delivering a one RGB pixel per cycle rate. It supports dual clock regions, facilitating integration with diverse system clocks and sensor frequencies, thereby maximizing flexibility within imaging applications. Developers can customize parameters such as Bayer pattern types and sensor signaling states on the fly, tailoring the converter to meet specific operational requirements without extensive redesign effort.\n\nBenefiting from minimal internal buffers requiring only two pixel row memories, it boasts lightweight resource consumption, suitable for resource-constrained environments. The Bayer To RGB Converter is versatile, handling unlimited input image sizes ensuring extensive compatibility with modern imaging sensors. Further enhancements such as borderless configurations are available, optimizing resource use while maintaining edge case precision, critical for high-definition applications such as video streaming and photographic processing.
Video Codec Standard AV1: Main/High profile @ L6 Main tier 50Mbps Professional profile except 12-bit @ L6 Main tier 50Mbps Mono/YUV420/YUV422/YUV444 8-/10-bit HEVC/H.265: Main/Main 10/Main 4:2:2 10 profile @ L6 High tier Main 4:4:4/Main 4:4:4 10 profile @ L6 High tier (Only support 4:2:0 coding tools, high precision weighted prediction, and chroma QP offset list) AVC/H.264: Baseline/Constrained Baseline/Main/High/High10 profile @ L6 High 10 Intra/High 4:2:2/High 4:2:2 Intra profile with frame_mbs_only_flag = 1 @ L6 High 4:4:4 Predictive/High 4:4:4 Intra/CAVLC 4:4:4 Intra profile @ L6 with: frame_mbs_only_flag = 1 bit_depth_luma ≤ 10 bit_depth_chroma ≤ 10 frame_mbs_only_flag = 1 and qpprime_y_zero_transform_bypass_flag = 0 VP9 (Decoder only): Profile 0 and Profile 2 (12-bit not supported), YUV420 8/10-bit Performance 4K120fps@500MHz with a dual-core 4K240fps@1GHz or 8K60fps@1GHz with a dual-core Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit depth and YUV format conversion of the source picture Rotate/Mirror Down-scaler Crop Encoder Features I/P/B picture coding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer (optional AXI can be used to alleviate bandwidth usage.)
The IMG B-Series GPU exemplifies the pinnacle of multi-core graphics technology, designed to deliver scalable performance across a wide array of applications, from automotive to cloud computing. With over twenty configurations available, it provides flexibility for integrating multi-GPU core setups, enhancing both graphical and computational throughput for a variety of demanding scenarios. Aimed at offering maximum performance, this GPU series supports intensive graphical effects like volumetric lighting and advanced physical shading systems. Its architecture is also conducive to safety-critical applications in automotive markets, where it ensures compliance with ISO 26262 standards, making it a reliable choice for high-quality, functionally safe graphics. The B-Series is engineered for high efficiency and supports integration in cloud-based systems, where its robust multi-core configurations and superior power management significantly optimize operational costs while ensuring peak performance. Its deployment in consumer electronics also highlights its versatility, adapting flexibly to various compute and display demands while maintaining optimal energy usage.
Video Codec Standard HEVC: Main/Main Still Picture profile @ L5.1 High tier AVC: Baseline/Constrained Baseline/Main/High profiles @ L5.2 Performance 4K60fps@500MHz Max resolution: 8192 x 4096 Min resolution: 256 x 128 Bit depth: 8-bit Features Multi-instances Frame-buffer compression (CFrame) In-loop filter Rotation & Mirroring Bit depth & chroma sample format conversion Lossless coding Background coding Down-scaler (On-the-fly mode) MapConverter 3DNR, etc. Interface 32-bit AMBA3 APB bus 128-bit AMBA3 AXI buses Primary AXI interface and an optional secondary AXI interface
Video Codec Standard HEVC/H.265: Main profile @ L5.1 High tier AVC/H.264: Baseline/Constrained Baseline/Main/High profile @ L5.2 Performance 4K60fps@500MHz with a single-core Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit depth and YUV format conversion of the source picture Encoder Features I/P/B picture coding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer (Optional AXI can be used to alleviate bandwidth usage.)
The TicoXS FPGA/ASIC IP Cores from intoPIX represent a groundbreaking technology for high-efficiency video compression. These IP cores utilize the JPEG XS standard to deliver ultra-low latency and visually lossless compression, making them ideal for latency-sensitive applications such as live production and broadcasting. The technology is engineered to operate at the speed of light, offering a near-zero latency experience. TicoXS is incredibly efficient in terms of resource usage, allowing for the implementation in even the smallest FPGA and ASIC devices while ensuring high-quality image outputs. The compression technology supports a range of video resolutions from HD to 8K, with flexibility in color sampling and bit depths, covering diverse industry needs from professional audio-visual environments to automotive and machine vision applications. Moreover, intoPIX's TicoXS provides significant compression without compromising visual quality, thanks to its lightweight coding approach. This allows organizations to maintain bandwidth efficiency, saving costs associated with data transport and storage. The IP cores are highly configurable, supporting various pixel formats, frame rates, and networking standards, facilitating easy integration into existing and future video processing workflows.
Video Codec Standard AV1: Main profile @ L6 Main tier 50Mbps HEVC/H.265: Main/Main10 profile @ L6 High tier AVC/H.264: Baseline/Constrained Baseline/Main/High/High 10 profile @ L6 VP9 (Decoder only): Profile 0 and Profile 2 (12-bit not supported) Performance 4K120fps@500MHz with a dual-core 4K240fps@1GHz or 8K60fps@1GHz with a dual-core Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit depth and YUV format conversion of the source picture Encoder Features I/P/B picture coding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer (Optional AXI can be used to alleviate bandwidth usage.)
intoPIX's JPEG XS Encoder & Decoder offers a cutting-edge solution for real-time video stream compression, ensuring minimal latency without sacrificing image quality. This standard, co-developed by intoPIX, provides the industry's lowest complexity and smallest latency, designed specifically for environments where every second counts—such as live AV productions and industrial applications. JPEG XS has been praised for its efficiency, achieving compression ratios up to 36:1 while maintaining lossless quality critical for professional uses. Capable of operating on various platforms including FPGA, ASIC, CPU, and GPU, the encoder and decoder streamline integration across different systems and technologies. Additionally, JPEG XS supports a wide color gamut, high dynamic range (HDR), and high frame rates, catering to the most demanding visual needs. It's designed to work seamlessly with existing infrastructures, optimizing the transmission of high-quality video over IP networks, including standard Ethernet setups, making it a flexible and adaptable choice for video compression.
Video Codec Standard AV1: Main Profile @ L5.1 Performance 4K60fps@500MHz Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit-depth and YUV format conversion of the source picture Encoder Features I/P/B picture coding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer * Optional AXI can be used to alleviate bandwidth usage
Decoding/Encoding Tools Support Extended Sequential ISO/IEC 10918-1 JPEG compliance Support one or three color components Three components in a scan (interleaved only) 8-bit and 12-bit samples for each component Support 4:2:0, 4:2:2, 4:4:0, 4:4:4 and 4:0:0 color formats Max. six 8x8 blocks in one MCU Support NV12/NV16/NV24 (CbCr Interleaved), NV21/NV61/NV42 (CrCb Interleaved) Support from 16 x 16 to 32K x 32K (32,768 x 32,768) image size Packed mode is supported 12-bit PPM format is supported Value-added Features Partial mode for encoding and decoding On-the-fly rotator/mirror ROI(Region of Interest) for decoding On-the-fly downsampler for decoding Color format converting for decoding Performance Decode up to 290M pix/s for 4:2:0 color format Encode up to 290M pix/s for 4:2:0 color format Operating clock frequency: 200MHz Ease of integration AMBA 32-bit APB (w/ PREADY) interface for communication with a host processor AMBA 64-bit AXI interface for the external memory
Supported standards for Decoder ISO/IEC23008-2 HEVC/H.265, ITU-T Rec. H.265 Main/Main10 Profile L5.1 AVC/H.264 BP/CBP/MP/HP/HP10 Profile @ L5.2 AVS2 Main/Main10 Profile @L8.0.60 Main performance 4K(3840x2160) 60fps @ 450MHz Max. resolution: 8192x4096 Features Frame buffer compression (CFrame) Embedded Post-processing (w/Down-scaler) Low delay Low power consumption Latency tolerance Interface AMBA 32-bit APB interface for Host CPU AMBA 128-bit AXI interface for the external memory
Brief specification HEVC/H.265 Main/Main10 Profile @L5.1 AV1 Main Profile @ L5.1 VP9 Profile 0/ Profile 2 @L5.1 AVC/H.264 BP/CBP/MP/HP/HP10 Profile @ L5.2 AVS2 Main/Main10 Profile @L8.0.60 Main performance 4K(3840x2160) 60fps @ 450MHz Max. resolution: 8192x4096 System I/F A 32-bit APB bus and 128-bit AMBA3 AXI buses (w/additional Secondary AXI) Burst Write Back (BWB) Features Frame buffer compression (CFrame) Embedded Post-processing (w/Down-scaler) Low delay Low power consumption Latency tolerance
HEVC/H.265 Main/Main10 Profile @L5.1 AVC/H.264 BP/CBP/MP/HP/HP10 Profile @ L5.2 VP9 Profile 0/Profile 2 (HBD) AVS2 Main10 Profile @L8.0.60 Capable of decoding up to 4Kp60 (8192x4096) A 32-bit APB bus and 128-bit AMBA3 AXI buses (w/ additional secondary AXI) Burst Write Back Map converter Low delay Low power consumption Configurable IP Latency tolerance Programmability Multi-instances Frame buffer compression (CFrame) Downscaler (on-the-fly mode)
High-resolution Image Processing IP Performance 4K60p@400MHz (600MHz for display interface) Features Support various color format : YUV420, YUV422, YUV444, and RGB Up-/Down-scaler x1/8~x8 : selectable scaler algorithm with Bi-cubic and Lanczos Two scalers, connected to DRAM and display/direct I/F respectively, operating at different ratios at the same time (configurable to one scaler option) Color space conversion : YUV2RGB and RGB2YUV, coefficient downloadable Optional features Crop and digital zoom : scaling on cropped region Flip : horizontal and vertical 3rd Party interfaces: such as AFBC v1.2 and PVRIC v4 (support output only) Interface Display Interface : 3 channels for components with vertical/horizontal sync signal (ITU-R BT.601 compatible) Direct Interface (optional feature) : On-the-fly interface based on ready-valid protocol Support CF10 (Chips&Media’s Frame buffer compression) for Chips&Media video codec Support AFBC v1.2 and PVRIC v4 (optional feature) for output of MAPI
H.264, MVC, VP8, MPEG-1/2/4, VC-1, AVS, AVS+, H.263, Sorenson Decoding and encoding support at 1080p 60fps Supported standards for Decoder ISO/IEC 14496-10 AVC/H.264 BP/MP/HP@L4.2 ISO/IEC 14496-10/5 MVC Stereo High Profile@L4.1 ISO/IEC 14496-2 MPEG-4 SP,ASP@L6 SMPTE 421M-2006 VC-1 SP/MP/AP@L3 ISO/IEC 13818-2 MPEG-2 MP@HL ITU-T H.263(Annex I,J,K,T) AVS Jizhun @L6.2 AVS+ Guangdian @L6.2 On2 VP8 Sorenson Spark Theora Supported standards for Encoder ISO/IEC 14496-10 AVC/H.264 BP/MP/HP@L4.2 ISO/IEC 14496-10/5 MVC Stereo High Profile@L4.1 ISO/IEC 14496-2 MPEG-4 SP@L6 ITU-T H.263(Annex J,K,T) Supported Max. Resolution Supports up to 2048x2048 resolution Performance Single-stream H.264 HD(1920x1080p) 30fps decoding at <133MHz core clock H.264 HD(1920x1080p) 60fps decoding at <266MHz core clock H.264 HD(1920x1080p) 30fps encoding at <133MHz core clock H.264 HD(1920x1080p) 60fps encoding at <266MHz core clock Multi-stream Dual H.264 HD(1920x1080p) 30fps decoding at <266MHz core clock Dual H.264 HD(1920x1080p) 30fps encoding at <266MHz core clock 6SD/D1(NTSC&PAL) 30fps decoding at <133MHz core clock Full HD(1080p) encoding and decoding at <266MHz core clock Encoding Tools Selective [+/-64,+/-48] Quarter-pel and half-pel accuracy motion estimation using a full- search algorithm Flexible bit-rate control CBR VBR Fixed QP CABAC/CAVLC for AVC/H.264 Built-in pre- rotation/mirroring function 90xn degree rotation Vertical/horizontal mirroring Decoding Tools CABAC/CAVLC for AVC/H.264 MPEG-4 AC/DC prediction AVC/H.264 intra-prediction In-loop deblocking filter for H.264, H.263, and AVS Overlapped smoothing filter for VC-1 Built-in post-processing function 90xn degree rotation Vertical/horizontal mirroring De-ringing De-blocking filter for MPEG-2/4 Interface AMBA 32-bit APB interface for Host CPU AMBA 64-bit AXI interface for the external memory
H.264, MVC, VP8, MPEG-1/2/4, VC-1, AVS, AVS+, H.263, and Sorenson decoder HW IP for 2Kp60, 4:2:0 Standards AVC/H.264 BP/CBP/MP/HP L.4.1 Max: 1920x1088; Min: 16x16 MVC SHP L.4.1 Max: 1920x1088; Min: 16x16 MPEG-4 SP/ASP L.5 Max: 1920x1088; Min: 16x16 H.263 Profile 3 Max: 1920x1088; Min: 16x16 VC-1 SP/MP/AP L.3 Max: 1920x1088 or 2048x1024 Min: 16x16 MPEG-1/2 MP L.high Max: 1920x1088; Min: 16x16 Sorenson Spark Max: 1920x1088; Min: 16x16 VP8 WebM/WebP Max: 1920x1088; Min: 16x16 Theora Max: 1920x1088; Min: 16x16 AVS Jizhun/Guangdian L6.2 Max: 1920x1088; Min: 16x16 Features Frame buffer compression (CFrame) Low delay decoding Configurable IP Programmability Low power consumption Frame-based processing Multi-instances Latency tolerance Burst Write Back Down-scaler (on-the-fly mode) Map converter MPEG-2/4 De-ringing Built-in de-blocking filter A 32-bit AMBA3 APB bus and 64-bit AMBA3 AXI buses (w/additional Secondary AXI buses)
Video Codec Standard HEVC: Main/Main10 profile @ L6 High tier AVC: Baseline/Constrained Baseline/Main/High/High 10 profile @ L6 (Interlaced coding tools are not supported) Performance 4K120fps@500MHz or 8K60fps@1GHz Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit depth and YUV format conversion of the source picture Encoder Features I/P/B picture encoding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer *Optional AXI can be used to alleviate bandwidth usage
Video Codec Standard HEVC: Main/Main Still Picture profile @ L5.1 High tier AVC: Baseline/Constrained Baseline/Main/High profiles @ L5.2 Performance 4K60fps@500MHz Max resolution: 8192 x 4096 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Multi-instances Frame-buffer compression (CFrame) In-loop filter Rotation & Mirroring Bit depth & chroma sample format conversion Lossless coding Background coding MapConverter 3DNR, etc. Interface 32-bit AMBA3 APB bus 128-bit AMBA3 AXI buses Primary AXI interface and an optional secondary AXI interface
Video Codec Standard HEVC: Main/Main Still Picture profile @ L5.1 High tier AVC: Baseline/Constrained Baseline/Main/High profiles @ L5.2 Performance 4K60fps@500MHz Max resolution: 8192 x 4096 Min resolution: 256 x 128 Bit depth: 8-bit Features Multi-instances Frame-buffer compression (CFrame) In-loop filter Rotation & Mirroring Bit depth & chroma sample format conversion Lossless coding Background coding 3DNR, etc. Interface 32-bit AMBA3 APB bus 128-bit AMBA3 AXI buses Primary AXI interface and an optional secondary AXI interface
Video Codec Standard HEVC/H.265: Main/Main 10 profile @ L6 High tier AVC/H.264: Baseline/Constrained Baseline/Main/High/High 10 profile @ L6 Performance 4K120fps@500MHz or 8K30fps@500MHz with a dual-core 4K240fps@1GHz or 8K60fps@1GHz with a dual-core Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit-depth and YUV format conversion of the source picture Encoder Features I/P/B picture coding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer (optional AXI can be used to alleviate bandwidth usage.)
The Hantro VPU VC9800D by VeriSilicon delivers high-efficiency video processing capabilities, tailored to decode and encode a wide array of video formats. This VPU is designed for intensive video applications, delivering superior processing speed and picture quality. The VC9800D efficiently manages video encoding tasks, optimizing for both bandwidth and power use, which is ideal for modern multimedia devices demanding high-quality video playback.
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