All IPs > Memory & Logic Library > I/O Library
The I/O Library within the Memory & Logic Library category encompasses a wide range of semiconductor IPs focused on input and output interfacing. These IPs are critical for ensuring efficient data communication and integration between different parts of an electronic system. They play a pivotal role in defining how devices connect and interact with each other, which is crucial for the design of versatile and robust electronic products.
I/O Libraries are meticulously designed to support various communication protocols and standards, enabling seamless connectivity. They can include a variety of interfaces such as GPIOs (General Purpose Input/Outputs), UARTs (Universal Asynchronous Receiver-Transmitter), SPI (Serial Peripheral Interface), and I2C (Inter-Integrated Circuit) among others. Each type of interface IP ensures high compatibility and interaction efficiency, tailored to meet the specific needs of different applications ranging from simple consumer electronics to complex industrial solutions.
These semiconductor IPs are integral in reducing design time by providing pre-verified components, which developers can modularly integrate into their chip designs. By utilizing these I/O IP components, designers can significantly streamline the development process, meeting tight deadlines while achieving high-performance standards. The versatility of these IPs allows for easy customization and adaptation to various technological requirements, thus providing a flexible foundation for innovative electronic product development.
In addition to supporting various communication protocols, I/O Libraries also adhere to stringent electrical and timing specifications, ensuring reliable and consistent performance across devices. These libraries are critical in environments where precision and reliability are paramount, making them indispensable for designers focused on creating cutting-edge technology solutions. Overall, I/O Library semiconductor IPs are a cornerstone of contemporary electronics design, enabling a seamless blend of performance, compatibility, and scalability.
The xcore.ai platform by XMOS is a versatile, high-performance microcontroller designed for the integration of AI, DSP, and real-time I/O processing. Focusing on bringing intelligence to the edge, this platform facilitates the construction of entire DSP systems using software without the need for multiple discrete chips. Its architecture is optimized for low-latency operation, making it suitable for diverse applications from consumer electronics to industrial automation. This platform offers a robust set of features conducive to sophisticated computational tasks, including support for AI workloads and enhanced control logic. The xcore.ai platform streamlines development processes by providing a cohesive environment that blends DSP capabilities with AI processing, enabling developers to realize complex applications with greater efficiency. By doing so, it reduces the complexity typically associated with chip integration in advanced systems. Designed for flexibility, xcore.ai supports a wide array of applications across various markets. Its ability to handle audio, voice, and general-purpose processing makes it an essential building block for smart consumer devices, industrial control systems, and AI-powered solutions. Coupled with comprehensive software support and development tools, the xcore.ai ensures a seamless integration path for developers aiming to push the boundaries of AI-enabled technologies.
Certus Semiconductor's Digital I/O solutions are engineered to meet various GPIO/ODIO standards. These versatile libraries offer support for standards such as I2C, I3C, SPI, JEDEC CMOS, and more. Designed to withstand extreme conditions, these I/Os incorporate features like ultra-low power consumption, multiple drive strengths, and high levels of ESD protection. These attributes make them suitable for applications requiring resilient performance under harsh conditions. Certus Semiconductor’s offerings also include a variety of advanced features like RGMII-compliant IO cells, offering flexibility for different project needs.
The Universal DSP Library by Enclustra is designed to simplify digital signal processing across various applications. This library supports users in implementing sophisticated DSP algorithms without needing deep-dive expertise in the field. Its robust features allow for efficient data manipulation and transformation in real-time, making it suitable for high-demand environments. Whether used in audio processing, communications, or industrial signal control, Enclustra's Universal DSP Library delivers consistent performance and adaptability. Integrated with scalability at its core, the DSP Library assists in managing resources efficiently, ensuring optimal use of FPGA capabilities. By providing clear interfaces and components, users can focus on application-specific needs while leveraging the library's powerful processing capabilities. This makes it an ideal choice for businesses looking to optimize DSP workflows without overextending development resources. In addition to its core functionalities, the DSP Library interfaces seamlessly with other Enclustra solutions, which simplifies the integration and maximizes the library's effectiveness. Overall, it offers a flexible platform for realizing DSP projects across multiple tech domains.
Silvaco's Standard Cell Libraries are pivotal in providing fundamental building blocks for digital design, focusing on high-performance and low-power applications. These libraries are highly optimized for advanced FinFET process nodes, accommodating the latest semiconductor trends and design needs. With innovative cell architecture and state-of-the-art layout techniques, they deliver exceptional speed and density benefits necessary for modern digital designs. Leveraging advanced design automation tools, these libraries simplify the design flow by enabling seamless integration into a variety of design environments. They ensure consistent performance and reliability across diverse applications, accommodating a range of customer requirements from high-speed computing to energy-efficient mobile applications. Silvaco’s standard cell libraries are available for multiple process technologies, providing designers with the flexibility they need to optimize for both power and performance. The libraries are further characterized by stringent quality checks and are supported by extensive documentation, which streamlines implementation processes while mitigating risk. Silvaco's attention to detail and commitment to quality assurance ensure that their standard cell libraries consistently meet or exceed industry benchmarks, reinforcing their reputation as a trusted provider of digital design IP solutions.
The APB4 General Purpose Input/Output (GPIO) core is a fully parameterized component designed to provide customizable I/O solutions for designs using the APB4 protocol. It is essential for systems that require a user-defined number of bidirectional IO pins, bringing flexibility to interfacing strategies. This core is adaptable to various applications, allowing for easy integration with existing system architectures. It supports configuration for a wide range of IO operations, ensuring seamless interaction with other peripheral components or external systems. Comprehensive test benches and detailed documentation are provided with this core, aiding developers in quick deployment and efficient implementation, enhancing the functionality of complex systems.
Spectral CustomIP encompasses an expansive suite of specialized memory architectures, tailored for diverse integrated circuit applications. Known for breadth in memory compiler designs, Spectral offers solutions like Binary and Ternary CAMs, various Multi-Ported memories, Low Voltage SRAMs, and advanced cache configurations. These bespoke designs integrate either foundry-standard or custom-designed bit cells providing robust performance across varied operational scenarios. The CustomIP products are engineered for low dynamic power usage and high density, utilizing Spectral’s Memory Development Platform. Available in source code form, these solutions offer users the flexibility to modify designs, adapt them for new technologies, or extend capabilities—facilitating seamless integration within standard CMOS processes or more advanced SOI and embedded Flash processes. Spectral's proprietary SpectralTrak technology enhances CustomIP with precise environmental monitoring, ensuring operational integrity through real-time Process, Voltage, and Temperature adjustments. With options like advanced compiler features, multi-banked architectures, and standalone or compiler instances, Spectral CustomIP suits businesses striving to distinguish their IC offerings with unique, high-performance memory solutions.
The Configurable I/O from SkyeChip is designed to support high-speed signaling needs across various standards such as LVDS, HCSL, POD, SSTL, HSTL, and LVCMOS. Capable of signaling speeds up to 3.2 GT/s, this I/O is adaptable to a range of voltage requirements, enhancing flexibility in design applications. The ability to configure for multiple protocols makes it indispensable for projects demanding versatile integration capabilities, particularly in environments requiring high adaptability without sacrificing speed or performance.
Analog Bits specializes in low power I/O technologies designed with customization for die-to-die communication needs. These I/O solutions, proven efficient with low transistor usage, offer high signal quality specifically at 5nm and with future applications extending into 3nm technology nodes. The customizable differential clocking and crystal oscillator IPs optimize noise levels and energy efficiency in diverse environments, ensuring robust operations in integrated circuits.
Tower Semiconductor offers advanced Non-Volatile Memory (NVM) Solutions that are integral for data retention in electronic systems without continuous power supply. This technology forms the backbone of various memory applications, enabling efficient storage and retrieval of data in systems such as electronic components across automotive, industrial, and consumer sectors. The company's NVM technology is designed to integrate seamlessly with other semiconductor technologies, providing a compact and energy-efficient solution essential for modern electronic devices. It supports applications requiring reliable memory retention, such as in microcontrollers, smart cards, and flash storage devices, thanks to its ability to endure numerous program/erase cycles while maintaining data integrity. In consumer electronics, NVM allows for quick data access and minimal energy consumption, crucial in portable devices like mobile phones and wearables. In automotive sectors, it supports critical data retention even in adverse conditions, ensuring system reliability and enhanced performance across a vehicle's electronics. Tower Semiconductor's approach ensures these NVM solutions are a fitting match for various application needs, supporting innovation and efficiency in data management systems.
Arteris' CodaCache Last-Level Cache IP is meticulously crafted to resolve critical challenges in SoC designs, such as optimizing data access and performance while reducing power consumption. This scalable and configurable cache solution aids in minimizing memory latency, thus enhancing overall data flow efficiency and system performance. CodaCache supports seamless integration into existing SoC environments and provides significant advantages in applications demanding real-time processing capabilities due to its configurable architecture and robust integration features.
The SoC Platform offered by SEMIFIVE is a versatile solution that accelerates the design and development of System-on-Chip (SoC) products. Leveraging domain-specific architecture and a rich pool of silicon-proven IP, this platform is crafted for key applications, ensuring reduced costs and risks while speeding up time-to-market. It provides a pre-configured and verified IP ecosystem that is ready for immediate hardware and software bring-up. One of the platform's standout features is its flexible architecture model, which supports a broad range of applications from AI inference to IoT and high-performance computing. This modular approach enables users to efficiently integrate their unique requirements with a lower non-recurring engineering (NRE) cost, maximizing component reusability and minimizing engineering risks. Additionally, the SoC platform facilitates rapid prototyping by offering a pre-selected and tested range of platform IP pools. These components are silicon-proven, ensuring seamless integration and reliability. With SEMIFIVE’s extensive support and comprehensive solutions, customers can confidently bring their innovative ideas to silicon, backed by state-of-the-art technology and industry expertise.
Dolphin Semiconductor's Foundation IPs are crafted to enhance the efficiency and cost-effectiveness of System-on-Chip (SoC) designs through robust offerings of embedded memories and standard-cell libraries. Specially designed for energy-efficient applications, these components help optimize space and power usage while ensuring the cutting-edge performance of modern electronic devices. Incorporated within Dolphin's Foundation IP portfolio are standard cells that allow chip designers to achieve up to 30% density gains at the cell level, compared to conventional libraries. Further, these components are engineered to support always-on applications with exceptionally low leakage rates. The Foundation IP suite optimizes SoC designs by delivering dramatically reduced leakage and area consumption, avoiding the additional cost and complexity of using a regulator. The memory compilers within Foundation IPs offer ultra-low power and high-density memory solutions, including SRAM and via-programmable ROMs. These are formulated to deliver up to 50% energy savings, providing flexibility with multi-power modes and adaptable to varied instances. With optimization for TSMC processes, Dolphin's Foundation IPs provide an essential backbone for creating innovative, efficient, and sustainable SoC products.
The 1D Optical Micrometers from Riftek Europe are non-contact devices specifically fashioned to measure diameters, gaps, and displacements with exceptional accuracy. They cater to the dimensional measurement needs across a wide range extending from 5 mm to 100 mm, with an impressive measuring accuracy of +/- 0.3 um aided by a sampling rate of 10000 Hz. These micrometers are indispensable in production lines where small part measurement is vital, such as mechanical engineering and electronic component manufacturing. Their high-speed data acquisition and precision allow for dynamic measurement, ensuring that product specifications are consistently met. Their efficient design and robust capabilities provide significant advantages in applications requiring quick and accurate dimensional checks, thereby minimizing manual inspection processes. The integration of this technology supports comprehensive monitoring and control frameworks that enhance overall production quality.
Rabbit 2000 is a pioneering microprocessor suitable for a wide array of applications, featuring 19K gates in its design and occupying 100 pins. It offers a compact and efficient core, well-suited for integrating into systems where space and power are constrained. This processor is foundational in the Rabbit series and demonstrates excellent performance as a standard 8-bit microprocessor. The Rabbit 2000 architecture promotes seamless integration into larger systems with minimal design overhead. It provides a reliable base for developing sophisticated projects that require a blend of processing power and unique peripheral interfaces. The model has been thoroughly proven in silicon, ensuring robustness and reliability from prototype to mass production. This processor also supports various standard interfaces, simplifying the design process for developers needing a versatile processing unit with peripheral connectivity. Its versatile design makes it applicable in numerous applications, from embedded systems to industrial controllers.
Static Random-Access Memory, commonly known as SRAM, is a type of computer memory that uses latching circuitry to store each bit. Its primary feature is its ability to retain data bits in memory as long as power is being supplied. Unlike Dynamic Random-Access Memory (DRAM), which needs periodic refreshing, SRAM does not require refreshing, making it faster and more reliable for certain applications. SRAM is designed to perform read and write operations at a faster rate, often used in applications where speed is critical. It is typically employed in cache memory and other high-speed storage solutions. The architecture of SRAM includes a series of transistors arranged in a way that data is maintained in a stable state, allowing swift access and modification. This type of memory is commonly found in applications where performance and reliability are more important than capacity. SRAM's swift access time and its ability to be used at high speeds make it ideal for use in processors, networking applications, and in various embedded systems requiring rapid data access and processing capabilities.
The Absolute Linear Position Sensors developed by Riftek Europe are precision instruments designed to measure and check displacements, dimensions, and surface profiles. Utilizing absolute linear encoder technology, these sensors promise an innovative approach to absolute measurement over ranges of 3 mm to 55 mm with a resolution of 0.1 um. These sensors address the demand for accurate measurement within manufacturing environments, ensuring that the run-outs and deformations are controlled to enhance product quality. They are built for reliability, delivering robust performance in challenging industrial conditions where precision is a crucial aspect of equipment and product assembly. Engineered to provide real-time feedback, these sensors aid in automating quality checks and maintaining operational efficiencies. They offer manufacturers the ability to optimize processes and reduce errors, further promoting productivity and reducing material wastage due to inaccurate measurement during production.
XMOS's xcore-200 is an advanced processor that excels in delivering multichannel audio processing and low-latency performance. Designed to support complex audio and voice processing requirements, it provides developers with the ability to integrate high-quality audio functionalities into their products. The xcore-200's architecture is engineered to allow precise control and processing capabilities, making it ideal for applications in consumer electronics and professional audio equipment. With an emphasis on reducing development time and enhancing product capabilities, the xcore-200 offers an adaptable solution equipped with an array of input and output options to meet diverse processing needs. Its powerful DSP capabilities ensure efficient processing of audio signals, enabling smoother, more reliable audio experiences for end-users. Moreover, the xcore-200 is optimized for power efficiency, supporting a range of applications without significant energy expenditure. The xcore-200 facilitates seamless integration with other technologies, making it a versatile choice for developers who need flexibility in their design process. Whether it's embedded AI functionalities or advanced audio processing demands, the xcore-200 provides a comprehensive platform for building sophisticated digital audio systems. Its capacity to manage multiple processing tasks concurrently ensures that products powered by this processor deliver robust and high-performance outcomes.
X-REL is EASii IC’s line of semiconductor products explicitly tailored for extreme environments, featuring extraordinary reliability at temperatures ranging from -60°C to +230°C. These high-reliability components address the rigorous demands across sectors like oil and gas, geothermal energy, aerospace, and automotive. Available in various packages, including ceramic, metal, and, for less constrained environments, plastic, X-REL products offer extended life with minimum system cost. These components are engineered to fulfill the need for continuous operation under severe conditions, delivering five years of guaranteed reliability. X-REL’s diverse lineup encompasses power management solutions, clock and timing circuits, discrete transistors and diodes, and interfaces. The robust performance of these components, coupled with certifications like ISO9001 and EN9100, underscores their suitability for mission-critical applications, where traditional designs may falter due to adverse heat and stress.
Riftek Europe’s 2D Optical Micrometers are designed for batch in-line dimensional measurement, offering a sophisticated solution for industries demanding precision in wire and rod measurements. The measurement scope of these micrometers spans from 8x10 mm to 60x80 mm, with outstanding accuracy up to +/-0.5 um, making them suitable for high-precision industries. These micrometers expedite measurement tasks in industrial environments, reducing manual work by automating the dimensional analysis of numerous components rapidly. By employing advanced optoelectronic technology, these devices simplify the acquisition of precise dimensional characteristics across multiple parameters. The real-time data collection capability of these devices supports seamless integration into assembly lines, enabling consistent measurement that reduces defects and assures high manufacturing standards. This contributes significantly to improving efficiency and operational throughput, aligning with the demands of fast-paced production environments.
Rezonent's Compute-in-Memory Technology fuses computational and memory functionalities within a single architecture to enhance processing speed and reduce power consumption. This innovative technology minimizes data movement between memory and the processor, which significantly speeds up data-intensive tasks and dramatically lowers energy usage. By utilizing sophisticated data encoding techniques, the technology optimizes storage and retrieval processes, making it ideal for AI and machine learning applications. Designed to excel in scenarios that require rapid data processing and efficient power management, Compute-in-Memory Technology addresses practical challenges faced by data centers and IoT devices. This technology effectively supports the burgeoning demand for faster processing in edge computing, where power efficiency is paramount. Its architecture is adaptable, allowing deployment across various systems, from conventional servers to cutting-edge AI models. Moreover, its integration into semiconductor designs ensures backward compatibility, offering enhanced performance without drastic changes to existing infrastructure. As data demands continue to rise, Rezonent's technology provides a scalable solution that meets the needs of modern computing applications, delivering both speed and sustainability.
MiniMiser articulates a revolutionary multi-port register file architecture designed with dual focuses on both low power and high performance. This product delivers over 50% reduction in power consumption, allowing developers to finely tune the power envelope through substituted standard register files with MiniMiser. Such power-saving measures help extend the design's practicality in spaces traditionally constrained by power budgets. With its stress on wide operating voltages and flexibility, MiniMiser effectively replaces standard bit cell implementations without the need for excessive clock domain adjustments, level shifters, or static timing analyses. It operates seamlessly in high-density environments where logic blocks interface and interim calculation storage is necessary, making it integral for AI-enhanced wearables. The product's architecture adapts to multiple performance modes assigning them to varying voltage levels, which keeps instantaneous power demands and total power use in check more effectively. Through these enhancements, MiniMiser innovatively cap size and energy requisites while improving the system's competitive sustainability via elongated recharge cycles and reduced thermal management overhead.
PQSecure's Cryptographic Core serves as a comprehensive solution for implementing standardized cryptographic algorithms within system-on-chip (SoC) designs. This product is tailored for diverse applications, ranging from high-end servers to low-end embedded systems, ensuring broad compatibility. It effectively offloads both symmetric and asymmetric cryptographic operations, boosting execution efficiency. The core includes hardware accelerators capable of performing various cryptographic functions, such as true random number generation and classical public key cryptographic algorithms like ECDSA and ECDH. Incorporating next-generation post-quantum cryptographic methods, this core tackles the imminent threats posed by quantum computing. By supporting isogeny-based, lattice-based, and code-based cryptographies, it prepares systems for the quantum evolution. Furthermore, this Cryptographic Core supports secure hashing algorithms and a variety of advanced encryption standards, ensuring robust protection across different security levels recommended by standardization bodies. As an embodiment of both agility and security, it integrates seamlessly into various SoC and FPGA architectures, providing substantial power reductions compared to traditional software implementations. Designed with future-proofing in mind, PQSecure's Cryptographic Core features optional side-channel protection mechanisms validated by standard techniques, delivering DPA countermeasures without significant overhead. It boasts a comprehensive suite of verification tools, including test benches and simulation scripts, making integration into existing systems both easy and efficient. With customizable performance profiles, the Cryptographic Core is engineered to meet the demanding security requirements of tomorrow's digital environments.
The Security Protocol Accelerator from PQSecure is a pivotal component in enhancing the performance of cryptographic operations within embedded systems and processors. This accelerator facilitates the efficient execution of security protocols, such as post-quantum cryptographic algorithms, providing hardware-accelerated computation to offload intensive tasks from the main CPU. PQSecure's accelerator design focuses on optimizing the speed and efficiency of complex cryptographic tasks, including key exchange operations, digital signatures, and hashing. It is engineered to support a broad spectrum of cryptographic standards while maintaining configurability for various security and performance levels. This product stands out due to its ability to integrate seamlessly into various processor architectures and its compatibility with existing SoC and FPGA platforms. Key features of the Security Protocol Accelerator include customizable performance settings and support for both classical and post-quantum cryptographic operations. It provides significant improvements in power efficiency and computational speed, ensuring systems are prepared for future quantum challenges. With available side-channel attack countermeasures, this accelerator not only secures data but also mitigates potential vulnerabilities common in cryptographic implementations.
Our Embedded ReRAM technology empowers seamless integration into existing system-on-chip (SoC) designs, delivering a compact, efficient memory solution. Designed to cater to the needs of modern electronics, it provides significant advancements in speed and power efficiency over traditional non-volatile memory (NVM) options. With the ability to operate reliably under diverse environmental conditions, this embedded solution is ideal for a wide range of applications including IoT devices, automotive systems, and smarter consumer electronics. One of the standout features of Embedded ReRAM is its eco-friendliness and scalability. Despite being embedded, it ensures a minimal footprint while maintaining high performance, making it a favorable choice for future-proof designs. This technology is engineered to enhance data retention and withstand the rigors of extreme operational environments, reinforcing its suitability for automotive and aerospace applications. The innovation behind Embedded ReRAM focuses on delivering a combination of low-power operation and high-speed performance, overcoming the limitations associated with traditional flash memory. This makes it an exceptionally versatile component in designing edge computing solutions and energy-efficient AI hardware, driving forward the evolution of next-gen intelligent devices.
This library is a production-quality, silicon-proven I/O library in TSMC 12nm technology. Supports multi-voltage GPIOs, capable of operating at 1.8V or 3.3V, dynamically selectable at the system level. Also included are various open-drain I/Os and hot plug detects capable of up to 5V operation. The library also includes a wide-variety of low-capacitance RF and analog ESD. There have operating ranges from 0 to 5V protection and support a wide range of high-performance interfaces including HDMI, LVDS, USB and wireless front-ends. Also included is a range of IEC 61000-4-2 system-level ESD protection that supports digital and analog I/O cells.
The Intelligent Sensor and Power Management Platform (ISP) by IQonIC Works provides a comprehensive foundation for developing sensor and power-efficient IoT applications. This platform integrates pre-assembled subsystems and design blocks for reduced time to market and development cost. Focusing on energy efficiency, the platform offers multiple power modes for optimal energy management, including low-power modes tailored for battery and energy-harvesting applications. The inclusion of adaptable analog front ends and signal processing caters to diverse sensing needs, making it suitable for a wide range of applications. The ISP supports a variety of MCU cores and peripheral IPs, facilitating flexible integration in various system configurations. It also engages a virtual testing environment for early prototyping, ensuring robust development and validation processes before final deployment.
Key ASIC offers a comprehensive range of fundamental semiconductor intellectual property solutions. Their collection includes general purpose I/O libraries, standard cell libraries, SRAM, register file, and ROM compilers. These fundamental components are crucial for a wide variety of electronic applications, providing the building blocks for more complex circuit designs. Their portfolio has been crafted to ensure maximum performance and compatibility across a wide span of uses, reflecting Key ASIC's commitment to foundational technology development. In addition to standard I/O offerings, Key ASIC has developed high-voltage I/O libraries and programmable logic components to meet specific application needs. Their solutions are designed for scalability and adaptability, ensuring that clients can leverage these foundational IP offerings across different platforms and technologies. By providing these essential IP building blocks, Key ASIC facilitates the development of complex and efficient electronic systems. The company's extensive selection of foundational IP underscores its focus on enhancing design flexibility and integration efficiency, which are crucial factors for customers seeking to optimize their design and manufacturing processes. Key ASIC continues to innovate in this field, ensuring their clients have access to the latest developments in semiconductor technologies.
The Quazar Quad Partition Rate Memories are designed to support the next generation of high-speed, low-latency, and high-bandwidth random access memory applications. The Quazar architecture allows a single memory IC to replace multiple QDRs, providing high capacity and simplified design integration within FPGA systems. This memory solution offers flexibility through its operational modes: DEEP mode, which configures memory access as four independent SRAMs, and WIDE mode, which configures as eight independent SRAMs, enabling dynamic memory partitioning. Each Quazar IC features a high capacity of either 576Mb or 1Gb, with operational modes that improve system bandwidth and reduce board complexity by utilizing fewer serial SERDES connections. This leads to lower costs and simpler board designs. The use of dual-port memory supports advanced applications where high throughput and data integrity are paramount, such as network switches and data planes. The Quazar memory systems greatly enhance system-level performance by offering increased memory bandwidth and simplified FPGA interfacing through the MoSys-supplied RTL Memory Controller. This controller ensures efficient management of high-speed SERDES interfaces while maintaining system integrity, positioning the Quazar memory as an ideal replacement for traditional QDR memory configurations.
The Foundation IP suite by InPsytech consists of essential components crucial for building sophisticated semiconductor designs. It includes standard cells, memory compilers, and I/O interfaces that form the foundational elements of integrated circuits. Each component is meticulously designed to ensure high performance, low power consumption, and robust reliability. Standard cells within the Foundation IP are designed to optimize space and performance in IC layouts, while memory compilers offer scalable and efficient solutions for memory integration. I/O interfaces within the suite are made to ensure seamless communication across different chip components, supporting wide-ranging application needs. The Foundation IP solutions are tailored for maximal compatibility across various manufacturing processes and technologies, ensuring that semiconductor designers can achieve the highest levels of efficiency and innovation in their products. These fundamental building blocks lay the groundwork for more advanced functionality and performance in semiconductor devices.
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The BCH Encoder/Decoder core from IP-Maker is essential for mitigating errors in NAND Flash memory, thus extending the lifetime and reliability of storage devices. Built on the powerful BCH algorithm, this IP core is fully customizable based on application-specific needs, from consuming minimal resources to optimizing latency. By offering support for up to 84 error-bits per block and configurable block sizes, it ensures robust data protection across varied storage environments. The IPM-BCH benefits from a well-balanced performance and gate count, making it suitable for high-performance NAND Flash-based applications.
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SuperMTP® is a high-performance embedded non-volatile memory (eNVM) solution, known for its robustness and reliability. Designed for seamless integration into a variety of electronic devices, SuperMTP® can store significant data volumes without compromising on speed or efficiency. This eNVM IP is ideal for applications that require both endurance and data retention, such as in automotive and industrial devices where data integrity is crucial. The SuperMTP® technology allows for multiple program/erase cycles, ensuring that it meets the demanding needs of modern electronic systems. Its architecture is optimized for energy efficiency, making it a suitable choice for battery-operated devices. By offering high-speed data programming and retrieval, SuperMTP® enhances the overall performance and reliability of the host device. Actt’s SuperMTP® has been tailored to provide excellent performance in adverse conditions, holding up against variations in environmental and operational factors. The solution’s reliability makes it a preferred choice for designers focused on developing durable and long-lasting electronic products.
This library is a production-ready I/O library built on the TSMC 12nm process. The library features 1.8V to 3.3V GPIOs with programmable drive strength, hysteresis, and control logic. It includes support cells for all power domains: 0.8V, 1.8V, and I/O and incorporates latch-up immune, JEDEC-compliant ESD structures. The library is designed for flip-chip packaging and includes vertical and horizontal variants to support all die edge orientations. All power domains include integrated power-on control (POC) cells for safe and reliable sequencing.
This is an ultra-low leakage library. The GPIO has a typical leakage of only 150pA from VDDIO and 1nA from VDD. The library has a GPIO and an ODIO. The GPIO cell set can be configured as input or output and has an internal 50K ohm pull-up or pull-down resistor. Cells for I/O and core power and ground with built-in ESD circuitry are included. A power-on-control circuit is integrated into an available VDDIO cell. The library includes pads for analog signals and a 6.5V one-time-programming voltage. The GPIO can do TX and RX up to 100MHz. The ODIO is I2C compliant. ESD targets are 2KV HBM / 500V CDM with 2KV IEC 61000-4-2 system stress capability.
This is an ultra-low leakage library. The GPIO has a worst-case leakage of only 425nA. It works with a wide VDDIO supply range from 1.8V to 3.3V during system operation without the need for the customer to manually switch between high and low-voltage modes. The GPIO cell set can be configured as input or output and has an internal 50K ohm pull-up or pull-down resistor. It has a sleep function which - when enabled - puts the I/O into an ultra-low power state and latches the I/O in the previous state. Cells for I/O, core power, and ground with built-in ESD circuitry are included. A power-on-control circuit is integrated into an available VDDIO cell. The GPIO can do TX and RX up to 150MHz. ESD targets are 2KV HBM / 500V CDM with 2KV IEC 61000-4-2 system stress capability.
This silicon-proven TSMC 28nm Digital I/O Library delivers a low-capacitance, high-reliability interface solution optimized for advanced semiconductor applications. Featuring low-capacitance LVDS differential pairs (<250fF per pin) at 0.8V, this library ensures superior signal integrity for high-speed applications. The I/O macro seamlessly integrates with the TSMC 1.0V I/O Library, sharing a compatible VDDA and VSSA bus structure for streamlined power management. Designed with a 14-bondpad ESD macro, including two differential pairs and dedicated power/ground cells, it provides a robust 0.8V VDDA power domain with a 0V ground reference. Engineered for reliability, the library avoids minimum-width metal traces and adheres to enhanced via/contact recommendations for long-term durability. With Cadence OA database compatibility, the library supports Spectre and auCdl views, enabling seamless simulation, LVS verification, and integration into standard design flows.
This library is a mixed Digital and Analog library built for the TSMC 65nm process. It is based around a Fail-Safe General Purpose Input/Output (FSGPIO) cell that is compatible with both I2C and I3C protocols. The FSGPIO operates with a power supply of 1.0 to 1.2V and can tolerate external signals up to 3.3V. The library contains all the power, ground, and ESD cells to support the FSGPIO as well as an Analog I/O cell. The cells are laid out in an inline wirebond format.
This silicon-proven, flip chip library in TSMC 22nm boasts three variants of GPIOs and one ODIO. All GPIO and ODIO cells have NS and EW orientation. All GPIO types are classified based on speed: 25MHz, 75MHz and 150MHz. All GPIO speed variants can operate at different post-driver voltage, which can be set at the system level and dynamically changed in the system if needed. The I/O includes a weak pull-up or pull-down resistor (approx. 60 Ohms). The ODIO is designed for lower speed interfaces but can be used as a high-voltage, high-speed input at up to 100MHz. The library is designed to allow for independent power sequences of any I/O cell, which is accomplished with an intrinsic power-on-control architecture. In the case of GPIO and ODIO, only when all powers are up and detected as ON, will the I/Os begin to function, otherwise they will remain in a high impedance state. Beyond standard ESD protection, the library is tolerant to 61000-4-2 IEC standard to 2kV.
This radiation-hardened, by design, library features both a 1.8 and 3.3V GPIO with multiple drive strengths of 2mA, 4mA, 8mA, and 16mA, along with a full-speed output enable function. The library includes an LDO to generate a 1.8V reference which has been optimized for use with the 3.3V GPIO. The library incorporates radiation-hardened ESD cells, which are silicon-proven. A fail-safe GPI allows user to interface with bus-type protocols like I2C. All cells support independent power sequencing and integrate power-on-control circuitry for a clean low-leakage power-up. A selectable Schmitt trigger receiver adds input flexibility, while a 50K ohm pull-up or pull-down resistor is available for termination configurations. The library is enriched with feed-through, filler, transition, and domain-break cells to allow for flexible pad ring construction while maintaining ESD robustness. ESD targets are 2KV HBM / 500V CDM with 2KV IEC 61000-4-2 system stress capability.
This silicon-proven, I/O Library features a 5V General Purpose I/O, 5V Open-Drain I/O, 5V Analog I/O, 5V Power Supply and an area efficient 5V ESD protection scheme. The functional cells in the library (GPIO & ODIO) feature an Output Enable pin which, when de-asserted, place the I/O in a HiZ state, and can control multiple modes of output operation with the Output Mode Control pins. The input RX path for this library all have selectable operations between a Schmitt trigger input with hysteresis, a standard buffer with no hysteresis, and a low input voltage mode that can receive a voltage level much lower than the I/O supply without causing metastability or large leakage current. The library has no poly orientation limitations and can be used in any orientation. The library cells are only built up to metal three, but include an metal 4 pad anchor that can be overlaid with either a wirebond or connected to a BUMP. ESD design level are 2kV HBM, 500V CDM and +/-125mA Latch-up.
This library is a production-quality, silicon-proven I/O library in GlobalFoundries 65/55nm technology. The library offers a 3.3V GPIO with two selectable inputs, slew rate control, and an optional active tri-state, as well as a GPIO with an ultra-wide supply range and an optional glitch filter. The library also includes a 1.2V ODIO with two slew rate options as well as a 3.3V ODIO with a 5V tolerance. All I/Os have highly programmable POC options and active pull up/down. The library is compliant with ANSI/JEDEC/ESDA JS-001-2014 ESD standards.
A key attribute of this library is its ability to detect and dynamically adjust to a VDDIO supply of 1.8V or 3.3V during system operation. The GPIO cell can be configured as input, output, open source, or open drain with an optional internal 50K ohm pull up or pull down resistor. Four selectable drive strengths are offered (25 235MHz @ 1.8V, 10pF) to optimize across SS) currents & power. The output driver exhibits 50 ((20%) termination across PVT to reduce reflections at higher operating frequencies. Supply cells for VDDIO, VREF, and core VDD include necessary built in ESD circuitry. A 5VI2C / SMBUS open drain (fail safe) cell, 5V OTP, programming gate cell and 1.8V & 3.3V analog cells with ESD protection are included. The library features protection break cells to allow for separate grounds while maintaining ESD robustness. ESD design targets 2kV HBM, & 50 0V CDM, yet this library has constantly demonstrated 4kV HBM. This library can also support 2kV IEC 6100-4-2 system ESD with appropriate integration.
This flip-chip compatible library in Dongbu HiTek 130nm features a fail-safe GPIO, two standard GPIOs, a 5V GPI, and 5V I2C-compliant ODIO. The GFGPIO is a highly configurable 5V tolerant, multi-voltage, multi=-protocol I/O. The standard GPIO, both regular and reduced footprint, in this library is a highly configurable 5V tolerant, multi-voltage, multi-protocol I/O. The library’s GPI is a highly configurable general-purpose input cell which features three selectable input modes, three selectable resistive termination options, and a wide supply range. The library’s ODIO is a 5V I2C-compliant ODIO which features standard mode, fast-mode, and fast-mode plus, as well as selectable input modes, drive strength control and robust 2kV HBM protection. The library also supports I3C, SPI and QSPI standards. The library includes all layout and support cells. ESD targets are 2kV HBM and 500V CDM.
This silicon-proven Wirebond compatible library in Dongbu HiTek 110nm features a multi-voltage, multi-standard General Purpose Input Output with an Open-Drain Input Output capability, that targets the I2C standard. The library is built as a Fail- Safe I/O design. There is no poly-orientation for this library. The library features an Analog Mux, which allows for core direct access to the bondpad, either to drive externally a signal or receive a signal from the PAD. The I/O Library is compliant with standards regarding all 1.2V, 1.8V, and 3.3V operation. The library can support various standards, including I3C, I2C, SPI and QSPI. ESD targets are 2kV HMB and 500V CDM.
This I/O Library, developed on GlobalFoundries 55nm CMOS, delivers a complete suite of digital and analog I/O solutions with robust 2 kV HBM / 500 V CDM ESD protection and latch-up immunity. The library includes 1.83.3 V GPIOs supporting GMII and LVCMOS standards, I2C-compliant ODIOs, and flexible analog I/Os (ANA/DANA) with integrated ESD. Complemented by a full set of power, filler, corner, and transition cells, the VZ55 library enables reliable padring construction across mixed-signal designs. With wide voltage support, industrial temperature range (-40C to 125C), and cross-domain ESD protection, VZ55 provides a scalable, production-ready I/O platform for advanced SoC integration.
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