Suite-Q HW is a comprehensive system-on-chip (SoC) design crafted to provide a complete suite of standardized cryptographic operations essential for securing communication protocols. Targeting both high-end servers and low-end embedded systems, this design leverages the same hardware accelerators but differs in processor core choices and connectivity solutions to cater to varied application needs. By offloading symmetric and asymmetric cryptographic operations, Suite-Q HW enhances execution efficiency while integrating features such as the NIST 800-90-compliant True Random Number Generator.
Classical and post-quantum public key cryptographic support is provided, encompassing a range of protocols such as ECDSA, Ed25519, and Curve25519, alongside emerging post-quantum methodologies like isogeny-based and lattice-based cryptography. Furthermore, it supports hash-based signature protocols including XMSS and LMS, and integrates the Advanced Encryption Standard for versatile encryption needs. This SoC design is crafted to simplify integration into SoC and FPGA architectures while offering various performance grades to balance silicon footprint and overall performance.
Beyond its seamless integration capability, Suite-Q HW demonstrates substantial power reductions compared to software implementations, making it a suitable choice for power-sensitive applications. Comprehensive validation tests, including known answer test vectors and simulation scripts, ensure reliability and integration efficiency.
