The Non-Coherent Network-on-Chip (NOC) offers a performance-centric interconnect solution designed to optimize bandwidth and latency while minimizing silicon wire utilization. This results in power and area-efficient IC designs. It supports a wide range of protocols including AXI4, AXI5, and APB, along with proprietary protocols, ensuring compatibility across various system architectures.
This NOC is crafted for high frequency operation, handling up to 2GHz across source synchronous and synchronous clocking topologies. It has been architected to significantly reduce routing congestion, thus facilitating easier high-frequency timing closure in complex multi-core systems.
Furthermore, it seamlessly integrates with SkyeChip’s Coherent NOC, enabling efficient interconnect systems suitable for hybrid configurations. The NOC is also compatible with 2.5D and 3D die-to-die NOC bridging, providing comprehensive scalability for advanced semiconductor solutions.
