The HBM3 PHY & Memory Controller is optimized for AI, HPC, data centers, and networking, conforming to the HBM3 (JESD238A) JEDEC standards. This solution provides a comprehensive PHY and Controller package delivering an average random efficiency exceeding 85%. It supports data rates up to 6400 MT/s for HBM3 and up to 9600 MT/s for HBM3E. Additionally, it features flexible PHY architecture with programmable interface training sequences to customize memory vendor interactions.
The design accommodates up to 32Gb per die and supports 16H HBM3 DRAM stacks, being compatible with major 2.5D and 3D packaging technologies. This solution also integrates features for MPFE, RAS, and Debug, making it adaptable for complex design environments. Additional capabilities include support for 2.5D die-to-die interconnects, enhancing its versatility in multi-die configurations.
