Aimed at high-speed data communication, the Aurora 64B/66B protocol supports chip-to-chip, board-to-board, and backplane applications. ALSE's implementation of the Aurora 64B/66B Core is notable for its compact and optimized design, offering increased compatibility and functionality without the trade-offs commonly seen in other designs. Fully interoperable with Xilinx IP cores, it has been thoroughly tested to ensure seamless integration across multiple platforms.
One of the key advantages of the 64B/66B encoding is the improved bandwidth efficiency — up to 97% in comparison to 8B/10B's 80%. This provides an effective means for intra-board communications at higher rates, making it indispensable for cutting-edge applications and next-gen systems. Designed for FPGA platforms ranging from Intel's Stratix devices to Lattice's PolarFire, it has proven to be versatile for varied design needs, ensuring that the IP can cater to both FPGA and ASIC environments.
Supporting up to 16 lanes per instance, the IP includes features such as full-duplex operation, framing and streaming interfaces, and native flow control. These capabilities make it an excellent choice for systems looking to leverage high-speed serial data paths efficiently. Incorporating reliability and performance, the Aurora 64B/66B Core stands as a valuable asset in modern high-demand data environments.
