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All IPs > Interface Controller & PHY > PCI > 700Mbps Sub-LVDS Rx PHY

700Mbps Sub-LVDS Rx PHY

From Leo LSI Co., Ltd.

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Description

The 700Mbps Sub-LVDS Rx PHY is engineered for high data rate receivers, capable of supporting up to 700Mbps per lane, which equals a total throughput of 5.6Gbps across its eight data lanes. This capability makes it an excellent choice for applications requiring significant data bandwidth.

The PHY supports dual power supply operations at 1.2V and 1.8V, allowing for compatibility with a range of systems. It features selectable multi-level common-mode applications with rail-to-rail receiver capability. The internal termination resistors support wide input signal range while maintaining signal integrity.

Additional features include lane data and clock delay control with manual skew adjustment settings, ensuring optimal performance even in demanding environments. Its parallel data output is configurable to 8, 10, 12, 14, or 16 bits, allowing for versatility in data connection setups.

Features
  • Rail to rail receiver
  • 100ohm input termination resistors
Tech Specs
Class Value
Categories Interface Controller & PHY > PCI
Interface Controller & PHY > PCMCIA
Interface Controller & PHY > SAS
Interface Controller & PHY > RapidIO
Interface Controller & PHY > MIPI
Interface Controller & PHY > AMBA AHB / APB/ AXI
Data rate per lane 700Mbps (350MHz DDR)
Selectable bit parallel data output 8/10/12/14/16 bit
Supply Voltage 1.2V and 1.8V
Availability All Countries & Regions
Applications
  • Telecommunications
  • High-bandwidth data systems
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