Is this your business? Claim it to manage your IP and profile
LeWiz's Time Sensitive Network IP Core is engineered for fault-tolerant networking with precise data handling capabilities. Scalable from 1Gbps to 10Gbps, it integrates features like babbling protection and anti-masquerading to maintain network integrity and security. By utilizing the AXI standard, it offers a user-friendly interface for hardware and software implementations. This IP core is crucial for applications that require synchronized data transmission with minimal latency, such as in automotive and industrial IoT environments.
The Radiation Hardened eFPGA technology by LeWiz is a cutting-edge solution designed for environments requiring high reliability and protection against radiation effects. This self-correcting FPGA technology features a scalable Look-Up Table (LUT) array that is both protected and extendable. The inclusion of multi-configuration methods enhances its adaptability, making it ideal for aerospace and other mission-critical applications where radiation exposure is a concern. This technology emphasizes reliability, ensuring continued operation even in challenging conditions such as outer space.
The Programmable TCP Offload Engine (TOE) by LeWiz is designed to acceleraate TCP/UDP/IP processing, eliminating the need for extensive CPU involvement by offloading these tasks to specialized hardware. This not only boosts system throughput but retains the ease of use associated with the traditional TCP/IP socket programming interface. By offering performance from 1Gbps to 10Gbps with customizable options, this TOE is ideal for applications that demand high-speed data transfer while minimizing CPU load, such as large-scale server environments and high-frequency trading platforms.
LeWiz's Low Latency IP Cores are designed for applications requiring rapid data processing with minimal delay. These cores are ideal for both FPGA and ASIC deployments, particularly in high-frequency trading environments where every microsecond counts. By optimizing the design for low latency, these IP cores enable financial markets and other fast-paced industries to gain real-time insights and execute trades with exceptional speed, ensuring competitive advantage and efficiency. Their adaptability and performance are integral to high-performance computing tasks where speed is critical.
This 10G Ethernet MAC solution from LeWiz offers an ultra-low-latency path without requiring an external PHY, making it a streamlined choice for high-performance networking applications. Designed to deliver exceptional speed and efficiency in data transmission, this IP core is particularly geared towards environments where low latency and high throughput are critical, such as financial trading platforms and next-generation data centers.
The AXI-Lite I2C Controller Core simplifies I2C communication with a 32-bit AXI-Lite interface for FPGA and ASIC applications. It is designed to offer simple, register-based communication, ensuring efficient data transfer between master and slave devices over the I2C bus. This IP core enhances compatibility across various applications requiring reliable and straightforward I2C interfacing, making it an essential component for embedded systems and smart device applications.
The AXI4 Memory Controller by LeWiz is engineered to maximize on-chip memory performance, supporting various burst types including FIXED, INCR, and WRAP. It facilitates simultaneous read and write operations, optimizing throughput for program execution and data storage tasks. This controller is integral for applications demanding high-performance memory mapping and is especially effective in systems requiring robust data handling capabilities like high-speed computing and intensive processing environments.
The HBM Memory Controller encompasses advanced fault-tolerant and high-bandwidth memory solutions. It is designed with a multi-channel architecture to offer optimal data parallelism, supporting both NOC and AXI-stream interfaces. This controller is compatible with HBM devices and provides integrated support for DDR ECC, memory scrubbing, and triple modular redundancy (TMR), ensuring data integrity and reliability in high-performance applications. It is especially suitable for systems that demand robust memory management capabilities, such as in aerospace and other critical sectors.
The Time Triggered Ethernet Core is a high-reliability network solution conforming to the SAE Time-Triggered Ethernet standards. It is designed for applications requiring high accuracy and fault tolerance, making it suitable for aerospace and space missions. The core uses a well-known AXI interface and allows configuration of multiple virtual links or streams, facilitating complex and time-critical data processes with ease. This adaptability is vital for maintaining stringent operational standards in dynamic environments.
Join the world's most advanced semiconductor IP marketplace!
It's free, and you'll get all the tools you need to discover IP, meet vendors and manage your IP workflow!
No credit card or payment details required.
Join the world's most advanced AI-powered semiconductor IP marketplace!
It's free, and you'll get all the tools you need to advertise and discover semiconductor IP, keep up-to-date with the latest semiconductor news and more!
Plus we'll send you our free weekly report on the semiconductor industry and the latest IP launches!
To evaluate IP you need to be logged into a buyer profile. Select a profile below, or create a new buyer profile for your company.
