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The logiCVC-ML is a compact multilayer video controller tailored for advanced display control of TFT LCD displays, offering resolutions up to 2048x2048. It is particularly optimized for implementation within AMD Zynq 7000 AP SoC and FPGA platforms. This IP core supports multiple operating systems, including Linux, Android, and Windows Embedded Compact 7, thereby fostering a versatile application landscape for system designers.
The logiVIEW IP core is a sophisticated video and image processing solution that corrects fish-eye lens distortions and performs arbitrary homographic transformations. It also enables video texturing on curved surfaces and allows for image stitching from multiple video inputs. This versatile IP is crucial for enhancing video imagery quality in applications where multiple viewpoints or perspectives are required, such as in advanced automotive systems and 3D imaging setups.
The logiMEM provides a size-optimized, flexible memory controller solution for DDR3 SDRAMs compatible with AMD Series 7 FPGAs/SoCs. Its parametric and synthesizable design supports industry-standard DDR3 memory modules, enabling efficient memory management in high-performance computing environments.
The logiWIN IP core facilitates the integration of high-performance frame grabbers for real-time video processing in AMD FPGA systems. It ensures superior picture quality, making it indispensable for applications that require high-quality video input and processing. This core empowers users to seamlessly capture and process complex video signals, significantly enhancing the functionality of video-based applications.
Enabling smooth inter-chip communication, the logiSPI controller bridge connects microcontrollers with AMD FPGAs and Zynq 7000 SoCs using the Serial Peripheral Interface (SPI) bus. It facilitates efficient data exchange at the board level, proving essential for designs that necessitate robust interfacing of multiple chip components.
The logiHSSL controller supports Infineon’s High Speed Serial Link (HSSL), integrating functionality and security of Infineon's AURIX family with AMD programmable devices. This IP core allows developers to leverage a wide range of AMD's programmable capabilities while ensuring safety in microcontroller-based designs, making it pivotal in automotive and industrial applications.
The logiREF-ACAP-MULTICAM-ISP framework facilitates the development of ACAP-based multi-camera systems using AMD's Versal Adaptive Compute Acceleration Platform. With this framework, users can efficiently manage multi-camera vision systems by providing optimized hardware platforms and frameworks that meet diverse design and functional needs.
The logiISP-UHD provides an advanced ultra-high-definition video pipeline, supporting resolutions such as 4K2Kp60, tailored for enhancing image quality in digital processing. Optimized for AMD Zynq UltraScale+ MPSoC, Zynq 7000 AP SoC, and newer FPGA devices, this IP core is particularly designed for embedded applications requiring superior video input processing and quality enhancement.
The logiJPGD is designed as a multi-channel MJPEG decoder, compliant with JPEG standard Baseline DCT for still images and video decompression. Capable of processing up to four HD video inputs simultaneously, this IP core facilitates video over IP applications, efficiently managing complex data streams and ensuring high-quality output in demanding environments.
The logiHDR pipeline is designed to optimize camera image quality by extracting the fullest detail from high-contrast scenes. Capable of processing ultra-high-definition (UHD) content, including 4K2Kp60, it enhances elements in scenes affected by bright sunlight or deep shadows, making it ideal for use in environments that require excellent image clarity and contrast.
The logi3D Graphics Accelerator is engineered for AMD Versal Adaptive SoC and Zynq 7000 SoC platforms, offering robust support for industry-standard APIs for 3D graphics rendering. This IP core is essential for applications that demand high-quality 3D visualization, such as gaming, simulation, and advanced graphic processing in automotive systems.
This comprehensive IP design framework is optimized for use with Xylon's logiVID-ZU vision kit, leveraging the AMD Zynq UltraScale+ MPSoC. By delivering pre-verified camera-to-display reference designs, it significantly expedites design processes, allowing developers to focus on application-specific enhancements in fields such as AD/ADAS, machine vision, and robotics.
The logiI2S transmitter/receiver IP core facilitates audio data exchange over the Inter-IC Sound (I2S) standard, compatible with AMD FPGAs and Zynq 7000 SoCs. This IP ensures the seamless transmission and reception of digital audio data, forming a reliable backbone for multimedia and audio processing applications.
Providing MOST connectivity for multimedia transport, the logiMLB enhances AMD FPGAs with capabilities crucial for automotive infotainment systems. This IP core ensures efficient multimedia data exchange in complex vehicle architectures, supporting the seamless integration of diverse in-vehicle systems.
Designed to alleviate processing burdens from the CPU, the logiBITBLT provides a powerful 2D graphics acceleration solution, boosting graphic generation capabilities within AMD FPGA and Zynq 7000 SoC environments. It enables the development of visually appealing graphics while optimizing system performance, integral for modern graphical interfaces.
Designed for multi-camera applications, the logiREF-MULTICAM-ISP framework processes multiple Ultra HD video inputs across various AMD devices, from small Artix FPGAs to advanced Versal Adaptive Computing platforms. This framework provides the foundation for developing sophisticated vision systems, enabling seamless integration and processing of multi-source video feeds.
The logiCLK is a sophisticated clock generator IP for use with AMD Zynq 7000 AP SoC and FPGA devices, featuring frequency synthesis, deskew capabilities, and jitter reduction. With twelve configurable outputs, six of which can be dynamically reconfigured, it offers versatile clock management for complex systems, ensuring optimal synchronization across components.
This IP core enables the interfacing of ultra high resolution Sony CMOS image sensors with Sub-LVDS differential signaling to processing pipelines with AMD programmable devices. It's essential for advanced imaging systems requiring reliable high-speed image data transfer, particularly in sophisticated camera and video applications.
Adding mass storage capabilities to AMD FPGA designs, the logiSDHC controller provides comprehensive File System support along with full compatibility for integration with Linux operating systems. It streamlines the design process for systems requiring reliable and efficient data storage solutions within a programmable logic environment.
Converting monochrome Bayer-filtered videos into full-color RGB, the logiBAYER IP core processes inputs from camera CMOS sensors. It enables real-time video conversion, crucial for systems requiring high fidelity color reproduction and processing in imaging applications across various industries.
This accelerator specializes in bitmap operations, delivering perspective-correct renderings to support 2.5D graphics scene rendering. Optimized for AMD FPGAs, the logiBMP enhances visual processing capabilities, crucial for applications that rely on detailed and dynamic graphical outputs such as simulations and advanced user interfaces.
The logiCAN controller equips AMD FPGA designs with CAN 2.0B compatibility, supporting robust automotive network communication. Easily integrated using AMD development tools, this IP core facilitates the implementation of reliable, high-speed automotive communication networks, central to modern vehicle electronics.
The logiMEM_arb combines memory control and arbitration features, designed specifically for AMD Spartan 6 FPGA interfaces. It supports simultaneous accesses from multiple sources, integrating well with various bus standards to efficiently manage memory resources in sophisticated digital environments.
Tailored for automotive use, the logiSTEP controller can drive up to 16 stepper motors simultaneously within an AMD FPGA. This capability supports intricate automotive mechanical systems and simplifies the management of multiple motors, essential for precise control in various automotive applications.
The logiJPGD-LS is a lossless Motion JPEG decoder, compliant with Annex H of the ISO/IEC 10918-1 JPEG standard. It is designed for use in still image and video decompression applications for AMD MPSoC, SoC, and FPGA devices, offering high efficiency in solutions that demand high-quality image fidelity.
The logiUART is a programmable Universal Asynchronous Receiver-Transmitter capable of LIN network integrations. Primarily tailored for automotive ECUs, it allows seamless communication across Local Interconnect Network (LIN), enhancing in-vehicle networking capabilities for AMD FPGA designs.
Utilizing HOG and SVM algorithms, the logiHOG IP core supports multi-object detection capabilities, essential for advanced camera-based systems. It provides accurate object classification in video analytics, bolstering functionalities in security, automotive assistance, and automated surveillance systems.
This MJPEG encoder complies with Annex H of the ISO/IEC 10918-1 JPEG standard, providing lossless video and image compression for AMD MPSoC, SoC, and FPGA environments. Essential for applications requiring high image quality and efficient storage or transmission, this encoder ensures maximized data integrity and minimal loss during compression.
The logiJPGE encoder IP core facilitates JPEG standard Baseline DCT compliant image and video compression for AMD SoC and FPGA platforms. This critical component in multimedia systems ensures efficient handling of image data, preserving quality while minimizing storage requirements, making it instrumental in video-oriented data management applications.
The logiREF-DFX-IDF offers a comprehensive framework demonstrating AMD's Dynamic Function eXchange (DFX) capabilities. This advanced framework allows users to reconfigure parts of a running FPGA/SoC system, enabling feature swaps without disrupting the ongoing operations, thus proving invaluable in adaptive and dynamic systems requiring flexible processing capabilities.
The logiI2C core provides a master controller interface for the I2C bus, meeting all the requirements for I2C serial communication in AMD FPGA and Zynq 7000 SoC designs. It offers a reliable mechanism for interconnecting various peripherals in a unified communication framework, critical for integrated system designs.
The logiVDET IP core provides advanced object classification for vehicle detection in video systems, crucial for enhancing driver assistance and surveillance applications. It employs sophisticated algorithmic processing to identify vehicles within data streams accurately, supporting robust automotive safety systems.
The logiDROWSINE utilizes computer vision to detect driver drowsiness by analyzing facial movements through a camera. Optimized for AMD Zynq 7000 All Programmable SoC, this IP core provides crucial safety measures in automotive systems, identifying signs of fatigue to prevent potential accidents on the road.
The logiFDT integrates a configurable face tracking engine that identifies and tracks faces and features within video sequences in real-time. Offering full 3D head pose and gaze direction, this IP core is essential for applications in surveillance, automotive safety, and other systems requiring precise facial recognition and tracking capabilities.
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