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Terminus Circuits' SerDes PHY caters to diverse market needs, from networking and data storage to enterprise-level routers and industrial applications. It enables seamless data rate configurations, supporting multiple standards like PCI Express Gen1 to Gen4, USB3.1, and more. The PHY is engineered to deliver high speed and low power while maintaining stringent control over channel characteristics through adaptive equalization techniques. Its broad compatibility with different protocols and data rates makes it a highly versatile solution in complex system integrations.
The Low Jitter Digital PLL from Terminus Circuits is a multi-band quadrature frequency synthesizer capable of generating precise frequencies ranging from 1.25 GHz to 5 GHz. Designed for high-speed communication systems, its applications span clock multiplication and recovery in USB 3.0/3.1 and other PHY transceivers. The component boasts a Type II, 3rd order configuration, offering unparalleled low jitter output with automated calibration over a range of process nodes and temperatures. Its compact design ensures low silicon area usage, making it ideal for integration into modern electronic systems.
The MIPI M-PHY HS Gear 4 by Terminus Circuits fits seamlessly into mobile system applications, ensuring efficiency, power savings, and robust performance. This product complies with all necessary MIPI standards, supporting a wide array of protocols tailored for data storage, transfer, and more. Notable for its modularity and scalability, it allows application-specific customization to maximize compatibility and performance. Leveraging high-speed compatibility and low power needs, it adeptly manages data for advanced mobile technologies.
The PCIe PHY developed by Terminus Circuits is engineered to support high-speed communication, providing low latency and robust handle of PCIe 4.0, 3.0, and 2.0 protocols. This PHY incorporates a comprehensive design, including the PMA hard macro for enhanced PCIe protocols and a soft macro that aligns with PIPE4.3 standards. The design excels in ensuring tight control over termination resistance and skew, offering an optimal balance of speed and power efficiency. It supports bifurcation and quadfurcation modes, demonstrating flexibility by managing multiple lanes, which is ideal for high-performance computing environments.
Terminus Circuits presents their USB 3.1 PHY, crafted to integrate flawlessly into SoCs for media and playback devices. This component is optimized for low latency and high speed, with PHY supporting USB 3.0 and 3.1 protocols. Designers can utilize this robust solution to deliver elevated bandwidth requirements while maintaining a compact form factor ideal for various high-performance computing devices. Its configuration accommodates both QUAD and single-lane operations, ensuring extensive adaptability across applications requiring rapid data transfer between PCs and portable electronics.
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