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SLL’s unified xSPI Memory Controller (xSPI MBMC) supports all the major JEDEC xSPI and xSPI-like protocols, including: - JEDEC xSPI Profile 1.0 and 2.0 - HyperBus 1.0, 2.0 and 3.0 - OctaBus, Octal Bus; and - Xccela Bus. SLL's xSPI Memory Controller core has been physically qualified for use with all the major memory device variants: - AP Memory (x8 Xccela PSRAM, x4/x8/x16 IoT memory) - Everspin (xSPI Profile 1.0 STT-MRAM) - GigaDevice (xSPI Profile 1.0 NOR Flash) - Infineon (HyperRAM 2.0, HyperRAM 3.0, xSPI Profile 1.0 SemperFlash, xSPI Profile 2.0 SemperFlash) - ISSI (Octal RAM, Octal Flash) - Macronix (OctaFlash) - Micron (Xccela Flash) - Winbond (HyperRAM 2.0, HyperRAM 3.0) - SLL can also add support on request for: - Micron Serial NAND (8D-8D-8D DS) - Winbond Serial NAND (8D-8D-8D DS) - Winbond Octal NOR Flash (8D-8D-8D DS) SLL’s has officially partnered with all the above memory vendors. SLL’s xSPI Controller also has been extensively tested using an end-to-end test bench that achieve near 100% code coverage. -- JEDEC xSPI and xSPI-like memories offer good performance with lower hardware and power costs. Memory device variants offer up to up to 128 Mbit STT-MRAM, 512 Mbit PSRAM, up to 2 Gigabit NOR Flash, up to 4 Gigabit NAND Flash, up to 333 MHz DDR clock speeds, with x4, x8 and x16 data path widths, and a wide range of package options including 4mm x 4mm BGA49 and tiny WLCSP footprints. Some PRSAM devices are now also available with internal ECC. SLL’s small xSPI Memory Controller core enables you to easily evaluate, select and adopt the benefits of the latest xSPI-style memories in your projects and products. SLL provides world class pre-sales and post-sales technical support for all the major memory vendors and FPGA vendors, helping you navigate the rapidly evolving market, on the platform of your choice. SLL also offers a high performance PVT-aware xSPI PHY along with an integration support package for ASIC customers seeking to support their specific {Foundry, Process Node} of choice. Get to market faster, with lower power consumption, lower pin count, lower cost, and far lower project risk by using SLL’s memory controller in your project/s.
SLL's Modular PHY Type 01 Suite is a PVT aware, foundry and process agnostic, PHY for use with most single-ended LVCMOS protocols up to 400 MHz DDR. The PHY has a highly modular architecture that supports x1, x4, x8, and x16 data paths. Its has process-voltage-temperature (PVT) controls that are suitable for use in hard realtime systems (zero timing interference on PVT adjustments). The PHY includes a full standard cell library abstraction. The PHY also offers >1000 configurable options at compile time, enabling coarse grain capabilities such as pin-level deskew to be enabled/disabled, along with precise fine-grain control of mapping of RTL to gates through various data paths. It supports a range of protocols such as SPI, QSPI, xSPI, eMMC, .. and allows run-time configuration via an APB3 control port. It is designed to support easy place-and-route in a broad range of customer designs.
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