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EverOn is a groundbreaking Single Port Ultra Low Voltage SRAM IP that delivers exemplary dynamic and static power savings. It is particularly suited for IoT and wearable device markets, where energy efficiency and performance are both critically required. Silicon-proven on 40ULP BULK CMOS processes, EverOn brings forth a new paradigm in power savings, offering up to 80% reduction in dynamic power and 75% in static power. Operating in a broad voltage range from 0.6V to 1.21V, EverOn achieves record-setting operational capabilities with its pioneering cycle time dynamics. Boasting a 20MHz cycle time at the ultra-low 0.6V mark, scaling to 300MHz at its upper voltage threshold, this IP is instrumental in the development of future-facing applications. The ULV compiler supports flexible configurations, enabling tailor-fit solutions suiting specific system requirements. EverOn’s SMART-Assist technology allows for robust operation down to retention voltages, complimenting its ultra-low power profile with considerable system flexibility. Features include memory bank subdivision and advanced sleep modes, tuned for maximum energy efficiency. Such characteristics make EverOn a frontrunner for products needing extended operational times and robust battery longevity.
PowerMiser represents a leading-edge Low Power SRAM IP designed for advanced devices that require extended battery life with minimal operational and standby power usage. PowerMiser is effectively utilised across several manufacturing processes including 28nm FDSOI, 28nm HDC+, and 22nm ULL BULK CMOS. It offers remarkable dynamic power savings of over 50% compared to its commercial counterparts and achieves substantial leakage power reductions depending on the operating environment. Even with its significant power-saving capabilities, PowerMiser incurs only a slight area penalty, catering to the dense requirements of modern systems. The PowerMiser compilers are highly versatile, supporting large capacities and offering various trade-offs between word numbers, lengths, and multiplexing factors. This flexibility is crucial in managing the intricate needs of contemporary SoCs, ensuring power efficiency without performance compromise. Moreover, PowerMiser's architecture eliminates the need for power-intensive level shifters, further optimising power consumption for applications demanding rigorous efficiency such as edge-AI deployments. Standing out with a retentive sleep mode feature, PowerMiser ensures rapid wake-up times and maximal leakage current savings. Its innovative design techniques paired with SureCore’s extensive expertise in power management lead to a unique product that significantly reduces the energy footprint of embedded systems, allowing manufacturers to meet the ever-tightening energy standards of today's market.
MiniMiser is a highly efficient multi-port register file architecture designed for both low power and high-performance requirements. Its innovative design significantly reduces power consumption, offering more than a 50% decrease compared to traditional register file solutions. MiniMiser allows designers to finely tune their power usage profile in accordance with their application's specific operational needs. This IP is uniquely implemented without reliance on the foundry bit cells, opting instead for a single rail design. This architecture enables seamless integration with system logic, bypassing conventional challenges such as level shifting and static timing analysis. MiniMiser is particularly critical in applications involving AI capabilities in wearable devices, which are increasingly demanding in their processing power yet restricted in energy budgets. MiniMiser sets itself apart by providing developers with innovative avenues for optimizing power envelopes, essential for extending battery life and performance efficiency in competitive markets. By enhancing SO-C performance through varied voltage modes, MiniMiser is an ideal choice for developers looking to merge energy savings with cutting-edge functional demands.
CryoIP is an advanced suite of IP developed for operation at cryogenic temperatures, tailored specifically for Quantum Computing (QC). It facilitates the creation of CryoCMOS control chips capable of operating alongside qubits within a cryostat, addressing the critical challenge of extensive cabling required in current quantum systems. SureCore’s CryoIP is designed to support the development of scaled quantum systems by moving control electronics closer to the qubits, reducing the thermal load and improving system scalability. By extending its proven low-power CMOS techniques to CryoCMOS environments, SureCore aids in minimizing heat generation, which is crucial in maintaining the qubits at optimal cryogenic conditions. This innovative approach to quantum control electronics not only diminishes the complications in current architectures but also stands as a testament to SureCore’s engineering prowess in low-power semiconductor solutions. CryoIP's development will leverage the expertise gained through SureCore’s CryoMem range, providing the highly efficient, low thermal footprint control systems necessary for advancing quantum computing technologies.
PowerMiser Plus is an advancement in low-power SRAM technology, building upon SureCore's renowned PowerMiser architecture. Designed for applications needing ultra-low voltage operations, it significantly enhances low-power product development through its dual rail capability. This feature permits interfacing down to 0.45V, facilitating synchronized operation of logic and memory at reduced voltages, which is vital for performance scaling while conserving power. With PowerMiser Plus, users can achieve revolutionary energy savings especially pertinent in edge-AI applications where SRAM is heavily used for pattern matching and similar processes. By focusing on minimizing the differential between core array and periphery supplies, this IP circumvents the necessity for power-hungry level shifting devices, rendering it an optimal choice for power-restricted applications. SureCore’s PowerMiser Plus positions itself as the go-to solution for enterprises aiming to extend battery life and reduce the power footprint in their SoCs. The architecture sets a new industry benchmark for low voltage operation, effectively meeting the strict power budgets necessitated by modern technology sectors like wearables and IoT.
sureCore introduces a silicon service suite, offering a complete package for low-power, next-gen device design, addressing power efficiency across multiple applications. Read more
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