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This highly integrated core from Soft Mixed Signal Corporation combines advanced technologies to deliver a robust gigabit Ethernet transceiver designed for both fiber and copper mediums. The transceiver is compliant with IEEE 802.3z standards and incorporates unique features such as a 10-bit controller interface for bidirectional data paths, ensuring reliable and fast data transmission. It integrates various high-speed drivers along with clock recovery digital logic, phase-locked and delay-locked loop architectures, serializer/deserializer modules, and low-jitter PECL interfaces. This makes it an ideal solution for network systems requiring consistent performance under demanding conditions. The transceiver is tailored for low cost and low power CMOS processes, offering both 75 and 50 Ohm termination compatibility, and includes optional embedded Bit Error Rate Testing (BER), enhancing its utility in complex environments. It is mainly designed to optimize data alignment and ensure effective jitter performance, positioning it as a distinctive asset for advanced Ethernet networking solutions.
The SMS OC-3/12 Transceiver Core addresses the demanding specifications of SONET/SDH networks, supporting data rates of 622.08 Mbit/s (OC-12) and 2.4 Gbit/s (OC-48) with selectable reference frequencies. It boasts a deep sub-micron CMOS implementation for effective system-on-chip integration. The core features integrated clock synthesis and recovery, wave shaping, and low-jitter LVPECL interfaces, compliant with rigorous industry standards such as ANSI, Bellcore, and ITU. This ensures it meets essential jitter tolerance, transfer, and generation specifications, crucial for reliable data transmission over SONET networks. Patented signal processing techniques enhance clock recovery capabilities, providing immunity to external and PCB noise. This makes the transceiver a robust solution for high-frequency applications requiring secure data transmission across optical networks and supports multiple integrations on a single IC, catering to scalable system designs.
The UTMI Compliant USB 2.0 PHY Core from Soft Mixed Signal Corporation is designed to support a wide range of USB applications, offering full compliance with the USB 2.0 specification. This transceiver features an integrated approach that includes OTG (On-The-Go) capabilities and offers advanced functionalities such as data and VBUS pulsing support necessary for session request protocols. Incorporating high-frequency PLL technology and an advanced transmitter and receiver, the core maintains efficient data flow and communication. It supports high-speed, full-speed, and low-speed operations with versatile termination resistor configurations, providing flexibility and reliability in various applications, from host controllers to portable devices. Designed as a super-set of HOST and DEVICE PHY with integrated transceivers, it also offers simplified integration with ASIC designs, ensuring vendors are insulated from complex high-speed and analog circuitry. This not only reduces design risks but also accelerates the time-to-market for USB 2.0 integrated applications.
Soft Mixed Signal's SATA PHY IP is built to adhere to both SATA 1.0a and Serial ATA II standards, supporting 1.5Gbps and 3.0Gbps data rates. Designed for efficiency, the PHY is prepared to manage the complex needs of data transfer with compliance to electrical specifications for SAS as well. The solution integrates a 0.18µm PHY with clock synthesis and OOB processors, facilitating extensive applications through scaled multi-port and multi-lane designs. Furthermore, the PHY’s architecture allows integration within newer SOC frameworks, providing high flexibility and reduced area and power consumption. Its versatility is apparent as it interoperates with various Link and Transport Layer IP blocks, presenting a comprehensive approach to incorporating SATA technology into designs ranging from PCs to consumer electronics. With focus on streamlined power usage and compact silicon footprint, this PHY IP aids in seamless upgrades and transitions within storage technology applications.
The PCI-Express PHY IP from Soft Mixed Signal Corporation is designed to meet the high demands of modern enterprise and mobile platforms by supporting the PCI-Express Base Specification Revision 1.0a and PIPE standards. This PHY features a scalable, low-power design enabling efficient use in power-sensitive applications. It is a full PIPE-compliant transceiver, incorporating integrated clock synthesis and capable of supporting multi-lane configurations for enhanced performance in complex systems. The PHY includes both PMA and PCS layers of the PCI-Express Networking Layers, enabling seamless integration with the MAC layer via a configurable PIPE interface, supporting both 8-bit and 16-bit configurations. The design is crafted for robustness, using proprietary clock recovery architectures that minimize issues in noise-prone environments typical of today’s multi-million gate ICs. The innovation behind this PHY is set to make it a preferred choice for high-speed connectivity standards. Furthermore, Soft Mixed Signal Corporation offers extensive customer support for ASIC and SOC integration, ensuring compliant implementations and providing technical support for packaging options, easing the integration process into customer simulation environments and ensuring an efficient design cycle.
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