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The ARINC 429 Receiver Core is built in accordance with the ARINC Specification 429 Part 1-17, supporting reliable and accurate data reception in aviation digital data transfer systems. This core receives data over a specified pair of wires, designed to operate as part of a Mark 33 Digital Information Transfer System (DITS). The core ensures high integrity in signal reception, essential for applications in avionics where reliable and constant data stream processing is critical. This IP core, developed to meet Design Assurance Level A under the DO-254 criteria, benefits from accompanying certification kits to ease the verification and compliance process. Its robust architecture conducts extensive error checking, addressing frequency, gap, parity, and data form errors, ensuring the seamless reception of data under various conditions. By being technology and vendor-independent, the ARINC 429 Receiver Core can be synthesized and integrated into numerous FPGA and ASIC platforms, thus supporting a broad range of avionics applications. It is designed not only to meet but exceed the rigorous demands in data communication systems within aircraft and other aerospace vehicles, offering dependability under the most demanding operational scenarios.
The ARINC 429 Transmitter Core is engineered to implement robust transmission capabilities as specified by ARINC Specification 429 Part 1-17. Ideal for Mark 33 Digital Information Transfer Systems, this solution facilitates the uni-directional transfer of digital data between avionics system elements over twisted pair cabling. This functionality is pivotal in ensuring seamless communication in airborne environments, often necessitating separate cores for transmitting and receiving data. Developed with Design Assurance Level A according to DO-254 standards, this core is equipped with a comprehensive Certification Kit, enabling easy navigation through certification processes. It features multiple error-checking mechanisms such as frequency, gap, parity, and form checks to maintain a high integrity of data transmission across various operational environments. Radiation-hardened versions with TMR coding are available to enhance resilience against SEUs. Carrier-independent, the ARINC 429 Transmitter Core can be synthesized to fit any FPGA or ASIC technology, providing flexibility in adapting to different design specifications. This adaptability ensures that the core can meet diverse architectural demands while offering robust performance in mission-critical aviation communications.
The CAN FD Controller is a versatile solution designed to implement the Controller Area Network with Flexible Data Rate (CAN FD) as specified in the ISO 11898:2015 Part 1. This IP provides robust support for both Classical and Flexible Data Rate CAN frame formats, operating at bit rates up to 1 Mbit/s for Classical CAN and up to 10 Mbit/s for CAN FD formats. It facilitates efficient real-time control in distributed network systems across high-speed networks and cost-effective multiplex wiring applications. The CAN FD Controller is developed with Design Assurance Level A, ensuring compliance with the DO-254 standard for airborne electronic hardware. This IP core has been extensively tested in accordance with ISO 16845-1:2016 standards, guaranteeing a high level of security and reliability. The Controller's design is fully synchronous, supporting standard transceiver interfaces without need for additional logic, making it a seamless component of any airborne or automotive control system. This technology-independent core can be synthesized to fit any FPGA or CPLD vendor specifications, offering flexibility and compatibility across different platforms. It also includes optional TMR coding for improved immunity to radiation-induced errors, critical for maintaining operational integrity in harsh environments.
The 10/100/1000 Ethernet MAC provides a comprehensive solution for implementing Ethernet Media Access Control as outlined by the IEEE 802.3-2008 specification. This IP core can interface with various physical layer interfaces like MII, RMII, GMII, or SGMII, offering users flexibility to choose the suitable chip for their design requirements. Configurable for operations at 10 Mbps, 100 Mbps, or 1000 Mbps, it caters to diverse needs regarding power, latency, and size considerations in network systems. With Design Assurance Level A accreditation under DO-254 standards, this Ethernet MAC IP core ensures high reliability necessary for aviation and other high-stakes sectors. It comes with a Certification Kit for further assurance, facilitating integration and compliance checks. Among its features, the IP includes TMR coding for enhanced radiation resilience, crucial for endurance in adverse conditions. Technology agnostic, this core can be synthesized across various FPGA and ASIC vendor platforms, thereby supporting wide applicability. Accompanying tools ensure users can effectively implement and optimize for specific network configurations, enabling efficient data transmission and reception across secure systems.
The MIL-STD-1553B Remote Terminal implements a versatile communication solution adhering to the MIL-STD-1553B specification with full compliance to all applicable notes. This standard sets guidelines for a time-division command/response multiplexed data bus, crucial for military and aerospace applications where communication integrity and real-time control are paramount. Built to Design Assurance Level A standards set by DO-254, this IP core includes a Certification Kit to guide through the aviation compliance process. The core's architecture supports dual-redundancy with Manchester II encoded data transmission, enabling high-reliability communication in mission-critical environments. Its fully synchronous design is ideal for minimizing data errors and maximizing data integrity across bus networks. The MIL-STD-1553B Remote Terminal Core's universal nature allows it to be synthesized onto any FPGA or CPLD device, providing adaptability in varying technological setups. TMR coding is available for applications requiring radiation tolerance, ensuring the core remains robust and resilient in adverse conditions, typical of aerospace and military applications.
The ARINC 664 (AFDX) End System is designed to implement an Avionics Full-Duplex Switched Ethernet (AFDX) Network, compliant with ARINC 664 Part 7. It supports multiple physical interfaces including MII, RMII, GMII, and SGMII, capable of handling data transmission at 10 Mbps, 100 Mbps, or 1000 Mbps efficiently. This IP core enables robust communication between avionics systems, utilizing AXI interfaces for host control, status management, and message transactions. The core employs internal buffering to handle message loads without requiring external memory, improving system performance and reliability. This optimization is pivotal in sustaining efficient data flow and minimizing latency in avionics applications. Developed to Design Assurance Level A standards per DO-254 guidelines, it also includes a Certification Kit to support regulatory compliance efforts for its users. Enhanced with optional radiation-hardened configurations, the ARINC 664 (AFDX) End System is built to endure rigorous conditions, making it ideal for in-flight and other high-security communication environments. The IP's modular design ensures it can be easily incorporated into a variety of system architectures, further broadening its applicability across the aviation industry.
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