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The InfiniBand Transport Layer Core from Polybus is designed to enhance data acquisition and networking capabilities by supporting UC SEND and UC RDMA write operations across various virtual lanes and queue pairs. Suitable for high-performance environments, it offers robust integration capabilities with existing systems.
The InfiniBand DDR (Double Data Rate) Link Layer Core from Polybus functions at 250 MHz with support for 20GBits/second bidirectional speeds. Suitable for FPGAs and ASICs, this core requires a 5 GHz SerDes and is compatible with Xilinx and Altera devices across various speed grades.
Polybus Systems offers a comprehensive suite of customizable FPGA test patterns specifically designed for Xilinx FPGAs. This suite, consisting of over 400 patterns, is aimed at detecting defects and ensuring system reliability through in-system testing methodologies that exceed typical manufacturer screenings.
Polybus's InfiniBand QDR (Quad Data Rate) Link Layer Core offers substantial throughput, operating at 500 MHz in ASICs and 250 MHz in FPGAs, accommodating 80G operation in ASICs. This core is optimized for use with major FPGA manufacturers and supports extensive data communication and processing tasks.
Polybus Systems offers the InfiniBand SDR (Single Data Rate) Link Layer Core, which is their smallest core operating at 125 MHz, capable of delivering bi-directional speeds of 10GBits/second. This core is designed for a variety of FPGAs including Xilinx Virtex and Altera Stratix. Its efficient operation in low-speed grade settings makes it a versatile option for diverse development needs.
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