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Specially designed for performance computing and complex system-on-chips (SoCs), the pPLL03F-GF22FDX is a Fractional-N PLL optimized for low-jitter applications in GF's 22FDX technology. The PLL caters to high-specificity clocking requirements, driving critical components like ADCs/DACs with moderate signal-to-noise ratio needs. Its architecture allows flexibility in multi-domain SoC environments, maintaining low power consumption under 5mW and occupying minimal die space. This second-generation digital PLL capitalizes on Perceptia's robust technology, ensuring stable performance across a wide array of environments. Easily integrated into existing SoC frameworks, pPLL03F-GF22FDX provides precise clock frequency modulation in both integer and fractional modes, aligning system requirements with input-output clock frequency combinations. This adaptability is crucial for refining complex digital systems. Availability in multiple technologies exemplifies its versatility, suitable for integrating in various technology nodes beyond GlobalFoundries, including options from Samsung, TSMC, and UMC. With its compact design and ability to meet critical timing requirements, the pPLL03F-GF22FDX is an ideal choice for performance-focused digital applications where reliability and flexibility are paramount.
Perceptia's pPLL08 family offers cutting-edge all-digital RF frequency synthesizer PLLs ideal for advanced RF applications, such as 5G and WiFi. Designed for ultra-low jitter, this PLL line features sub-300 femtoseconds RMS jitter, making it perfect for use as a local oscillator or for clocking ADCs/DACs in scenarios requiring stringent signal-to-noise ratios. The pPLL08 family is distinguished by its ability to support multiple wireless standards including 5G and WiFi, and it delivers frequencies up to 8GHz. Its compact form factor and power efficiency are achieved using a LC tank DCO, maintaining interference-free operation even amidst complex integrations. The technology provides extensive flexibility in frequency modulation through its fractional-N capability, which supports up to 24-bit multiplication, allowing for meticulous clock system customization. Integrated seamlessly into system-on-chip environments, the pPLL08 family is engineered to provide robust performance regardless of process variations. Its versatility extends over various process nodes and foundries. Delivering consistent and reliable performance, it remains a preferred solution for professionals seeking precise clocking mechanisms in cutting-edge communication technologies.
The pPLL05 family targets low-power applications, particularly within IoT and embedded system environments. Its design focuses on achieving low power consumption and compact area. These PLLs are tailored for use in systems operating with a reduced voltage, efficiently handling frequencies up to 1.0GHz. Their application extends to clocking moderate-speed digital logic and processors, benefiting spaces where power availability is limited. Occupying less than 0.01 square millimeters, pPLL05 finds easy integration into various technology nodes, ranging from 5 nm to 40 nm, ensuring compatibility with an array of foundry processes. Known for its reliability, the PLL delivers stable performance across diverse PVT (process, voltage, temperature) conditions. The modular design supports both fractional and integer-N modes of frequency multiplication, advantageous for flexible system designs. Integrated seamlessly into SOC infrastructures, it utilizes minimal resources while offering high-efficiency outputs. The versatility in power supply offers improved jitter performance when dedicated supplies are used, resulting in optimized performance for IoT and other constrained environments wanting extended battery life and low operational costs.
The pPLL02F family from Perceptia is engineered to serve as general-purpose all-digital Fractional-N PLLs suitable for moderate-speed digital systems and logic clocking. Designed with versatility in mind, this PLL range is ideal for clocking microprocessor blocks and mixed-domain systems. It boasts a compact footprint, occupying less than 0.01 square millimeters, while maintaining low power consumption, typically under 3.5 milliwatts. These PLLs integrate seamlessly into system-on-a-chip (SoC) designs, accommodating multiple domains by allowing instances of the PLL to share power supplies or integrate with existing power architecture. The family is founded on Perceptia's second-generation all-digital PLL technology, which ensures consistent performance across various manufacturing processes, unaffected by variations in process, voltage, or temperature. The integration of these PLLs is straightforward, aided by comprehensive design support including all necessary models and verification reports for backend procedures. In fractional-N mode, the pPLL02F family offers flexibility in clock frequency modulation, ensuring precise fit for demanding timing scenarios. Available across several foundry processes, from 5nm to 40nm, the pPLL02F family provides support for multiple designs and platforms, with proven silicon across major industry players. It's a robust solution for systems requiring multiple PLL operations, offering features like low jitter and high integration capabilities. These characteristics make the pPLL02F family a practical choice for designers seeking a balance between area efficiency, power conservation, and performance in their clocking solutions.
The pPOR01 is a power-on reset solution developed by Perceptia, designed to support stable system initialization processes. This component is essential for digital systems requiring robust reset mechanisms that can withstand the challenges of power transitions and fluctuating states. Integrating the pPOR01 into a variety of semiconductors enhances system reliability by ensuring devices return to a defined state upon start-up or after power interruptions. This feature is crucial for maintaining the integrity and performance of advanced digital circuits. Constructed with a focus on efficiency, the pPOR01 accommodates diverse system requirements, making it an ideal choice for enhancing the dependability of complex semiconductor designs. Its functionality supports broad application scenarios, providing a reliable reset strategy pivotal for modern digital architectures.
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