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Designed for performance computing, the pPLL03F-GF22FDX is an advanced all-digital fractional-N PLL developed for low-jitter and compact applications. It operates efficiently at clock frequencies reaching up to 4GHz, specifically crafted to meet the demands of performance computing blocks and ADCs/DACs that have moderate SNR prerequisites. A crucial aspect of its design is its compatibility with multi-PLL systems, enabling implementations in complex SoCs with numerous clock domains. Tailored for GlobalFoundries 22FDX, this IP ensures robust and reliable performance across varied PVT conditions.
The pPLL08 Family represents Perceptia's suite of all-digital RF frequency synthesizer PLLs designed for high-frequency applications, such as 5G and WiFi. With frequencies reaching up to 8GHz and jitter below 300fs RMS, this PLL family is ideal for both RF LO clocks and the clocking of ADCs/DACs in rigorous RF environments. Featuring a compact architecture, these PLLs are built with a LC tank DCO to meet stringent performance specifications. Flexibility is a hallmark of this IP; it allows for seamless integration across various SoC designs, supported by robust performance across multiple foundry process nodes from 5nm to 40nm.
The pPLL05 Family offers a line of low-power all-digital fractional-N PLLs that are ideally suited for IoT and embedded applications where energy efficiency is paramount. These PLLs operate at frequencies up to 1GHz, delivering clocking capabilities for moderate speed microprocessor blocks under a reduced power footprint of less than 1.0mW. The architecture is easily integrable into any system design, maintaining performance consistency across diverse processes. Silicon-proven from 40nm down to 5nm, these PLLs support integer and fractional multiplication for flexible frequency management in a variety of digital systems.
The pPLL02F Family is a comprehensive collection of all-digital fractional-N PLLs tailored for general-purpose applications. It integrates seamlessly into systems requiring moderate speed digital logic, especially suitable as a clock source for microprocessor blocks. Operating at up to 2GHz, these PLLs maintain low jitter (<18ps RMS) and consume minimal power (<3.5mW), making them ideal for multi-domain clock systems. The architecture supports both integer and fractional multiplication, offering flexibility in clock frequency configuration. This IP is silicon-proven across process technologies spanning from 5nm to 40nm, enabling broad adaptability across various foundries.
The pPOR01 is a robust power-on reset circuit designed for reliable initialization of digital systems. Engineered to handle various power-up scenarios, this circuit ensures that digital devices start in a known state despite possible fluctuations during power application. The pPOR01 is characterized by its low power consumption and compact design, which facilitates easy integration into diverse digital platforms. It provides an essential reset mechanism critical for stable system performance across an array of technology nodes.
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