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Orthogone’s ULL PCIe DMA Controller is engineered for ultra-fast data transfer between FPGA and host CPU via a PCIe interface, crucial for data center applications that demand low latency. This controller features a round-trip latency of less than 585 nanoseconds, optimized for high-speed data streaming applications. Built on a custom multi-channel Circular Buffer DMA architecture, the controller supports kernel bypass, enhancing performance by reducing latency and jitter. It is designed for seamless integration with standard PCIe endpoints, navigating gen 3 and gen 4 specifications, making it highly adaptable. Key features of this controller include high timing margins, easy integration with Orthogone’s other networking solutions, and efficient resource utilization within FPGA platforms. It is particularly tailored for environments necessitating top-tier latency metrics, supporting kernel-bypass Linux applications.
The ULL TCP/IP and UDP/IP Offload Engine from Orthogone offers high-performance network protocol processing, tailored for data centers and financial applications requiring low latency and high throughput. Designed to efficiently handle Layer 2, 3, and 4 protocols, this engine provides configurability for connection management and supports both server-side and client-side support per connection. One of the standout features is its ability to deliver outstanding latency performance, with transmission path latency as low as 6.2 nanoseconds in cut-through mode. The engine's architecture is built to integrate seamlessly with standard Linux networking stacks, supporting AXI-4 streaming interfaces for easy connectivity. The ULL TCP/IP engine supports key protocols such as ARP, IPv4, ICMP, TCP, and UDP. Its enterprise-grade design ensures robust session management, congestion control, and excellent interoperability, all while maintaining low resource utilization.
Orthogone’s Ultra-Low Latency Ethernet MAC & PCS provides industry-leading network connectivity with unmatched latency performance, optimized for high-frequency trading and high-performance computing. This IP core supports data rates ranging from 1 to 100 Gbps and incorporates advanced features including optional RS-FEC error correction for enhanced reliability. Built using advanced design techniques, it significantly reduces time-to-market while maintaining optimal latency, making it ideal for financial and networking applications. The architecture offers robust performance, supporting 1GbE, 10GbE, 25GbE, 40GbE, and 100GbE line rates. The inclusion of a rich feature set makes it adaptable for various applications, offering full wire line speed without packet loss for frame sizes up to jumbo frame size. The IP core is compliant with the IEEE 802.3 High Speed Ethernet Standard, ensuring broad interoperability with other standard-compliant systems. Developers benefit from a unified Verilog source code solution that adapts across different data rates, securing investment in existing IP. The design is highly optimized for low gate count and resource utilization, supporting a variety of SERDES data bus widths and maintaining excellent timing margins across configurations.
Explore how FPGAs are revolutionizing high-frequency trading with ultra-low latency and deterministic performance, reshaping the future of financial markets. Read more
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