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TwinBit Gen-1 stands as a cutting-edge, logic-based non-volatile memory suitable for 180nm to 55nm process nodes. It prides itself on remarkable endurance, capable of performing over 10,000 programming cycles. This IP macro is designed for integration into CMOS logic processes without extra masking steps, easing the implementation in advanced technology nodes. The TwinBit Gen-1 series is well-adapted for a diverse range of applications, including IoT devices, microcontrollers, FPGAs, and ASICs with embedded NOR FLASH, offering memory sizes from 64 bits to 512K bits. It provides a high-density, small-area solution, which is particularly beneficial for applications requiring field-rewritable firmware or secure data storage. This memory technology ensures low-voltage and low-power operations, accommodating automotive industry standards through compliance with AEC-Q100. TwinBit Gen-1 includes built-in test circuits that allow for stress-free testing, ensuring reliability in diverse operating conditions. The technology also supports low-cost manufacturing and faster development turnaround times.
TwinBit Gen-2 builds upon the foundation of its predecessor by supporting more advanced process nodes from 40nm to 22nm. Like the Gen-1 version, it is integrated into CMOS processes without necessitating additional masks or processing steps. This technology incorporates the novel Pch Schottky Non-Volatile Memory Cell, facilitating ultra-low-power operation. With the Gen-2, users gain access to a memory solution that handles both programming and erasing effectively through controlled hot carrier injection. This is achieved through intelligent cell bias manipulation, ensuring optimal performance. The process of hot-hole and hot-electron generation is finely distributed to maintain integrity during both program and erase operations. TwinBit Gen-2 is specifically advantageous for applications that demand ultra-low-power memory solutions. Its structure caters well to IoT and automotive applications where energy efficiency and reliability are paramount. Maintaining compactness and efficiency, this IP further enhances NSCore's portfolio in serving advanced technological requirements.
PermSRAM offers a flexible non-volatile memory solution designed for seamless integration with standard CMOS processes from 180nm to 28nm and potentially beyond. Its key features include one-time programmable and pseudo multi-time capabilities with a variety of memory configurations, ranging from 64 bits to 512K bits. Notably, PermSRAM incorporates a non-rewritable hardware safety lock, which is ideal for secure storage of codes. This memory macro caters to applications requiring high security and reliability such as security code storage and program management. It provides a robust solution with stable yield performance, making it an excellent choice for various security-sensitive uses. Furthermore, it eliminates the need for additional charging circuits by operating with a typical system board voltage of 5V, which leads to significant savings in silicon area. PermSRAM is structured to handle stress-free testing environments thanks to its built-in self-test circuits, maintaining efficiency even under demanding conditions. Its small silicon footprint and highly secure data storage make it suitable for a comprehensive set of applications, including analog trimming, gamma correction, and chip identification solutions.
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