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Mobiveil's NAND Flash Controller is crafted for enterprise storage solutions requiring high-speed data transactions with NAND flash memory. Equipped to handle ONFI/Toggle protocols, it supports comprehensive control over a wide variety of NAND devices with intricate addressing. This controller is ideal for SSD solutions where rapid read/write operations are paramount. Coupled with capability for high pipeline performance, it caters to demands of modern NAND flash by offering configurable solutions tailored to specific needs.
The 5G NR LDPC Decoder by Mobiveil is a specialized IP core designed to deliver exceptional error correction performance in wireless communication applications. Employing the Min-Sum algorithm, it allows for customizable bit-widths and iteration settings. Its architecture includes early iteration termination based on parity checking, enhancing efficiency. This decoder optimally handles decoding for 5G data, supporting the accumulation of LLRs for HARQ, and thus provides robust performance in high-demand wireless networks.
Mobiveil’s NVM Express Controller is engineered for versatility and high performance in both enterprise and client SSD solutions. It efficiently supports multi-core architectures with differentiated queue handling per core, which enhances parallel operation without traditional locking mechanisms. The architecture focuses on maximizing link utilization and minimizing latency, making it ideal for optimizing throughput and power consumption in PCIe SSD applications. Integration with PCIe controllers and third-party NAND controllers extends its adaptability across various storage scenarios.
Mobiveil’s RapidIO Verification IP provides a robust solution for compliance verification with the RapidIO protocol. This IP uses System Verilog based architecture and supports the Universal Verification Methodology, making it straightforward to integrate with other verification components. Divided into logical, transport, and physical layers, it ensures compliance by employing protocol monitors and provides substantial hooks for functional coverage, scoreboards, and checker setups. Its automated stimulus generation offers flexibility and efficiency in verification, suited for IP, SoC, or system level verification scenarios.
This IP bridge by Mobiveil facilitates intercommunication between systems utilizing PCI Express Gen3 and Serial RapidIO Gen3. Tailored for FPGA implementations, it combines PCIe's flexibility with SRIO's superior networking capabilities. The bridge allows for full line-rate data transactions and is equipped with advanced DMA engines and messaging tools, ensuring minimal processor interference. Its compact footprint and power efficiency make it a suitable choice for diverse markets like defense and medical imaging, where efficient data bridging is essential.
The RapidIO-AXI Bridge by Mobiveil presents a highly flexible interconnect solution offering seamless data transfer between RapidIO and AXI interfaces. It is designed for use in systems requiring robust throughput with a RapidIO controller functioning as a host or device. This bridge brings advanced DMA and messaging controllers, which meet the bandwidth demands and ensure high-speed data movement across the interfaces. This makes it relevant for a range of applications in high-performance environments where rapid data exchange is critical.
The UFS Host Controller (UFSHC) designed by Mobiveil facilitates ultra-fast communication with storage devices in an efficient manner. This solution is crafted to meet the high-speed demands intrinsic to contemporary data handling requirements, ensuring robust data transfer between host and storage interfaces. Tailored for a variety of embedded solutions and applications, it emphasizes low latency and power efficiency within its operational parameters, making it highly applicable in both consumer and industrial settings.
The HyperBus Flash Interface by Mobiveil offers a compact, efficient solution for bridging high-speed communications with SPI-based NOR flash memories. By utilizing a low pin count design, it outperforms traditional parallel and SPI methods with significantly enhanced throughput. This controller is adept at managing both memory and peripheral interfaces, presenting a new standard with up to 333 MB/s using only 12 pins. The interface simplifies connectivity while meeting the high-speed demands of emerging applications.
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