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Engineered with SMIC 55nm 2P7M CMOS technology, this 16-bit Sigma-Delta ADC is tailored for precise audio applications. It offers flexible gain settings from 0 to 50dB and intuitive support for PDM, I2S, and TDM interfaces. The versatile design integrates a digital serial interface with selectable microphone bias ranging from -1.3V to 2.9V. Low power consumption is a hallmark, with typical values at 2.0mA for analog and 0.2mA for digital circuits. Ideal for audio, the ADC delivers a superb signal-to-noise ratio of 90 dB, ensuring clarity across uses.
The 65nm ADC is optimized for low-power operations, offering a 12-bit resolution over eight channels with a conversion rate up to 1MSPS. It takes advantage of a 2.4V to 3.6V analog voltage supply and a 1.08V to 1.32V digital supply. Ideal for data acquisition and portable systems, the ADC comes with a power-efficient design, consuming 1.1mA in typical use and dropping below 0.1µA in power-save mode. Thanks to its precision performance, it achieves 72dB of SNR and maintains accuracy with 11.0 / 12.0 LSB for DNL and INL, respectively.
This low-power ADC operates on a 55nm process, designed for minimal power draw while providing 12-bit resolution. Conversion rates vary from 0.1MSPS up to 1MSPS, with an analog power supply ranging from 2.4V to 3.6V and digital supply between 1.08V and 1.32V. Featuring eight single-ended input channels, its architecture supports data acquisition systems and battery-powered devices. Delivering a high SNR of 72dB, this ADC performs effectively across a -40°C to 125°C temperature range. Compact yet powerful, it consumes only 1.1mA typically, and less than 0.1µA in power-down mode.
This ADC features advanced Samsung 100nm (LF6) CMOS technology, providing a wide operational range from 2.7V to 5.5V. It boasts a maximum conversion rate of 1MHz at higher operating voltages and retains full functionality down to 400kHz at lower ranges. With 16-channel single-ended inputs, it is designed for diverse applications. High precision is ensured with typical DNL at ±1.0 LSB and INL at ±1.5 LSB. Providing dynamic performance, the signal-to-noise ratio (SNR) reaches 70.7dB. The ADC is power-efficient, consuming just 8.0mW and even less in standby mode.
Utilizing Magnachip 0.18um 1P4M CMOS technology, this high-performance 12-bit ADC offers a conversion rate of 1MHz. With a supply range of 4.5V to 5.5V for analog and 1.62V to 1.98V for digital, it's well-suited for precision applications. Its temperature operating range of -40°C to 85°C and current consumption of 2mA enhances its adaptability across various environments. The differential nonlinearity (DNL) is maintained at ±1 LSB, and integral nonlinearity (INL) at ±2 LSB, assuring accurate conversions.
This ADC is designed using 0.18um CMOS technology for dependable performance with a 12-bit resolution across eight channels. It operates efficiently with 1.8V supply voltages for both analog and digital sections, fostering power-efficient designs in demanding environments. Its conversion rate ranges from 0.1MSPS to 1MSPS, ensuring adaptability to various data acquisition needs. The ADC's precision is maintained through low DNL/INL values, affording a reliable signal integrity for applications such as battery systems and wireless networks.
The 65nm SAR ADC presents a 10-bit resolution, operating at up to 1MSPS. Built for low power scenarios, it features automatic power-down to under 1uA and superb digital precision with a DNL of ±0.5 LSB. Optimized for a wide range of applications, it is powered by an analog supply ranging from 2.2V to 3.6V and a digital supply from 1.08V to 1.32V. Its compact form factor ensures minimal power use while maintaining high-performance standards ideal for data-sensitive devices.
This LVDS receiver supports shift clock frequencies from 12MHz to 85MHz, aimed at applications requiring low power consumption and robust transmission capabilities. It offers up to 2.38Gbps throughput and a bandwidth of 297.53Mbytes/sec. The device operates efficiently within a common-mode range around 1.2V, and its design minimizes electromagnetic interference using PLL technology with no external component requirements. This makes it particularly suitable for low-EMI environments and sophisticated digital communications.
This Video DAC utilizes a 55nm process and delivers 10-bit resolution at an impressive 250MHz conversion rate. Designed for high-speed video systems, it operates on a 3.3V analog and 1.2V digital power supply while maintaining a low power dissipation of 62mW. The Video DAC supports 75-ohm loads and features a low typical INL/DNL, ensuring quality performance in digital video broadcasting and high-speed instrumentation. Its compact design fits within a core area of 0.9mm2, making it optimal for constrained spaces.
This MiPi D-PHY supports version 1.2 for high-speed serial communication in mobile and other embedded applications. It handles data rates from 80Mbps up to 1.5Gbps per lane without skew calibration, and with calibration up to 2.5Gbps, enhancing data throughput significantly. Supporting low power modes and internal loopback modes for testing, this IP allows for flexible integration into a wide range of devices requiring efficient data transfer capabilities.
The HF-mini LVDS transmitter is engineered for precise and efficient data transmission, using power supplies of 2.5V/3.3V for analog and 1.1V for digital. It offers an output frequency ranging from 90MHz to 300MHz, with options for channel-specific power management. Due to its integrated Phase-Locked Loop (PLL) and four-channel outputs, this transmitter is perfect for systems requiring robust LVDS signaling with minimal electromagnetic interference (EMI).
The Sub-LVDS Tx PHY allows for high-speed transmission with a 700Mbps data rate, tailored for systems necessitating exact timing and signal integrity. Boasting dual supply voltages of 1.2V and 1.8V, it enhances efficiency with selectable mode channels and advanced delay control for skew adjustment purposes. Its robust architecture makes it ideal for sophisticated electronic applications requiring reliable and efficient signal propagation.
Designed for high-speed data reception, the 700Mbps Sub-LVDS Rx PHY supports dual power supplies of 1.2V and 1.8V. It facilitates a maximum data rate of 700Mbps for each lane, with versatile applications requiring high data throughput. The PHY accommodates up to 8/10/12/14/16 bits selectable parallel data output and provides skew adjustments for precise timing control. Its robust design ensures reliable data reception across a wide range of interface requirements.
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