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KMX 100G UDPIP Core implements UDP/IP protocol hardware stack that achieves high-speed communication over a LAN or a point-to-point connection, which is ideal to offload systems from demanding tasks of UDP/IP encapsulation and to enable media streaming in both FPGA and RISC designs. The core supports ARP request, reply and manages 32-entry ARP cache. ICMP ping reply is included. The core provides DHCP client engine, which can get an IP address from external DHCP servers. The 100G UDPIP Core implements V3 IGMP membership Query/Report messaging. IP jumbo packets are supported as well as UDP port number filters and VLAN. IP/UDP checksum generation and validation are implemented. They can be enabled or disabled. The MDIO bus access to external device via AXI4-Lite bus is included. The IP raw packets are supported in both TX and RX. IP fragmentation and TCP protocol hardware stack companion core are available on demand. The core supports 32 RX channels and 32 TX channels. Each of the RX channels can be configured and associated with any of five RX ports. Each of the TX channels can be used to send IP packets on any of five TX Ports. The core connects to user logic through Control write Interface and Control Read Interface of AXI4-Lite buses; five RX Dedicated Ports of AXI4-Stream buses and five TX Dedicated Ports of AXI4-Stream buses. The core connects to 100G MAC module through AXI4-Stream bus. KMX 100G MAC and PCS cores are available to KMX customers.
The KMX AN and LT core consists of Auto-Negotiation and Link-Training modules for reliable communication with remote link partners. It conforms to IEEE 802.3ap-2007 standards, enhancing link quality for BER of 10^-12. Key features include AutoNeg RX and TX, various encoders and decoders, training engines, and control modules. It's applied in areas requiring ultra-low latency such as streaming, IP cameras, and high-speed data centers.
The core is widely used in applications where ultra-low, deterministic latency and high performance of throughput are required, such as video, image and audio streaming over Ethernet, IP cameras VOIP and smart phones, high frequency trading system, high-speed communication data centers, device monitoring and control over IP networks. It works as a key component in network architecture. The 100G MAC and PCS Core has been evaluated on Xilinx platform. The core is highly pipelined and optimized to achieve ultra-low latency and high performance. The core implements RS FEC as defined in IEEE 802.3bj Clause 91 with independent bit error detection and bit error correction. It implements configuration, control, status, statistical information collection and it supports VLAN tagged frame defined IEEE 802.1Q.
The core implements a UDP/IP hardware protocol stack that enables high-speed communication over a LAN or a point-to-point connection. It is ideal to offload systems from demanding tasks of UDP/IP and to enable media streaming in both FPGA and RISC designs. The core supports ARP request, reply and manages 32-entry ARP cache. ICMP ping reply is included. The core provides DHCP client engine, which can get an IP address from external DHCP servers. The 10G UDPIP Core implements V3 IGMP membership Query/Report messaging. The UDP jumbo packets are supported as well as UDP port number filters and VLAN.\n\nIP/UDP checksum generation and validation are implemented. MDIO bus access to external device via AXI4-Lite bus is included. IP raw packets are supported in both TX and RX.\n\nIP fragmentation and TCP hardware protocol stack companion core are available on demand.\n\nThe core supports 32 RX channels and 32 TX channels. Each of the RX channels can be configured and associated with any of five RX ports. Each of the TX channels can be used to send IP packets on any of five TX Ports.\n\nThe core connects to user logic through Control Interface of AXI4-Lite buses; five RX Dedicated Ports of AXI4-Stream buses and five TX Dedicated Ports of AXI4-Stream buses.\n\nThe core connects to 10G MAC module through AXI4-Stream bus. KMX 10G MAC and PCS cores are available to our customers.\n\nThe core is designed to well handle exceptions of internal memory exhaustion and invalid incoming packets while it makes the max use of internal memory to deal with TX and RX burst traffic effectively.\n\nThere is a fully implemented reference design which is shipped with the core delivery.
KMX 10G MAC and PCS core, which includes media access control (MAC) module, physical coding sublayer (PCS) module and physical medium attachment (PMA) module, is compliant with the IEEE 802.3ba-2010 standard. The core supports RS FEC defined in IEEE 802.3 Clause 108 with independent bit error detection and bit error correction. It connects to user logic via AXI4-Stream interface of 64 bits at 156.25MHZ and to 10G PCS core via XGMII interface of 64 bits at 156.25 MHZ. It also connects to user logic via AXI4-Lite interface. The MAC core accepts packets from user logic and generates new format packets by adding Preamble/SFD; padding zero bytes for short packets to 64 bytes; generating 32 bit CRC and padding it. It receives packets from 10G PCS via XGMII interface and generates new format packet by removing Preamble/SFD and 32 bit CRC after CRC checking. It supports Pause Frame processing for flow control and Implements Deficit Idle Count algorithm to ensure maximum possible throughput at the transmit interface. It implements internal XGMII loopback for debug purpose, which at the XGMII interface, the data flow on TX path is redirected to RX path and no data is forwarded to XGMII TX interface. It implements configuration, control, status, statistical information collection and it supports VLAN tagged frame defined IEEE 802.1Q. KMX 10G PCS module connects to 10G MAC module via XGMII of 64 bits at 156.25MHZ and connects to transceiver interface at 64 bits at 161.1328125MHZ. The PCS core is compliant with IEEE 802.3ba specifications. The core supports the following features: It implements 64b/66b encoding/decoding. The core supports 10G scrambling/descrambling of polynomial 1 + x^39 + x^58. It implements gearbox on both TX and RX. The 66-bit block synchronization algorithm implementation is included. The BIP-8 generation/insertion on TX and checking on RX are supported. It implements Bit Error Rate (BER) for monitoring excessive error ratio. The transceiver interface loopback for debug purpose is implemented, which at transceiver interface, the data flow on TX path is redirected to the RX path and no data is forwarded to transceiver TX interface. The core supports link signaling protocol.
The core implements a UDP/IP hardware protocol stack that enables high-speed communication over a LAN or point-to-point connection, ideal for offloading systems from demanding tasks of UDP/IP and enabling media streaming in both FPGA and RISC designs. It features support for ARP request, reply, and management, 32-entry ARP cache, ICMP ping reply, and DHCP client engine. It includes IP/UDP checksum generation and validation, MDIO bus access, and supports raw packets in both TX and RX. IP fragmentation and TCP hardware protocol stack companion core are available on demand. The design handles exceptions of internal memory exhaustion and invalid packets effectively. The core has been evaluated on Xilinx and Altera platforms for high performance.
The core implements a 40G UDPIP hardware protocol stack that enables high-speed communication over a LAN or point-to-point connection. It is ideal for offload systems demanding tasks of UDP/IP and media streaming in FPGA and RISC designs. Features include ARP request, reply, and a 32-entry ARP cache, ICMP ping reply, DHCP client engine, V3 IGMP membership messaging, IP jumbo packets, and more. The core is designed to handle exceptions of internal memory exhaustion and invalid incoming packets while maximizing internal memory usage for TX and RX burst traffic. The VHDL source code is provided on delivery.
KMX 40G MAC and PCS Core, which including media access control (MAC) module, physical coding sublayer (PCS) module and physical medium attachment (PMA) module, is compliant with the IEEE 802.3ba-2010 standard. The core supports RS FEC as defined in Clause 74 IEEE 802.3 with independent error bit detection and error bit correction. KMX 40G MAC module connects to user logic via AXI4-Stream interface of 128 bits at 312.5MHZ and to 40G PCS core via XLGMIIL interface of 128 bits at 312.5 MHZ. The MAC core accepts packets from user logic and generates new format packets by adding Preamble/SFD; padding zero bytes for short packets to 64 bytes; generating 32 bit CRC and padding it. It supports various advanced features and configurations. Widely used in applications where ultra-low, deterministic latency and high performance of throughput are required, such as video, image and audio streaming over Ethernet, IP cameras VOIP and smart phones, high frequency trading system, high-speed communication data centers.
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