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The RV32EC_P2 core is a streamlined 2-stage pipeline RISC-V processor core aimed at small, low-power embedded applications. This processor core is designed to run only trusted firmware and can be implemented in both ASIC and FPGA-based design flows. It is compliant with RISC-V User-Level ISA V2.2, incorporating standard compressed instructions to minimize code size and optional integer multiplication and division instructions for flexibility. With a simple machine-mode privileged architecture, it supports direct physical memory addressing, along with an external interrupt controller for expanded interrupt handling. The core also integrates tightly-coupled memory interfaces and a low-power idle state option, making it highly adaptable for various low-energy applications.
The USB-C/PD IP suite by IQonIC Works is tailored for developing and integrating USB Power Delivery and Type-C functionalities into ICs and ASICs. This IP offers a mix of digital soft IP blocks, firmware solutions, and hard macros to enable comprehensive support for USB-C/PD protocols. With a focus on flexibility, the offerings cover source-only, sink-only, and dual-role port configurations, along with accessory and debug support. The stack is architected to work either as a standalone block or integrated with an application CPU, providing versatile options for USB-C/PD deployment in designs.
The RV32IC_P5 processor core is tailored for medium-scale embedded applications that require enhanced performance. Featuring a 5-stage pipeline, this RISC-V processor supports a wider range of applications due to its ability to handle both trusted firmware and user-level applications. Enhanced with machine-mode and user-mode privileged architecture, it is compliant with RISC-V Privileged Architecture Version 1.10. The core offers optional support for branch prediction and data cache memories, delivering high-speed processing capabilities. With its sophisticated design, it is suitable for ASIC and FPGA-based implementations, supporting various execution contexts through an array of configurable options such as interrupt management and memory protection.
The RISC-V Platform-Level Interrupt Controller (PLIC) is a highly configurable module designed for handling a broad scope of interrupt sources within systems incorporating multiple processing units. Conforming to the RISC-V PLIC specification, it is suitable for both single and multiprocessor environments, providing controlled interrupt handling with multiple configuration options for sources, targets, and priority levels. The PLIC offers secure management of interrupts, interfacing seamlessly with associated AHB/APB devices, and integrates with RISC-V processors to support various interrupt contexts.
IQonIC Works provides a RISC-V Timer suite designed in accordance with the RISC-V standard machine timer specifications. The product offers flexibility with variants that operate both with and without clock-domain crossing. For conventional applications, the timers count processor clock cycles directly, while in low-power settings, they're integrated with a persistent low-frequency oscillator to maintain accuracy even when the main system clocks are gated. Designed for adaptability, they come with AHB and APB interfaces to fit into both complex and simple bus architectures.
The Intelligent Sensor and Power Management Platform (ISP) from IQonIC Works is a comprehensive solution for developing sensor-based, low-power embedded applications. The platform includes pre-assembled subsystems and a wide array of supporting tools designed to manage power efficiently and integrate seamlessly with digital processing units. It supports versatile options for embedding microcontroller units and I/O components to fit a variety of application needs. By providing a robust framework for the development of IoT devices, the ISP ensures efficient design and shorter time to market for advanced sensor and control applications.
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