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The RV32EC_P2 Processor Core is a streamlined, 2-stage pipeline RISC-V processor core developed to meet the requirements of compact, power-efficient embedded applications running exclusively on trusted firmware. Engineered for use in both ASIC and FPGA design flows, it supports the RISC-V RV32E base instruction set and is compliant with RISC-V User-Level ISA Version 2.2. Its design includes RVC compressed instructions to minimize code size, along with optional integer multiplication and division instructions ("M" standard extension). A key feature of the RV32EC_P2 Processor Core is its provision for custom, application-specific instruction set extensions, making it particularly suited for digital signal processing tasks. It employs a straightforward machine-mode privileged architecture, ensuring compliance with the RISC-V Privileged Architecture Version 1.10, and offers 20 extended interrupts, along with support for external controllers to handle additional interrupts. Designed to deliver fast interrupt responses, this processor core includes vectored interrupts and clock gating to aid low-power idling, ensuring energy efficiency. It supports tightly-coupled memory interfaces applicable to both ASIC ROM and SRAM or FPGA block memories. Its functionality is enhanced by AHB-Lite or APB interfaces for expanded memory access, and it comes equipped with GNU toolchain and Eclipse support for efficient firmware development.
IQonIC Works’ Intelligent Sensor and Power Management Platform (ISP) provides an all-encompassing solution for the development of sensor-based, intelligent, embedded applications. The platform emphasizes key areas like power management, energy harvesting, sensor interfacing, and processing, utilizing a rich variety of design building blocks and pre-assembled, validated sub-systems. By offering this suite as an integrated platform, IQonIC Works ensures that projects aimed at developing new ASICs or improving existing designs can maintain budget and time constraints more typical of derivative projects. The ISP expands the scope of possibilities in diverse applications, especially those associated with IoT, by delivering modular and scalable design tools. Additionally, the ISP supports various MCU cores and I/O IP configurations, allowing solutions to be tailored to specific application requirements. It integrates easily with other design blocks, providing the flexibility needed to accommodate additional features such as communication and security, making it an invaluable resource for advanced IoT and sensor applications.
The RV32IC_P5 Processor Core is a high-performance, 5-stage pipeline RISC-V processor designed to support medium-scale embedded systems that demand elevated performance levels. It features capabilities like caching and support for both trusted firmware and general user applications. Using the RISC-V RV32I base instruction set, this core complies with the RISC-V User-Level ISA V 2.2 and introduces several optional standard extensions. The processor includes "A" standard extensions, which aid in critical section handling in uniprocessor systems, and support for RVC standard compressed instructions to optimize code size. Developed with both machine-mode and user-mode privileged architectures, it ensures direct physical memory access while supporting potential application-specific DSP operations through customizable instruction set extensions. It is equipped with a robust interrupt handling mechanism, including vectoring of interrupts and exceptions delegated to user mode, allowing for expedited response times. Its power efficiency is maintained by a wait-for-interrupt instruction that enables clock gating during low-power idle states, and it interfaces through AHB-Lite paths for extended memory and memory-mapped I/O access.
IQonIC Works’ RISC-V Platform-Level Interrupt Controller (PLIC) IP is designed in adherence to the RISC-V PLIC specification for managing numerous interrupt sources in systems featuring multiple processor targets. This controller is highly configurable, allowing adjustments to match the specifics of an application's interrupt source and target requirements. The PLIC supports a configurable number of interrupt sources, ranging from 31 to as many as 1023, catering to a wide array of potential system demands. Its capability extends to supporting numerous target hart contexts and multiple priority levels, making it an adaptable solution for differing project complexities. Each interrupt source can be tailored for synchronous or asynchronous signals, and sensitivity choices include level and edge (rising/falling) detection. The interrupt controller is equipped with an AHB-Lite interface to facilitate register access for setting and managing priorities, enabling or disabling interrupts, and co-ordinating the handling of claims and completions of interrupts. This makes the PLIC vital for applications where robust, secure, and efficient management of interrupts is critical, aiding in the seamless operation of complex embedded systems.
The RISC-V Timer IP from IQonIC Works offers a collection of timers that adhere to the RISC-V standard machine timer specification, providing essential timing solutions for embedded systems. These timers are versatile, supporting simple setups that count processor-clock cycles without involving clock-domain crossing (CDC), and more complex arrangements suitable for low-power applications, where the system clock might be gated off. For such low-power use cases, the timer can instead count cycles from a low-frequency, always-on clock like a 32kHz oscillator, making it ideal for applications where energy efficiency is paramount. Different timer variants come with an AHB bus interface for sophisticated systems or an APB interface for more streamlined, simpler bus structures. The inclusion of an AHB interface in some versions allows integration into systems with layered buses, whereas APB-only options cater to systems with straightforward APB buses. This timer IP suite ensures flexibility and performance for a wide range of design needs in both simple and complex embedded environments.
IQonIC Works offers advanced USB-C/PD IP solutions that encompass both hardware and firmware requirements for integrating USB-C/PD functions into IC/ASIC designs. With a focus on flexibility and integration, this IP supports various configurations, such as source-only, sink-only, and full Dual-Role Port (DRP) functions, each designed to facilitate different usage scenarios and accessory support. These USB-C/PD solutions are available in both soft IP and hard macros, allowing manufacturers to cater to specific needs, whether it's creating discrete devices or incorporating them into multi-die packaged solutions. The IP further provides debug and accessory support options, enabling a comprehensive approach to USB-C/PD implementation.
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