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IPM-NVMe Device is a high-performance data transfer management solution crafted for PCIe-based storage systems. This IP core functions as a vital interface between communication and NAND flash controllers, effectively relieving host CPU workloads. Fully compliant with UNH-IOL NVM Express, it provides extensive integration options for a host of system designs. The IPM-NVMe Device supports automatic command processing and multi-channel DMA, capable of managing up to 65,536 I/O queues. It features advanced capabilities such as weighted round-robin queue arbitration, asynchronous event management, and low-power architecture, all optimized for seamless scalability and integration into multiple PCIe generations. Manufacturers benefit from its standardized driver, facilitating easier software development and reducing costs. Whether in FPGA or SoC designs, this IP core is designed to support next-generation emerging memory solutions like MRAM and ReRAM, making it adaptable for use in both consumer and enterprise products.
The IPM-NVMe Host is a versatile NVMe and PCIe protocol management IP designed for integration in FPGA or ASIC systems. It enables seamless data transfer management in high-throughput storage applications without necessitating a CPU, thereby offering cost, space, and power efficiencies critical for embedded systems. It is particularly well-suited for applications requiring rapid data access, such as video and recording devices. This IP core is fully-featured and boasts an automatic PCIe/NVMe initialization engine, multiple queue management, ultra-low latency, and very high throughput capabilities. Its scalable architecture supports various application interfaces, including AXI or RAM-like interfaces, making it user-friendly and reducing the time-to-market for OEMs. Additionally, the NVMe host manages commands and data transfers autonomously, which maximizes performance and power efficiency. Evaluation of the IPM-NVMe Host is facilitated through reference designs on platforms like Xilinx Ultrascale FPGA, compatible with NVMe SSDs available commercially. The design reduces development risks by providing a ready-to-use, high-performance data transfer manager optimized for embedded solutions.
IPM-LDPC is a dynamic encoder/decoder IP core utilizing the LDPC algorithm to fortify NAND flash storage against data errors. This core is configurable, allowing adjustments to accommodate various error correction levels and computational demands, thus enhancing the reliability and lifespan of NAND flash memory. The core is designed to provide full customization options across a range of performance metrics, enabling developers to optimize for latency, gate count, or other specific requirements. Its versatile architecture covers Galois fields and optional short code paths to maintain high throughput and efficiency, crucial for handling complex data storage tasks effectively. With a robust set of features including adaptable bit error rates and multiple iteration checks, IPM-LDPC stands as a vital component in sophisticated data correction for secure storage environments. Its implementation reduces development risk and accelerates time to market by providing a proven, scalable solution for modern data management challenges.
IPM-NVMe2NVMe is a sophisticated reference design aimed at enhancing NVMe storage environments with customized data management logic. Integrated into an FPGA or ASIC platform, this solution allows the incorporation of additional processing elements like erasure coding, RAID systems, and encryption, aligning with cutting-edge computational storage needs. This design supports dynamic enhancements to NVMe architectures, making it a versatile foundation for introducing custom features seamlessly and efficiently. With support for multiple host interfaces, it acts as a pivotal intermediary to ensure optimal throughput and scalable performance in NVMe ecosystems. Developers can benefit from the flexible architecture, which is not only easy to integrate but also capable of extensive modifications according to user-specific requirements. This solution distinctly accommodates the integration of proprietary algorithms and processes, transforming mainstream NVMe setups into highly specialized storage systems tailored to unique business exigencies.
The IPM-BCH encoder/decoder core is integral to enhancing NAND flash memory durability by detecting and correcting errors inherent in NAND's operation. Utilizing the BCH algorithm, this IP core delivers a powerful error correction capability, essential for maintaining data integrity in NAND flash-based storage solutions. It offers full customizability to meet specific latency or gate count requirements, whether for FPGA or SoC designs. The IP is engineered to protect data using adjustable block sizes, Galois field computations, and support for error correction up to 84 bits per block, ensuring robust protection and reliability in varying storage environments. With options for asynchronous operation and optimized latency paths, the IPM-BCH is well-suited for applications that prioritise high-speed data processing while preserving minimal silicon footprint. This comprehensive hardware solution not only enhances performance but also reduces time to market by providing prevalidated implementations adaptable to specific design needs.
The IPM-UNFC, or Universal NAND Flash Controller, is designed to empower enterprise storage solutions by effectively leveraging commodity flash memory. With compliance up to ONFI 5.x, it supports multiple NAND flash types such as SLC, MLC, TLC, and QLC, enhancing reliability and data integrity in high-performance storage applications. This IP core provides complete hardware support for NAND flash operations, including ECC and configurable BCH to meet specific NAND vendor requirements. The universal design eases the integration into systems with interface options like AXI, Avalon, and RAM, significantly shortening development cycles for OEMs. IPM-UNFC is a comprehensive solution catering to both FPGA and SoC implementations. Its versatility allows OEMs to harness NAND flash benefits across different modes and configurations, enabling scalable page size and spare size adjustments, thus broadening its suitability for a wide range of storage products.
The IPM-SSD is a reference design architecture tailored for crafting custom PCIe NVMe SSD solutions. Leveraging the robust capabilities of NVMe and NAND Flash offloaded IPs, it offers significant design flexibility suitable for both FPGA and ASIC implementations, primarily aimed at computational storage solutions. This reference architecture enables customization of logic components, such as encryption and compression modules, catering to unique storage requirements. Users maintain control over address management strategies and data operations within the system, promoting versatility across various use cases from simple consumer devices to complex enterprise applications. IPM-SSD is instrumental for developers aiming to create SSDs quickly without profound resource investments. It serves as a baseline for developing feature-rich SSDs, maximizing efficiency while simplifying the integration process. Complemented by IP-Maker’s support services, this design reduces complexity and accelerates the transition from concept to production-ready storage solutions.
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