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The DES/3DES Core offers an extensive design that implements both the Data Encryption Standard (DES) and Triple DES (3DES) encryption and decryption, following the NIST FIPS 46-3 specification. It features the ability to process 64-bit data blocks using one, two, or three 56-bit keys across several cipher modes including ECB, CBC, and OFB. Because of its compact design, utilizing only 3,000 ASIC gates, it ensures high-speed operations reaching up to 3 Gbps at 90nm technology. This IP core is delivered as synthesizable Verilog or netlist format, featuring a completely self-contained design without the need for external memory.
The AES IP Core is an ultra-compact implementation of the Advanced Encryption Standard (AES), utilizing the Rijndael block cipher algorithm. It is capable of processing 128-bit data blocks using either 128-bit, 192-bit, or 256-bit keys, and is compliant with NIST FIPS-197 standards. Offering a spectrum of encryption and decryption modes such as ECB, CBC, and CTR, this core supports various data paths, allowing for an efficient trade-off between size and performance. Designed for both ASIC and FPGA implementations, the AES core is self-contained, requiring no external memory, thus providing robustness against differential power attacks through optional data masking and cycle hiding features.
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