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SystemBIST is a cutting-edge solution designed for flexible FPGA configuration and JTAG embedded test. It is a complete plug-and-play device providing a code-less configuration methodology. SystemBIST caters to high-quality products that require self-testable and in-field reconfigurable capabilities, independent of vendor-specific limitations. This enables devices to support IEEE 1532 and IEEE 1149.1 compliant FPGAs and CPLDs, allowing seamless integration across various systems. This robust BIST solution eliminates the complexity of traditional firmware-based tests by embedding JTAG-derived test patterns directly onto the PCB. Stored into system FLASH memory, these patterns enable thorough testing anywhere the PCB is powered, thus extending the test environment into the field without the need for additional test equipment. The deterministic BIST uniquely positions SystemBIST as a reliable solution compared to traditional methods requiring substantial engineering and testing resources. SystemBIST also incorporates anti-tamper technologies, featuring on-chip security identifiers to deter cloning and maintain system integrity. This security feature, alongside its embedded self-test capabilities, makes SystemBIST ideal for mission-critical applications demanding reliable performance and security.
Scan Ring Linker (SRL) is a versatile solution that simplifies the complexity of designing with multiple JTAG (IEEE 1149.1) scan rings. It acts as an intermediary test bus, centralizing the test and configuration processes across various scan paths on a circuit board. SRL can be effortlessly embedded within CPLDs, FPGAs, or ASICs on a PCB, significantly reducing the associated design costs and complexities typically encountered. This integration links numerous scan rings into a singular high-speed interface, ensuring devices on secondary chains are independently accessed for testing and configuration without redundancy or interference. Utilizing SRL translates to achieving higher efficiency within the test suite development while maintaining robust device interconnection tests. This is particularly beneficial when dealing with designs that implement a multitude of embedded systems, where effective testing of interconnections is paramount, and single access points prove to be a strategic advantage.
Fast Access Controller (FAC) is an efficient pre-engineered IP solution designed to enhance on-board Flash programming and test performance, particularly in high-demand production environments. FAC caters to processor and ASIC/SoC designers by providing accelerated programming capabilities, minimizing turnaround times for external Flash devices. This solution utilizes the IEEE 1149.1 (JTAG) test bus to streamline data transfer, enabling swift programming of Flash memory connected through FPGA interfaces. Its implementation results in considerable reductions in programming time compared to traditional methods, directly impacting production efficiency. The FAC's robust architecture promotes seamless integration into existing systems, affording design teams the ability to respond quickly to evolving test demands. This makes it a vital component of modern electronic production lines, where quick adaptation and minimal downtime are critical.
JTAG Test and Configuration is a solution that provides powerful hardware and software tools for executing IEEE 1149.1 (JTAG) based testing and configuration. It is designed to be used in the production environment where cost-effective high fault coverage is essential. Leveraging boundary-scan technology, it enables efficient testing of IC interconnections, even within complex PCBs, ensuring that digital faults can be isolated and rectified swiftly. This configuration toolkit supports the execution of IPC test programs that can be seamlessly transitioned from development to production environments. By harnessing the capabilities of the Eclipse Test Development Environment, it allows for the embedding of comprehensive tests directly into designs. Users can manipulate pin states and perform system-wide diagnostics without the need for traditional physical access points like test pads, significantly improving test coverage and accuracy. JTAG Test and Configuration also integrates with external test tools, blending industry-standard protocols and custom scripting to manage complex test scenarios. This flexibility ensures that even the most intricate assemblies can be tested with minimal setup time, thus improving overall productivity and lowering costs in high-volume manufacturing scenarios.
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