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SystemBIST is a sophisticated, plug-and-play configuration module designed to streamline FPGA configuration and embedded JTAG testing within PCBs. Built on patented architectures, it simplifies the creation of high-quality, self-testable products that can be reconfigured in the field. This vendor-independent device supports extensive compatibility, enabling the configuration of any IEEE 1532 or IEEE 1149.1 compliant FPGA and CPLD in-system. SystemBIST notably improves the efficiency of embedded test processes by repurposing manufacturing JTAG/IEEE 1149.1 based test patterns into the PCB design, providing significant savings on production costs. The SystemBIST architecture not only re-uses existing test scripts but also compresses them into onboard FLASH memory, allowing for fast and reliable PCB testing anywhere. This capability is crucial for modern electronics, where flexibility and security, such as mitigating risks from trojan bitstreams and cloning, are vital considerations. Intellitech's device incorporates AES encryption for secure configurations, ensuring product integrity and protecting against unauthorized cloning. SystemBIST's failsafe update feature allows field updates without erasing the entire FLASH, safeguarding original FPGA designs. With its robust testing and configuration capabilities, SystemBIST paves the way for efficient debugging and maintenance, offering a unified methodology for in-system configuration and test across the entire product lifecycle. It serves as both a debugging tool and an updater, adding value by facilitating anytime and anywhere PCB testing.
The Scan Ring Linker (SRL) is an advanced solution designed to simplify the integration of 1149.1 (JTAG) infrastructure into PCB designs. This complete IP module can be embedded into CPLD, FPGA, or ASIC designs on PCBs to address the challenges of managing multiple scan rings in advanced digital architectures. By linking any number of secondary scan paths into a single high-speed test bus, SRL allows for independent testing and configuration through a unified 1149.1 external interface. The SRL IP module is engineered to enhance design flexibility and reduce the costs associated with JTAG integration by seamlessly consolidating multiple scan chains. This consolidation streamlines testing processes significantly, cutting down on the time and resource investments typically required to develop and maintain ad-hoc testing structures. Moreover, the SRL supports high-speed data transfers, making it a critical asset for designs that demand rigorous testing standards and rapid configurations. Intellitech's SRL module delivers a path to cost savings by eliminating redundant parts and reducing the engineering time devoted to designing JTAG components. It is suitable for a wide array of applications, including large-scale production testing and configurations where independent high-speed scan ring integration is required. The SRL enhances a product's lifecycle by facilitating ongoing updates and reconfigurations without the need for substantial redesign efforts.
The Fast Access Controller (FAC) by Intellitech is a pre-engineered IP solution that responds swiftly to the demands for enhanced design-for-test features and improved programming performance of external FLASH memory in production environments. Especially beneficial for processor and ASIC/SoC designers, FAC provides the fastest method for programming on-board FLASH, leveraging a small bitstream that transmits data over the 1149.1 bus. This innovation significantly reduces in-system FLASH programming times, catering to the high speeds required in modern digital environments. FAC is particularly synergistic when used in conjunction with FPGA, facilitating streamlined operations that bypass the need for traditional, time-consuming programming methods. This setup reduces overall design complexity and improves operational efficiency by eliminating the need for additional components such as configuration PROMs and voltage translators. FAC's capability to manage multiple scan chains also contributes to simplified designs, minimizing redundant engineering efforts. By integrating FAC into a design, developers can create scalable, testable products without extensive rework for each product generation. It supports both fast configuration and embedded test processes, enhancing the flexibility of products across their lifecycle. FAC's compatibility with the Eclipse Test Development Environment ensures seamless integration and validation of configuration data, ensuring superior performance in both prototype and production phases.
The JTAG Test and Configuration solution by Intellitech leverages IEEE 1149.1/JTAG techniques to provide an extensive set of boundary scan test tools for PCBs. This solution empowers design teams with the capability to not only perform high-quality self-testing but also to undertake in-field reconfiguration of products. By using patented plug-and-play scan components, Intellitech reduces BOM costs while enhancing product functionalities. The Eclipse Test Development Environment is a comprehensive toolkit that allows seamless integration of debug and test processes into PCB designs, significantly lowering development time. The suite supports concurrent testing, eliminating production bottlenecks by executing tests across multiple PCBs simultaneously. This makes the Intellitech solution ideal for deployment in both prototyping and high-volume production environments.
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