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SystemBIST offers a versatile plug-and-play solution for FPGA configuration and JTAG testing with its unique patented architecture. This product is ideal for creating high-quality, self-testable, and in-the-field reconfigurable equipment, ensuring reliable integration and testing in any IEEE 1532 or 1149.1 compliant devices. SystemBIST efficiently utilizes existing system flash memory to store vital configuration and test data, which can be applied at power-up, enabling cost-effective setup without the need for multiple configuration PROMs. Additionally, SystemBIST enhances PCB testing efficacy by embedding deterministic Built-In Self-Test (BIST) capabilities, using manufacturing-based JTAG/IEEE 1149.1 test patterns to conduct efficient system tests. This platform simplifies the adoption of robust security measures, including 128-bit security identifiers, helping prevent unauthorized cloning and tampering of FPGAs. By doing so, it seamlessly supports the intricate demands of modern electronics and embedded systems. The platform not only reduces the cost associated with in-system configuration but also advances the embedded test methodology by enabling debugging without removing and replacing programmable components. It offers a scalable and reusable test infrastructure, applicable across different product generations and varying applications, thereby extending the operational life and value of the technology involved.
The Scan Ring Linker (SRL) serves as a fully-embeddable solution designed to streamline JTAG test infrastructure, significantly easing the design complexities and reducing the associated costs of implementing multiple scan rings within a single system. This IP module effectively transforms diverse scan paths into a unified high-speed test bus, enabling seamless access and configuration of components on secondary chains without cumbersome hardware redesigns. Especially beneficial for designs involving numerous interconnected scan rings, the SRL enables broad testing and configuration possibilities by linking all secondary paths to a central management bus. In doing so, engineers can independently test and configure each connected element through a singular 1149.1 interface, effectively consolidating test procedures and simplifying the design workflow. Moreover, the SRL reduces manufacturing and operational costs by cutting down the need for multiple configuration PROMs and voltage translators in multi-scan chain designs. By this, it not only aids in efficient product testing but also aligns with stringent standards for effective and rapid device configuration and testing in modern electronic manufacturing environments.
The Fast Access Controller (FAC) from Intellitech delivers an efficient solution for programming flash memory on industrial-grade boards. Primarily designed for processor (Micro-controller, DSP, or CPU) and ASIC/SoC design environments, this controller excels in speeding up the programming of onboard flash memory using the 1149.1 bus. The FAC's architecture allows for rapid data transmission to flash memory, minimizing the programming duration and accelerating production timelines. FAC enables quick data exchange by loading a small bitstream onto the connected FPGA, facilitating faster than standard data transfers over a single unified test bus. This innovative solution reduces the need for extensive manual interventions during device audits and offers a robust framework for enhancing the integrity of electronic systems under varied operating conditions. Intellectually tailored for high-demand environments, FAC's capabilities empower design teams to achieve heightened productivity levels while meeting the evolving demands of modern automated configurations. It supports comprehensive fault coverage evaluations, ensuring robust configurations that are constantly adaptable to dynamic production challenges.
Intellitech’s JTAG Test and Configuration solution offers a comprehensive toolkit leveraging boundary-scan technology to enhance design debug, in-system device configuration, and automated test program development. The Eclipse Family products encompass rigorous testing tools that employ the IEEE 1149.1 standard, empowering engineers to execute high-coverage tests efficiently. Through this integrated solution, manufacturers can swiftly move products from development into volume production, while minimizing risk and enhancing product quality. Moreover, this architecture supports streamlined device programming and configuration tasks, greatly reducing manufacturing costs and expediting time-to-market.
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