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The Scan Ring Linker (SRL) is meticulously crafted to integrate effortlessly into CPLDs, FPGAs, or ASICs within a PCB, with the specific purpose of streamlining the 1149.1 (JTAG) test infrastructure across multiple scan rings. This intuitive module is part of Intellitech's expansive TEST-IP family, known for optimizing design processes and reducing associated costs without sacrificing performance. The SRL plays a pivotal role by amalgamating any number of secondary scan paths into a singular, high-speed test bus. This consolidation enables a seamless selection and independent testing or configuration of devices aligned on secondary scan chains through one external 1149.1 interface. Consequently, the design complexities and expenses in creating comprehensive JTAG infrastructures diminish significant. Offering a simplified yet effective solution, SRL removes the need for custom mechanisms, ensuring that devices on multiple scan chains can undergo thorough testing and configuration, fostering efficiency and cost-effectiveness. With its plug-and-play nature, SRL assures design teams of reduced BOM costs while maintaining high-quality standards in thorough device testing and configuration scenarios.
SystemBIST is a revolutionary plug-and-play device designed to facilitate flexible FPGA configuration and embedded JTAG testing. As part of Intellitech's TEST-IP family, this tool is vendor-independent, capable of configuring all IEEE 1532 or IEEE 1149.1 compliant FPGAs and CPLDs in-system. SystemBIST employs patented architecture enabling design engineers to create high-quality, self-testable, and reconfigurable field-ready products, negating the need for custom firmware or software-driven built-in tests. Through its interface, SystemBIST allows for the reprogramming of system CPLDs, EEPROMs, and FLASH in the field, reusing manufacturing test patterns and scripts. This dramatically reduces the cost and complexity traditionally associated with board-level BIST systems. The ability to store tests and FPGA configurations compressed in FLASH memory, permits PCBs to be tested conveniently whenever power is available, enhancing the operational flexibility. Not only does this solution offer comprehensive testing capabilities, but it also includes troubleshooting and security features like anti-tamper FPGA security options, preventing unauthorized bitstream overwriting. SystemBIST, while reducing overall system costs, provides significant benefits such as deterministic built-in self-test, eliminating the need for costly ATE systems, and providing seamless test and configuration updates across a product’s lifecycle, making it an invaluable tool for modern PCB testing demands.
The Fast Access Controller (FAC) is a fast, efficient solution engineered for designers of processors such as microcontrollers, CPUs, and DSPs, looking to enhance Design-for-Test capabilities and improve performance. This controller significantly accelerates the process of programming on-board Flash memory, especially when it links with FPGA, delivering rapid data transfer via the JTAG 1149.1 bus. FAC is part of Intellitech's patented TEST-IP Family and answers the market demand for improved support and programming performance in production settings. The solution integrates seamless FLASH programming data transfer, reducing programming times substantially compared to traditional methods. This boosts overall production efficiency and ensures reliable functionality in testing environments. Incorporated within the Eclipse Test Development environment, FAC provides a high-speed interface through a small bitstream, facilitating the quick loading of FLASH programming data. It broadly reduces cost and enhances system reliability, pushing the boundaries of what can be achieved in high-volume manufacturing environments.
The JTAG Test and Configuration solution by Intellitech provides a robust framework for using IEEE 1149.1 (JTAG) techniques to lower system costs and enhance product testability and configurability. This patented infrastructure Intellectual Property enables design teams to develop high-quality, self-testable products that can be reconfigured in the field. By integrating plug-and-play scan components, it reduces design complexity, shortens development time, and provides capabilities that add significant value for customers. This solution supports a comprehensive range of tools for boundary scan, flash programming, and FPGA configuration, integrated into Intellitech's Eclipse Test Development Environment. This environment offers a complete suite for 1149.1-based testing and in-system configuration of complex PCBs and systems, reducing debug time and enhancing prototype testing efficiency. The capability to toggle and observe logic values directly enhances the ease and effectiveness of debugging processes. The tools included in this solution, such as the Scan Executive and accompanying production test platforms, ensure PCB shorts and opens can be identified with minimal effort, streamlining the testing process. Concurrent JTAG testing allows for the testing of multiple PCBs or System Under Test units simultaneously, optimizing throughput without creating production bottlenecks. Overall, this solution drastically improves testing experiences and operational efficiencies in high-volume manufacturing environments.
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