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Eliyan

Eliyan is a transformative entity in the semiconductor industry, renowned for its proprietary NuLink™ PHY technology. This innovative solution offers unprecedented performance on standard packaging, rivaling the capabilities that typically require advanced packaging. Eliyan’s technology focuses on high-speed serial die-to-die and die-to-memory connections, supporting both industry-standard and custom interconnect schemes. It showcases remarkable results in terms of performance, power efficiency, and area, making it highly attractive for applications like AI performance enhancement and overcoming memory bandwidth limitations. The company achieved a significant breakthrough in PHY technology architecture in 2016 under the guidance of Ramin Farjadrad, the recognized PHY expert and founder of Eliyan. This advancement capitalized on recognizing the distinct electrical environments between dies in multi-die packages, leading to enhanced power efficiency and performance. This breakthrough was promptly embraced as an industry standard by entities such as the Open Compute Project (OCP) for chiplet interconnect via Bunch of Wires (BoW), and later evolved to support Universal Chiplet Interface Express (UCIe). Eliyan’s contributions to the semiconductor space extend beyond PHY development, as they have proposed the Universal Memory Interface (UMI), enabling customizable ASIC configuration for different performance demands using various memory formats. They also pioneer simultaneous bidirectional signaling (SBD), allowing data to be received and transmitted on the same wires concurrently, thereby doubling interface bandwidth. Eliyan’s innovations aim to break bottlenecks in AI-intensive industries by significantly enhancing training and inference capabilities, as well as offering cost-effective and high-performing solutions in line with industry needs. Read more

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NuLink Die-to-Die PHY for Standard Packaging

The NuLink Die-to-Die PHY is a state-of-the-art IP solution designed to facilitate efficient die-to-die communication on standard organic/laminate packaging. It supports multiple industry standards, including UCIe and Bunch of Wires (BoW) protocols, and features advanced bidirectional signaling capabilities to enhance data transfer rates. The NuLink technology enables exceptional performance, power economy, and reduced area footprint, which elevates its utility in AI applications and complex chiplet systems. A unique feature of this PHY is its simultaneous bidirectional signaling (SBD), that allows data to be sent and received simultaneously on the same physical line, effectively doubling the available bandwidth. This capacity is crucial for applications needing high interconnect performance, such as AI training or inference workloads, without requiring advanced packaging techniques like silicon interposers. The PHY's design supports 64 data lanes configured for optimal placement and bump map layout. With a focus on power efficiency, the NuLink achieves competitive performance metrics even in standard packaging, making it particularly suitable for high-density systems-in-package solutions.

AMBA AHB / APB/ AXI, CXL, D2D, MIPI, Network on Chip, Processor Core Dependent

NuLink Die-to-Memory PHY Products

The NuLink Die-to-Memory PHY is crafted to enhance communication between dies and memory components, addressing the bandwidth needs of modern computational systems. By employing both unidirectional and half-duplex bidirectional lanes, this PHY adapts to dynamic data traffic conditions, ensuring seamless data flow between processors and memory banks like HBM or DDR. It leverages standard packaging to offer cost-effective yet high-performing interfaces that meet demanding bandwidth requirements. NuLink for Die-to-Memory applications optimizes memory traffic through its bidirectional transceivers that enable fast directional switching, ensuring efficient memory utilization. This configuration enhances the exclusive beachfront bandwidth available for memory operations, effectively bridging the bandwidth gap experienced in standard packaging solutions. Enabling scalability, the PHY facilitates the integration of large-scale HBM configurations in standard packages, a critical factor for AI and machine learning applications, where memory access speed dictates overall computational efficiency.

AMBA AHB / APB/ AXI, D2D, DDR, HBM, Mobile DDR Controller, NVM Express, SDRAM Controller

Latest News About Eliyan

Navigating the Complex Maze of Die-to-Die Interconnect Standards

Exploring the nuances of UCIe 2.0, its optional features, and the evolving chiplet marketplace. Read more