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The NuLink Die-to-Die PHY for Standard Packaging by Eliyan offers an innovative solution for high-performance interconnects between die on the same package. This technology significantly boosts bandwidth and energy efficiency, using industry-standard organic/laminate substrates to simplify design and reduce costs. It leverages a unique implementation that negates the need for more expensive silicon interposers or silicon bridges while maintaining exceptional signal integrity and compact form factors. With conventional bump pitches ranging from 100um to 130um, these PHY units support various industry standards such as UCIe, BoW, UMI, and SBD, delivering a versatile platform suitable for a wide array of applications. This flexibility ensures it meets the rigorous demands of data-centric and performance-oriented computing needs, with optimal performance observed at advanced process nodes like 5nm and below. Eliyan's NuLink PHY further breaks technological barriers by delivering synchronous unidirectional and bidirectional communication capabilities, achieving data rates up to 64 Gbps. Its design supports 32 transmission and receiving lanes to ensure robust data management in complex systems, making it an ideal solution for today's and future's data-heavy applications.
Eliyan's NuLink Die-to-Memory PHY is engineered to optimize memory interfaces within multi-chip systems, enhancing bandwidth and reducing latency between processing units and memory. Targeted at advanced computing applications, these PHY products leverage a standard interfacing approach to maintain compatibility while pushing the boundaries of performance, especially critical in data-intensive tasks like AI and machine learning. The PHY design supports a high degree of modularity, facilitating easy integration into systems with varying requirements, from HPC to embedded processing environments. Operating seamlessly across both standard and advanced packaging environments, it offers significant improvements over traditional memory interconnects, including substantial power savings and thermal efficiency, key considerations in the design of modern semiconductor devices. Designed to meet the performance demands of future applications, the NuLink Die-to-Memory PHY supports broad on-chip data exchange, crucial for fast and efficient communication between multi-core processors and memory modules. This results in a scalable, high-throughput interconnect capable of future-proofing technological investments against advancing data processing demands.
Exploring the nuances of UCIe 2.0, its optional features, and the evolving chiplet marketplace. Read more
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